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xhci.c 80KB

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  1. /*
  2. * Copyright (C) 2014 Michael Brown <mbrown@fensystems.co.uk>.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation; either version 2 of the
  7. * License, or (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but
  10. * WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  12. * General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  17. * 02110-1301, USA.
  18. */
  19. FILE_LICENCE ( GPL2_OR_LATER );
  20. #include <stdlib.h>
  21. #include <stdio.h>
  22. #include <unistd.h>
  23. #include <string.h>
  24. #include <strings.h>
  25. #include <errno.h>
  26. #include <byteswap.h>
  27. #include <ipxe/malloc.h>
  28. #include <ipxe/umalloc.h>
  29. #include <ipxe/pci.h>
  30. #include <ipxe/usb.h>
  31. #include <ipxe/profile.h>
  32. #include "xhci.h"
  33. /** @file
  34. *
  35. * USB eXtensible Host Controller Interface (xHCI) driver
  36. *
  37. */
  38. /** Message transfer profiler */
  39. static struct profiler xhci_message_profiler __profiler =
  40. { .name = "xhci.message" };
  41. /** Stream transfer profiler */
  42. static struct profiler xhci_stream_profiler __profiler =
  43. { .name = "xhci.stream" };
  44. /** Event ring profiler */
  45. static struct profiler xhci_event_profiler __profiler =
  46. { .name = "xhci.event" };
  47. /** Transfer event profiler */
  48. static struct profiler xhci_transfer_profiler __profiler =
  49. { .name = "xhci.transfer" };
  50. /* Disambiguate the various error causes */
  51. #define EIO_DATA \
  52. __einfo_error ( EINFO_EIO_DATA )
  53. #define EINFO_EIO_DATA \
  54. __einfo_uniqify ( EINFO_EIO, ( 2 - 0 ), \
  55. "Data buffer error" )
  56. #define EIO_BABBLE \
  57. __einfo_error ( EINFO_EIO_BABBLE )
  58. #define EINFO_EIO_BABBLE \
  59. __einfo_uniqify ( EINFO_EIO, ( 3 - 0 ), \
  60. "Babble detected" )
  61. #define EIO_USB \
  62. __einfo_error ( EINFO_EIO_USB )
  63. #define EINFO_EIO_USB \
  64. __einfo_uniqify ( EINFO_EIO, ( 4 - 0 ), \
  65. "USB transaction error" )
  66. #define EIO_TRB \
  67. __einfo_error ( EINFO_EIO_TRB )
  68. #define EINFO_EIO_TRB \
  69. __einfo_uniqify ( EINFO_EIO, ( 5 - 0 ), \
  70. "TRB error" )
  71. #define EIO_STALL \
  72. __einfo_error ( EINFO_EIO_STALL )
  73. #define EINFO_EIO_STALL \
  74. __einfo_uniqify ( EINFO_EIO, ( 6 - 0 ), \
  75. "Stall error" )
  76. #define EIO_RESOURCE \
  77. __einfo_error ( EINFO_EIO_RESOURCE )
  78. #define EINFO_EIO_RESOURCE \
  79. __einfo_uniqify ( EINFO_EIO, ( 7 - 0 ), \
  80. "Resource error" )
  81. #define EIO_BANDWIDTH \
  82. __einfo_error ( EINFO_EIO_BANDWIDTH )
  83. #define EINFO_EIO_BANDWIDTH \
  84. __einfo_uniqify ( EINFO_EIO, ( 8 - 0 ), \
  85. "Bandwidth error" )
  86. #define EIO_NO_SLOTS \
  87. __einfo_error ( EINFO_EIO_NO_SLOTS )
  88. #define EINFO_EIO_NO_SLOTS \
  89. __einfo_uniqify ( EINFO_EIO, ( 9 - 0 ), \
  90. "No slots available" )
  91. #define EIO_STREAM_TYPE \
  92. __einfo_error ( EINFO_EIO_STREAM_TYPE )
  93. #define EINFO_EIO_STREAM_TYPE \
  94. __einfo_uniqify ( EINFO_EIO, ( 10 - 0 ), \
  95. "Invalid stream type" )
  96. #define EIO_SLOT \
  97. __einfo_error ( EINFO_EIO_SLOT )
  98. #define EINFO_EIO_SLOT \
  99. __einfo_uniqify ( EINFO_EIO, ( 11 - 0 ), \
  100. "Slot not enabled" )
  101. #define EIO_ENDPOINT \
  102. __einfo_error ( EINFO_EIO_ENDPOINT )
  103. #define EINFO_EIO_ENDPOINT \
  104. __einfo_uniqify ( EINFO_EIO, ( 12 - 0 ), \
  105. "Endpoint not enabled" )
  106. #define EIO_SHORT \
  107. __einfo_error ( EINFO_EIO_SHORT )
  108. #define EINFO_EIO_SHORT \
  109. __einfo_uniqify ( EINFO_EIO, ( 13 - 0 ), \
  110. "Short packet" )
  111. #define EIO_UNDERRUN \
  112. __einfo_error ( EINFO_EIO_UNDERRUN )
  113. #define EINFO_EIO_UNDERRUN \
  114. __einfo_uniqify ( EINFO_EIO, ( 14 - 0 ), \
  115. "Ring underrun" )
  116. #define EIO_OVERRUN \
  117. __einfo_error ( EINFO_EIO_OVERRUN )
  118. #define EINFO_EIO_OVERRUN \
  119. __einfo_uniqify ( EINFO_EIO, ( 15 - 0 ), \
  120. "Ring overrun" )
  121. #define EIO_VF_RING_FULL \
  122. __einfo_error ( EINFO_EIO_VF_RING_FULL )
  123. #define EINFO_EIO_VF_RING_FULL \
  124. __einfo_uniqify ( EINFO_EIO, ( 16 - 0 ), \
  125. "Virtual function event ring full" )
  126. #define EIO_PARAMETER \
  127. __einfo_error ( EINFO_EIO_PARAMETER )
  128. #define EINFO_EIO_PARAMETER \
  129. __einfo_uniqify ( EINFO_EIO, ( 17 - 0 ), \
  130. "Parameter error" )
  131. #define EIO_BANDWIDTH_OVERRUN \
  132. __einfo_error ( EINFO_EIO_BANDWIDTH_OVERRUN )
  133. #define EINFO_EIO_BANDWIDTH_OVERRUN \
  134. __einfo_uniqify ( EINFO_EIO, ( 18 - 0 ), \
  135. "Bandwidth overrun" )
  136. #define EIO_CONTEXT \
  137. __einfo_error ( EINFO_EIO_CONTEXT )
  138. #define EINFO_EIO_CONTEXT \
  139. __einfo_uniqify ( EINFO_EIO, ( 19 - 0 ), \
  140. "Context state error" )
  141. #define EIO_NO_PING \
  142. __einfo_error ( EINFO_EIO_NO_PING )
  143. #define EINFO_EIO_NO_PING \
  144. __einfo_uniqify ( EINFO_EIO, ( 20 - 0 ), \
  145. "No ping response" )
  146. #define EIO_RING_FULL \
  147. __einfo_error ( EINFO_EIO_RING_FULL )
  148. #define EINFO_EIO_RING_FULL \
  149. __einfo_uniqify ( EINFO_EIO, ( 21 - 0 ), \
  150. "Event ring full" )
  151. #define EIO_INCOMPATIBLE \
  152. __einfo_error ( EINFO_EIO_INCOMPATIBLE )
  153. #define EINFO_EIO_INCOMPATIBLE \
  154. __einfo_uniqify ( EINFO_EIO, ( 22 - 0 ), \
  155. "Incompatible device" )
  156. #define EIO_MISSED \
  157. __einfo_error ( EINFO_EIO_MISSED )
  158. #define EINFO_EIO_MISSED \
  159. __einfo_uniqify ( EINFO_EIO, ( 23 - 0 ), \
  160. "Missed service error" )
  161. #define EIO_CMD_STOPPED \
  162. __einfo_error ( EINFO_EIO_CMD_STOPPED )
  163. #define EINFO_EIO_CMD_STOPPED \
  164. __einfo_uniqify ( EINFO_EIO, ( 24 - 0 ), \
  165. "Command ring stopped" )
  166. #define EIO_CMD_ABORTED \
  167. __einfo_error ( EINFO_EIO_CMD_ABORTED )
  168. #define EINFO_EIO_CMD_ABORTED \
  169. __einfo_uniqify ( EINFO_EIO, ( 25 - 0 ), \
  170. "Command aborted" )
  171. #define EIO_STOP \
  172. __einfo_error ( EINFO_EIO_STOP )
  173. #define EINFO_EIO_STOP \
  174. __einfo_uniqify ( EINFO_EIO, ( 26 - 0 ), \
  175. "Stopped" )
  176. #define EIO_STOP_LEN \
  177. __einfo_error ( EINFO_EIO_STOP_LEN )
  178. #define EINFO_EIO_STOP_LEN \
  179. __einfo_uniqify ( EINFO_EIO, ( 27 - 0 ), \
  180. "Stopped - length invalid" )
  181. #define EIO_STOP_SHORT \
  182. __einfo_error ( EINFO_EIO_STOP_SHORT )
  183. #define EINFO_EIO_STOP_SHORT \
  184. __einfo_uniqify ( EINFO_EIO, ( 28 - 0 ), \
  185. "Stopped - short packet" )
  186. #define EIO_LATENCY \
  187. __einfo_error ( EINFO_EIO_LATENCY )
  188. #define EINFO_EIO_LATENCY \
  189. __einfo_uniqify ( EINFO_EIO, ( 29 - 0 ), \
  190. "Maximum exit latency too large" )
  191. #define EIO_ISOCH \
  192. __einfo_error ( EINFO_EIO_ISOCH )
  193. #define EINFO_EIO_ISOCH \
  194. __einfo_uniqify ( EINFO_EIO, ( 31 - 0 ), \
  195. "Isochronous buffer overrun" )
  196. #define EPROTO_LOST \
  197. __einfo_error ( EINFO_EPROTO_LOST )
  198. #define EINFO_EPROTO_LOST \
  199. __einfo_uniqify ( EINFO_EPROTO, ( 32 - 32 ), \
  200. "Event lost" )
  201. #define EPROTO_UNDEFINED \
  202. __einfo_error ( EINFO_EPROTO_UNDEFINED )
  203. #define EINFO_EPROTO_UNDEFINED \
  204. __einfo_uniqify ( EINFO_EPROTO, ( 33 - 32 ), \
  205. "Undefined error" )
  206. #define EPROTO_STREAM_ID \
  207. __einfo_error ( EINFO_EPROTO_STREAM_ID )
  208. #define EINFO_EPROTO_STREAM_ID \
  209. __einfo_uniqify ( EINFO_EPROTO, ( 34 - 32 ), \
  210. "Invalid stream ID" )
  211. #define EPROTO_SECONDARY \
  212. __einfo_error ( EINFO_EPROTO_SECONDARY )
  213. #define EINFO_EPROTO_SECONDARY \
  214. __einfo_uniqify ( EINFO_EPROTO, ( 35 - 32 ), \
  215. "Secondary bandwidth error" )
  216. #define EPROTO_SPLIT \
  217. __einfo_error ( EINFO_EPROTO_SPLIT )
  218. #define EINFO_EPROTO_SPLIT \
  219. __einfo_uniqify ( EINFO_EPROTO, ( 36 - 32 ), \
  220. "Split transaction error" )
  221. #define ECODE(code) \
  222. ( ( (code) < 32 ) ? \
  223. EUNIQ ( EINFO_EIO, ( (code) & 31 ), EIO_DATA, EIO_BABBLE, \
  224. EIO_USB, EIO_TRB, EIO_STALL, EIO_RESOURCE, \
  225. EIO_BANDWIDTH, EIO_NO_SLOTS, EIO_STREAM_TYPE, \
  226. EIO_SLOT, EIO_ENDPOINT, EIO_SHORT, EIO_UNDERRUN, \
  227. EIO_OVERRUN, EIO_VF_RING_FULL, EIO_PARAMETER, \
  228. EIO_BANDWIDTH_OVERRUN, EIO_CONTEXT, EIO_NO_PING, \
  229. EIO_RING_FULL, EIO_INCOMPATIBLE, EIO_MISSED, \
  230. EIO_CMD_STOPPED, EIO_CMD_ABORTED, EIO_STOP, \
  231. EIO_STOP_LEN, EIO_STOP_SHORT, EIO_LATENCY, \
  232. EIO_ISOCH ) : \
  233. ( (code) < 64 ) ? \
  234. EUNIQ ( EINFO_EPROTO, ( (code) & 31 ), EPROTO_LOST, \
  235. EPROTO_UNDEFINED, EPROTO_STREAM_ID, \
  236. EPROTO_SECONDARY, EPROTO_SPLIT ) : \
  237. EFAULT )
  238. /******************************************************************************
  239. *
  240. * Register access
  241. *
  242. ******************************************************************************
  243. */
  244. /**
  245. * Initialise device
  246. *
  247. * @v xhci xHCI device
  248. * @v regs MMIO registers
  249. */
  250. static void xhci_init ( struct xhci_device *xhci, void *regs ) {
  251. uint32_t hcsparams1;
  252. uint32_t hcsparams2;
  253. uint32_t hccparams1;
  254. uint32_t pagesize;
  255. size_t caplength;
  256. size_t rtsoff;
  257. size_t dboff;
  258. /* Locate capability, operational, runtime, and doorbell registers */
  259. xhci->cap = regs;
  260. caplength = readb ( xhci->cap + XHCI_CAP_CAPLENGTH );
  261. rtsoff = readl ( xhci->cap + XHCI_CAP_RTSOFF );
  262. dboff = readl ( xhci->cap + XHCI_CAP_DBOFF );
  263. xhci->op = ( xhci->cap + caplength );
  264. xhci->run = ( xhci->cap + rtsoff );
  265. xhci->db = ( xhci->cap + dboff );
  266. DBGC2 ( xhci, "XHCI %p cap %08lx op %08lx run %08lx db %08lx\n",
  267. xhci, virt_to_phys ( xhci->cap ), virt_to_phys ( xhci->op ),
  268. virt_to_phys ( xhci->run ), virt_to_phys ( xhci->db ) );
  269. /* Read structural parameters 1 */
  270. hcsparams1 = readl ( xhci->cap + XHCI_CAP_HCSPARAMS1 );
  271. xhci->slots = XHCI_HCSPARAMS1_SLOTS ( hcsparams1 );
  272. xhci->intrs = XHCI_HCSPARAMS1_INTRS ( hcsparams1 );
  273. xhci->ports = XHCI_HCSPARAMS1_PORTS ( hcsparams1 );
  274. DBGC ( xhci, "XHCI %p has %d slots %d intrs %d ports\n",
  275. xhci, xhci->slots, xhci->intrs, xhci->ports );
  276. /* Read structural parameters 2 */
  277. hcsparams2 = readl ( xhci->cap + XHCI_CAP_HCSPARAMS2 );
  278. xhci->scratchpads = XHCI_HCSPARAMS2_SCRATCHPADS ( hcsparams2 );
  279. DBGC2 ( xhci, "XHCI %p needs %d scratchpads\n",
  280. xhci, xhci->scratchpads );
  281. /* Read capability parameters 1 */
  282. hccparams1 = readl ( xhci->cap + XHCI_CAP_HCCPARAMS1 );
  283. xhci->addr64 = XHCI_HCCPARAMS1_ADDR64 ( hccparams1 );
  284. xhci->csz_shift = XHCI_HCCPARAMS1_CSZ_SHIFT ( hccparams1 );
  285. xhci->xecp = XHCI_HCCPARAMS1_XECP ( hccparams1 );
  286. /* Read page size */
  287. pagesize = readl ( xhci->op + XHCI_OP_PAGESIZE );
  288. xhci->pagesize = XHCI_PAGESIZE ( pagesize );
  289. assert ( xhci->pagesize != 0 );
  290. assert ( ( ( xhci->pagesize ) & ( xhci->pagesize - 1 ) ) == 0 );
  291. DBGC2 ( xhci, "XHCI %p page size %zd bytes\n",
  292. xhci, xhci->pagesize );
  293. }
  294. /**
  295. * Find extended capability
  296. *
  297. * @v xhci xHCI device
  298. * @v id Capability ID
  299. * @v offset Offset to previous extended capability instance, or zero
  300. * @ret offset Offset to extended capability, or zero if not found
  301. */
  302. static unsigned int xhci_extended_capability ( struct xhci_device *xhci,
  303. unsigned int id,
  304. unsigned int offset ) {
  305. uint32_t xecp;
  306. unsigned int next;
  307. /* Locate the extended capability */
  308. while ( 1 ) {
  309. /* Locate first or next capability as applicable */
  310. if ( offset ) {
  311. xecp = readl ( xhci->cap + offset );
  312. next = XHCI_XECP_NEXT ( xecp );
  313. } else {
  314. next = xhci->xecp;
  315. }
  316. if ( ! next )
  317. return 0;
  318. offset += next;
  319. /* Check if this is the requested capability */
  320. xecp = readl ( xhci->cap + offset );
  321. if ( XHCI_XECP_ID ( xecp ) == id )
  322. return offset;
  323. }
  324. }
  325. /**
  326. * Write potentially 64-bit register
  327. *
  328. * @v xhci xHCI device
  329. * @v value Value
  330. * @v reg Register address
  331. * @ret rc Return status code
  332. */
  333. static inline __attribute__ (( always_inline )) int
  334. xhci_writeq ( struct xhci_device *xhci, physaddr_t value, void *reg ) {
  335. /* If this is a 32-bit build, then this can never fail
  336. * (allowing the compiler to optimise out the error path).
  337. */
  338. if ( sizeof ( value ) <= sizeof ( uint32_t ) ) {
  339. writel ( value, reg );
  340. writel ( 0, ( reg + sizeof ( uint32_t ) ) );
  341. return 0;
  342. }
  343. /* If the device does not support 64-bit addresses and this
  344. * address is outside the 32-bit address space, then fail.
  345. */
  346. if ( ( value & ~0xffffffffULL ) && ! xhci->addr64 ) {
  347. DBGC ( xhci, "XHCI %p cannot access address %lx\n",
  348. xhci, value );
  349. return -ENOTSUP;
  350. }
  351. /* If this is a 64-bit build, then writeq() is available */
  352. writeq ( value, reg );
  353. return 0;
  354. }
  355. /**
  356. * Calculate buffer alignment
  357. *
  358. * @v len Length
  359. * @ret align Buffer alignment
  360. *
  361. * Determine alignment required for a buffer which must be aligned to
  362. * at least XHCI_MIN_ALIGN and which must not cross a page boundary.
  363. */
  364. static inline size_t xhci_align ( size_t len ) {
  365. size_t align;
  366. /* Align to own length (rounded up to a power of two) */
  367. align = ( 1 << fls ( len - 1 ) );
  368. /* Round up to XHCI_MIN_ALIGN if needed */
  369. if ( align < XHCI_MIN_ALIGN )
  370. align = XHCI_MIN_ALIGN;
  371. return align;
  372. }
  373. /**
  374. * Calculate device context offset
  375. *
  376. * @v xhci xHCI device
  377. * @v ctx Context index
  378. */
  379. static inline size_t xhci_device_context_offset ( struct xhci_device *xhci,
  380. unsigned int ctx ) {
  381. return ( XHCI_DCI ( ctx ) << xhci->csz_shift );
  382. }
  383. /**
  384. * Calculate input context offset
  385. *
  386. * @v xhci xHCI device
  387. * @v ctx Context index
  388. */
  389. static inline size_t xhci_input_context_offset ( struct xhci_device *xhci,
  390. unsigned int ctx ) {
  391. return ( XHCI_ICI ( ctx ) << xhci->csz_shift );
  392. }
  393. /******************************************************************************
  394. *
  395. * Diagnostics
  396. *
  397. ******************************************************************************
  398. */
  399. /**
  400. * Dump host controller registers
  401. *
  402. * @v xhci xHCI device
  403. */
  404. static inline void xhci_dump ( struct xhci_device *xhci ) {
  405. uint32_t usbcmd;
  406. uint32_t usbsts;
  407. uint32_t pagesize;
  408. uint32_t dnctrl;
  409. uint32_t config;
  410. /* Do nothing unless debugging is enabled */
  411. if ( ! DBG_LOG )
  412. return;
  413. /* Dump USBCMD */
  414. usbcmd = readl ( xhci->op + XHCI_OP_USBCMD );
  415. DBGC ( xhci, "XHCI %p USBCMD %08x%s%s\n", xhci, usbcmd,
  416. ( ( usbcmd & XHCI_USBCMD_RUN ) ? " run" : "" ),
  417. ( ( usbcmd & XHCI_USBCMD_HCRST ) ? " hcrst" : "" ) );
  418. /* Dump USBSTS */
  419. usbsts = readl ( xhci->op + XHCI_OP_USBSTS );
  420. DBGC ( xhci, "XHCI %p USBSTS %08x%s\n", xhci, usbsts,
  421. ( ( usbsts & XHCI_USBSTS_HCH ) ? " hch" : "" ) );
  422. /* Dump PAGESIZE */
  423. pagesize = readl ( xhci->op + XHCI_OP_PAGESIZE );
  424. DBGC ( xhci, "XHCI %p PAGESIZE %08x\n", xhci, pagesize );
  425. /* Dump DNCTRL */
  426. dnctrl = readl ( xhci->op + XHCI_OP_DNCTRL );
  427. DBGC ( xhci, "XHCI %p DNCTRL %08x\n", xhci, dnctrl );
  428. /* Dump CONFIG */
  429. config = readl ( xhci->op + XHCI_OP_CONFIG );
  430. DBGC ( xhci, "XHCI %p CONFIG %08x\n", xhci, config );
  431. }
  432. /**
  433. * Dump port registers
  434. *
  435. * @v xhci xHCI device
  436. * @v port Port number
  437. */
  438. static inline void xhci_dump_port ( struct xhci_device *xhci,
  439. unsigned int port ) {
  440. uint32_t portsc;
  441. uint32_t portpmsc;
  442. uint32_t portli;
  443. uint32_t porthlpmc;
  444. /* Do nothing unless debugging is enabled */
  445. if ( ! DBG_LOG )
  446. return;
  447. /* Dump PORTSC */
  448. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port ) );
  449. DBGC ( xhci, "XHCI %p port %d PORTSC %08x%s%s%s%s psiv=%d\n",
  450. xhci, port, portsc,
  451. ( ( portsc & XHCI_PORTSC_CCS ) ? " ccs" : "" ),
  452. ( ( portsc & XHCI_PORTSC_PED ) ? " ped" : "" ),
  453. ( ( portsc & XHCI_PORTSC_PR ) ? " pr" : "" ),
  454. ( ( portsc & XHCI_PORTSC_PP ) ? " pp" : "" ),
  455. XHCI_PORTSC_PSIV ( portsc ) );
  456. /* Dump PORTPMSC */
  457. portpmsc = readl ( xhci->op + XHCI_OP_PORTPMSC ( port ) );
  458. DBGC ( xhci, "XHCI %p port %d PORTPMSC %08x\n", xhci, port, portpmsc );
  459. /* Dump PORTLI */
  460. portli = readl ( xhci->op + XHCI_OP_PORTLI ( port ) );
  461. DBGC ( xhci, "XHCI %p port %d PORTLI %08x\n", xhci, port, portli );
  462. /* Dump PORTHLPMC */
  463. porthlpmc = readl ( xhci->op + XHCI_OP_PORTHLPMC ( port ) );
  464. DBGC ( xhci, "XHCI %p port %d PORTHLPMC %08x\n",
  465. xhci, port, porthlpmc );
  466. }
  467. /******************************************************************************
  468. *
  469. * USB legacy support
  470. *
  471. ******************************************************************************
  472. */
  473. /**
  474. * Initialise USB legacy support
  475. *
  476. * @v xhci xHCI device
  477. */
  478. static void xhci_legacy_init ( struct xhci_device *xhci ) {
  479. unsigned int legacy;
  480. uint8_t bios;
  481. /* Locate USB legacy support capability (if present) */
  482. legacy = xhci_extended_capability ( xhci, XHCI_XECP_ID_LEGACY, 0 );
  483. if ( ! legacy ) {
  484. /* Not an error; capability may not be present */
  485. DBGC ( xhci, "XHCI %p has no USB legacy support capability\n",
  486. xhci );
  487. return;
  488. }
  489. /* Check if legacy USB support is enabled */
  490. bios = readb ( xhci->cap + legacy + XHCI_USBLEGSUP_BIOS );
  491. if ( ! ( bios & XHCI_USBLEGSUP_BIOS_OWNED ) ) {
  492. /* Not an error; already owned by OS */
  493. DBGC ( xhci, "XHCI %p USB legacy support already disabled\n",
  494. xhci );
  495. return;
  496. }
  497. /* Record presence of USB legacy support capability */
  498. xhci->legacy = legacy;
  499. }
  500. /**
  501. * Claim ownership from BIOS
  502. *
  503. * @v xhci xHCI device
  504. * @ret rc Return status code
  505. */
  506. static int xhci_legacy_claim ( struct xhci_device *xhci ) {
  507. uint32_t ctlsts;
  508. uint8_t bios;
  509. unsigned int i;
  510. /* Do nothing unless legacy support capability is present */
  511. if ( ! xhci->legacy )
  512. return 0;
  513. /* Claim ownership */
  514. writeb ( XHCI_USBLEGSUP_OS_OWNED,
  515. xhci->cap + xhci->legacy + XHCI_USBLEGSUP_OS );
  516. /* Wait for BIOS to release ownership */
  517. for ( i = 0 ; i < XHCI_USBLEGSUP_MAX_WAIT_MS ; i++ ) {
  518. /* Check if BIOS has released ownership */
  519. bios = readb ( xhci->cap + xhci->legacy + XHCI_USBLEGSUP_BIOS );
  520. if ( ! ( bios & XHCI_USBLEGSUP_BIOS_OWNED ) ) {
  521. DBGC ( xhci, "XHCI %p claimed ownership from BIOS\n",
  522. xhci );
  523. ctlsts = readl ( xhci->cap + xhci->legacy +
  524. XHCI_USBLEGSUP_CTLSTS );
  525. if ( ctlsts ) {
  526. DBGC ( xhci, "XHCI %p warning: BIOS retained "
  527. "SMIs: %08x\n", xhci, ctlsts );
  528. }
  529. return 0;
  530. }
  531. /* Delay */
  532. mdelay ( 1 );
  533. }
  534. DBGC ( xhci, "XHCI %p timed out waiting for BIOS to release "
  535. "ownership\n", xhci );
  536. return -ETIMEDOUT;
  537. }
  538. /**
  539. * Release ownership back to BIOS
  540. *
  541. * @v xhci xHCI device
  542. */
  543. static void xhci_legacy_release ( struct xhci_device *xhci ) {
  544. /* Do nothing unless legacy support capability is present */
  545. if ( ! xhci->legacy )
  546. return;
  547. /* Release ownership */
  548. writeb ( 0, xhci->cap + xhci->legacy + XHCI_USBLEGSUP_OS );
  549. DBGC ( xhci, "XHCI %p released ownership to BIOS\n", xhci );
  550. }
  551. /******************************************************************************
  552. *
  553. * Supported protocols
  554. *
  555. ******************************************************************************
  556. */
  557. /**
  558. * Transcribe port speed (for debugging)
  559. *
  560. * @v psi Protocol speed ID
  561. * @ret speed Transcribed speed
  562. */
  563. static inline const char * xhci_speed_name ( uint32_t psi ) {
  564. static const char *exponents[4] = { "", "k", "M", "G" };
  565. static char buf[ 10 /* "xxxxxXbps" + NUL */ ];
  566. unsigned int mantissa;
  567. unsigned int exponent;
  568. /* Extract mantissa and exponent */
  569. mantissa = XHCI_SUPPORTED_PSI_MANTISSA ( psi );
  570. exponent = XHCI_SUPPORTED_PSI_EXPONENT ( psi );
  571. /* Transcribe speed */
  572. snprintf ( buf, sizeof ( buf ), "%d%sbps",
  573. mantissa, exponents[exponent] );
  574. return buf;
  575. }
  576. /**
  577. * Find supported protocol extended capability for a port
  578. *
  579. * @v xhci xHCI device
  580. * @v port Port number
  581. * @ret supported Offset to extended capability, or zero if not found
  582. */
  583. static unsigned int xhci_supported_protocol ( struct xhci_device *xhci,
  584. unsigned int port ) {
  585. unsigned int supported = 0;
  586. unsigned int offset;
  587. unsigned int count;
  588. uint32_t ports;
  589. /* Iterate over all supported protocol structures */
  590. while ( ( supported = xhci_extended_capability ( xhci,
  591. XHCI_XECP_ID_SUPPORTED,
  592. supported ) ) ) {
  593. /* Determine port range */
  594. ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS );
  595. offset = XHCI_SUPPORTED_PORTS_OFFSET ( ports );
  596. count = XHCI_SUPPORTED_PORTS_COUNT ( ports );
  597. /* Check if port lies within this range */
  598. if ( ( port - offset ) < count )
  599. return supported;
  600. }
  601. DBGC ( xhci, "XHCI %p port %d has no supported protocol\n",
  602. xhci, port );
  603. return 0;
  604. }
  605. /**
  606. * Find port protocol
  607. *
  608. * @v xhci xHCI device
  609. * @v port Port number
  610. * @ret protocol USB protocol, or zero if not found
  611. */
  612. static unsigned int xhci_port_protocol ( struct xhci_device *xhci,
  613. unsigned int port ) {
  614. unsigned int supported = xhci_supported_protocol ( xhci, port );
  615. union {
  616. uint32_t raw;
  617. char text[5];
  618. } name;
  619. unsigned int protocol;
  620. unsigned int type;
  621. unsigned int psic;
  622. unsigned int psiv;
  623. unsigned int i;
  624. uint32_t revision;
  625. uint32_t ports;
  626. uint32_t slot;
  627. uint32_t psi;
  628. /* Fail if there is no supported protocol */
  629. if ( ! supported )
  630. return 0;
  631. /* Determine protocol version */
  632. revision = readl ( xhci->cap + supported + XHCI_SUPPORTED_REVISION );
  633. protocol = XHCI_SUPPORTED_REVISION_VER ( revision );
  634. /* Describe port protocol */
  635. if ( DBG_EXTRA ) {
  636. name.raw = cpu_to_le32 ( readl ( xhci->cap + supported +
  637. XHCI_SUPPORTED_NAME ) );
  638. name.text[4] = '\0';
  639. slot = readl ( xhci->cap + supported + XHCI_SUPPORTED_SLOT );
  640. type = XHCI_SUPPORTED_SLOT_TYPE ( slot );
  641. DBGC2 ( xhci, "XHCI %p port %d %sv%04x type %d",
  642. xhci, port, name.text, protocol, type );
  643. ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS );
  644. psic = XHCI_SUPPORTED_PORTS_PSIC ( ports );
  645. if ( psic ) {
  646. DBGC2 ( xhci, " speeds" );
  647. for ( i = 0 ; i < psic ; i++ ) {
  648. psi = readl ( xhci->cap + supported +
  649. XHCI_SUPPORTED_PSI ( i ) );
  650. psiv = XHCI_SUPPORTED_PSI_VALUE ( psi );
  651. DBGC2 ( xhci, " %d:%s", psiv,
  652. xhci_speed_name ( psi ) );
  653. }
  654. }
  655. DBGC2 ( xhci, "\n" );
  656. }
  657. return protocol;
  658. }
  659. /**
  660. * Find port slot type
  661. *
  662. * @v xhci xHCI device
  663. * @v port Port number
  664. * @ret type Slot type, or negative error
  665. */
  666. static int xhci_port_slot_type ( struct xhci_device *xhci, unsigned int port ) {
  667. unsigned int supported = xhci_supported_protocol ( xhci, port );
  668. unsigned int type;
  669. uint32_t slot;
  670. /* Fail if there is no supported protocol */
  671. if ( ! supported )
  672. return -ENOTSUP;
  673. /* Get slot type */
  674. slot = readl ( xhci->cap + supported + XHCI_SUPPORTED_SLOT );
  675. type = XHCI_SUPPORTED_SLOT_TYPE ( slot );
  676. return type;
  677. }
  678. /**
  679. * Find port speed
  680. *
  681. * @v xhci xHCI device
  682. * @v port Port number
  683. * @v psiv Protocol speed ID value
  684. * @ret speed Port speed, or negative error
  685. */
  686. static int xhci_port_speed ( struct xhci_device *xhci, unsigned int port,
  687. unsigned int psiv ) {
  688. unsigned int supported = xhci_supported_protocol ( xhci, port );
  689. unsigned int psic;
  690. unsigned int mantissa;
  691. unsigned int exponent;
  692. unsigned int speed;
  693. unsigned int i;
  694. uint32_t ports;
  695. uint32_t psi;
  696. /* Fail if there is no supported protocol */
  697. if ( ! supported )
  698. return -ENOTSUP;
  699. /* Get protocol speed ID count */
  700. ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS );
  701. psic = XHCI_SUPPORTED_PORTS_PSIC ( ports );
  702. /* Use the default mappings if applicable */
  703. if ( ! psic ) {
  704. switch ( psiv ) {
  705. case XHCI_SPEED_LOW : return USB_SPEED_LOW;
  706. case XHCI_SPEED_FULL : return USB_SPEED_FULL;
  707. case XHCI_SPEED_HIGH : return USB_SPEED_HIGH;
  708. case XHCI_SPEED_SUPER : return USB_SPEED_SUPER;
  709. default:
  710. DBGC ( xhci, "XHCI %p port %d non-standard PSI value "
  711. "%d\n", xhci, port, psiv );
  712. return -ENOTSUP;
  713. }
  714. }
  715. /* Iterate over PSI dwords looking for a match */
  716. for ( i = 0 ; i < psic ; i++ ) {
  717. psi = readl ( xhci->cap + supported + XHCI_SUPPORTED_PSI ( i ));
  718. if ( psiv == XHCI_SUPPORTED_PSI_VALUE ( psi ) ) {
  719. mantissa = XHCI_SUPPORTED_PSI_MANTISSA ( psi );
  720. exponent = XHCI_SUPPORTED_PSI_EXPONENT ( psi );
  721. speed = USB_SPEED ( mantissa, exponent );
  722. return speed;
  723. }
  724. }
  725. DBGC ( xhci, "XHCI %p port %d spurious PSI value %d\n",
  726. xhci, port, psiv );
  727. return -ENOENT;
  728. }
  729. /**
  730. * Find protocol speed ID value
  731. *
  732. * @v xhci xHCI device
  733. * @v port Port number
  734. * @v speed USB speed
  735. * @ret psiv Protocol speed ID value, or negative error
  736. */
  737. static int xhci_port_psiv ( struct xhci_device *xhci, unsigned int port,
  738. unsigned int speed ) {
  739. unsigned int supported = xhci_supported_protocol ( xhci, port );
  740. unsigned int psic;
  741. unsigned int mantissa;
  742. unsigned int exponent;
  743. unsigned int psiv;
  744. unsigned int i;
  745. uint32_t ports;
  746. uint32_t psi;
  747. /* Fail if there is no supported protocol */
  748. if ( ! supported )
  749. return -ENOTSUP;
  750. /* Get protocol speed ID count */
  751. ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS );
  752. psic = XHCI_SUPPORTED_PORTS_PSIC ( ports );
  753. /* Use the default mappings if applicable */
  754. if ( ! psic ) {
  755. switch ( speed ) {
  756. case USB_SPEED_LOW : return XHCI_SPEED_LOW;
  757. case USB_SPEED_FULL : return XHCI_SPEED_FULL;
  758. case USB_SPEED_HIGH : return XHCI_SPEED_HIGH;
  759. case USB_SPEED_SUPER : return XHCI_SPEED_SUPER;
  760. default:
  761. DBGC ( xhci, "XHCI %p port %d non-standad speed %d\n",
  762. xhci, port, speed );
  763. return -ENOTSUP;
  764. }
  765. }
  766. /* Iterate over PSI dwords looking for a match */
  767. for ( i = 0 ; i < psic ; i++ ) {
  768. psi = readl ( xhci->cap + supported + XHCI_SUPPORTED_PSI ( i ));
  769. mantissa = XHCI_SUPPORTED_PSI_MANTISSA ( psi );
  770. exponent = XHCI_SUPPORTED_PSI_EXPONENT ( psi );
  771. if ( speed == USB_SPEED ( mantissa, exponent ) ) {
  772. psiv = XHCI_SUPPORTED_PSI_VALUE ( psi );
  773. return psiv;
  774. }
  775. }
  776. DBGC ( xhci, "XHCI %p port %d unrepresentable speed %#x\n",
  777. xhci, port, speed );
  778. return -ENOENT;
  779. }
  780. /******************************************************************************
  781. *
  782. * Device context base address array
  783. *
  784. ******************************************************************************
  785. */
  786. /**
  787. * Allocate device context base address array
  788. *
  789. * @v xhci xHCI device
  790. * @ret rc Return status code
  791. */
  792. static int xhci_dcbaa_alloc ( struct xhci_device *xhci ) {
  793. size_t len;
  794. physaddr_t dcbaap;
  795. int rc;
  796. /* Allocate and initialise structure. Must be at least
  797. * 64-byte aligned and must not cross a page boundary, so
  798. * align on its own size (rounded up to a power of two and
  799. * with a minimum of 64 bytes).
  800. */
  801. len = ( ( xhci->slots + 1 ) * sizeof ( xhci->dcbaa[0] ) );
  802. xhci->dcbaa = malloc_dma ( len, xhci_align ( len ) );
  803. if ( ! xhci->dcbaa ) {
  804. DBGC ( xhci, "XHCI %p could not allocate DCBAA\n", xhci );
  805. rc = -ENOMEM;
  806. goto err_alloc;
  807. }
  808. memset ( xhci->dcbaa, 0, len );
  809. /* Program DCBAA pointer */
  810. dcbaap = virt_to_phys ( xhci->dcbaa );
  811. if ( ( rc = xhci_writeq ( xhci, dcbaap,
  812. xhci->op + XHCI_OP_DCBAAP ) ) != 0 )
  813. goto err_writeq;
  814. DBGC2 ( xhci, "XHCI %p DCBAA at [%08lx,%08lx)\n",
  815. xhci, dcbaap, ( dcbaap + len ) );
  816. return 0;
  817. err_writeq:
  818. free_dma ( xhci->dcbaa, len );
  819. err_alloc:
  820. return rc;
  821. }
  822. /**
  823. * Free device context base address array
  824. *
  825. * @v xhci xHCI device
  826. */
  827. static void xhci_dcbaa_free ( struct xhci_device *xhci ) {
  828. size_t len;
  829. unsigned int i;
  830. /* Sanity check */
  831. for ( i = 0 ; i <= xhci->slots ; i++ )
  832. assert ( xhci->dcbaa[i] == 0 );
  833. /* Clear DCBAA pointer */
  834. xhci_writeq ( xhci, 0, xhci->op + XHCI_OP_DCBAAP );
  835. /* Free DCBAA */
  836. len = ( ( xhci->slots + 1 ) * sizeof ( xhci->dcbaa[0] ) );
  837. free_dma ( xhci->dcbaa, len );
  838. }
  839. /******************************************************************************
  840. *
  841. * Scratchpad buffers
  842. *
  843. ******************************************************************************
  844. */
  845. /**
  846. * Allocate scratchpad buffers
  847. *
  848. * @v xhci xHCI device
  849. * @ret rc Return status code
  850. */
  851. static int xhci_scratchpad_alloc ( struct xhci_device *xhci ) {
  852. size_t array_len;
  853. size_t len;
  854. physaddr_t phys;
  855. unsigned int i;
  856. int rc;
  857. /* Do nothing if no scratchpad buffers are used */
  858. if ( ! xhci->scratchpads )
  859. return 0;
  860. /* Allocate scratchpads */
  861. len = ( xhci->scratchpads * xhci->pagesize );
  862. xhci->scratchpad = umalloc ( len );
  863. if ( ! xhci->scratchpad ) {
  864. DBGC ( xhci, "XHCI %p could not allocate scratchpad buffers\n",
  865. xhci );
  866. rc = -ENOMEM;
  867. goto err_alloc;
  868. }
  869. memset_user ( xhci->scratchpad, 0, 0, len );
  870. /* Allocate scratchpad array */
  871. array_len = ( xhci->scratchpads * sizeof ( xhci->scratchpad_array[0] ));
  872. xhci->scratchpad_array =
  873. malloc_dma ( array_len, xhci_align ( array_len ) );
  874. if ( ! xhci->scratchpad_array ) {
  875. DBGC ( xhci, "XHCI %p could not allocate scratchpad buffer "
  876. "array\n", xhci );
  877. rc = -ENOMEM;
  878. goto err_alloc_array;
  879. }
  880. /* Populate scratchpad array */
  881. for ( i = 0 ; i < xhci->scratchpads ; i++ ) {
  882. phys = user_to_phys ( xhci->scratchpad, ( i * xhci->pagesize ));
  883. xhci->scratchpad_array[i] = phys;
  884. }
  885. /* Set scratchpad array pointer */
  886. assert ( xhci->dcbaa != NULL );
  887. xhci->dcbaa[0] = cpu_to_le64 ( virt_to_phys ( xhci->scratchpad_array ));
  888. DBGC2 ( xhci, "XHCI %p scratchpad [%08lx,%08lx) array [%08lx,%08lx)\n",
  889. xhci, user_to_phys ( xhci->scratchpad, 0 ),
  890. user_to_phys ( xhci->scratchpad, len ),
  891. virt_to_phys ( xhci->scratchpad_array ),
  892. ( virt_to_phys ( xhci->scratchpad_array ) + array_len ) );
  893. return 0;
  894. free_dma ( xhci->scratchpad_array, array_len );
  895. err_alloc_array:
  896. ufree ( xhci->scratchpad );
  897. err_alloc:
  898. return rc;
  899. }
  900. /**
  901. * Free scratchpad buffers
  902. *
  903. * @v xhci xHCI device
  904. */
  905. static void xhci_scratchpad_free ( struct xhci_device *xhci ) {
  906. size_t array_len;
  907. /* Do nothing if no scratchpad buffers are used */
  908. if ( ! xhci->scratchpads )
  909. return;
  910. /* Clear scratchpad array pointer */
  911. assert ( xhci->dcbaa != NULL );
  912. xhci->dcbaa[0] = 0;
  913. /* Free scratchpad array */
  914. array_len = ( xhci->scratchpads * sizeof ( xhci->scratchpad_array[0] ));
  915. free_dma ( xhci->scratchpad_array, array_len );
  916. /* Free scratchpads */
  917. ufree ( xhci->scratchpad );
  918. }
  919. /******************************************************************************
  920. *
  921. * Run / stop / reset
  922. *
  923. ******************************************************************************
  924. */
  925. /**
  926. * Start xHCI device
  927. *
  928. * @v xhci xHCI device
  929. */
  930. static void xhci_run ( struct xhci_device *xhci ) {
  931. uint32_t config;
  932. uint32_t usbcmd;
  933. /* Configure number of device slots */
  934. config = readl ( xhci->op + XHCI_OP_CONFIG );
  935. config &= ~XHCI_CONFIG_MAX_SLOTS_EN_MASK;
  936. config |= XHCI_CONFIG_MAX_SLOTS_EN ( xhci->slots );
  937. writel ( config, xhci->op + XHCI_OP_CONFIG );
  938. /* Set run/stop bit */
  939. usbcmd = readl ( xhci->op + XHCI_OP_USBCMD );
  940. usbcmd |= XHCI_USBCMD_RUN;
  941. writel ( usbcmd, xhci->op + XHCI_OP_USBCMD );
  942. }
  943. /**
  944. * Stop xHCI device
  945. *
  946. * @v xhci xHCI device
  947. * @ret rc Return status code
  948. */
  949. static int xhci_stop ( struct xhci_device *xhci ) {
  950. uint32_t usbcmd;
  951. uint32_t usbsts;
  952. unsigned int i;
  953. /* Clear run/stop bit */
  954. usbcmd = readl ( xhci->op + XHCI_OP_USBCMD );
  955. usbcmd &= ~XHCI_USBCMD_RUN;
  956. writel ( usbcmd, xhci->op + XHCI_OP_USBCMD );
  957. /* Wait for device to stop */
  958. for ( i = 0 ; i < XHCI_STOP_MAX_WAIT_MS ; i++ ) {
  959. /* Check if device is stopped */
  960. usbsts = readl ( xhci->op + XHCI_OP_USBSTS );
  961. if ( usbsts & XHCI_USBSTS_HCH )
  962. return 0;
  963. /* Delay */
  964. mdelay ( 1 );
  965. }
  966. DBGC ( xhci, "XHCI %p timed out waiting for stop\n", xhci );
  967. return -ETIMEDOUT;
  968. }
  969. /**
  970. * Reset xHCI device
  971. *
  972. * @v xhci xHCI device
  973. * @ret rc Return status code
  974. */
  975. static int xhci_reset ( struct xhci_device *xhci ) {
  976. uint32_t usbcmd;
  977. unsigned int i;
  978. int rc;
  979. /* The xHCI specification states that resetting a running
  980. * device may result in undefined behaviour, so try stopping
  981. * it first.
  982. */
  983. if ( ( rc = xhci_stop ( xhci ) ) != 0 ) {
  984. /* Ignore errors and attempt to reset the device anyway */
  985. }
  986. /* Reset device */
  987. writel ( XHCI_USBCMD_HCRST, xhci->op + XHCI_OP_USBCMD );
  988. /* Wait for reset to complete */
  989. for ( i = 0 ; i < XHCI_RESET_MAX_WAIT_MS ; i++ ) {
  990. /* Check if reset is complete */
  991. usbcmd = readl ( xhci->op + XHCI_OP_USBCMD );
  992. if ( ! ( usbcmd & XHCI_USBCMD_HCRST ) )
  993. return 0;
  994. /* Delay */
  995. mdelay ( 1 );
  996. }
  997. DBGC ( xhci, "XHCI %p timed out waiting for reset\n", xhci );
  998. return -ETIMEDOUT;
  999. }
  1000. /******************************************************************************
  1001. *
  1002. * Transfer request blocks
  1003. *
  1004. ******************************************************************************
  1005. */
  1006. /**
  1007. * Allocate transfer request block ring
  1008. *
  1009. * @v xhci xHCI device
  1010. * @v ring TRB ring
  1011. * @v shift Ring size (log2)
  1012. * @v slot Device slot
  1013. * @v target Doorbell target
  1014. * @v stream Doorbell stream ID
  1015. * @ret rc Return status code
  1016. */
  1017. static int xhci_ring_alloc ( struct xhci_device *xhci,
  1018. struct xhci_trb_ring *ring,
  1019. unsigned int shift, unsigned int slot,
  1020. unsigned int target, unsigned int stream ) {
  1021. struct xhci_trb_link *link;
  1022. unsigned int count;
  1023. int rc;
  1024. /* Sanity check */
  1025. assert ( shift > 0 );
  1026. /* Initialise structure */
  1027. memset ( ring, 0, sizeof ( *ring ) );
  1028. ring->shift = shift;
  1029. count = ( 1U << shift );
  1030. ring->mask = ( count - 1 );
  1031. ring->len = ( ( count + 1 /* Link TRB */ ) * sizeof ( ring->trb[0] ) );
  1032. ring->db = ( xhci->db + ( slot * sizeof ( ring->dbval ) ) );
  1033. ring->dbval = XHCI_DBVAL ( target, stream );
  1034. /* Allocate I/O buffers */
  1035. ring->iobuf = zalloc ( count * sizeof ( ring->iobuf[0] ) );
  1036. if ( ! ring->iobuf ) {
  1037. rc = -ENOMEM;
  1038. goto err_alloc_iobuf;
  1039. }
  1040. /* Allocate TRBs */
  1041. ring->trb = malloc_dma ( ring->len, xhci_align ( ring->len ) );
  1042. if ( ! ring->trb ) {
  1043. rc = -ENOMEM;
  1044. goto err_alloc_trb;
  1045. }
  1046. memset ( ring->trb, 0, ring->len );
  1047. /* Initialise Link TRB */
  1048. link = &ring->trb[count].link;
  1049. link->next = cpu_to_le64 ( virt_to_phys ( ring->trb ) );
  1050. link->flags = XHCI_TRB_TC;
  1051. link->type = XHCI_TRB_LINK;
  1052. ring->link = link;
  1053. return 0;
  1054. free_dma ( ring->trb, ring->len );
  1055. err_alloc_trb:
  1056. free ( ring->iobuf );
  1057. err_alloc_iobuf:
  1058. return rc;
  1059. }
  1060. /**
  1061. * Reset transfer request block ring
  1062. *
  1063. * @v ring TRB ring
  1064. */
  1065. static void xhci_ring_reset ( struct xhci_trb_ring *ring ) {
  1066. unsigned int count = ( 1U << ring->shift );
  1067. /* Reset producer and consumer counters */
  1068. ring->prod = 0;
  1069. ring->cons = 0;
  1070. /* Reset TRBs (except Link TRB) */
  1071. memset ( ring->trb, 0, ( count * sizeof ( ring->trb[0] ) ) );
  1072. }
  1073. /**
  1074. * Free transfer request block ring
  1075. *
  1076. * @v ring TRB ring
  1077. */
  1078. static void xhci_ring_free ( struct xhci_trb_ring *ring ) {
  1079. unsigned int count = ( 1U << ring->shift );
  1080. unsigned int i;
  1081. /* Sanity checks */
  1082. assert ( ring->cons == ring->prod );
  1083. for ( i = 0 ; i < count ; i++ )
  1084. assert ( ring->iobuf[i] == NULL );
  1085. /* Free TRBs */
  1086. free_dma ( ring->trb, ring->len );
  1087. /* Free I/O buffers */
  1088. free ( ring->iobuf );
  1089. }
  1090. /**
  1091. * Enqueue a transfer request block
  1092. *
  1093. * @v ring TRB ring
  1094. * @v iobuf I/O buffer (if any)
  1095. * @v trb Transfer request block (with empty Cycle flag)
  1096. * @ret rc Return status code
  1097. *
  1098. * This operation does not implicitly ring the doorbell register.
  1099. */
  1100. static int xhci_enqueue ( struct xhci_trb_ring *ring, struct io_buffer *iobuf,
  1101. const union xhci_trb *trb ) {
  1102. union xhci_trb *dest;
  1103. unsigned int prod;
  1104. unsigned int mask;
  1105. unsigned int index;
  1106. unsigned int cycle;
  1107. /* Sanity check */
  1108. assert ( ! ( trb->common.flags & XHCI_TRB_C ) );
  1109. /* Fail if ring is full */
  1110. if ( ! xhci_ring_remaining ( ring ) )
  1111. return -ENOBUFS;
  1112. /* Update producer counter (and link TRB, if applicable) */
  1113. prod = ring->prod++;
  1114. mask = ring->mask;
  1115. cycle = ( ( ~( prod >> ring->shift ) ) & XHCI_TRB_C );
  1116. index = ( prod & mask );
  1117. if ( index == 0 )
  1118. ring->link->flags = ( XHCI_TRB_TC | ( cycle ^ XHCI_TRB_C ) );
  1119. /* Record I/O buffer */
  1120. ring->iobuf[index] = iobuf;
  1121. /* Enqueue TRB */
  1122. dest = &ring->trb[index];
  1123. dest->template.parameter = trb->template.parameter;
  1124. dest->template.status = trb->template.status;
  1125. wmb();
  1126. dest->template.control = ( trb->template.control |
  1127. cpu_to_le32 ( cycle ) );
  1128. return 0;
  1129. }
  1130. /**
  1131. * Dequeue a transfer request block
  1132. *
  1133. * @v ring TRB ring
  1134. * @ret iobuf I/O buffer
  1135. */
  1136. static struct io_buffer * xhci_dequeue ( struct xhci_trb_ring *ring ) {
  1137. struct io_buffer *iobuf;
  1138. unsigned int cons;
  1139. unsigned int mask;
  1140. unsigned int index;
  1141. /* Sanity check */
  1142. assert ( xhci_ring_fill ( ring ) != 0 );
  1143. /* Update consumer counter */
  1144. cons = ring->cons++;
  1145. mask = ring->mask;
  1146. index = ( cons & mask );
  1147. /* Retrieve I/O buffer */
  1148. iobuf = ring->iobuf[index];
  1149. ring->iobuf[index] = NULL;
  1150. return iobuf;
  1151. }
  1152. /**
  1153. * Enqueue multiple transfer request blocks
  1154. *
  1155. * @v ring TRB ring
  1156. * @v iobuf I/O buffer
  1157. * @v trbs Transfer request blocks (with empty Cycle flag)
  1158. * @v count Number of transfer request blocks
  1159. * @ret rc Return status code
  1160. *
  1161. * This operation does not implicitly ring the doorbell register.
  1162. */
  1163. static int xhci_enqueue_multi ( struct xhci_trb_ring *ring,
  1164. struct io_buffer *iobuf,
  1165. const union xhci_trb *trbs,
  1166. unsigned int count ) {
  1167. const union xhci_trb *trb = trbs;
  1168. int rc;
  1169. /* Sanity check */
  1170. assert ( iobuf != NULL );
  1171. /* Fail if ring does not have sufficient space */
  1172. if ( xhci_ring_remaining ( ring ) < count )
  1173. return -ENOBUFS;
  1174. /* Enqueue each TRB, recording the I/O buffer with the final TRB */
  1175. while ( count-- ) {
  1176. rc = xhci_enqueue ( ring, ( count ? NULL : iobuf ), trb++ );
  1177. assert ( rc == 0 ); /* Should never be able to fail */
  1178. }
  1179. return 0;
  1180. }
  1181. /**
  1182. * Dequeue multiple transfer request blocks
  1183. *
  1184. * @v ring TRB ring
  1185. * @ret iobuf I/O buffer
  1186. */
  1187. static struct io_buffer * xhci_dequeue_multi ( struct xhci_trb_ring *ring ) {
  1188. struct io_buffer *iobuf;
  1189. /* Dequeue TRBs until we reach the final TRB for an I/O buffer */
  1190. do {
  1191. iobuf = xhci_dequeue ( ring );
  1192. } while ( iobuf == NULL );
  1193. return iobuf;
  1194. }
  1195. /**
  1196. * Ring doorbell register
  1197. *
  1198. * @v ring TRB ring
  1199. */
  1200. static inline __attribute__ (( always_inline )) void
  1201. xhci_doorbell ( struct xhci_trb_ring *ring ) {
  1202. wmb();
  1203. writel ( ring->dbval, ring->db );
  1204. }
  1205. /******************************************************************************
  1206. *
  1207. * Command and event rings
  1208. *
  1209. ******************************************************************************
  1210. */
  1211. /**
  1212. * Allocate command ring
  1213. *
  1214. * @v xhci xHCI device
  1215. * @ret rc Return status code
  1216. */
  1217. static int xhci_command_alloc ( struct xhci_device *xhci ) {
  1218. physaddr_t crp;
  1219. int rc;
  1220. /* Allocate TRB ring */
  1221. if ( ( rc = xhci_ring_alloc ( xhci, &xhci->command, XHCI_CMD_TRBS_LOG2,
  1222. 0, 0, 0 ) ) != 0 )
  1223. goto err_ring_alloc;
  1224. /* Program command ring control register */
  1225. crp = virt_to_phys ( xhci->command.trb );
  1226. if ( ( rc = xhci_writeq ( xhci, ( crp | XHCI_CRCR_RCS ),
  1227. xhci->op + XHCI_OP_CRCR ) ) != 0 )
  1228. goto err_writeq;
  1229. DBGC2 ( xhci, "XHCI %p CRCR at [%08lx,%08lx)\n",
  1230. xhci, crp, ( crp + xhci->command.len ) );
  1231. return 0;
  1232. err_writeq:
  1233. xhci_ring_free ( &xhci->command );
  1234. err_ring_alloc:
  1235. return rc;
  1236. }
  1237. /**
  1238. * Free command ring
  1239. *
  1240. * @v xhci xHCI device
  1241. */
  1242. static void xhci_command_free ( struct xhci_device *xhci ) {
  1243. /* Sanity check */
  1244. assert ( ( readl ( xhci->op + XHCI_OP_CRCR ) & XHCI_CRCR_CRR ) == 0 );
  1245. /* Clear command ring control register */
  1246. xhci_writeq ( xhci, 0, xhci->op + XHCI_OP_CRCR );
  1247. /* Free TRB ring */
  1248. xhci_ring_free ( &xhci->command );
  1249. }
  1250. /**
  1251. * Allocate event ring
  1252. *
  1253. * @v xhci xHCI device
  1254. * @ret rc Return status code
  1255. */
  1256. static int xhci_event_alloc ( struct xhci_device *xhci ) {
  1257. struct xhci_event_ring *event = &xhci->event;
  1258. unsigned int count;
  1259. size_t len;
  1260. int rc;
  1261. /* Allocate event ring */
  1262. count = ( 1 << XHCI_EVENT_TRBS_LOG2 );
  1263. len = ( count * sizeof ( event->trb[0] ) );
  1264. event->trb = malloc_dma ( len, xhci_align ( len ) );
  1265. if ( ! event->trb ) {
  1266. rc = -ENOMEM;
  1267. goto err_alloc_trb;
  1268. }
  1269. memset ( event->trb, 0, len );
  1270. /* Allocate event ring segment table */
  1271. event->segment = malloc_dma ( sizeof ( event->segment[0] ),
  1272. xhci_align ( sizeof (event->segment[0])));
  1273. if ( ! event->segment ) {
  1274. rc = -ENOMEM;
  1275. goto err_alloc_segment;
  1276. }
  1277. memset ( event->segment, 0, sizeof ( event->segment[0] ) );
  1278. event->segment[0].base = cpu_to_le64 ( virt_to_phys ( event->trb ) );
  1279. event->segment[0].count = cpu_to_le32 ( count );
  1280. /* Program event ring registers */
  1281. writel ( 1, xhci->run + XHCI_RUN_ERSTSZ ( 0 ) );
  1282. if ( ( rc = xhci_writeq ( xhci, virt_to_phys ( event->trb ),
  1283. xhci->run + XHCI_RUN_ERDP ( 0 ) ) ) != 0 )
  1284. goto err_writeq_erdp;
  1285. if ( ( rc = xhci_writeq ( xhci, virt_to_phys ( event->segment ),
  1286. xhci->run + XHCI_RUN_ERSTBA ( 0 ) ) ) != 0 )
  1287. goto err_writeq_erstba;
  1288. DBGC2 ( xhci, "XHCI %p event ring [%08lx,%08lx) table [%08lx,%08lx)\n",
  1289. xhci, virt_to_phys ( event->trb ),
  1290. ( virt_to_phys ( event->trb ) + len ),
  1291. virt_to_phys ( event->segment ),
  1292. ( virt_to_phys ( event->segment ) +
  1293. sizeof (event->segment[0] ) ) );
  1294. return 0;
  1295. xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERSTBA ( 0 ) );
  1296. err_writeq_erstba:
  1297. xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERDP ( 0 ) );
  1298. err_writeq_erdp:
  1299. free_dma ( event->trb, len );
  1300. err_alloc_segment:
  1301. free_dma ( event->segment, sizeof ( event->segment[0] ) );
  1302. err_alloc_trb:
  1303. return rc;
  1304. }
  1305. /**
  1306. * Free event ring
  1307. *
  1308. * @v xhci xHCI device
  1309. */
  1310. static void xhci_event_free ( struct xhci_device *xhci ) {
  1311. struct xhci_event_ring *event = &xhci->event;
  1312. unsigned int count;
  1313. size_t len;
  1314. /* Clear event ring registers */
  1315. writel ( 0, xhci->run + XHCI_RUN_ERSTSZ ( 0 ) );
  1316. xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERSTBA ( 0 ) );
  1317. xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERDP ( 0 ) );
  1318. /* Free event ring segment table */
  1319. free_dma ( event->segment, sizeof ( event->segment[0] ) );
  1320. /* Free event ring */
  1321. count = ( 1 << XHCI_EVENT_TRBS_LOG2 );
  1322. len = ( count * sizeof ( event->trb[0] ) );
  1323. free_dma ( event->trb, len );
  1324. }
  1325. /**
  1326. * Handle transfer event
  1327. *
  1328. * @v xhci xHCI device
  1329. * @v transfer Transfer event TRB
  1330. */
  1331. static void xhci_transfer ( struct xhci_device *xhci,
  1332. struct xhci_trb_transfer *transfer ) {
  1333. struct xhci_slot *slot;
  1334. struct xhci_endpoint *endpoint;
  1335. struct io_buffer *iobuf;
  1336. int rc;
  1337. /* Profile transfer events */
  1338. profile_start ( &xhci_transfer_profiler );
  1339. /* Identify slot */
  1340. if ( ( transfer->slot > xhci->slots ) ||
  1341. ( ( slot = xhci->slot[transfer->slot] ) == NULL ) ) {
  1342. DBGC ( xhci, "XHCI %p transfer event invalid slot %d:\n",
  1343. xhci, transfer->slot );
  1344. DBGC_HDA ( xhci, 0, transfer, sizeof ( *transfer ) );
  1345. return;
  1346. }
  1347. /* Identify endpoint */
  1348. if ( ( transfer->endpoint > XHCI_CTX_END ) ||
  1349. ( ( endpoint = slot->endpoint[transfer->endpoint] ) == NULL ) ) {
  1350. DBGC ( xhci, "XHCI %p slot %d transfer event invalid epid "
  1351. "%d:\n", xhci, slot->id, transfer->endpoint );
  1352. DBGC_HDA ( xhci, 0, transfer, sizeof ( *transfer ) );
  1353. return;
  1354. }
  1355. /* Dequeue TRB(s) */
  1356. iobuf = xhci_dequeue_multi ( &endpoint->ring );
  1357. assert ( iobuf != NULL );
  1358. /* Check for errors */
  1359. if ( ! ( ( transfer->code == XHCI_CMPLT_SUCCESS ) ||
  1360. ( transfer->code == XHCI_CMPLT_SHORT ) ) ) {
  1361. /* Construct error */
  1362. rc = -ECODE ( transfer->code );
  1363. DBGC ( xhci, "XHCI %p slot %d ctx %d failed (code %d): %s\n",
  1364. xhci, slot->id, endpoint->ctx, transfer->code,
  1365. strerror ( rc ) );
  1366. DBGC_HDA ( xhci, 0, transfer, sizeof ( *transfer ) );
  1367. /* Sanity check */
  1368. assert ( ( endpoint->context->state & XHCI_ENDPOINT_STATE_MASK )
  1369. != XHCI_ENDPOINT_RUNNING );
  1370. /* Report failure to USB core */
  1371. usb_complete_err ( endpoint->ep, iobuf, rc );
  1372. return;
  1373. }
  1374. /* Record actual transfer size */
  1375. iob_unput ( iobuf, le16_to_cpu ( transfer->residual ) );
  1376. /* Sanity check (for successful completions only) */
  1377. assert ( xhci_ring_consumed ( &endpoint->ring ) ==
  1378. le64_to_cpu ( transfer->transfer ) );
  1379. /* Report completion to USB core */
  1380. usb_complete ( endpoint->ep, iobuf );
  1381. profile_stop ( &xhci_transfer_profiler );
  1382. }
  1383. /**
  1384. * Handle command completion event
  1385. *
  1386. * @v xhci xHCI device
  1387. * @v complete Command completion event
  1388. */
  1389. static void xhci_complete ( struct xhci_device *xhci,
  1390. struct xhci_trb_complete *complete ) {
  1391. int rc;
  1392. /* Ignore "command ring stopped" notifications */
  1393. if ( complete->code == XHCI_CMPLT_CMD_STOPPED ) {
  1394. DBGC2 ( xhci, "XHCI %p command ring stopped\n", xhci );
  1395. return;
  1396. }
  1397. /* Ignore unexpected completions */
  1398. if ( ! xhci->pending ) {
  1399. rc = -ECODE ( complete->code );
  1400. DBGC ( xhci, "XHCI %p unexpected completion (code %d): %s\n",
  1401. xhci, complete->code, strerror ( rc ) );
  1402. DBGC_HDA ( xhci, 0, complete, sizeof ( *complete ) );
  1403. return;
  1404. }
  1405. /* Dequeue command TRB */
  1406. xhci_dequeue ( &xhci->command );
  1407. /* Sanity check */
  1408. assert ( xhci_ring_consumed ( &xhci->command ) ==
  1409. le64_to_cpu ( complete->command ) );
  1410. /* Record completion */
  1411. memcpy ( xhci->pending, complete, sizeof ( *xhci->pending ) );
  1412. xhci->pending = NULL;
  1413. }
  1414. /**
  1415. * Handle port status event
  1416. *
  1417. * @v xhci xHCI device
  1418. * @v port Port status event
  1419. */
  1420. static void xhci_port_status ( struct xhci_device *xhci,
  1421. struct xhci_trb_port_status *port ) {
  1422. uint32_t portsc;
  1423. /* Sanity check */
  1424. assert ( ( port->port > 0 ) && ( port->port <= xhci->ports ) );
  1425. /* Clear port status change bits */
  1426. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port->port ) );
  1427. portsc &= ( XHCI_PORTSC_PRESERVE | XHCI_PORTSC_CHANGE );
  1428. writel ( portsc, xhci->op + XHCI_OP_PORTSC ( port->port ) );
  1429. /* Report port status change */
  1430. usb_port_changed ( usb_port ( xhci->bus->hub, port->port ) );
  1431. }
  1432. /**
  1433. * Handle host controller event
  1434. *
  1435. * @v xhci xHCI device
  1436. * @v host Host controller event
  1437. */
  1438. static void xhci_host_controller ( struct xhci_device *xhci,
  1439. struct xhci_trb_host_controller *host ) {
  1440. int rc;
  1441. /* Construct error */
  1442. rc = -ECODE ( host->code );
  1443. DBGC ( xhci, "XHCI %p host controller event (code %d): %s\n",
  1444. xhci, host->code, strerror ( rc ) );
  1445. }
  1446. /**
  1447. * Poll event ring
  1448. *
  1449. * @v xhci xHCI device
  1450. */
  1451. static void xhci_event_poll ( struct xhci_device *xhci ) {
  1452. struct xhci_event_ring *event = &xhci->event;
  1453. union xhci_trb *trb;
  1454. unsigned int shift = XHCI_EVENT_TRBS_LOG2;
  1455. unsigned int count = ( 1 << shift );
  1456. unsigned int mask = ( count - 1 );
  1457. unsigned int consumed;
  1458. unsigned int type;
  1459. /* Poll for events */
  1460. profile_start ( &xhci_event_profiler );
  1461. for ( consumed = 0 ; ; consumed++ ) {
  1462. /* Stop if we reach an empty TRB */
  1463. rmb();
  1464. trb = &event->trb[ event->cons & mask ];
  1465. if ( ! ( ( trb->common.flags ^
  1466. ( event->cons >> shift ) ) & XHCI_TRB_C ) )
  1467. break;
  1468. /* Handle TRB */
  1469. type = ( trb->common.type & XHCI_TRB_TYPE_MASK );
  1470. switch ( type ) {
  1471. case XHCI_TRB_TRANSFER :
  1472. xhci_transfer ( xhci, &trb->transfer );
  1473. break;
  1474. case XHCI_TRB_COMPLETE :
  1475. xhci_complete ( xhci, &trb->complete );
  1476. break;
  1477. case XHCI_TRB_PORT_STATUS:
  1478. xhci_port_status ( xhci, &trb->port );
  1479. break;
  1480. case XHCI_TRB_HOST_CONTROLLER:
  1481. xhci_host_controller ( xhci, &trb->host );
  1482. break;
  1483. default:
  1484. DBGC ( xhci, "XHCI %p unrecognised event %#x\n:",
  1485. xhci, event->cons );
  1486. DBGC_HDA ( xhci, virt_to_phys ( trb ),
  1487. trb, sizeof ( *trb ) );
  1488. break;
  1489. }
  1490. /* Consume this TRB */
  1491. event->cons++;
  1492. }
  1493. /* Update dequeue pointer if applicable */
  1494. if ( consumed ) {
  1495. xhci_writeq ( xhci, virt_to_phys ( trb ),
  1496. xhci->run + XHCI_RUN_ERDP ( 0 ) );
  1497. profile_stop ( &xhci_event_profiler );
  1498. }
  1499. }
  1500. /**
  1501. * Abort command
  1502. *
  1503. * @v xhci xHCI device
  1504. */
  1505. static void xhci_abort ( struct xhci_device *xhci ) {
  1506. physaddr_t crp;
  1507. /* Abort the command */
  1508. DBGC2 ( xhci, "XHCI %p aborting command\n", xhci );
  1509. xhci_writeq ( xhci, XHCI_CRCR_CA, xhci->op + XHCI_OP_CRCR );
  1510. /* Allow time for command to abort */
  1511. mdelay ( XHCI_COMMAND_ABORT_DELAY_MS );
  1512. /* Sanity check */
  1513. assert ( ( readl ( xhci->op + XHCI_OP_CRCR ) & XHCI_CRCR_CRR ) == 0 );
  1514. /* Consume (and ignore) any final command status */
  1515. xhci_event_poll ( xhci );
  1516. /* Reset the command ring control register */
  1517. xhci_ring_reset ( &xhci->command );
  1518. crp = virt_to_phys ( xhci->command.trb );
  1519. xhci_writeq ( xhci, ( crp | XHCI_CRCR_RCS ), xhci->op + XHCI_OP_CRCR );
  1520. }
  1521. /**
  1522. * Issue command and wait for completion
  1523. *
  1524. * @v xhci xHCI device
  1525. * @v trb Transfer request block (with empty Cycle flag)
  1526. * @ret rc Return status code
  1527. *
  1528. * On a successful completion, the TRB will be overwritten with the
  1529. * completion.
  1530. */
  1531. static int xhci_command ( struct xhci_device *xhci, union xhci_trb *trb ) {
  1532. struct xhci_trb_complete *complete = &trb->complete;
  1533. unsigned int i;
  1534. int rc;
  1535. /* Record the pending command */
  1536. xhci->pending = trb;
  1537. /* Enqueue the command */
  1538. if ( ( rc = xhci_enqueue ( &xhci->command, NULL, trb ) ) != 0 )
  1539. goto err_enqueue;
  1540. /* Ring the command doorbell */
  1541. xhci_doorbell ( &xhci->command );
  1542. /* Wait for the command to complete */
  1543. for ( i = 0 ; i < XHCI_COMMAND_MAX_WAIT_MS ; i++ ) {
  1544. /* Poll event ring */
  1545. xhci_event_poll ( xhci );
  1546. /* Check for completion */
  1547. if ( ! xhci->pending ) {
  1548. if ( complete->code != XHCI_CMPLT_SUCCESS ) {
  1549. rc = -ECODE ( complete->code );
  1550. DBGC ( xhci, "XHCI %p command failed (code "
  1551. "%d): %s\n", xhci, complete->code,
  1552. strerror ( rc ) );
  1553. DBGC_HDA ( xhci, 0, trb, sizeof ( *trb ) );
  1554. return rc;
  1555. }
  1556. return 0;
  1557. }
  1558. /* Delay */
  1559. mdelay ( 1 );
  1560. }
  1561. /* Timeout */
  1562. DBGC ( xhci, "XHCI %p timed out waiting for completion\n", xhci );
  1563. rc = -ETIMEDOUT;
  1564. /* Abort command */
  1565. xhci_abort ( xhci );
  1566. err_enqueue:
  1567. xhci->pending = NULL;
  1568. return rc;
  1569. }
  1570. /**
  1571. * Issue NOP and wait for completion
  1572. *
  1573. * @v xhci xHCI device
  1574. * @ret rc Return status code
  1575. */
  1576. static inline int xhci_nop ( struct xhci_device *xhci ) {
  1577. union xhci_trb trb;
  1578. struct xhci_trb_common *nop = &trb.common;
  1579. int rc;
  1580. /* Construct command */
  1581. memset ( nop, 0, sizeof ( *nop ) );
  1582. nop->flags = XHCI_TRB_IOC;
  1583. nop->type = XHCI_TRB_NOP_CMD;
  1584. /* Issue command and wait for completion */
  1585. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 )
  1586. return rc;
  1587. return 0;
  1588. }
  1589. /**
  1590. * Enable slot
  1591. *
  1592. * @v xhci xHCI device
  1593. * @v type Slot type
  1594. * @ret slot Device slot ID, or negative error
  1595. */
  1596. static inline int xhci_enable_slot ( struct xhci_device *xhci,
  1597. unsigned int type ) {
  1598. union xhci_trb trb;
  1599. struct xhci_trb_enable_slot *enable = &trb.enable;
  1600. struct xhci_trb_complete *enabled = &trb.complete;
  1601. unsigned int slot;
  1602. int rc;
  1603. /* Construct command */
  1604. memset ( enable, 0, sizeof ( *enable ) );
  1605. enable->slot = type;
  1606. enable->type = XHCI_TRB_ENABLE_SLOT;
  1607. /* Issue command and wait for completion */
  1608. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 ) {
  1609. DBGC ( xhci, "XHCI %p could not enable new slot: %s\n",
  1610. xhci, strerror ( rc ) );
  1611. return rc;
  1612. }
  1613. /* Extract slot number */
  1614. slot = enabled->slot;
  1615. DBGC2 ( xhci, "XHCI %p slot %d enabled\n", xhci, slot );
  1616. return slot;
  1617. }
  1618. /**
  1619. * Disable slot
  1620. *
  1621. * @v xhci xHCI device
  1622. * @v slot Device slot
  1623. * @ret rc Return status code
  1624. */
  1625. static inline int xhci_disable_slot ( struct xhci_device *xhci,
  1626. unsigned int slot ) {
  1627. union xhci_trb trb;
  1628. struct xhci_trb_disable_slot *disable = &trb.disable;
  1629. int rc;
  1630. /* Construct command */
  1631. memset ( disable, 0, sizeof ( *disable ) );
  1632. disable->type = XHCI_TRB_DISABLE_SLOT;
  1633. disable->slot = slot;
  1634. /* Issue command and wait for completion */
  1635. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 ) {
  1636. DBGC ( xhci, "XHCI %p could not disable slot %d: %s\n",
  1637. xhci, slot, strerror ( rc ) );
  1638. return rc;
  1639. }
  1640. DBGC2 ( xhci, "XHCI %p slot %d disabled\n", xhci, slot );
  1641. return 0;
  1642. }
  1643. /**
  1644. * Issue context-based command and wait for completion
  1645. *
  1646. * @v xhci xHCI device
  1647. * @v slot Device slot
  1648. * @v endpoint Endpoint
  1649. * @v type TRB type
  1650. * @v populate Input context populater
  1651. * @ret rc Return status code
  1652. */
  1653. static int xhci_context ( struct xhci_device *xhci, struct xhci_slot *slot,
  1654. struct xhci_endpoint *endpoint, unsigned int type,
  1655. void ( * populate ) ( struct xhci_device *xhci,
  1656. struct xhci_slot *slot,
  1657. struct xhci_endpoint *endpoint,
  1658. void *input ) ) {
  1659. union xhci_trb trb;
  1660. struct xhci_trb_context *context = &trb.context;
  1661. size_t len;
  1662. void *input;
  1663. int rc;
  1664. /* Allocate an input context */
  1665. len = xhci_input_context_offset ( xhci, XHCI_CTX_END );
  1666. input = malloc_dma ( len, xhci_align ( len ) );
  1667. if ( ! input ) {
  1668. rc = -ENOMEM;
  1669. goto err_alloc;
  1670. }
  1671. memset ( input, 0, len );
  1672. /* Populate input context */
  1673. populate ( xhci, slot, endpoint, input );
  1674. /* Construct command */
  1675. memset ( context, 0, sizeof ( *context ) );
  1676. context->type = type;
  1677. context->input = cpu_to_le64 ( virt_to_phys ( input ) );
  1678. context->slot = slot->id;
  1679. /* Issue command and wait for completion */
  1680. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 )
  1681. goto err_command;
  1682. err_command:
  1683. free_dma ( input, len );
  1684. err_alloc:
  1685. return rc;
  1686. }
  1687. /**
  1688. * Populate address device input context
  1689. *
  1690. * @v xhci xHCI device
  1691. * @v slot Device slot
  1692. * @v endpoint Endpoint
  1693. * @v input Input context
  1694. */
  1695. static void xhci_address_device_input ( struct xhci_device *xhci,
  1696. struct xhci_slot *slot,
  1697. struct xhci_endpoint *endpoint,
  1698. void *input ) {
  1699. struct xhci_control_context *control_ctx;
  1700. struct xhci_slot_context *slot_ctx;
  1701. struct xhci_endpoint_context *ep_ctx;
  1702. /* Sanity checks */
  1703. assert ( endpoint->ctx == XHCI_CTX_EP0 );
  1704. /* Populate control context */
  1705. control_ctx = input;
  1706. control_ctx->add = cpu_to_le32 ( ( 1 << XHCI_CTX_SLOT ) |
  1707. ( 1 << XHCI_CTX_EP0 ) );
  1708. /* Populate slot context */
  1709. slot_ctx = ( input + xhci_input_context_offset ( xhci, XHCI_CTX_SLOT ));
  1710. slot_ctx->info = cpu_to_le32 ( XHCI_SLOT_INFO ( 1, 0, slot->psiv,
  1711. slot->route ) );
  1712. slot_ctx->port = slot->port;
  1713. /* Populate control endpoint context */
  1714. ep_ctx = ( input + xhci_input_context_offset ( xhci, XHCI_CTX_EP0 ) );
  1715. ep_ctx->type = XHCI_EP_TYPE_CONTROL;
  1716. ep_ctx->burst = endpoint->ep->burst;
  1717. ep_ctx->mtu = cpu_to_le16 ( endpoint->ep->mtu );
  1718. ep_ctx->dequeue = cpu_to_le64 ( virt_to_phys ( endpoint->ring.trb ) |
  1719. XHCI_EP_DCS );
  1720. ep_ctx->trb_len = cpu_to_le16 ( XHCI_EP0_TRB_LEN );
  1721. }
  1722. /**
  1723. * Address device
  1724. *
  1725. * @v xhci xHCI device
  1726. * @v slot Device slot
  1727. * @ret rc Return status code
  1728. */
  1729. static inline int xhci_address_device ( struct xhci_device *xhci,
  1730. struct xhci_slot *slot ) {
  1731. struct usb_device *usb = slot->usb;
  1732. struct xhci_slot_context *slot_ctx;
  1733. int rc;
  1734. /* Assign device address */
  1735. if ( ( rc = xhci_context ( xhci, slot, slot->endpoint[XHCI_CTX_EP0],
  1736. XHCI_TRB_ADDRESS_DEVICE,
  1737. xhci_address_device_input ) ) != 0 )
  1738. return rc;
  1739. /* Get assigned address */
  1740. slot_ctx = ( slot->context +
  1741. xhci_device_context_offset ( xhci, XHCI_CTX_SLOT ) );
  1742. usb->address = slot_ctx->address;
  1743. DBGC2 ( xhci, "XHCI %p assigned address %d to %s\n",
  1744. xhci, usb->address, usb->name );
  1745. return 0;
  1746. }
  1747. /**
  1748. * Populate configure endpoint input context
  1749. *
  1750. * @v xhci xHCI device
  1751. * @v slot Device slot
  1752. * @v endpoint Endpoint
  1753. * @v input Input context
  1754. */
  1755. static void xhci_configure_endpoint_input ( struct xhci_device *xhci,
  1756. struct xhci_slot *slot __unused,
  1757. struct xhci_endpoint *endpoint,
  1758. void *input ) {
  1759. struct xhci_control_context *control_ctx;
  1760. struct xhci_slot_context *slot_ctx;
  1761. struct xhci_endpoint_context *ep_ctx;
  1762. /* Populate control context */
  1763. control_ctx = input;
  1764. control_ctx->add = cpu_to_le32 ( ( 1 << XHCI_CTX_SLOT ) |
  1765. ( 1 << endpoint->ctx ) );
  1766. /* Populate slot context */
  1767. slot_ctx = ( input + xhci_input_context_offset ( xhci, XHCI_CTX_SLOT ));
  1768. slot_ctx->info = cpu_to_le32 ( XHCI_SLOT_INFO ( ( XHCI_CTX_END - 1 ),
  1769. 0, 0, 0 ) );
  1770. /* Populate endpoint context */
  1771. ep_ctx = ( input + xhci_input_context_offset ( xhci, endpoint->ctx ) );
  1772. ep_ctx->interval = endpoint->interval;
  1773. ep_ctx->type = endpoint->type;
  1774. ep_ctx->burst = endpoint->ep->burst;
  1775. ep_ctx->mtu = cpu_to_le16 ( endpoint->ep->mtu );
  1776. ep_ctx->dequeue = cpu_to_le64 ( virt_to_phys ( endpoint->ring.trb ) |
  1777. XHCI_EP_DCS );
  1778. ep_ctx->trb_len = cpu_to_le16 ( endpoint->ep->mtu ); /* best guess */
  1779. }
  1780. /**
  1781. * Configure endpoint
  1782. *
  1783. * @v xhci xHCI device
  1784. * @v slot Device slot
  1785. * @v endpoint Endpoint
  1786. * @ret rc Return status code
  1787. */
  1788. static inline int xhci_configure_endpoint ( struct xhci_device *xhci,
  1789. struct xhci_slot *slot,
  1790. struct xhci_endpoint *endpoint ) {
  1791. int rc;
  1792. /* Configure endpoint */
  1793. if ( ( rc = xhci_context ( xhci, slot, endpoint,
  1794. XHCI_TRB_CONFIGURE_ENDPOINT,
  1795. xhci_configure_endpoint_input ) ) != 0 )
  1796. return rc;
  1797. DBGC2 ( xhci, "XHCI %p slot %d ctx %d configured\n",
  1798. xhci, slot->id, endpoint->ctx );
  1799. return 0;
  1800. }
  1801. /**
  1802. * Populate deconfigure endpoint input context
  1803. *
  1804. * @v xhci xHCI device
  1805. * @v slot Device slot
  1806. * @v endpoint Endpoint
  1807. * @v input Input context
  1808. */
  1809. static void
  1810. xhci_deconfigure_endpoint_input ( struct xhci_device *xhci __unused,
  1811. struct xhci_slot *slot __unused,
  1812. struct xhci_endpoint *endpoint,
  1813. void *input ) {
  1814. struct xhci_control_context *control_ctx;
  1815. struct xhci_slot_context *slot_ctx;
  1816. /* Populate control context */
  1817. control_ctx = input;
  1818. control_ctx->add = cpu_to_le32 ( 1 << XHCI_CTX_SLOT );
  1819. control_ctx->drop = cpu_to_le32 ( 1 << endpoint->ctx );
  1820. /* Populate slot context */
  1821. slot_ctx = ( input + xhci_input_context_offset ( xhci, XHCI_CTX_SLOT ));
  1822. slot_ctx->info = cpu_to_le32 ( XHCI_SLOT_INFO ( ( XHCI_CTX_END - 1 ),
  1823. 0, 0, 0 ) );
  1824. }
  1825. /**
  1826. * Deconfigure endpoint
  1827. *
  1828. * @v xhci xHCI device
  1829. * @v slot Device slot
  1830. * @v endpoint Endpoint
  1831. * @ret rc Return status code
  1832. */
  1833. static inline int xhci_deconfigure_endpoint ( struct xhci_device *xhci,
  1834. struct xhci_slot *slot,
  1835. struct xhci_endpoint *endpoint ) {
  1836. int rc;
  1837. /* Deconfigure endpoint */
  1838. if ( ( rc = xhci_context ( xhci, slot, endpoint,
  1839. XHCI_TRB_CONFIGURE_ENDPOINT,
  1840. xhci_deconfigure_endpoint_input ) ) != 0 )
  1841. return rc;
  1842. DBGC2 ( xhci, "XHCI %p slot %d ctx %d deconfigured\n",
  1843. xhci, slot->id, endpoint->ctx );
  1844. return 0;
  1845. }
  1846. /**
  1847. * Populate evaluate context input context
  1848. *
  1849. * @v xhci xHCI device
  1850. * @v slot Device slot
  1851. * @v endpoint Endpoint
  1852. * @v input Input context
  1853. */
  1854. static void xhci_evaluate_context_input ( struct xhci_device *xhci,
  1855. struct xhci_slot *slot __unused,
  1856. struct xhci_endpoint *endpoint,
  1857. void *input ) {
  1858. struct xhci_control_context *control_ctx;
  1859. struct xhci_slot_context *slot_ctx;
  1860. struct xhci_endpoint_context *ep_ctx;
  1861. /* Populate control context */
  1862. control_ctx = input;
  1863. control_ctx->add = cpu_to_le32 ( ( 1 << XHCI_CTX_SLOT ) |
  1864. ( 1 << endpoint->ctx ) );
  1865. /* Populate slot context */
  1866. slot_ctx = ( input + xhci_input_context_offset ( xhci, XHCI_CTX_SLOT ));
  1867. slot_ctx->info = cpu_to_le32 ( XHCI_SLOT_INFO ( ( XHCI_CTX_END - 1 ),
  1868. 0, 0, 0 ) );
  1869. /* Populate endpoint context */
  1870. ep_ctx = ( input + xhci_input_context_offset ( xhci, endpoint->ctx ) );
  1871. ep_ctx->mtu = cpu_to_le16 ( endpoint->ep->mtu );
  1872. }
  1873. /**
  1874. * Evaluate context
  1875. *
  1876. * @v xhci xHCI device
  1877. * @v slot Device slot
  1878. * @v endpoint Endpoint
  1879. * @ret rc Return status code
  1880. */
  1881. static inline int xhci_evaluate_context ( struct xhci_device *xhci,
  1882. struct xhci_slot *slot,
  1883. struct xhci_endpoint *endpoint ) {
  1884. int rc;
  1885. /* Configure endpoint */
  1886. if ( ( rc = xhci_context ( xhci, slot, endpoint,
  1887. XHCI_TRB_EVALUATE_CONTEXT,
  1888. xhci_evaluate_context_input ) ) != 0 )
  1889. return rc;
  1890. DBGC2 ( xhci, "XHCI %p slot %d ctx %d (re-)evaluated\n",
  1891. xhci, slot->id, endpoint->ctx );
  1892. return 0;
  1893. }
  1894. /**
  1895. * Reset endpoint
  1896. *
  1897. * @v xhci xHCI device
  1898. * @v slot Device slot
  1899. * @v endpoint Endpoint
  1900. * @ret rc Return status code
  1901. */
  1902. static inline int xhci_reset_endpoint ( struct xhci_device *xhci,
  1903. struct xhci_slot *slot,
  1904. struct xhci_endpoint *endpoint ) {
  1905. union xhci_trb trb;
  1906. struct xhci_trb_reset_endpoint *reset = &trb.reset;
  1907. int rc;
  1908. /* Construct command */
  1909. memset ( reset, 0, sizeof ( *reset ) );
  1910. reset->slot = slot->id;
  1911. reset->endpoint = endpoint->ctx;
  1912. reset->type = XHCI_TRB_RESET_ENDPOINT;
  1913. /* Issue command and wait for completion */
  1914. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 ) {
  1915. DBGC ( xhci, "XHCI %p slot %d ctx %d could not reset endpoint "
  1916. "in state %d: %s\n", xhci, slot->id, endpoint->ctx,
  1917. endpoint->context->state, strerror ( rc ) );
  1918. return rc;
  1919. }
  1920. return 0;
  1921. }
  1922. /**
  1923. * Stop endpoint
  1924. *
  1925. * @v xhci xHCI device
  1926. * @v slot Device slot
  1927. * @v endpoint Endpoint
  1928. * @ret rc Return status code
  1929. */
  1930. static inline int xhci_stop_endpoint ( struct xhci_device *xhci,
  1931. struct xhci_slot *slot,
  1932. struct xhci_endpoint *endpoint ) {
  1933. union xhci_trb trb;
  1934. struct xhci_trb_stop_endpoint *stop = &trb.stop;
  1935. int rc;
  1936. /* Construct command */
  1937. memset ( stop, 0, sizeof ( *stop ) );
  1938. stop->slot = slot->id;
  1939. stop->endpoint = endpoint->ctx;
  1940. stop->type = XHCI_TRB_STOP_ENDPOINT;
  1941. /* Issue command and wait for completion */
  1942. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 ) {
  1943. DBGC ( xhci, "XHCI %p slot %d ctx %d could not stop endpoint "
  1944. "in state %d: %s\n", xhci, slot->id, endpoint->ctx,
  1945. endpoint->context->state, strerror ( rc ) );
  1946. return rc;
  1947. }
  1948. return 0;
  1949. }
  1950. /**
  1951. * Set transfer ring dequeue pointer
  1952. *
  1953. * @v xhci xHCI device
  1954. * @v slot Device slot
  1955. * @v endpoint Endpoint
  1956. * @ret rc Return status code
  1957. */
  1958. static inline int
  1959. xhci_set_tr_dequeue_pointer ( struct xhci_device *xhci,
  1960. struct xhci_slot *slot,
  1961. struct xhci_endpoint *endpoint ) {
  1962. union xhci_trb trb;
  1963. struct xhci_trb_set_tr_dequeue_pointer *dequeue = &trb.dequeue;
  1964. struct xhci_trb_ring *ring = &endpoint->ring;
  1965. unsigned int cons;
  1966. unsigned int mask;
  1967. unsigned int index;
  1968. unsigned int dcs;
  1969. int rc;
  1970. /* Construct command */
  1971. memset ( dequeue, 0, sizeof ( *dequeue ) );
  1972. cons = ring->cons;
  1973. mask = ring->mask;
  1974. dcs = ( ( ~( cons >> ring->shift ) ) & XHCI_EP_DCS );
  1975. index = ( cons & mask );
  1976. dequeue->dequeue =
  1977. cpu_to_le64 ( virt_to_phys ( &ring->trb[index] ) | dcs );
  1978. dequeue->slot = slot->id;
  1979. dequeue->endpoint = endpoint->ctx;
  1980. dequeue->type = XHCI_TRB_SET_TR_DEQUEUE_POINTER;
  1981. /* Issue command and wait for completion */
  1982. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 ) {
  1983. DBGC ( xhci, "XHCI %p slot %d ctx %d could not set TR dequeue "
  1984. "pointer in state %d: %s\n", xhci, slot->id,
  1985. endpoint->ctx, endpoint->context->state, strerror ( rc));
  1986. return rc;
  1987. }
  1988. return 0;
  1989. }
  1990. /******************************************************************************
  1991. *
  1992. * Endpoint operations
  1993. *
  1994. ******************************************************************************
  1995. */
  1996. /**
  1997. * Open endpoint
  1998. *
  1999. * @v ep USB endpoint
  2000. * @ret rc Return status code
  2001. */
  2002. static int xhci_endpoint_open ( struct usb_endpoint *ep ) {
  2003. struct usb_device *usb = ep->usb;
  2004. struct xhci_slot *slot = usb_get_hostdata ( usb );
  2005. struct xhci_device *xhci = slot->xhci;
  2006. struct xhci_endpoint *endpoint;
  2007. unsigned int ctx;
  2008. unsigned int type;
  2009. unsigned int interval;
  2010. int rc;
  2011. /* Calculate context index */
  2012. ctx = XHCI_CTX ( ep->address );
  2013. assert ( slot->endpoint[ctx] == NULL );
  2014. /* Calculate endpoint type */
  2015. type = XHCI_EP_TYPE ( ep->attributes & USB_ENDPOINT_ATTR_TYPE_MASK );
  2016. if ( type == XHCI_EP_TYPE ( USB_ENDPOINT_ATTR_CONTROL ) )
  2017. type = XHCI_EP_TYPE_CONTROL;
  2018. if ( ep->address & USB_DIR_IN )
  2019. type |= XHCI_EP_TYPE_IN;
  2020. /* Calculate interval */
  2021. if ( type & XHCI_EP_TYPE_PERIODIC ) {
  2022. interval = ( fls ( ep->interval ) - 1 );
  2023. } else {
  2024. interval = ep->interval;
  2025. }
  2026. /* Allocate and initialise structure */
  2027. endpoint = zalloc ( sizeof ( *endpoint ) );
  2028. if ( ! endpoint ) {
  2029. rc = -ENOMEM;
  2030. goto err_alloc;
  2031. }
  2032. usb_endpoint_set_hostdata ( ep, endpoint );
  2033. slot->endpoint[ctx] = endpoint;
  2034. endpoint->xhci = xhci;
  2035. endpoint->slot = slot;
  2036. endpoint->ep = ep;
  2037. endpoint->ctx = ctx;
  2038. endpoint->type = type;
  2039. endpoint->interval = interval;
  2040. endpoint->context = ( ( ( void * ) slot->context ) +
  2041. xhci_device_context_offset ( xhci, ctx ) );
  2042. /* Allocate transfer ring */
  2043. if ( ( rc = xhci_ring_alloc ( xhci, &endpoint->ring,
  2044. XHCI_TRANSFER_TRBS_LOG2,
  2045. slot->id, ctx, 0 ) ) != 0 )
  2046. goto err_ring_alloc;
  2047. /* Configure endpoint, if applicable */
  2048. if ( ( ctx != XHCI_CTX_EP0 ) &&
  2049. ( ( rc = xhci_configure_endpoint ( xhci, slot, endpoint ) ) != 0 ))
  2050. goto err_configure_endpoint;
  2051. DBGC2 ( xhci, "XHCI %p slot %d ctx %d ring [%08lx,%08lx)\n",
  2052. xhci, slot->id, ctx, virt_to_phys ( endpoint->ring.trb ),
  2053. ( virt_to_phys ( endpoint->ring.trb ) + endpoint->ring.len ) );
  2054. return 0;
  2055. xhci_deconfigure_endpoint ( xhci, slot, endpoint );
  2056. err_configure_endpoint:
  2057. xhci_ring_free ( &endpoint->ring );
  2058. err_ring_alloc:
  2059. slot->endpoint[ctx] = NULL;
  2060. free ( endpoint );
  2061. err_alloc:
  2062. return rc;
  2063. }
  2064. /**
  2065. * Close endpoint
  2066. *
  2067. * @v ep USB endpoint
  2068. */
  2069. static void xhci_endpoint_close ( struct usb_endpoint *ep ) {
  2070. struct xhci_endpoint *endpoint = usb_endpoint_get_hostdata ( ep );
  2071. struct xhci_slot *slot = endpoint->slot;
  2072. struct xhci_device *xhci = slot->xhci;
  2073. struct io_buffer *iobuf;
  2074. unsigned int ctx = endpoint->ctx;
  2075. /* Deconfigure endpoint, if applicable */
  2076. if ( ctx != XHCI_CTX_EP0 )
  2077. xhci_deconfigure_endpoint ( xhci, slot, endpoint );
  2078. /* Cancel any incomplete transfers */
  2079. while ( xhci_ring_fill ( &endpoint->ring ) ) {
  2080. iobuf = xhci_dequeue_multi ( &endpoint->ring );
  2081. usb_complete_err ( ep, iobuf, -ECANCELED );
  2082. }
  2083. /* Free endpoint */
  2084. xhci_ring_free ( &endpoint->ring );
  2085. slot->endpoint[ctx] = NULL;
  2086. free ( endpoint );
  2087. }
  2088. /**
  2089. * Reset endpoint
  2090. *
  2091. * @v ep USB endpoint
  2092. * @ret rc Return status code
  2093. */
  2094. static int xhci_endpoint_reset ( struct usb_endpoint *ep ) {
  2095. struct xhci_endpoint *endpoint = usb_endpoint_get_hostdata ( ep );
  2096. struct xhci_slot *slot = endpoint->slot;
  2097. struct xhci_device *xhci = slot->xhci;
  2098. int rc;
  2099. /* Reset endpoint context */
  2100. if ( ( rc = xhci_reset_endpoint ( xhci, slot, endpoint ) ) != 0 )
  2101. return rc;
  2102. /* Set transfer ring dequeue pointer */
  2103. if ( ( rc = xhci_set_tr_dequeue_pointer ( xhci, slot, endpoint ) ) != 0)
  2104. return rc;
  2105. DBGC ( xhci, "XHCI %p slot %d ctx %d reset\n",
  2106. xhci, slot->id, endpoint->ctx );
  2107. return 0;
  2108. }
  2109. /**
  2110. * Update MTU
  2111. *
  2112. * @v ep USB endpoint
  2113. * @ret rc Return status code
  2114. */
  2115. static int xhci_endpoint_mtu ( struct usb_endpoint *ep ) {
  2116. struct xhci_endpoint *endpoint = usb_endpoint_get_hostdata ( ep );
  2117. struct xhci_slot *slot = endpoint->slot;
  2118. struct xhci_device *xhci = slot->xhci;
  2119. int rc;
  2120. /* Evalulate context */
  2121. if ( ( rc = xhci_evaluate_context ( xhci, slot, endpoint ) ) != 0 )
  2122. return rc;
  2123. return 0;
  2124. }
  2125. /**
  2126. * Enqueue message transfer
  2127. *
  2128. * @v ep USB endpoint
  2129. * @v packet Setup packet
  2130. * @v iobuf I/O buffer
  2131. * @ret rc Return status code
  2132. */
  2133. static int xhci_endpoint_message ( struct usb_endpoint *ep,
  2134. struct usb_setup_packet *packet,
  2135. struct io_buffer *iobuf ) {
  2136. struct xhci_endpoint *endpoint = usb_endpoint_get_hostdata ( ep );
  2137. unsigned int input = ( le16_to_cpu ( packet->request ) & USB_DIR_IN );
  2138. size_t len = iob_len ( iobuf );
  2139. union xhci_trb trbs[ 1 /* setup */ + 1 /* possible data */ +
  2140. 1 /* status */ ];
  2141. union xhci_trb *trb = trbs;
  2142. struct xhci_trb_setup *setup;
  2143. struct xhci_trb_data *data;
  2144. struct xhci_trb_status *status;
  2145. int rc;
  2146. /* Profile message transfers */
  2147. profile_start ( &xhci_message_profiler );
  2148. /* Construct setup stage TRB */
  2149. memset ( trbs, 0, sizeof ( trbs ) );
  2150. setup = &(trb++)->setup;
  2151. memcpy ( &setup->packet, packet, sizeof ( setup->packet ) );
  2152. setup->len = cpu_to_le32 ( sizeof ( *packet ) );
  2153. setup->flags = XHCI_TRB_IDT;
  2154. setup->type = XHCI_TRB_SETUP;
  2155. if ( len )
  2156. setup->direction = ( input ? XHCI_SETUP_IN : XHCI_SETUP_OUT );
  2157. /* Construct data stage TRB, if applicable */
  2158. if ( len ) {
  2159. data = &(trb++)->data;
  2160. data->data = cpu_to_le64 ( virt_to_phys ( iobuf->data ) );
  2161. data->len = cpu_to_le32 ( len );
  2162. data->type = XHCI_TRB_DATA;
  2163. data->direction = ( input ? XHCI_DATA_IN : XHCI_DATA_OUT );
  2164. }
  2165. /* Construct status stage TRB */
  2166. status = &(trb++)->status;
  2167. status->flags = XHCI_TRB_IOC;
  2168. status->type = XHCI_TRB_STATUS;
  2169. status->direction =
  2170. ( ( len && input ) ? XHCI_STATUS_OUT : XHCI_STATUS_IN );
  2171. /* Enqueue TRBs */
  2172. if ( ( rc = xhci_enqueue_multi ( &endpoint->ring, iobuf, trbs,
  2173. ( trb - trbs ) ) ) != 0 )
  2174. return rc;
  2175. /* Ring the doorbell */
  2176. xhci_doorbell ( &endpoint->ring );
  2177. profile_stop ( &xhci_message_profiler );
  2178. return 0;
  2179. }
  2180. /**
  2181. * Enqueue stream transfer
  2182. *
  2183. * @v ep USB endpoint
  2184. * @v iobuf I/O buffer
  2185. * @v terminate Terminate using a short packet
  2186. * @ret rc Return status code
  2187. */
  2188. static int xhci_endpoint_stream ( struct usb_endpoint *ep,
  2189. struct io_buffer *iobuf, int terminate ) {
  2190. struct xhci_endpoint *endpoint = usb_endpoint_get_hostdata ( ep );
  2191. union xhci_trb trbs[ 1 /* Normal */ + 1 /* Possible zero-length */ ];
  2192. union xhci_trb *trb = trbs;
  2193. struct xhci_trb_normal *normal;
  2194. size_t len = iob_len ( iobuf );
  2195. int rc;
  2196. /* Profile stream transfers */
  2197. profile_start ( &xhci_stream_profiler );
  2198. /* Construct normal TRBs */
  2199. memset ( &trbs, 0, sizeof ( trbs ) );
  2200. normal = &(trb++)->normal;
  2201. normal->data = cpu_to_le64 ( virt_to_phys ( iobuf->data ) );
  2202. normal->len = cpu_to_le32 ( len );
  2203. normal->type = XHCI_TRB_NORMAL;
  2204. if ( terminate && ( ( len & ( ep->mtu - 1 ) ) == 0 ) ) {
  2205. normal->flags = XHCI_TRB_CH;
  2206. normal = &(trb++)->normal;
  2207. normal->type = XHCI_TRB_NORMAL;
  2208. }
  2209. normal->flags = XHCI_TRB_IOC;
  2210. /* Enqueue TRBs */
  2211. if ( ( rc = xhci_enqueue_multi ( &endpoint->ring, iobuf, trbs,
  2212. ( trb - trbs ) ) ) != 0 )
  2213. return rc;
  2214. /* Ring the doorbell */
  2215. xhci_doorbell ( &endpoint->ring );
  2216. profile_stop ( &xhci_stream_profiler );
  2217. return 0;
  2218. }
  2219. /******************************************************************************
  2220. *
  2221. * Device operations
  2222. *
  2223. ******************************************************************************
  2224. */
  2225. /**
  2226. * Open device
  2227. *
  2228. * @v usb USB device
  2229. * @ret rc Return status code
  2230. */
  2231. static int xhci_device_open ( struct usb_device *usb ) {
  2232. struct xhci_device *xhci = usb_bus_get_hostdata ( usb->port->hub->bus );
  2233. struct xhci_slot *slot;
  2234. size_t len;
  2235. int type;
  2236. int id;
  2237. int rc;
  2238. /* Determine applicable slot type */
  2239. type = xhci_port_slot_type ( xhci, usb->port->address );
  2240. if ( type < 0 ) {
  2241. rc = type;
  2242. DBGC ( xhci, "XHCI %p port %d has no slot type\n",
  2243. xhci, usb->port->address );
  2244. goto err_type;
  2245. }
  2246. /* Allocate a device slot number */
  2247. id = xhci_enable_slot ( xhci, type );
  2248. if ( id < 0 ) {
  2249. rc = id;
  2250. goto err_enable_slot;
  2251. }
  2252. assert ( xhci->slot[id] == NULL );
  2253. /* Allocate and initialise structure */
  2254. slot = zalloc ( sizeof ( *slot ) );
  2255. if ( ! slot ) {
  2256. rc = -ENOMEM;
  2257. goto err_alloc;
  2258. }
  2259. usb_set_hostdata ( usb, slot );
  2260. xhci->slot[id] = slot;
  2261. slot->xhci = xhci;
  2262. slot->usb = usb;
  2263. slot->id = id;
  2264. /* Allocate a device context */
  2265. len = xhci_device_context_offset ( xhci, XHCI_CTX_END );
  2266. slot->context = malloc_dma ( len, xhci_align ( len ) );
  2267. if ( ! slot->context ) {
  2268. rc = -ENOMEM;
  2269. goto err_alloc_context;
  2270. }
  2271. memset ( slot->context, 0, len );
  2272. /* Set device context base address */
  2273. assert ( xhci->dcbaa[id] == 0 );
  2274. xhci->dcbaa[id] = cpu_to_le64 ( virt_to_phys ( slot->context ) );
  2275. DBGC2 ( xhci, "XHCI %p slot %d device context [%08lx,%08lx) for %s\n",
  2276. xhci, slot->id, virt_to_phys ( slot->context ),
  2277. ( virt_to_phys ( slot->context ) + len ), usb->name );
  2278. return 0;
  2279. xhci->dcbaa[id] = 0;
  2280. free_dma ( slot->context, len );
  2281. err_alloc_context:
  2282. xhci->slot[id] = NULL;
  2283. free ( slot );
  2284. err_alloc:
  2285. xhci_disable_slot ( xhci, id );
  2286. err_enable_slot:
  2287. err_type:
  2288. return rc;
  2289. }
  2290. /**
  2291. * Close device
  2292. *
  2293. * @v usb USB device
  2294. */
  2295. static void xhci_device_close ( struct usb_device *usb ) {
  2296. struct xhci_slot *slot = usb_get_hostdata ( usb );
  2297. struct xhci_device *xhci = slot->xhci;
  2298. size_t len = xhci_device_context_offset ( xhci, XHCI_CTX_END );
  2299. unsigned int id = slot->id;
  2300. int rc;
  2301. /* Disable slot */
  2302. if ( ( rc = xhci_disable_slot ( xhci, id ) ) != 0 ) {
  2303. /* Slot is still enabled. Leak the slot context,
  2304. * since the controller may still write to this
  2305. * memory, and leave the DCBAA entry intact.
  2306. *
  2307. * If the controller later reports that this same slot
  2308. * has been re-enabled, then some assertions will be
  2309. * triggered.
  2310. */
  2311. DBGC ( xhci, "XHCI %p slot %d leaking context memory\n",
  2312. xhci, slot->id );
  2313. slot->context = NULL;
  2314. }
  2315. /* Free slot */
  2316. if ( slot->context ) {
  2317. free_dma ( slot->context, len );
  2318. xhci->dcbaa[id] = 0;
  2319. }
  2320. xhci->slot[id] = NULL;
  2321. free ( slot );
  2322. }
  2323. /**
  2324. * Assign device address
  2325. *
  2326. * @v usb USB device
  2327. * @ret rc Return status code
  2328. */
  2329. static int xhci_device_address ( struct usb_device *usb ) {
  2330. struct xhci_slot *slot = usb_get_hostdata ( usb );
  2331. struct xhci_device *xhci = slot->xhci;
  2332. struct usb_port *port = usb->port;
  2333. struct usb_port *root_port;
  2334. int psiv;
  2335. int rc;
  2336. /* Calculate route string */
  2337. slot->route = usb_route_string ( usb );
  2338. /* Calculate root hub port number */
  2339. root_port = usb_root_hub_port ( usb );
  2340. slot->port = root_port->address;
  2341. /* Calculate protocol speed ID */
  2342. psiv = xhci_port_psiv ( xhci, slot->port, port->speed );
  2343. if ( psiv < 0 ) {
  2344. rc = psiv;
  2345. return rc;
  2346. }
  2347. slot->psiv = psiv;
  2348. /* Address device */
  2349. if ( ( rc = xhci_address_device ( xhci, slot ) ) != 0 )
  2350. return rc;
  2351. return 0;
  2352. }
  2353. /******************************************************************************
  2354. *
  2355. * Bus operations
  2356. *
  2357. ******************************************************************************
  2358. */
  2359. /**
  2360. * Open USB bus
  2361. *
  2362. * @v bus USB bus
  2363. * @ret rc Return status code
  2364. */
  2365. static int xhci_bus_open ( struct usb_bus *bus ) {
  2366. struct xhci_device *xhci = usb_bus_get_hostdata ( bus );
  2367. int rc;
  2368. /* Allocate device slot array */
  2369. xhci->slot = zalloc ( xhci->slots * sizeof ( xhci->slot[0] ) );
  2370. if ( ! xhci->slot ) {
  2371. rc = -ENOMEM;
  2372. goto err_slot_alloc;
  2373. }
  2374. /* Allocate device context base address array */
  2375. if ( ( rc = xhci_dcbaa_alloc ( xhci ) ) != 0 )
  2376. goto err_dcbaa_alloc;
  2377. /* Allocate scratchpad buffers */
  2378. if ( ( rc = xhci_scratchpad_alloc ( xhci ) ) != 0 )
  2379. goto err_scratchpad_alloc;
  2380. /* Allocate command ring */
  2381. if ( ( rc = xhci_command_alloc ( xhci ) ) != 0 )
  2382. goto err_command_alloc;
  2383. /* Allocate event ring */
  2384. if ( ( rc = xhci_event_alloc ( xhci ) ) != 0 )
  2385. goto err_event_alloc;
  2386. /* Start controller */
  2387. xhci_run ( xhci );
  2388. return 0;
  2389. xhci_stop ( xhci );
  2390. xhci_event_free ( xhci );
  2391. err_event_alloc:
  2392. xhci_command_free ( xhci );
  2393. err_command_alloc:
  2394. xhci_scratchpad_free ( xhci );
  2395. err_scratchpad_alloc:
  2396. xhci_dcbaa_free ( xhci );
  2397. err_dcbaa_alloc:
  2398. free ( xhci->slot );
  2399. err_slot_alloc:
  2400. return rc;
  2401. }
  2402. /**
  2403. * Close USB bus
  2404. *
  2405. * @v bus USB bus
  2406. */
  2407. static void xhci_bus_close ( struct usb_bus *bus ) {
  2408. struct xhci_device *xhci = usb_bus_get_hostdata ( bus );
  2409. unsigned int i;
  2410. /* Sanity checks */
  2411. assert ( xhci->slot != NULL );
  2412. for ( i = 0 ; i < xhci->slots ; i++ )
  2413. assert ( xhci->slot[i] == NULL );
  2414. xhci_stop ( xhci );
  2415. xhci_event_free ( xhci );
  2416. xhci_command_free ( xhci );
  2417. xhci_scratchpad_free ( xhci );
  2418. xhci_dcbaa_free ( xhci );
  2419. free ( xhci->slot );
  2420. }
  2421. /**
  2422. * Poll USB bus
  2423. *
  2424. * @v bus USB bus
  2425. */
  2426. static void xhci_bus_poll ( struct usb_bus *bus ) {
  2427. struct xhci_device *xhci = usb_bus_get_hostdata ( bus );
  2428. /* Poll event ring */
  2429. xhci_event_poll ( xhci );
  2430. }
  2431. /******************************************************************************
  2432. *
  2433. * Root hub operations
  2434. *
  2435. ******************************************************************************
  2436. */
  2437. /**
  2438. * Open root hub
  2439. *
  2440. * @v hub USB hub
  2441. * @ret rc Return status code
  2442. */
  2443. static int xhci_hub_open ( struct usb_hub *hub ) {
  2444. struct usb_bus *bus = hub->bus;
  2445. struct xhci_device *xhci = usb_bus_get_hostdata ( bus );
  2446. struct usb_port *port;
  2447. uint32_t portsc;
  2448. unsigned int i;
  2449. /* Enable power to all ports */
  2450. for ( i = 1 ; i <= xhci->ports ; i++ ) {
  2451. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( i ) );
  2452. portsc &= XHCI_PORTSC_PRESERVE;
  2453. portsc |= XHCI_PORTSC_PP;
  2454. writel ( portsc, xhci->op + XHCI_OP_PORTSC ( i ) );
  2455. }
  2456. /* xHCI spec requires us to potentially wait 20ms after
  2457. * enabling power to a port.
  2458. */
  2459. mdelay ( XHCI_PORT_POWER_DELAY_MS );
  2460. /* USB3 ports may power up as Disabled */
  2461. for ( i = 1 ; i <= xhci->ports ; i++ ) {
  2462. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( i ) );
  2463. port = usb_port ( hub, i );
  2464. if ( ( port->protocol >= USB_PROTO_3_0 ) &&
  2465. ( ( portsc & XHCI_PORTSC_PLS_MASK ) ==
  2466. XHCI_PORTSC_PLS_DISABLED ) ) {
  2467. /* Force link state to RxDetect */
  2468. portsc &= XHCI_PORTSC_PRESERVE;
  2469. portsc |= ( XHCI_PORTSC_PLS_RXDETECT | XHCI_PORTSC_LWS);
  2470. writel ( portsc, xhci->op + XHCI_OP_PORTSC ( i ) );
  2471. }
  2472. }
  2473. /* Some xHCI cards seem to require an additional delay after
  2474. * setting the link state to RxDetect.
  2475. */
  2476. mdelay ( XHCI_LINK_STATE_DELAY_MS );
  2477. /* Record hub driver private data */
  2478. usb_hub_set_drvdata ( hub, xhci );
  2479. return 0;
  2480. }
  2481. /**
  2482. * Close root hub
  2483. *
  2484. * @v hub USB hub
  2485. */
  2486. static void xhci_hub_close ( struct usb_hub *hub ) {
  2487. /* Clear hub driver private data */
  2488. usb_hub_set_drvdata ( hub, NULL );
  2489. }
  2490. /**
  2491. * Enable port
  2492. *
  2493. * @v hub USB hub
  2494. * @v port USB port
  2495. * @ret rc Return status code
  2496. */
  2497. static int xhci_hub_enable ( struct usb_hub *hub, struct usb_port *port ) {
  2498. struct xhci_device *xhci = usb_hub_get_drvdata ( hub );
  2499. uint32_t portsc;
  2500. unsigned int i;
  2501. /* Reset port if applicable */
  2502. if ( port->protocol < USB_PROTO_3_0 ) {
  2503. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2504. portsc &= XHCI_PORTSC_PRESERVE;
  2505. portsc |= XHCI_PORTSC_PR;
  2506. writel ( portsc, xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2507. }
  2508. /* Wait for port to become enabled */
  2509. for ( i = 0 ; i < XHCI_PORT_RESET_MAX_WAIT_MS ; i++ ) {
  2510. /* Check port status */
  2511. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2512. if ( portsc & XHCI_PORTSC_PED )
  2513. return 0;
  2514. /* Delay */
  2515. mdelay ( 1 );
  2516. }
  2517. DBGC ( xhci, "XHCI %p timed out waiting for port %d to enable\n",
  2518. xhci, port->address );
  2519. return -ETIMEDOUT;
  2520. }
  2521. /**
  2522. * Disable port
  2523. *
  2524. * @v hub USB hub
  2525. * @v port USB port
  2526. * @ret rc Return status code
  2527. */
  2528. static int xhci_hub_disable ( struct usb_hub *hub, struct usb_port *port ) {
  2529. struct xhci_device *xhci = usb_hub_get_drvdata ( hub );
  2530. uint32_t portsc;
  2531. /* Disable port */
  2532. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2533. portsc &= XHCI_PORTSC_PRESERVE;
  2534. portsc |= XHCI_PORTSC_PED;
  2535. writel ( portsc, xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2536. return 0;
  2537. }
  2538. /**
  2539. * Update root hub port speed
  2540. *
  2541. * @v hub USB hub
  2542. * @v port USB port
  2543. * @ret rc Return status code
  2544. */
  2545. static int xhci_hub_speed ( struct usb_hub *hub, struct usb_port *port ) {
  2546. struct xhci_device *xhci = usb_hub_get_drvdata ( hub );
  2547. uint32_t portsc;
  2548. unsigned int psiv;
  2549. int ccs;
  2550. int ped;
  2551. int speed;
  2552. int rc;
  2553. /* Read port status */
  2554. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2555. DBGC2 ( xhci, "XHCI %p port %d status is %08x\n",
  2556. xhci, port->address, portsc );
  2557. /* Check whether or not port is connected */
  2558. ccs = ( portsc & XHCI_PORTSC_CCS );
  2559. if ( ! ccs ) {
  2560. port->speed = USB_SPEED_NONE;
  2561. return 0;
  2562. }
  2563. /* For USB2 ports, the PSIV field is not valid until the port
  2564. * completes reset and becomes enabled.
  2565. */
  2566. ped = ( portsc & XHCI_PORTSC_PED );
  2567. if ( ( port->protocol < USB_PROTO_3_0 ) && ! ped ) {
  2568. port->speed = USB_SPEED_FULL;
  2569. return 0;
  2570. }
  2571. /* Get port speed and map to generic USB speed */
  2572. psiv = XHCI_PORTSC_PSIV ( portsc );
  2573. speed = xhci_port_speed ( xhci, port->address, psiv );
  2574. if ( speed < 0 ) {
  2575. rc = speed;
  2576. return rc;
  2577. }
  2578. port->speed = speed;
  2579. return 0;
  2580. }
  2581. /******************************************************************************
  2582. *
  2583. * PCI interface
  2584. *
  2585. ******************************************************************************
  2586. */
  2587. /** USB host controller operations */
  2588. static struct usb_host_operations xhci_operations = {
  2589. .endpoint = {
  2590. .open = xhci_endpoint_open,
  2591. .close = xhci_endpoint_close,
  2592. .reset = xhci_endpoint_reset,
  2593. .mtu = xhci_endpoint_mtu,
  2594. .message = xhci_endpoint_message,
  2595. .stream = xhci_endpoint_stream,
  2596. },
  2597. .device = {
  2598. .open = xhci_device_open,
  2599. .close = xhci_device_close,
  2600. .address = xhci_device_address,
  2601. },
  2602. .bus = {
  2603. .open = xhci_bus_open,
  2604. .close = xhci_bus_close,
  2605. .poll = xhci_bus_poll,
  2606. },
  2607. .hub = {
  2608. .open = xhci_hub_open,
  2609. .close = xhci_hub_close,
  2610. .enable = xhci_hub_enable,
  2611. .disable = xhci_hub_disable,
  2612. .speed = xhci_hub_speed,
  2613. },
  2614. };
  2615. /**
  2616. * Probe PCI device
  2617. *
  2618. * @v pci PCI device
  2619. * @ret rc Return status code
  2620. */
  2621. static int xhci_probe ( struct pci_device *pci ) {
  2622. struct xhci_device *xhci;
  2623. struct usb_port *port;
  2624. unsigned long bar_start;
  2625. size_t bar_size;
  2626. unsigned int i;
  2627. int rc;
  2628. /* Allocate and initialise structure */
  2629. xhci = zalloc ( sizeof ( *xhci ) );
  2630. if ( ! xhci ) {
  2631. rc = -ENOMEM;
  2632. goto err_alloc;
  2633. }
  2634. /* Fix up PCI device */
  2635. adjust_pci_device ( pci );
  2636. /* Map registers */
  2637. bar_start = pci_bar_start ( pci, XHCI_BAR );
  2638. bar_size = pci_bar_size ( pci, XHCI_BAR );
  2639. xhci->regs = ioremap ( bar_start, bar_size );
  2640. if ( ! xhci->regs ) {
  2641. rc = -ENODEV;
  2642. goto err_ioremap;
  2643. }
  2644. /* Initialise xHCI device */
  2645. xhci_init ( xhci, xhci->regs );
  2646. /* Initialise USB legacy support and claim ownership */
  2647. xhci_legacy_init ( xhci );
  2648. if ( ( rc = xhci_legacy_claim ( xhci ) ) != 0 )
  2649. goto err_legacy_claim;
  2650. /* Reset device */
  2651. if ( ( rc = xhci_reset ( xhci ) ) != 0 )
  2652. goto err_reset;
  2653. /* Allocate USB bus */
  2654. xhci->bus = alloc_usb_bus ( &pci->dev, xhci->ports,
  2655. &xhci_operations );
  2656. if ( ! xhci->bus ) {
  2657. rc = -ENOMEM;
  2658. goto err_alloc_bus;
  2659. }
  2660. usb_bus_set_hostdata ( xhci->bus, xhci );
  2661. usb_hub_set_drvdata ( xhci->bus->hub, xhci );
  2662. /* Set port protocols */
  2663. for ( i = 1 ; i <= xhci->ports ; i++ ) {
  2664. port = usb_port ( xhci->bus->hub, i );
  2665. port->protocol = xhci_port_protocol ( xhci, i );
  2666. }
  2667. /* Register USB bus */
  2668. if ( ( rc = register_usb_bus ( xhci->bus ) ) != 0 )
  2669. goto err_register;
  2670. pci_set_drvdata ( pci, xhci );
  2671. return 0;
  2672. unregister_usb_bus ( xhci->bus );
  2673. err_register:
  2674. free_usb_bus ( xhci->bus );
  2675. err_alloc_bus:
  2676. xhci_reset ( xhci );
  2677. err_reset:
  2678. xhci_legacy_release ( xhci );
  2679. err_legacy_claim:
  2680. iounmap ( xhci->regs );
  2681. err_ioremap:
  2682. free ( xhci );
  2683. err_alloc:
  2684. return rc;
  2685. }
  2686. /**
  2687. * Remove PCI device
  2688. *
  2689. * @v pci PCI device
  2690. */
  2691. static void xhci_remove ( struct pci_device *pci ) {
  2692. struct xhci_device *xhci = pci_get_drvdata ( pci );
  2693. struct usb_bus *bus = xhci->bus;
  2694. unregister_usb_bus ( bus );
  2695. free_usb_bus ( bus );
  2696. xhci_reset ( xhci );
  2697. xhci_legacy_release ( xhci );
  2698. iounmap ( xhci->regs );
  2699. free ( xhci );
  2700. }
  2701. /** XHCI PCI device IDs */
  2702. static struct pci_device_id xhci_ids[] = {
  2703. PCI_ROM ( 0xffff, 0xffff, "xhci", "xHCI", 0 ),
  2704. };
  2705. /** XHCI PCI driver */
  2706. struct pci_driver xhci_driver __pci_driver = {
  2707. .ids = xhci_ids,
  2708. .id_count = ( sizeof ( xhci_ids ) / sizeof ( xhci_ids[0] ) ),
  2709. .class = PCI_CLASS ( PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB,
  2710. PCI_CLASS_SERIAL_USB_XHCI ),
  2711. .probe = xhci_probe,
  2712. .remove = xhci_remove,
  2713. };