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hermon.c 85KB

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  1. /*
  2. * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
  3. * Copyright (C) 2008 Mellanox Technologies Ltd.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License as
  7. * published by the Free Software Foundation; either version 2 of the
  8. * License, or any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. */
  19. FILE_LICENCE ( GPL2_OR_LATER );
  20. #include <stdint.h>
  21. #include <stdlib.h>
  22. #include <stdio.h>
  23. #include <string.h>
  24. #include <strings.h>
  25. #include <unistd.h>
  26. #include <errno.h>
  27. #include <byteswap.h>
  28. #include <ipxe/io.h>
  29. #include <ipxe/pci.h>
  30. #include <ipxe/pcibackup.h>
  31. #include <ipxe/malloc.h>
  32. #include <ipxe/umalloc.h>
  33. #include <ipxe/iobuf.h>
  34. #include <ipxe/netdevice.h>
  35. #include <ipxe/infiniband.h>
  36. #include <ipxe/ib_smc.h>
  37. #include "hermon.h"
  38. /**
  39. * @file
  40. *
  41. * Mellanox Hermon Infiniband HCA
  42. *
  43. */
  44. /***************************************************************************
  45. *
  46. * Queue number allocation
  47. *
  48. ***************************************************************************
  49. */
  50. /**
  51. * Allocate offsets within usage bitmask
  52. *
  53. * @v bits Usage bitmask
  54. * @v bits_len Length of usage bitmask
  55. * @v num_bits Number of contiguous bits to allocate within bitmask
  56. * @ret bit First free bit within bitmask, or negative error
  57. */
  58. static int hermon_bitmask_alloc ( hermon_bitmask_t *bits,
  59. unsigned int bits_len,
  60. unsigned int num_bits ) {
  61. unsigned int bit = 0;
  62. hermon_bitmask_t mask = 1;
  63. unsigned int found = 0;
  64. /* Search bits for num_bits contiguous free bits */
  65. while ( bit < bits_len ) {
  66. if ( ( mask & *bits ) == 0 ) {
  67. if ( ++found == num_bits )
  68. goto found;
  69. } else {
  70. found = 0;
  71. }
  72. bit++;
  73. mask = ( mask << 1 ) | ( mask >> ( 8 * sizeof ( mask ) - 1 ) );
  74. if ( mask == 1 )
  75. bits++;
  76. }
  77. return -ENFILE;
  78. found:
  79. /* Mark bits as in-use */
  80. do {
  81. *bits |= mask;
  82. if ( mask == 1 )
  83. bits--;
  84. mask = ( mask >> 1 ) | ( mask << ( 8 * sizeof ( mask ) - 1 ) );
  85. } while ( --found );
  86. return ( bit - num_bits + 1 );
  87. }
  88. /**
  89. * Free offsets within usage bitmask
  90. *
  91. * @v bits Usage bitmask
  92. * @v bit Starting bit within bitmask
  93. * @v num_bits Number of contiguous bits to free within bitmask
  94. */
  95. static void hermon_bitmask_free ( hermon_bitmask_t *bits,
  96. int bit, unsigned int num_bits ) {
  97. hermon_bitmask_t mask;
  98. for ( ; num_bits ; bit++, num_bits-- ) {
  99. mask = ( 1 << ( bit % ( 8 * sizeof ( mask ) ) ) );
  100. bits[ ( bit / ( 8 * sizeof ( mask ) ) ) ] &= ~mask;
  101. }
  102. }
  103. /***************************************************************************
  104. *
  105. * HCA commands
  106. *
  107. ***************************************************************************
  108. */
  109. /**
  110. * Wait for Hermon command completion
  111. *
  112. * @v hermon Hermon device
  113. * @v hcr HCA command registers
  114. * @ret rc Return status code
  115. */
  116. static int hermon_cmd_wait ( struct hermon *hermon,
  117. struct hermonprm_hca_command_register *hcr ) {
  118. unsigned int wait;
  119. for ( wait = HERMON_HCR_MAX_WAIT_MS ; wait ; wait-- ) {
  120. hcr->u.dwords[6] =
  121. readl ( hermon->config + HERMON_HCR_REG ( 6 ) );
  122. if ( ( MLX_GET ( hcr, go ) == 0 ) &&
  123. ( MLX_GET ( hcr, t ) == hermon->toggle ) )
  124. return 0;
  125. mdelay ( 1 );
  126. }
  127. return -EBUSY;
  128. }
  129. /**
  130. * Issue HCA command
  131. *
  132. * @v hermon Hermon device
  133. * @v command Command opcode, flags and input/output lengths
  134. * @v op_mod Opcode modifier (0 if no modifier applicable)
  135. * @v in Input parameters
  136. * @v in_mod Input modifier (0 if no modifier applicable)
  137. * @v out Output parameters
  138. * @ret rc Return status code
  139. */
  140. static int hermon_cmd ( struct hermon *hermon, unsigned long command,
  141. unsigned int op_mod, const void *in,
  142. unsigned int in_mod, void *out ) {
  143. struct hermonprm_hca_command_register hcr;
  144. unsigned int opcode = HERMON_HCR_OPCODE ( command );
  145. size_t in_len = HERMON_HCR_IN_LEN ( command );
  146. size_t out_len = HERMON_HCR_OUT_LEN ( command );
  147. void *in_buffer;
  148. void *out_buffer;
  149. unsigned int status;
  150. unsigned int i;
  151. int rc;
  152. assert ( in_len <= HERMON_MBOX_SIZE );
  153. assert ( out_len <= HERMON_MBOX_SIZE );
  154. DBGC2 ( hermon, "Hermon %p command %02x in %zx%s out %zx%s\n",
  155. hermon, opcode, in_len,
  156. ( ( command & HERMON_HCR_IN_MBOX ) ? "(mbox)" : "" ), out_len,
  157. ( ( command & HERMON_HCR_OUT_MBOX ) ? "(mbox)" : "" ) );
  158. /* Check that HCR is free */
  159. if ( ( rc = hermon_cmd_wait ( hermon, &hcr ) ) != 0 ) {
  160. DBGC ( hermon, "Hermon %p command interface locked\n",
  161. hermon );
  162. return rc;
  163. }
  164. /* Flip HCR toggle */
  165. hermon->toggle = ( 1 - hermon->toggle );
  166. /* Prepare HCR */
  167. memset ( &hcr, 0, sizeof ( hcr ) );
  168. in_buffer = &hcr.u.dwords[0];
  169. if ( in_len && ( command & HERMON_HCR_IN_MBOX ) ) {
  170. in_buffer = hermon->mailbox_in;
  171. MLX_FILL_1 ( &hcr, 1, in_param_l, virt_to_bus ( in_buffer ) );
  172. }
  173. memcpy ( in_buffer, in, in_len );
  174. MLX_FILL_1 ( &hcr, 2, input_modifier, in_mod );
  175. out_buffer = &hcr.u.dwords[3];
  176. if ( out_len && ( command & HERMON_HCR_OUT_MBOX ) ) {
  177. out_buffer = hermon->mailbox_out;
  178. MLX_FILL_1 ( &hcr, 4, out_param_l,
  179. virt_to_bus ( out_buffer ) );
  180. }
  181. MLX_FILL_4 ( &hcr, 6,
  182. opcode, opcode,
  183. opcode_modifier, op_mod,
  184. go, 1,
  185. t, hermon->toggle );
  186. DBGC ( hermon, "Hermon %p issuing command %04x\n",
  187. hermon, opcode );
  188. DBGC2_HDA ( hermon, virt_to_phys ( hermon->config + HERMON_HCR_BASE ),
  189. &hcr, sizeof ( hcr ) );
  190. if ( in_len && ( command & HERMON_HCR_IN_MBOX ) ) {
  191. DBGC2 ( hermon, "Input mailbox:\n" );
  192. DBGC2_HDA ( hermon, virt_to_phys ( in_buffer ), in_buffer,
  193. ( ( in_len < 512 ) ? in_len : 512 ) );
  194. }
  195. /* Issue command */
  196. for ( i = 0 ; i < ( sizeof ( hcr ) / sizeof ( hcr.u.dwords[0] ) ) ;
  197. i++ ) {
  198. writel ( hcr.u.dwords[i],
  199. hermon->config + HERMON_HCR_REG ( i ) );
  200. barrier();
  201. }
  202. /* Wait for command completion */
  203. if ( ( rc = hermon_cmd_wait ( hermon, &hcr ) ) != 0 ) {
  204. DBGC ( hermon, "Hermon %p timed out waiting for command:\n",
  205. hermon );
  206. DBGC_HDA ( hermon,
  207. virt_to_phys ( hermon->config + HERMON_HCR_BASE ),
  208. &hcr, sizeof ( hcr ) );
  209. return rc;
  210. }
  211. /* Check command status */
  212. status = MLX_GET ( &hcr, status );
  213. if ( status != 0 ) {
  214. DBGC ( hermon, "Hermon %p command failed with status %02x:\n",
  215. hermon, status );
  216. DBGC_HDA ( hermon,
  217. virt_to_phys ( hermon->config + HERMON_HCR_BASE ),
  218. &hcr, sizeof ( hcr ) );
  219. return -EIO;
  220. }
  221. /* Read output parameters, if any */
  222. hcr.u.dwords[3] = readl ( hermon->config + HERMON_HCR_REG ( 3 ) );
  223. hcr.u.dwords[4] = readl ( hermon->config + HERMON_HCR_REG ( 4 ) );
  224. memcpy ( out, out_buffer, out_len );
  225. if ( out_len ) {
  226. DBGC2 ( hermon, "Output%s:\n",
  227. ( command & HERMON_HCR_OUT_MBOX ) ? " mailbox" : "" );
  228. DBGC2_HDA ( hermon, virt_to_phys ( out_buffer ), out_buffer,
  229. ( ( out_len < 512 ) ? out_len : 512 ) );
  230. }
  231. return 0;
  232. }
  233. static inline int
  234. hermon_cmd_query_dev_cap ( struct hermon *hermon,
  235. struct hermonprm_query_dev_cap *dev_cap ) {
  236. return hermon_cmd ( hermon,
  237. HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_DEV_CAP,
  238. 1, sizeof ( *dev_cap ) ),
  239. 0, NULL, 0, dev_cap );
  240. }
  241. static inline int
  242. hermon_cmd_query_fw ( struct hermon *hermon, struct hermonprm_query_fw *fw ) {
  243. return hermon_cmd ( hermon,
  244. HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_FW,
  245. 1, sizeof ( *fw ) ),
  246. 0, NULL, 0, fw );
  247. }
  248. static inline int
  249. hermon_cmd_init_hca ( struct hermon *hermon,
  250. const struct hermonprm_init_hca *init_hca ) {
  251. return hermon_cmd ( hermon,
  252. HERMON_HCR_IN_CMD ( HERMON_HCR_INIT_HCA,
  253. 1, sizeof ( *init_hca ) ),
  254. 0, init_hca, 0, NULL );
  255. }
  256. static inline int
  257. hermon_cmd_close_hca ( struct hermon *hermon ) {
  258. return hermon_cmd ( hermon,
  259. HERMON_HCR_VOID_CMD ( HERMON_HCR_CLOSE_HCA ),
  260. 0, NULL, 0, NULL );
  261. }
  262. static inline int
  263. hermon_cmd_init_port ( struct hermon *hermon, unsigned int port,
  264. const struct hermonprm_init_port *init_port ) {
  265. return hermon_cmd ( hermon,
  266. HERMON_HCR_IN_CMD ( HERMON_HCR_INIT_PORT,
  267. 1, sizeof ( *init_port ) ),
  268. 0, init_port, port, NULL );
  269. }
  270. static inline int
  271. hermon_cmd_close_port ( struct hermon *hermon, unsigned int port ) {
  272. return hermon_cmd ( hermon,
  273. HERMON_HCR_VOID_CMD ( HERMON_HCR_CLOSE_PORT ),
  274. 0, NULL, port, NULL );
  275. }
  276. static inline int
  277. hermon_cmd_sw2hw_mpt ( struct hermon *hermon, unsigned int index,
  278. const struct hermonprm_mpt *mpt ) {
  279. return hermon_cmd ( hermon,
  280. HERMON_HCR_IN_CMD ( HERMON_HCR_SW2HW_MPT,
  281. 1, sizeof ( *mpt ) ),
  282. 0, mpt, index, NULL );
  283. }
  284. static inline int
  285. hermon_cmd_write_mtt ( struct hermon *hermon,
  286. const struct hermonprm_write_mtt *write_mtt ) {
  287. return hermon_cmd ( hermon,
  288. HERMON_HCR_IN_CMD ( HERMON_HCR_WRITE_MTT,
  289. 1, sizeof ( *write_mtt ) ),
  290. 0, write_mtt, 1, NULL );
  291. }
  292. static inline int
  293. hermon_cmd_map_eq ( struct hermon *hermon, unsigned long index_map,
  294. const struct hermonprm_event_mask *mask ) {
  295. return hermon_cmd ( hermon,
  296. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_EQ,
  297. 0, sizeof ( *mask ) ),
  298. 0, mask, index_map, NULL );
  299. }
  300. static inline int
  301. hermon_cmd_sw2hw_eq ( struct hermon *hermon, unsigned int index,
  302. const struct hermonprm_eqc *eqctx ) {
  303. return hermon_cmd ( hermon,
  304. HERMON_HCR_IN_CMD ( HERMON_HCR_SW2HW_EQ,
  305. 1, sizeof ( *eqctx ) ),
  306. 0, eqctx, index, NULL );
  307. }
  308. static inline int
  309. hermon_cmd_hw2sw_eq ( struct hermon *hermon, unsigned int index,
  310. struct hermonprm_eqc *eqctx ) {
  311. return hermon_cmd ( hermon,
  312. HERMON_HCR_OUT_CMD ( HERMON_HCR_HW2SW_EQ,
  313. 1, sizeof ( *eqctx ) ),
  314. 1, NULL, index, eqctx );
  315. }
  316. static inline int
  317. hermon_cmd_query_eq ( struct hermon *hermon, unsigned int index,
  318. struct hermonprm_eqc *eqctx ) {
  319. return hermon_cmd ( hermon,
  320. HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_EQ,
  321. 1, sizeof ( *eqctx ) ),
  322. 0, NULL, index, eqctx );
  323. }
  324. static inline int
  325. hermon_cmd_sw2hw_cq ( struct hermon *hermon, unsigned long cqn,
  326. const struct hermonprm_completion_queue_context *cqctx ){
  327. return hermon_cmd ( hermon,
  328. HERMON_HCR_IN_CMD ( HERMON_HCR_SW2HW_CQ,
  329. 1, sizeof ( *cqctx ) ),
  330. 0, cqctx, cqn, NULL );
  331. }
  332. static inline int
  333. hermon_cmd_hw2sw_cq ( struct hermon *hermon, unsigned long cqn,
  334. struct hermonprm_completion_queue_context *cqctx ) {
  335. return hermon_cmd ( hermon,
  336. HERMON_HCR_OUT_CMD ( HERMON_HCR_HW2SW_CQ,
  337. 1, sizeof ( *cqctx ) ),
  338. 0, NULL, cqn, cqctx );
  339. }
  340. static inline int
  341. hermon_cmd_query_cq ( struct hermon *hermon, unsigned long cqn,
  342. struct hermonprm_completion_queue_context *cqctx ) {
  343. return hermon_cmd ( hermon,
  344. HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_CQ,
  345. 1, sizeof ( *cqctx ) ),
  346. 0, NULL, cqn, cqctx );
  347. }
  348. static inline int
  349. hermon_cmd_rst2init_qp ( struct hermon *hermon, unsigned long qpn,
  350. const struct hermonprm_qp_ee_state_transitions *ctx ){
  351. return hermon_cmd ( hermon,
  352. HERMON_HCR_IN_CMD ( HERMON_HCR_RST2INIT_QP,
  353. 1, sizeof ( *ctx ) ),
  354. 0, ctx, qpn, NULL );
  355. }
  356. static inline int
  357. hermon_cmd_init2rtr_qp ( struct hermon *hermon, unsigned long qpn,
  358. const struct hermonprm_qp_ee_state_transitions *ctx ){
  359. return hermon_cmd ( hermon,
  360. HERMON_HCR_IN_CMD ( HERMON_HCR_INIT2RTR_QP,
  361. 1, sizeof ( *ctx ) ),
  362. 0, ctx, qpn, NULL );
  363. }
  364. static inline int
  365. hermon_cmd_rtr2rts_qp ( struct hermon *hermon, unsigned long qpn,
  366. const struct hermonprm_qp_ee_state_transitions *ctx ) {
  367. return hermon_cmd ( hermon,
  368. HERMON_HCR_IN_CMD ( HERMON_HCR_RTR2RTS_QP,
  369. 1, sizeof ( *ctx ) ),
  370. 0, ctx, qpn, NULL );
  371. }
  372. static inline int
  373. hermon_cmd_rts2rts_qp ( struct hermon *hermon, unsigned long qpn,
  374. const struct hermonprm_qp_ee_state_transitions *ctx ) {
  375. return hermon_cmd ( hermon,
  376. HERMON_HCR_IN_CMD ( HERMON_HCR_RTS2RTS_QP,
  377. 1, sizeof ( *ctx ) ),
  378. 0, ctx, qpn, NULL );
  379. }
  380. static inline int
  381. hermon_cmd_2rst_qp ( struct hermon *hermon, unsigned long qpn ) {
  382. return hermon_cmd ( hermon,
  383. HERMON_HCR_VOID_CMD ( HERMON_HCR_2RST_QP ),
  384. 0x03, NULL, qpn, NULL );
  385. }
  386. static inline int
  387. hermon_cmd_query_qp ( struct hermon *hermon, unsigned long qpn,
  388. struct hermonprm_qp_ee_state_transitions *ctx ) {
  389. return hermon_cmd ( hermon,
  390. HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_QP,
  391. 1, sizeof ( *ctx ) ),
  392. 0, NULL, qpn, ctx );
  393. }
  394. static inline int
  395. hermon_cmd_conf_special_qp ( struct hermon *hermon, unsigned int internal_qps,
  396. unsigned long base_qpn ) {
  397. return hermon_cmd ( hermon,
  398. HERMON_HCR_VOID_CMD ( HERMON_HCR_CONF_SPECIAL_QP ),
  399. internal_qps, NULL, base_qpn, NULL );
  400. }
  401. static inline int
  402. hermon_cmd_mad_ifc ( struct hermon *hermon, unsigned int port,
  403. union hermonprm_mad *mad ) {
  404. return hermon_cmd ( hermon,
  405. HERMON_HCR_INOUT_CMD ( HERMON_HCR_MAD_IFC,
  406. 1, sizeof ( *mad ),
  407. 1, sizeof ( *mad ) ),
  408. 0x03, mad, port, mad );
  409. }
  410. static inline int
  411. hermon_cmd_read_mcg ( struct hermon *hermon, unsigned int index,
  412. struct hermonprm_mcg_entry *mcg ) {
  413. return hermon_cmd ( hermon,
  414. HERMON_HCR_OUT_CMD ( HERMON_HCR_READ_MCG,
  415. 1, sizeof ( *mcg ) ),
  416. 0, NULL, index, mcg );
  417. }
  418. static inline int
  419. hermon_cmd_write_mcg ( struct hermon *hermon, unsigned int index,
  420. const struct hermonprm_mcg_entry *mcg ) {
  421. return hermon_cmd ( hermon,
  422. HERMON_HCR_IN_CMD ( HERMON_HCR_WRITE_MCG,
  423. 1, sizeof ( *mcg ) ),
  424. 0, mcg, index, NULL );
  425. }
  426. static inline int
  427. hermon_cmd_mgid_hash ( struct hermon *hermon, const struct ib_gid *gid,
  428. struct hermonprm_mgm_hash *hash ) {
  429. return hermon_cmd ( hermon,
  430. HERMON_HCR_INOUT_CMD ( HERMON_HCR_MGID_HASH,
  431. 1, sizeof ( *gid ),
  432. 0, sizeof ( *hash ) ),
  433. 0, gid, 0, hash );
  434. }
  435. static inline int
  436. hermon_cmd_run_fw ( struct hermon *hermon ) {
  437. return hermon_cmd ( hermon,
  438. HERMON_HCR_VOID_CMD ( HERMON_HCR_RUN_FW ),
  439. 0, NULL, 0, NULL );
  440. }
  441. static inline int
  442. hermon_cmd_unmap_icm ( struct hermon *hermon, unsigned int page_count,
  443. const struct hermonprm_scalar_parameter *offset ) {
  444. return hermon_cmd ( hermon,
  445. HERMON_HCR_IN_CMD ( HERMON_HCR_UNMAP_ICM,
  446. 0, sizeof ( *offset ) ),
  447. 0, offset, page_count, NULL );
  448. }
  449. static inline int
  450. hermon_cmd_map_icm ( struct hermon *hermon,
  451. const struct hermonprm_virtual_physical_mapping *map ) {
  452. return hermon_cmd ( hermon,
  453. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_ICM,
  454. 1, sizeof ( *map ) ),
  455. 0, map, 1, NULL );
  456. }
  457. static inline int
  458. hermon_cmd_unmap_icm_aux ( struct hermon *hermon ) {
  459. return hermon_cmd ( hermon,
  460. HERMON_HCR_VOID_CMD ( HERMON_HCR_UNMAP_ICM_AUX ),
  461. 0, NULL, 0, NULL );
  462. }
  463. static inline int
  464. hermon_cmd_map_icm_aux ( struct hermon *hermon,
  465. const struct hermonprm_virtual_physical_mapping *map ) {
  466. return hermon_cmd ( hermon,
  467. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_ICM_AUX,
  468. 1, sizeof ( *map ) ),
  469. 0, map, 1, NULL );
  470. }
  471. static inline int
  472. hermon_cmd_set_icm_size ( struct hermon *hermon,
  473. const struct hermonprm_scalar_parameter *icm_size,
  474. struct hermonprm_scalar_parameter *icm_aux_size ) {
  475. return hermon_cmd ( hermon,
  476. HERMON_HCR_INOUT_CMD ( HERMON_HCR_SET_ICM_SIZE,
  477. 0, sizeof ( *icm_size ),
  478. 0, sizeof (*icm_aux_size) ),
  479. 0, icm_size, 0, icm_aux_size );
  480. }
  481. static inline int
  482. hermon_cmd_unmap_fa ( struct hermon *hermon ) {
  483. return hermon_cmd ( hermon,
  484. HERMON_HCR_VOID_CMD ( HERMON_HCR_UNMAP_FA ),
  485. 0, NULL, 0, NULL );
  486. }
  487. static inline int
  488. hermon_cmd_map_fa ( struct hermon *hermon,
  489. const struct hermonprm_virtual_physical_mapping *map ) {
  490. return hermon_cmd ( hermon,
  491. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_FA,
  492. 1, sizeof ( *map ) ),
  493. 0, map, 1, NULL );
  494. }
  495. static inline int
  496. hermon_cmd_sense_port ( struct hermon *hermon, unsigned int port,
  497. struct hermonprm_sense_port *port_type ) {
  498. return hermon_cmd ( hermon,
  499. HERMON_HCR_OUT_CMD ( HERMON_HCR_SENSE_PORT,
  500. 1, sizeof ( *port_type ) ),
  501. 0, NULL, port, port_type );
  502. }
  503. /***************************************************************************
  504. *
  505. * Memory translation table operations
  506. *
  507. ***************************************************************************
  508. */
  509. /**
  510. * Allocate MTT entries
  511. *
  512. * @v hermon Hermon device
  513. * @v memory Memory to map into MTT
  514. * @v len Length of memory to map
  515. * @v mtt MTT descriptor to fill in
  516. * @ret rc Return status code
  517. */
  518. static int hermon_alloc_mtt ( struct hermon *hermon,
  519. const void *memory, size_t len,
  520. struct hermon_mtt *mtt ) {
  521. struct hermonprm_write_mtt write_mtt;
  522. physaddr_t start;
  523. physaddr_t addr;
  524. unsigned int page_offset;
  525. unsigned int num_pages;
  526. int mtt_offset;
  527. unsigned int mtt_base_addr;
  528. unsigned int i;
  529. int rc;
  530. /* Find available MTT entries */
  531. start = virt_to_phys ( memory );
  532. page_offset = ( start & ( HERMON_PAGE_SIZE - 1 ) );
  533. start -= page_offset;
  534. len += page_offset;
  535. num_pages = ( ( len + HERMON_PAGE_SIZE - 1 ) / HERMON_PAGE_SIZE );
  536. mtt_offset = hermon_bitmask_alloc ( hermon->mtt_inuse, HERMON_MAX_MTTS,
  537. num_pages );
  538. if ( mtt_offset < 0 ) {
  539. DBGC ( hermon, "Hermon %p could not allocate %d MTT entries\n",
  540. hermon, num_pages );
  541. rc = mtt_offset;
  542. goto err_mtt_offset;
  543. }
  544. mtt_base_addr = ( ( hermon->cap.reserved_mtts + mtt_offset ) *
  545. hermon->cap.mtt_entry_size );
  546. addr = start;
  547. /* Fill in MTT structure */
  548. mtt->mtt_offset = mtt_offset;
  549. mtt->num_pages = num_pages;
  550. mtt->mtt_base_addr = mtt_base_addr;
  551. mtt->page_offset = page_offset;
  552. /* Construct and issue WRITE_MTT commands */
  553. for ( i = 0 ; i < num_pages ; i++ ) {
  554. memset ( &write_mtt, 0, sizeof ( write_mtt ) );
  555. MLX_FILL_1 ( &write_mtt.mtt_base_addr, 1,
  556. value, mtt_base_addr );
  557. MLX_FILL_2 ( &write_mtt.mtt, 1,
  558. p, 1,
  559. ptag_l, ( addr >> 3 ) );
  560. if ( ( rc = hermon_cmd_write_mtt ( hermon,
  561. &write_mtt ) ) != 0 ) {
  562. DBGC ( hermon, "Hermon %p could not write MTT at %x\n",
  563. hermon, mtt_base_addr );
  564. goto err_write_mtt;
  565. }
  566. addr += HERMON_PAGE_SIZE;
  567. mtt_base_addr += hermon->cap.mtt_entry_size;
  568. }
  569. DBGC ( hermon, "Hermon %p MTT entries [%#x,%#x] for "
  570. "[%08lx,%08lx,%08lx,%08lx)\n", hermon, mtt->mtt_offset,
  571. ( mtt->mtt_offset + mtt->num_pages - 1 ), start,
  572. ( start + page_offset ), ( start + len ), addr );
  573. return 0;
  574. err_write_mtt:
  575. hermon_bitmask_free ( hermon->mtt_inuse, mtt_offset, num_pages );
  576. err_mtt_offset:
  577. return rc;
  578. }
  579. /**
  580. * Free MTT entries
  581. *
  582. * @v hermon Hermon device
  583. * @v mtt MTT descriptor
  584. */
  585. static void hermon_free_mtt ( struct hermon *hermon,
  586. struct hermon_mtt *mtt ) {
  587. DBGC ( hermon, "Hermon %p MTT entries [%#x,%#x] freed\n",
  588. hermon, mtt->mtt_offset,
  589. ( mtt->mtt_offset + mtt->num_pages - 1 ) );
  590. hermon_bitmask_free ( hermon->mtt_inuse, mtt->mtt_offset,
  591. mtt->num_pages );
  592. }
  593. /***************************************************************************
  594. *
  595. * MAD operations
  596. *
  597. ***************************************************************************
  598. */
  599. /**
  600. * Issue management datagram
  601. *
  602. * @v ibdev Infiniband device
  603. * @v mad Management datagram
  604. * @ret rc Return status code
  605. */
  606. static int hermon_mad ( struct ib_device *ibdev, union ib_mad *mad ) {
  607. struct hermon *hermon = ib_get_drvdata ( ibdev );
  608. union hermonprm_mad mad_ifc;
  609. int rc;
  610. linker_assert ( sizeof ( *mad ) == sizeof ( mad_ifc.mad ),
  611. mad_size_mismatch );
  612. /* Copy in request packet */
  613. memcpy ( &mad_ifc.mad, mad, sizeof ( mad_ifc.mad ) );
  614. /* Issue MAD */
  615. if ( ( rc = hermon_cmd_mad_ifc ( hermon, ibdev->port,
  616. &mad_ifc ) ) != 0 ) {
  617. DBGC ( hermon, "Hermon %p port %d could not issue MAD IFC: "
  618. "%s\n", hermon, ibdev->port, strerror ( rc ) );
  619. return rc;
  620. }
  621. /* Copy out reply packet */
  622. memcpy ( mad, &mad_ifc.mad, sizeof ( *mad ) );
  623. if ( mad->hdr.status != 0 ) {
  624. DBGC ( hermon, "Hermon %p port %d MAD IFC status %04x\n",
  625. hermon, ibdev->port, ntohs ( mad->hdr.status ) );
  626. return -EIO;
  627. }
  628. return 0;
  629. }
  630. /***************************************************************************
  631. *
  632. * Completion queue operations
  633. *
  634. ***************************************************************************
  635. */
  636. /**
  637. * Dump completion queue context (for debugging only)
  638. *
  639. * @v hermon Hermon device
  640. * @v cq Completion queue
  641. * @ret rc Return status code
  642. */
  643. static __attribute__ (( unused )) int
  644. hermon_dump_cqctx ( struct hermon *hermon, struct ib_completion_queue *cq ) {
  645. struct hermonprm_completion_queue_context cqctx;
  646. int rc;
  647. memset ( &cqctx, 0, sizeof ( cqctx ) );
  648. if ( ( rc = hermon_cmd_query_cq ( hermon, cq->cqn, &cqctx ) ) != 0 ) {
  649. DBGC ( hermon, "Hermon %p CQN %#lx QUERY_CQ failed: %s\n",
  650. hermon, cq->cqn, strerror ( rc ) );
  651. return rc;
  652. }
  653. DBGC ( hermon, "Hermon %p CQN %#lx context:\n", hermon, cq->cqn );
  654. DBGC_HDA ( hermon, 0, &cqctx, sizeof ( cqctx ) );
  655. return 0;
  656. }
  657. /**
  658. * Create completion queue
  659. *
  660. * @v ibdev Infiniband device
  661. * @v cq Completion queue
  662. * @ret rc Return status code
  663. */
  664. static int hermon_create_cq ( struct ib_device *ibdev,
  665. struct ib_completion_queue *cq ) {
  666. struct hermon *hermon = ib_get_drvdata ( ibdev );
  667. struct hermon_completion_queue *hermon_cq;
  668. struct hermonprm_completion_queue_context cqctx;
  669. int cqn_offset;
  670. unsigned int i;
  671. int rc;
  672. /* Find a free completion queue number */
  673. cqn_offset = hermon_bitmask_alloc ( hermon->cq_inuse,
  674. HERMON_MAX_CQS, 1 );
  675. if ( cqn_offset < 0 ) {
  676. DBGC ( hermon, "Hermon %p out of completion queues\n",
  677. hermon );
  678. rc = cqn_offset;
  679. goto err_cqn_offset;
  680. }
  681. cq->cqn = ( hermon->cap.reserved_cqs + cqn_offset );
  682. /* Allocate control structures */
  683. hermon_cq = zalloc ( sizeof ( *hermon_cq ) );
  684. if ( ! hermon_cq ) {
  685. rc = -ENOMEM;
  686. goto err_hermon_cq;
  687. }
  688. /* Allocate completion queue itself */
  689. hermon_cq->cqe_size = ( cq->num_cqes * sizeof ( hermon_cq->cqe[0] ) );
  690. hermon_cq->cqe = malloc_dma ( hermon_cq->cqe_size,
  691. sizeof ( hermon_cq->cqe[0] ) );
  692. if ( ! hermon_cq->cqe ) {
  693. rc = -ENOMEM;
  694. goto err_cqe;
  695. }
  696. memset ( hermon_cq->cqe, 0, hermon_cq->cqe_size );
  697. for ( i = 0 ; i < cq->num_cqes ; i++ ) {
  698. MLX_FILL_1 ( &hermon_cq->cqe[i].normal, 7, owner, 1 );
  699. }
  700. barrier();
  701. /* Allocate MTT entries */
  702. if ( ( rc = hermon_alloc_mtt ( hermon, hermon_cq->cqe,
  703. hermon_cq->cqe_size,
  704. &hermon_cq->mtt ) ) != 0 )
  705. goto err_alloc_mtt;
  706. /* Hand queue over to hardware */
  707. memset ( &cqctx, 0, sizeof ( cqctx ) );
  708. MLX_FILL_1 ( &cqctx, 0, st, 0xa /* "Event fired" */ );
  709. MLX_FILL_1 ( &cqctx, 2,
  710. page_offset, ( hermon_cq->mtt.page_offset >> 5 ) );
  711. MLX_FILL_2 ( &cqctx, 3,
  712. usr_page, HERMON_UAR_NON_EQ_PAGE,
  713. log_cq_size, fls ( cq->num_cqes - 1 ) );
  714. MLX_FILL_1 ( &cqctx, 7, mtt_base_addr_l,
  715. ( hermon_cq->mtt.mtt_base_addr >> 3 ) );
  716. MLX_FILL_1 ( &cqctx, 15, db_record_addr_l,
  717. ( virt_to_phys ( &hermon_cq->doorbell ) >> 3 ) );
  718. if ( ( rc = hermon_cmd_sw2hw_cq ( hermon, cq->cqn, &cqctx ) ) != 0 ) {
  719. DBGC ( hermon, "Hermon %p CQN %#lx SW2HW_CQ failed: %s\n",
  720. hermon, cq->cqn, strerror ( rc ) );
  721. goto err_sw2hw_cq;
  722. }
  723. DBGC ( hermon, "Hermon %p CQN %#lx ring [%08lx,%08lx), doorbell "
  724. "%08lx\n", hermon, cq->cqn, virt_to_phys ( hermon_cq->cqe ),
  725. ( virt_to_phys ( hermon_cq->cqe ) + hermon_cq->cqe_size ),
  726. virt_to_phys ( &hermon_cq->doorbell ) );
  727. ib_cq_set_drvdata ( cq, hermon_cq );
  728. return 0;
  729. err_sw2hw_cq:
  730. hermon_free_mtt ( hermon, &hermon_cq->mtt );
  731. err_alloc_mtt:
  732. free_dma ( hermon_cq->cqe, hermon_cq->cqe_size );
  733. err_cqe:
  734. free ( hermon_cq );
  735. err_hermon_cq:
  736. hermon_bitmask_free ( hermon->cq_inuse, cqn_offset, 1 );
  737. err_cqn_offset:
  738. return rc;
  739. }
  740. /**
  741. * Destroy completion queue
  742. *
  743. * @v ibdev Infiniband device
  744. * @v cq Completion queue
  745. */
  746. static void hermon_destroy_cq ( struct ib_device *ibdev,
  747. struct ib_completion_queue *cq ) {
  748. struct hermon *hermon = ib_get_drvdata ( ibdev );
  749. struct hermon_completion_queue *hermon_cq = ib_cq_get_drvdata ( cq );
  750. struct hermonprm_completion_queue_context cqctx;
  751. int cqn_offset;
  752. int rc;
  753. /* Take ownership back from hardware */
  754. if ( ( rc = hermon_cmd_hw2sw_cq ( hermon, cq->cqn, &cqctx ) ) != 0 ) {
  755. DBGC ( hermon, "Hermon %p CQN %#lx FATAL HW2SW_CQ failed: "
  756. "%s\n", hermon, cq->cqn, strerror ( rc ) );
  757. /* Leak memory and return; at least we avoid corruption */
  758. return;
  759. }
  760. /* Free MTT entries */
  761. hermon_free_mtt ( hermon, &hermon_cq->mtt );
  762. /* Free memory */
  763. free_dma ( hermon_cq->cqe, hermon_cq->cqe_size );
  764. free ( hermon_cq );
  765. /* Mark queue number as free */
  766. cqn_offset = ( cq->cqn - hermon->cap.reserved_cqs );
  767. hermon_bitmask_free ( hermon->cq_inuse, cqn_offset, 1 );
  768. ib_cq_set_drvdata ( cq, NULL );
  769. }
  770. /***************************************************************************
  771. *
  772. * Queue pair operations
  773. *
  774. ***************************************************************************
  775. */
  776. /**
  777. * Assign queue pair number
  778. *
  779. * @v ibdev Infiniband device
  780. * @v qp Queue pair
  781. * @ret rc Return status code
  782. */
  783. static int hermon_alloc_qpn ( struct ib_device *ibdev,
  784. struct ib_queue_pair *qp ) {
  785. struct hermon *hermon = ib_get_drvdata ( ibdev );
  786. unsigned int port_offset;
  787. int qpn_offset;
  788. /* Calculate queue pair number */
  789. port_offset = ( ibdev->port - HERMON_PORT_BASE );
  790. switch ( qp->type ) {
  791. case IB_QPT_SMI:
  792. qp->qpn = ( hermon->special_qpn_base + port_offset );
  793. return 0;
  794. case IB_QPT_GSI:
  795. qp->qpn = ( hermon->special_qpn_base + 2 + port_offset );
  796. return 0;
  797. case IB_QPT_UD:
  798. case IB_QPT_RC:
  799. /* Find a free queue pair number */
  800. qpn_offset = hermon_bitmask_alloc ( hermon->qp_inuse,
  801. HERMON_MAX_QPS, 1 );
  802. if ( qpn_offset < 0 ) {
  803. DBGC ( hermon, "Hermon %p out of queue pairs\n",
  804. hermon );
  805. return qpn_offset;
  806. }
  807. qp->qpn = ( ( random() & HERMON_QPN_RANDOM_MASK ) |
  808. ( hermon->qpn_base + qpn_offset ) );
  809. return 0;
  810. default:
  811. DBGC ( hermon, "Hermon %p unsupported QP type %d\n",
  812. hermon, qp->type );
  813. return -ENOTSUP;
  814. }
  815. }
  816. /**
  817. * Free queue pair number
  818. *
  819. * @v ibdev Infiniband device
  820. * @v qp Queue pair
  821. */
  822. static void hermon_free_qpn ( struct ib_device *ibdev,
  823. struct ib_queue_pair *qp ) {
  824. struct hermon *hermon = ib_get_drvdata ( ibdev );
  825. int qpn_offset;
  826. qpn_offset = ( ( qp->qpn & ~HERMON_QPN_RANDOM_MASK )
  827. - hermon->qpn_base );
  828. if ( qpn_offset >= 0 )
  829. hermon_bitmask_free ( hermon->qp_inuse, qpn_offset, 1 );
  830. }
  831. /**
  832. * Calculate transmission rate
  833. *
  834. * @v av Address vector
  835. * @ret hermon_rate Hermon rate
  836. */
  837. static unsigned int hermon_rate ( struct ib_address_vector *av ) {
  838. return ( ( ( av->rate >= IB_RATE_2_5 ) && ( av->rate <= IB_RATE_120 ) )
  839. ? ( av->rate + 5 ) : 0 );
  840. }
  841. /**
  842. * Calculate schedule queue
  843. *
  844. * @v ibdev Infiniband device
  845. * @v qp Queue pair
  846. * @ret sched_queue Schedule queue
  847. */
  848. static unsigned int hermon_sched_queue ( struct ib_device *ibdev,
  849. struct ib_queue_pair *qp ) {
  850. return ( ( ( qp->type == IB_QPT_SMI ) ?
  851. HERMON_SCHED_QP0 : HERMON_SCHED_DEFAULT ) |
  852. ( ( ibdev->port - 1 ) << 6 ) );
  853. }
  854. /** Queue pair transport service type map */
  855. static uint8_t hermon_qp_st[] = {
  856. [IB_QPT_SMI] = HERMON_ST_MLX,
  857. [IB_QPT_GSI] = HERMON_ST_MLX,
  858. [IB_QPT_UD] = HERMON_ST_UD,
  859. [IB_QPT_RC] = HERMON_ST_RC,
  860. };
  861. /**
  862. * Dump queue pair context (for debugging only)
  863. *
  864. * @v hermon Hermon device
  865. * @v qp Queue pair
  866. * @ret rc Return status code
  867. */
  868. static __attribute__ (( unused )) int
  869. hermon_dump_qpctx ( struct hermon *hermon, struct ib_queue_pair *qp ) {
  870. struct hermonprm_qp_ee_state_transitions qpctx;
  871. int rc;
  872. memset ( &qpctx, 0, sizeof ( qpctx ) );
  873. if ( ( rc = hermon_cmd_query_qp ( hermon, qp->qpn, &qpctx ) ) != 0 ) {
  874. DBGC ( hermon, "Hermon %p QPN %#lx QUERY_QP failed: %s\n",
  875. hermon, qp->qpn, strerror ( rc ) );
  876. return rc;
  877. }
  878. DBGC ( hermon, "Hermon %p QPN %#lx context:\n", hermon, qp->qpn );
  879. DBGC_HDA ( hermon, 0, &qpctx.u.dwords[2], ( sizeof ( qpctx ) - 8 ) );
  880. return 0;
  881. }
  882. /**
  883. * Create queue pair
  884. *
  885. * @v ibdev Infiniband device
  886. * @v qp Queue pair
  887. * @ret rc Return status code
  888. */
  889. static int hermon_create_qp ( struct ib_device *ibdev,
  890. struct ib_queue_pair *qp ) {
  891. struct hermon *hermon = ib_get_drvdata ( ibdev );
  892. struct hermon_queue_pair *hermon_qp;
  893. struct hermonprm_qp_ee_state_transitions qpctx;
  894. int rc;
  895. /* Calculate queue pair number */
  896. if ( ( rc = hermon_alloc_qpn ( ibdev, qp ) ) != 0 )
  897. goto err_alloc_qpn;
  898. /* Allocate control structures */
  899. hermon_qp = zalloc ( sizeof ( *hermon_qp ) );
  900. if ( ! hermon_qp ) {
  901. rc = -ENOMEM;
  902. goto err_hermon_qp;
  903. }
  904. /* Calculate doorbell address */
  905. hermon_qp->send.doorbell =
  906. ( hermon->uar + HERMON_UAR_NON_EQ_PAGE * HERMON_PAGE_SIZE +
  907. HERMON_DB_POST_SND_OFFSET );
  908. /* Allocate work queue buffer */
  909. hermon_qp->send.num_wqes = ( qp->send.num_wqes /* headroom */ + 1 +
  910. ( 2048 / sizeof ( hermon_qp->send.wqe[0] ) ) );
  911. hermon_qp->send.num_wqes =
  912. ( 1 << fls ( hermon_qp->send.num_wqes - 1 ) ); /* round up */
  913. hermon_qp->send.wqe_size = ( hermon_qp->send.num_wqes *
  914. sizeof ( hermon_qp->send.wqe[0] ) );
  915. hermon_qp->recv.wqe_size = ( qp->recv.num_wqes *
  916. sizeof ( hermon_qp->recv.wqe[0] ) );
  917. hermon_qp->wqe_size = ( hermon_qp->send.wqe_size +
  918. hermon_qp->recv.wqe_size );
  919. hermon_qp->wqe = malloc_dma ( hermon_qp->wqe_size,
  920. sizeof ( hermon_qp->send.wqe[0] ) );
  921. if ( ! hermon_qp->wqe ) {
  922. rc = -ENOMEM;
  923. goto err_alloc_wqe;
  924. }
  925. hermon_qp->send.wqe = hermon_qp->wqe;
  926. memset ( hermon_qp->send.wqe, 0xff, hermon_qp->send.wqe_size );
  927. hermon_qp->recv.wqe = ( hermon_qp->wqe + hermon_qp->send.wqe_size );
  928. memset ( hermon_qp->recv.wqe, 0, hermon_qp->recv.wqe_size );
  929. /* Allocate MTT entries */
  930. if ( ( rc = hermon_alloc_mtt ( hermon, hermon_qp->wqe,
  931. hermon_qp->wqe_size,
  932. &hermon_qp->mtt ) ) != 0 ) {
  933. goto err_alloc_mtt;
  934. }
  935. /* Transition queue to INIT state */
  936. memset ( &qpctx, 0, sizeof ( qpctx ) );
  937. MLX_FILL_2 ( &qpctx, 2,
  938. qpc_eec_data.pm_state, HERMON_PM_STATE_MIGRATED,
  939. qpc_eec_data.st, hermon_qp_st[qp->type] );
  940. MLX_FILL_1 ( &qpctx, 3, qpc_eec_data.pd, HERMON_GLOBAL_PD );
  941. MLX_FILL_4 ( &qpctx, 4,
  942. qpc_eec_data.log_rq_size, fls ( qp->recv.num_wqes - 1 ),
  943. qpc_eec_data.log_rq_stride,
  944. ( fls ( sizeof ( hermon_qp->recv.wqe[0] ) - 1 ) - 4 ),
  945. qpc_eec_data.log_sq_size,
  946. fls ( hermon_qp->send.num_wqes - 1 ),
  947. qpc_eec_data.log_sq_stride,
  948. ( fls ( sizeof ( hermon_qp->send.wqe[0] ) - 1 ) - 4 ) );
  949. MLX_FILL_1 ( &qpctx, 5,
  950. qpc_eec_data.usr_page, HERMON_UAR_NON_EQ_PAGE );
  951. MLX_FILL_1 ( &qpctx, 33, qpc_eec_data.cqn_snd, qp->send.cq->cqn );
  952. MLX_FILL_4 ( &qpctx, 38,
  953. qpc_eec_data.rre, 1,
  954. qpc_eec_data.rwe, 1,
  955. qpc_eec_data.rae, 1,
  956. qpc_eec_data.page_offset,
  957. ( hermon_qp->mtt.page_offset >> 6 ) );
  958. MLX_FILL_1 ( &qpctx, 41, qpc_eec_data.cqn_rcv, qp->recv.cq->cqn );
  959. MLX_FILL_1 ( &qpctx, 43, qpc_eec_data.db_record_addr_l,
  960. ( virt_to_phys ( &hermon_qp->recv.doorbell ) >> 2 ) );
  961. MLX_FILL_1 ( &qpctx, 53, qpc_eec_data.mtt_base_addr_l,
  962. ( hermon_qp->mtt.mtt_base_addr >> 3 ) );
  963. if ( ( rc = hermon_cmd_rst2init_qp ( hermon, qp->qpn,
  964. &qpctx ) ) != 0 ) {
  965. DBGC ( hermon, "Hermon %p QPN %#lx RST2INIT_QP failed: %s\n",
  966. hermon, qp->qpn, strerror ( rc ) );
  967. goto err_rst2init_qp;
  968. }
  969. hermon_qp->state = HERMON_QP_ST_INIT;
  970. DBGC ( hermon, "Hermon %p QPN %#lx send ring [%08lx,%08lx), doorbell "
  971. "%08lx\n", hermon, qp->qpn,
  972. virt_to_phys ( hermon_qp->send.wqe ),
  973. ( virt_to_phys ( hermon_qp->send.wqe ) +
  974. hermon_qp->send.wqe_size ),
  975. virt_to_phys ( hermon_qp->send.doorbell ) );
  976. DBGC ( hermon, "Hermon %p QPN %#lx receive ring [%08lx,%08lx), "
  977. "doorbell %08lx\n", hermon, qp->qpn,
  978. virt_to_phys ( hermon_qp->recv.wqe ),
  979. ( virt_to_phys ( hermon_qp->recv.wqe ) +
  980. hermon_qp->recv.wqe_size ),
  981. virt_to_phys ( &hermon_qp->recv.doorbell ) );
  982. DBGC ( hermon, "Hermon %p QPN %#lx send CQN %#lx receive CQN %#lx\n",
  983. hermon, qp->qpn, qp->send.cq->cqn, qp->recv.cq->cqn );
  984. ib_qp_set_drvdata ( qp, hermon_qp );
  985. return 0;
  986. hermon_cmd_2rst_qp ( hermon, qp->qpn );
  987. err_rst2init_qp:
  988. hermon_free_mtt ( hermon, &hermon_qp->mtt );
  989. err_alloc_mtt:
  990. free_dma ( hermon_qp->wqe, hermon_qp->wqe_size );
  991. err_alloc_wqe:
  992. free ( hermon_qp );
  993. err_hermon_qp:
  994. hermon_free_qpn ( ibdev, qp );
  995. err_alloc_qpn:
  996. return rc;
  997. }
  998. /**
  999. * Modify queue pair
  1000. *
  1001. * @v ibdev Infiniband device
  1002. * @v qp Queue pair
  1003. * @ret rc Return status code
  1004. */
  1005. static int hermon_modify_qp ( struct ib_device *ibdev,
  1006. struct ib_queue_pair *qp ) {
  1007. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1008. struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp );
  1009. struct hermonprm_qp_ee_state_transitions qpctx;
  1010. int rc;
  1011. /* Transition queue to RTR state, if applicable */
  1012. if ( hermon_qp->state < HERMON_QP_ST_RTR ) {
  1013. memset ( &qpctx, 0, sizeof ( qpctx ) );
  1014. MLX_FILL_2 ( &qpctx, 4,
  1015. qpc_eec_data.mtu, HERMON_MTU_2048,
  1016. qpc_eec_data.msg_max, 31 );
  1017. MLX_FILL_1 ( &qpctx, 7,
  1018. qpc_eec_data.remote_qpn_een, qp->av.qpn );
  1019. MLX_FILL_1 ( &qpctx, 9,
  1020. qpc_eec_data.primary_address_path.rlid,
  1021. qp->av.lid );
  1022. MLX_FILL_1 ( &qpctx, 10,
  1023. qpc_eec_data.primary_address_path.max_stat_rate,
  1024. hermon_rate ( &qp->av ) );
  1025. memcpy ( &qpctx.u.dwords[12], &qp->av.gid,
  1026. sizeof ( qp->av.gid ) );
  1027. MLX_FILL_1 ( &qpctx, 16,
  1028. qpc_eec_data.primary_address_path.sched_queue,
  1029. hermon_sched_queue ( ibdev, qp ) );
  1030. MLX_FILL_1 ( &qpctx, 39,
  1031. qpc_eec_data.next_rcv_psn, qp->recv.psn );
  1032. if ( ( rc = hermon_cmd_init2rtr_qp ( hermon, qp->qpn,
  1033. &qpctx ) ) != 0 ) {
  1034. DBGC ( hermon, "Hermon %p QPN %#lx INIT2RTR_QP failed:"
  1035. " %s\n", hermon, qp->qpn, strerror ( rc ) );
  1036. return rc;
  1037. }
  1038. hermon_qp->state = HERMON_QP_ST_RTR;
  1039. }
  1040. /* Transition queue to RTS state */
  1041. if ( hermon_qp->state < HERMON_QP_ST_RTS ) {
  1042. memset ( &qpctx, 0, sizeof ( qpctx ) );
  1043. MLX_FILL_1 ( &qpctx, 10,
  1044. qpc_eec_data.primary_address_path.ack_timeout,
  1045. 14 /* 4.096us * 2^(14) = 67ms */ );
  1046. MLX_FILL_2 ( &qpctx, 30,
  1047. qpc_eec_data.retry_count, HERMON_RETRY_MAX,
  1048. qpc_eec_data.rnr_retry, HERMON_RETRY_MAX );
  1049. MLX_FILL_1 ( &qpctx, 32,
  1050. qpc_eec_data.next_send_psn, qp->send.psn );
  1051. if ( ( rc = hermon_cmd_rtr2rts_qp ( hermon, qp->qpn,
  1052. &qpctx ) ) != 0 ) {
  1053. DBGC ( hermon, "Hermon %p QPN %#lx RTR2RTS_QP failed: "
  1054. "%s\n", hermon, qp->qpn, strerror ( rc ) );
  1055. return rc;
  1056. }
  1057. hermon_qp->state = HERMON_QP_ST_RTS;
  1058. }
  1059. /* Update parameters in RTS state */
  1060. memset ( &qpctx, 0, sizeof ( qpctx ) );
  1061. MLX_FILL_1 ( &qpctx, 0, opt_param_mask, HERMON_QP_OPT_PARAM_QKEY );
  1062. MLX_FILL_1 ( &qpctx, 44, qpc_eec_data.q_key, qp->qkey );
  1063. if ( ( rc = hermon_cmd_rts2rts_qp ( hermon, qp->qpn, &qpctx ) ) != 0 ){
  1064. DBGC ( hermon, "Hermon %p QPN %#lx RTS2RTS_QP failed: %s\n",
  1065. hermon, qp->qpn, strerror ( rc ) );
  1066. return rc;
  1067. }
  1068. return 0;
  1069. }
  1070. /**
  1071. * Destroy queue pair
  1072. *
  1073. * @v ibdev Infiniband device
  1074. * @v qp Queue pair
  1075. */
  1076. static void hermon_destroy_qp ( struct ib_device *ibdev,
  1077. struct ib_queue_pair *qp ) {
  1078. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1079. struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp );
  1080. int rc;
  1081. /* Take ownership back from hardware */
  1082. if ( ( rc = hermon_cmd_2rst_qp ( hermon, qp->qpn ) ) != 0 ) {
  1083. DBGC ( hermon, "Hermon %p QPN %#lx FATAL 2RST_QP failed: %s\n",
  1084. hermon, qp->qpn, strerror ( rc ) );
  1085. /* Leak memory and return; at least we avoid corruption */
  1086. return;
  1087. }
  1088. /* Free MTT entries */
  1089. hermon_free_mtt ( hermon, &hermon_qp->mtt );
  1090. /* Free memory */
  1091. free_dma ( hermon_qp->wqe, hermon_qp->wqe_size );
  1092. free ( hermon_qp );
  1093. /* Mark queue number as free */
  1094. hermon_free_qpn ( ibdev, qp );
  1095. ib_qp_set_drvdata ( qp, NULL );
  1096. }
  1097. /***************************************************************************
  1098. *
  1099. * Work request operations
  1100. *
  1101. ***************************************************************************
  1102. */
  1103. /**
  1104. * Construct UD send work queue entry
  1105. *
  1106. * @v ibdev Infiniband device
  1107. * @v qp Queue pair
  1108. * @v av Address vector
  1109. * @v iobuf I/O buffer
  1110. * @v wqe Send work queue entry
  1111. * @ret opcode Control opcode
  1112. */
  1113. static __attribute__ (( unused )) unsigned int
  1114. hermon_fill_nop_send_wqe ( struct ib_device *ibdev __unused,
  1115. struct ib_queue_pair *qp __unused,
  1116. struct ib_address_vector *av __unused,
  1117. struct io_buffer *iobuf __unused,
  1118. union hermon_send_wqe *wqe ) {
  1119. MLX_FILL_1 ( &wqe->ctrl, 1, ds, ( sizeof ( wqe->ctrl ) / 16 ) );
  1120. MLX_FILL_1 ( &wqe->ctrl, 2, c, 0x03 /* generate completion */ );
  1121. return HERMON_OPCODE_NOP;
  1122. }
  1123. /**
  1124. * Construct UD send work queue entry
  1125. *
  1126. * @v ibdev Infiniband device
  1127. * @v qp Queue pair
  1128. * @v av Address vector
  1129. * @v iobuf I/O buffer
  1130. * @v wqe Send work queue entry
  1131. * @ret opcode Control opcode
  1132. */
  1133. static unsigned int
  1134. hermon_fill_ud_send_wqe ( struct ib_device *ibdev,
  1135. struct ib_queue_pair *qp __unused,
  1136. struct ib_address_vector *av,
  1137. struct io_buffer *iobuf,
  1138. union hermon_send_wqe *wqe ) {
  1139. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1140. MLX_FILL_1 ( &wqe->ud.ctrl, 1, ds,
  1141. ( ( offsetof ( typeof ( wqe->ud ), data[1] ) / 16 ) ) );
  1142. MLX_FILL_1 ( &wqe->ud.ctrl, 2, c, 0x03 /* generate completion */ );
  1143. MLX_FILL_2 ( &wqe->ud.ud, 0,
  1144. ud_address_vector.pd, HERMON_GLOBAL_PD,
  1145. ud_address_vector.port_number, ibdev->port );
  1146. MLX_FILL_2 ( &wqe->ud.ud, 1,
  1147. ud_address_vector.rlid, av->lid,
  1148. ud_address_vector.g, av->gid_present );
  1149. MLX_FILL_1 ( &wqe->ud.ud, 2,
  1150. ud_address_vector.max_stat_rate, hermon_rate ( av ) );
  1151. MLX_FILL_1 ( &wqe->ud.ud, 3, ud_address_vector.sl, av->sl );
  1152. memcpy ( &wqe->ud.ud.u.dwords[4], &av->gid, sizeof ( av->gid ) );
  1153. MLX_FILL_1 ( &wqe->ud.ud, 8, destination_qp, av->qpn );
  1154. MLX_FILL_1 ( &wqe->ud.ud, 9, q_key, av->qkey );
  1155. MLX_FILL_1 ( &wqe->ud.data[0], 0, byte_count, iob_len ( iobuf ) );
  1156. MLX_FILL_1 ( &wqe->ud.data[0], 1, l_key, hermon->lkey );
  1157. MLX_FILL_1 ( &wqe->ud.data[0], 3,
  1158. local_address_l, virt_to_bus ( iobuf->data ) );
  1159. return HERMON_OPCODE_SEND;
  1160. }
  1161. /**
  1162. * Construct MLX send work queue entry
  1163. *
  1164. * @v ibdev Infiniband device
  1165. * @v qp Queue pair
  1166. * @v av Address vector
  1167. * @v iobuf I/O buffer
  1168. * @v wqe Send work queue entry
  1169. * @ret opcode Control opcode
  1170. */
  1171. static unsigned int
  1172. hermon_fill_mlx_send_wqe ( struct ib_device *ibdev,
  1173. struct ib_queue_pair *qp,
  1174. struct ib_address_vector *av,
  1175. struct io_buffer *iobuf,
  1176. union hermon_send_wqe *wqe ) {
  1177. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1178. struct io_buffer headers;
  1179. /* Construct IB headers */
  1180. iob_populate ( &headers, &wqe->mlx.headers, 0,
  1181. sizeof ( wqe->mlx.headers ) );
  1182. iob_reserve ( &headers, sizeof ( wqe->mlx.headers ) );
  1183. ib_push ( ibdev, &headers, qp, iob_len ( iobuf ), av );
  1184. /* Fill work queue entry */
  1185. MLX_FILL_1 ( &wqe->mlx.ctrl, 1, ds,
  1186. ( ( offsetof ( typeof ( wqe->mlx ), data[2] ) / 16 ) ) );
  1187. MLX_FILL_5 ( &wqe->mlx.ctrl, 2,
  1188. c, 0x03 /* generate completion */,
  1189. icrc, 0 /* generate ICRC */,
  1190. max_statrate, hermon_rate ( av ),
  1191. slr, 0,
  1192. v15, ( ( qp->ext_qpn == IB_QPN_SMI ) ? 1 : 0 ) );
  1193. MLX_FILL_1 ( &wqe->mlx.ctrl, 3, rlid, av->lid );
  1194. MLX_FILL_1 ( &wqe->mlx.data[0], 0,
  1195. byte_count, iob_len ( &headers ) );
  1196. MLX_FILL_1 ( &wqe->mlx.data[0], 1, l_key, hermon->lkey );
  1197. MLX_FILL_1 ( &wqe->mlx.data[0], 3,
  1198. local_address_l, virt_to_bus ( headers.data ) );
  1199. MLX_FILL_1 ( &wqe->mlx.data[1], 0,
  1200. byte_count, ( iob_len ( iobuf ) + 4 /* ICRC */ ) );
  1201. MLX_FILL_1 ( &wqe->mlx.data[1], 1, l_key, hermon->lkey );
  1202. MLX_FILL_1 ( &wqe->mlx.data[1], 3,
  1203. local_address_l, virt_to_bus ( iobuf->data ) );
  1204. return HERMON_OPCODE_SEND;
  1205. }
  1206. /**
  1207. * Construct RC send work queue entry
  1208. *
  1209. * @v ibdev Infiniband device
  1210. * @v qp Queue pair
  1211. * @v av Address vector
  1212. * @v iobuf I/O buffer
  1213. * @v wqe Send work queue entry
  1214. * @ret opcode Control opcode
  1215. */
  1216. static unsigned int
  1217. hermon_fill_rc_send_wqe ( struct ib_device *ibdev,
  1218. struct ib_queue_pair *qp __unused,
  1219. struct ib_address_vector *av __unused,
  1220. struct io_buffer *iobuf,
  1221. union hermon_send_wqe *wqe ) {
  1222. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1223. MLX_FILL_1 ( &wqe->rc.ctrl, 1, ds,
  1224. ( ( offsetof ( typeof ( wqe->rc ), data[1] ) / 16 ) ) );
  1225. MLX_FILL_1 ( &wqe->rc.ctrl, 2, c, 0x03 /* generate completion */ );
  1226. MLX_FILL_1 ( &wqe->rc.data[0], 0, byte_count, iob_len ( iobuf ) );
  1227. MLX_FILL_1 ( &wqe->rc.data[0], 1, l_key, hermon->lkey );
  1228. MLX_FILL_1 ( &wqe->rc.data[0], 3,
  1229. local_address_l, virt_to_bus ( iobuf->data ) );
  1230. return HERMON_OPCODE_SEND;
  1231. }
  1232. /** Work queue entry constructors */
  1233. static unsigned int
  1234. ( * hermon_fill_send_wqe[] ) ( struct ib_device *ibdev,
  1235. struct ib_queue_pair *qp,
  1236. struct ib_address_vector *av,
  1237. struct io_buffer *iobuf,
  1238. union hermon_send_wqe *wqe ) = {
  1239. [IB_QPT_SMI] = hermon_fill_mlx_send_wqe,
  1240. [IB_QPT_GSI] = hermon_fill_mlx_send_wqe,
  1241. [IB_QPT_UD] = hermon_fill_ud_send_wqe,
  1242. [IB_QPT_RC] = hermon_fill_rc_send_wqe,
  1243. };
  1244. /**
  1245. * Post send work queue entry
  1246. *
  1247. * @v ibdev Infiniband device
  1248. * @v qp Queue pair
  1249. * @v av Address vector
  1250. * @v iobuf I/O buffer
  1251. * @ret rc Return status code
  1252. */
  1253. static int hermon_post_send ( struct ib_device *ibdev,
  1254. struct ib_queue_pair *qp,
  1255. struct ib_address_vector *av,
  1256. struct io_buffer *iobuf ) {
  1257. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1258. struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp );
  1259. struct ib_work_queue *wq = &qp->send;
  1260. struct hermon_send_work_queue *hermon_send_wq = &hermon_qp->send;
  1261. union hermon_send_wqe *wqe;
  1262. union hermonprm_doorbell_register db_reg;
  1263. unsigned long wqe_idx_mask;
  1264. unsigned long wqe_idx;
  1265. unsigned int owner;
  1266. unsigned int opcode;
  1267. /* Allocate work queue entry */
  1268. wqe_idx = ( wq->next_idx & ( hermon_send_wq->num_wqes - 1 ) );
  1269. owner = ( ( wq->next_idx & hermon_send_wq->num_wqes ) ? 1 : 0 );
  1270. wqe_idx_mask = ( wq->num_wqes - 1 );
  1271. if ( wq->iobufs[ wqe_idx & wqe_idx_mask ] ) {
  1272. DBGC ( hermon, "Hermon %p QPN %#lx send queue full",
  1273. hermon, qp->qpn );
  1274. return -ENOBUFS;
  1275. }
  1276. wq->iobufs[ wqe_idx & wqe_idx_mask ] = iobuf;
  1277. wqe = &hermon_send_wq->wqe[wqe_idx];
  1278. /* Construct work queue entry */
  1279. memset ( ( ( ( void * ) wqe ) + 4 /* avoid ctrl.owner */ ), 0,
  1280. ( sizeof ( *wqe ) - 4 ) );
  1281. assert ( qp->type < ( sizeof ( hermon_fill_send_wqe ) /
  1282. sizeof ( hermon_fill_send_wqe[0] ) ) );
  1283. assert ( hermon_fill_send_wqe[qp->type] != NULL );
  1284. opcode = hermon_fill_send_wqe[qp->type] ( ibdev, qp, av, iobuf, wqe );
  1285. barrier();
  1286. MLX_FILL_2 ( &wqe->ctrl, 0,
  1287. opcode, opcode,
  1288. owner, owner );
  1289. DBGCP ( hermon, "Hermon %p QPN %#lx posting send WQE %#lx:\n",
  1290. hermon, qp->qpn, wqe_idx );
  1291. DBGCP_HDA ( hermon, virt_to_phys ( wqe ), wqe, sizeof ( *wqe ) );
  1292. /* Ring doorbell register */
  1293. MLX_FILL_1 ( &db_reg.send, 0, qn, qp->qpn );
  1294. barrier();
  1295. writel ( db_reg.dword[0], hermon_send_wq->doorbell );
  1296. /* Update work queue's index */
  1297. wq->next_idx++;
  1298. return 0;
  1299. }
  1300. /**
  1301. * Post receive work queue entry
  1302. *
  1303. * @v ibdev Infiniband device
  1304. * @v qp Queue pair
  1305. * @v iobuf I/O buffer
  1306. * @ret rc Return status code
  1307. */
  1308. static int hermon_post_recv ( struct ib_device *ibdev,
  1309. struct ib_queue_pair *qp,
  1310. struct io_buffer *iobuf ) {
  1311. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1312. struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp );
  1313. struct ib_work_queue *wq = &qp->recv;
  1314. struct hermon_recv_work_queue *hermon_recv_wq = &hermon_qp->recv;
  1315. struct hermonprm_recv_wqe *wqe;
  1316. unsigned int wqe_idx_mask;
  1317. /* Allocate work queue entry */
  1318. wqe_idx_mask = ( wq->num_wqes - 1 );
  1319. if ( wq->iobufs[wq->next_idx & wqe_idx_mask] ) {
  1320. DBGC ( hermon, "Hermon %p QPN %#lx receive queue full",
  1321. hermon, qp->qpn );
  1322. return -ENOBUFS;
  1323. }
  1324. wq->iobufs[wq->next_idx & wqe_idx_mask] = iobuf;
  1325. wqe = &hermon_recv_wq->wqe[wq->next_idx & wqe_idx_mask].recv;
  1326. /* Construct work queue entry */
  1327. MLX_FILL_1 ( &wqe->data[0], 0, byte_count, iob_tailroom ( iobuf ) );
  1328. MLX_FILL_1 ( &wqe->data[0], 1, l_key, hermon->lkey );
  1329. MLX_FILL_1 ( &wqe->data[0], 3,
  1330. local_address_l, virt_to_bus ( iobuf->data ) );
  1331. /* Update work queue's index */
  1332. wq->next_idx++;
  1333. /* Update doorbell record */
  1334. barrier();
  1335. MLX_FILL_1 ( &hermon_recv_wq->doorbell, 0, receive_wqe_counter,
  1336. ( wq->next_idx & 0xffff ) );
  1337. return 0;
  1338. }
  1339. /**
  1340. * Handle completion
  1341. *
  1342. * @v ibdev Infiniband device
  1343. * @v cq Completion queue
  1344. * @v cqe Hardware completion queue entry
  1345. * @ret rc Return status code
  1346. */
  1347. static int hermon_complete ( struct ib_device *ibdev,
  1348. struct ib_completion_queue *cq,
  1349. union hermonprm_completion_entry *cqe ) {
  1350. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1351. struct ib_work_queue *wq;
  1352. struct ib_queue_pair *qp;
  1353. struct hermon_queue_pair *hermon_qp;
  1354. struct io_buffer *iobuf;
  1355. struct ib_address_vector recv_av;
  1356. struct ib_global_route_header *grh;
  1357. struct ib_address_vector *av;
  1358. unsigned int opcode;
  1359. unsigned long qpn;
  1360. int is_send;
  1361. unsigned long wqe_idx;
  1362. unsigned long wqe_idx_mask;
  1363. size_t len;
  1364. int rc = 0;
  1365. /* Parse completion */
  1366. qpn = MLX_GET ( &cqe->normal, qpn );
  1367. is_send = MLX_GET ( &cqe->normal, s_r );
  1368. opcode = MLX_GET ( &cqe->normal, opcode );
  1369. if ( opcode >= HERMON_OPCODE_RECV_ERROR ) {
  1370. /* "s" field is not valid for error opcodes */
  1371. is_send = ( opcode == HERMON_OPCODE_SEND_ERROR );
  1372. DBGC ( hermon, "Hermon %p CQN %#lx syndrome %x vendor %x\n",
  1373. hermon, cq->cqn, MLX_GET ( &cqe->error, syndrome ),
  1374. MLX_GET ( &cqe->error, vendor_error_syndrome ) );
  1375. rc = -EIO;
  1376. /* Don't return immediately; propagate error to completer */
  1377. }
  1378. /* Identify work queue */
  1379. wq = ib_find_wq ( cq, qpn, is_send );
  1380. if ( ! wq ) {
  1381. DBGC ( hermon, "Hermon %p CQN %#lx unknown %s QPN %#lx\n",
  1382. hermon, cq->cqn, ( is_send ? "send" : "recv" ), qpn );
  1383. return -EIO;
  1384. }
  1385. qp = wq->qp;
  1386. hermon_qp = ib_qp_get_drvdata ( qp );
  1387. /* Identify work queue entry */
  1388. wqe_idx = MLX_GET ( &cqe->normal, wqe_counter );
  1389. wqe_idx_mask = ( wq->num_wqes - 1 );
  1390. DBGCP ( hermon, "Hermon %p CQN %#lx QPN %#lx %s WQE %#lx completed:\n",
  1391. hermon, cq->cqn, qp->qpn, ( is_send ? "send" : "recv" ),
  1392. wqe_idx );
  1393. DBGCP_HDA ( hermon, virt_to_phys ( cqe ), cqe, sizeof ( *cqe ) );
  1394. /* Identify I/O buffer */
  1395. iobuf = wq->iobufs[ wqe_idx & wqe_idx_mask ];
  1396. if ( ! iobuf ) {
  1397. DBGC ( hermon, "Hermon %p CQN %#lx QPN %#lx empty %s WQE "
  1398. "%#lx\n", hermon, cq->cqn, qp->qpn,
  1399. ( is_send ? "send" : "recv" ), wqe_idx );
  1400. return -EIO;
  1401. }
  1402. wq->iobufs[ wqe_idx & wqe_idx_mask ] = NULL;
  1403. if ( is_send ) {
  1404. /* Hand off to completion handler */
  1405. ib_complete_send ( ibdev, qp, iobuf, rc );
  1406. } else {
  1407. /* Set received length */
  1408. len = MLX_GET ( &cqe->normal, byte_cnt );
  1409. assert ( len <= iob_tailroom ( iobuf ) );
  1410. iob_put ( iobuf, len );
  1411. switch ( qp->type ) {
  1412. case IB_QPT_SMI:
  1413. case IB_QPT_GSI:
  1414. case IB_QPT_UD:
  1415. assert ( iob_len ( iobuf ) >= sizeof ( *grh ) );
  1416. grh = iobuf->data;
  1417. iob_pull ( iobuf, sizeof ( *grh ) );
  1418. /* Construct address vector */
  1419. av = &recv_av;
  1420. memset ( av, 0, sizeof ( *av ) );
  1421. av->qpn = MLX_GET ( &cqe->normal, srq_rqpn );
  1422. av->lid = MLX_GET ( &cqe->normal, slid_smac47_32 );
  1423. av->sl = MLX_GET ( &cqe->normal, sl );
  1424. av->gid_present = MLX_GET ( &cqe->normal, g );
  1425. memcpy ( &av->gid, &grh->sgid, sizeof ( av->gid ) );
  1426. break;
  1427. case IB_QPT_RC:
  1428. av = &qp->av;
  1429. break;
  1430. default:
  1431. assert ( 0 );
  1432. return -EINVAL;
  1433. }
  1434. /* Hand off to completion handler */
  1435. ib_complete_recv ( ibdev, qp, av, iobuf, rc );
  1436. }
  1437. return rc;
  1438. }
  1439. /**
  1440. * Poll completion queue
  1441. *
  1442. * @v ibdev Infiniband device
  1443. * @v cq Completion queue
  1444. */
  1445. static void hermon_poll_cq ( struct ib_device *ibdev,
  1446. struct ib_completion_queue *cq ) {
  1447. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1448. struct hermon_completion_queue *hermon_cq = ib_cq_get_drvdata ( cq );
  1449. union hermonprm_completion_entry *cqe;
  1450. unsigned int cqe_idx_mask;
  1451. int rc;
  1452. while ( 1 ) {
  1453. /* Look for completion entry */
  1454. cqe_idx_mask = ( cq->num_cqes - 1 );
  1455. cqe = &hermon_cq->cqe[cq->next_idx & cqe_idx_mask];
  1456. if ( MLX_GET ( &cqe->normal, owner ) ^
  1457. ( ( cq->next_idx & cq->num_cqes ) ? 1 : 0 ) ) {
  1458. /* Entry still owned by hardware; end of poll */
  1459. break;
  1460. }
  1461. /* Handle completion */
  1462. if ( ( rc = hermon_complete ( ibdev, cq, cqe ) ) != 0 ) {
  1463. DBGC ( hermon, "Hermon %p CQN %#lx failed to complete:"
  1464. " %s\n", hermon, cq->cqn, strerror ( rc ) );
  1465. DBGC_HDA ( hermon, virt_to_phys ( cqe ),
  1466. cqe, sizeof ( *cqe ) );
  1467. }
  1468. /* Update completion queue's index */
  1469. cq->next_idx++;
  1470. /* Update doorbell record */
  1471. MLX_FILL_1 ( &hermon_cq->doorbell, 0, update_ci,
  1472. ( cq->next_idx & 0x00ffffffUL ) );
  1473. }
  1474. }
  1475. /***************************************************************************
  1476. *
  1477. * Event queues
  1478. *
  1479. ***************************************************************************
  1480. */
  1481. /**
  1482. * Create event queue
  1483. *
  1484. * @v hermon Hermon device
  1485. * @ret rc Return status code
  1486. */
  1487. static int hermon_create_eq ( struct hermon *hermon ) {
  1488. struct hermon_event_queue *hermon_eq = &hermon->eq;
  1489. struct hermonprm_eqc eqctx;
  1490. struct hermonprm_event_mask mask;
  1491. unsigned int i;
  1492. int rc;
  1493. /* Select event queue number */
  1494. hermon_eq->eqn = ( 4 * hermon->cap.reserved_uars );
  1495. if ( hermon_eq->eqn < hermon->cap.reserved_eqs )
  1496. hermon_eq->eqn = hermon->cap.reserved_eqs;
  1497. /* Calculate doorbell address */
  1498. hermon_eq->doorbell =
  1499. ( hermon->uar + HERMON_DB_EQ_OFFSET ( hermon_eq->eqn ) );
  1500. /* Allocate event queue itself */
  1501. hermon_eq->eqe_size =
  1502. ( HERMON_NUM_EQES * sizeof ( hermon_eq->eqe[0] ) );
  1503. hermon_eq->eqe = malloc_dma ( hermon_eq->eqe_size,
  1504. sizeof ( hermon_eq->eqe[0] ) );
  1505. if ( ! hermon_eq->eqe ) {
  1506. rc = -ENOMEM;
  1507. goto err_eqe;
  1508. }
  1509. memset ( hermon_eq->eqe, 0, hermon_eq->eqe_size );
  1510. for ( i = 0 ; i < HERMON_NUM_EQES ; i++ ) {
  1511. MLX_FILL_1 ( &hermon_eq->eqe[i].generic, 7, owner, 1 );
  1512. }
  1513. barrier();
  1514. /* Allocate MTT entries */
  1515. if ( ( rc = hermon_alloc_mtt ( hermon, hermon_eq->eqe,
  1516. hermon_eq->eqe_size,
  1517. &hermon_eq->mtt ) ) != 0 )
  1518. goto err_alloc_mtt;
  1519. /* Hand queue over to hardware */
  1520. memset ( &eqctx, 0, sizeof ( eqctx ) );
  1521. MLX_FILL_1 ( &eqctx, 0, st, 0xa /* "Fired" */ );
  1522. MLX_FILL_1 ( &eqctx, 2,
  1523. page_offset, ( hermon_eq->mtt.page_offset >> 5 ) );
  1524. MLX_FILL_1 ( &eqctx, 3, log_eq_size, fls ( HERMON_NUM_EQES - 1 ) );
  1525. MLX_FILL_1 ( &eqctx, 7, mtt_base_addr_l,
  1526. ( hermon_eq->mtt.mtt_base_addr >> 3 ) );
  1527. if ( ( rc = hermon_cmd_sw2hw_eq ( hermon, hermon_eq->eqn,
  1528. &eqctx ) ) != 0 ) {
  1529. DBGC ( hermon, "Hermon %p EQN %#lx SW2HW_EQ failed: %s\n",
  1530. hermon, hermon_eq->eqn, strerror ( rc ) );
  1531. goto err_sw2hw_eq;
  1532. }
  1533. /* Map events to this event queue */
  1534. memset ( &mask, 0, sizeof ( mask ) );
  1535. MLX_FILL_1 ( &mask, 1, port_state_change, 1 );
  1536. if ( ( rc = hermon_cmd_map_eq ( hermon,
  1537. ( HERMON_MAP_EQ | hermon_eq->eqn ),
  1538. &mask ) ) != 0 ) {
  1539. DBGC ( hermon, "Hermon %p EQN %#lx MAP_EQ failed: %s\n",
  1540. hermon, hermon_eq->eqn, strerror ( rc ) );
  1541. goto err_map_eq;
  1542. }
  1543. DBGC ( hermon, "Hermon %p EQN %#lx ring [%08lx,%08lx), doorbell "
  1544. "%08lx\n", hermon, hermon_eq->eqn,
  1545. virt_to_phys ( hermon_eq->eqe ),
  1546. ( virt_to_phys ( hermon_eq->eqe ) + hermon_eq->eqe_size ),
  1547. virt_to_phys ( hermon_eq->doorbell ) );
  1548. return 0;
  1549. err_map_eq:
  1550. hermon_cmd_hw2sw_eq ( hermon, hermon_eq->eqn, &eqctx );
  1551. err_sw2hw_eq:
  1552. hermon_free_mtt ( hermon, &hermon_eq->mtt );
  1553. err_alloc_mtt:
  1554. free_dma ( hermon_eq->eqe, hermon_eq->eqe_size );
  1555. err_eqe:
  1556. memset ( hermon_eq, 0, sizeof ( *hermon_eq ) );
  1557. return rc;
  1558. }
  1559. /**
  1560. * Destroy event queue
  1561. *
  1562. * @v hermon Hermon device
  1563. */
  1564. static void hermon_destroy_eq ( struct hermon *hermon ) {
  1565. struct hermon_event_queue *hermon_eq = &hermon->eq;
  1566. struct hermonprm_eqc eqctx;
  1567. struct hermonprm_event_mask mask;
  1568. int rc;
  1569. /* Unmap events from event queue */
  1570. memset ( &mask, 0, sizeof ( mask ) );
  1571. MLX_FILL_1 ( &mask, 1, port_state_change, 1 );
  1572. if ( ( rc = hermon_cmd_map_eq ( hermon,
  1573. ( HERMON_UNMAP_EQ | hermon_eq->eqn ),
  1574. &mask ) ) != 0 ) {
  1575. DBGC ( hermon, "Hermon %p EQN %#lx FATAL MAP_EQ failed to "
  1576. "unmap: %s\n", hermon, hermon_eq->eqn, strerror ( rc ) );
  1577. /* Continue; HCA may die but system should survive */
  1578. }
  1579. /* Take ownership back from hardware */
  1580. if ( ( rc = hermon_cmd_hw2sw_eq ( hermon, hermon_eq->eqn,
  1581. &eqctx ) ) != 0 ) {
  1582. DBGC ( hermon, "Hermon %p EQN %#lx FATAL HW2SW_EQ failed: %s\n",
  1583. hermon, hermon_eq->eqn, strerror ( rc ) );
  1584. /* Leak memory and return; at least we avoid corruption */
  1585. return;
  1586. }
  1587. /* Free MTT entries */
  1588. hermon_free_mtt ( hermon, &hermon_eq->mtt );
  1589. /* Free memory */
  1590. free_dma ( hermon_eq->eqe, hermon_eq->eqe_size );
  1591. memset ( hermon_eq, 0, sizeof ( *hermon_eq ) );
  1592. }
  1593. /**
  1594. * Handle port state event
  1595. *
  1596. * @v hermon Hermon device
  1597. * @v eqe Port state change event queue entry
  1598. */
  1599. static void hermon_event_port_state_change ( struct hermon *hermon,
  1600. union hermonprm_event_entry *eqe){
  1601. unsigned int port;
  1602. int link_up;
  1603. /* Get port and link status */
  1604. port = ( MLX_GET ( &eqe->port_state_change, data.p ) - 1 );
  1605. link_up = ( MLX_GET ( &eqe->generic, event_sub_type ) & 0x04 );
  1606. DBGC ( hermon, "Hermon %p port %d link %s\n", hermon, ( port + 1 ),
  1607. ( link_up ? "up" : "down" ) );
  1608. /* Sanity check */
  1609. if ( port >= hermon->cap.num_ports ) {
  1610. DBGC ( hermon, "Hermon %p port %d does not exist!\n",
  1611. hermon, ( port + 1 ) );
  1612. return;
  1613. }
  1614. /* Update MAD parameters */
  1615. ib_smc_update ( hermon->ibdev[port], hermon_mad );
  1616. /* Notify Infiniband core of link state change */
  1617. ib_link_state_changed ( hermon->ibdev[port] );
  1618. }
  1619. /**
  1620. * Poll event queue
  1621. *
  1622. * @v ibdev Infiniband device
  1623. */
  1624. static void hermon_poll_eq ( struct ib_device *ibdev ) {
  1625. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1626. struct hermon_event_queue *hermon_eq = &hermon->eq;
  1627. union hermonprm_event_entry *eqe;
  1628. union hermonprm_doorbell_register db_reg;
  1629. unsigned int eqe_idx_mask;
  1630. unsigned int event_type;
  1631. while ( 1 ) {
  1632. /* Look for event entry */
  1633. eqe_idx_mask = ( HERMON_NUM_EQES - 1 );
  1634. eqe = &hermon_eq->eqe[hermon_eq->next_idx & eqe_idx_mask];
  1635. if ( MLX_GET ( &eqe->generic, owner ) ^
  1636. ( ( hermon_eq->next_idx & HERMON_NUM_EQES ) ? 1 : 0 ) ) {
  1637. /* Entry still owned by hardware; end of poll */
  1638. break;
  1639. }
  1640. DBGCP ( hermon, "Hermon %p EQN %#lx event:\n",
  1641. hermon, hermon_eq->eqn );
  1642. DBGCP_HDA ( hermon, virt_to_phys ( eqe ),
  1643. eqe, sizeof ( *eqe ) );
  1644. /* Handle event */
  1645. event_type = MLX_GET ( &eqe->generic, event_type );
  1646. switch ( event_type ) {
  1647. case HERMON_EV_PORT_STATE_CHANGE:
  1648. hermon_event_port_state_change ( hermon, eqe );
  1649. break;
  1650. default:
  1651. DBGC ( hermon, "Hermon %p EQN %#lx unrecognised event "
  1652. "type %#x:\n",
  1653. hermon, hermon_eq->eqn, event_type );
  1654. DBGC_HDA ( hermon, virt_to_phys ( eqe ),
  1655. eqe, sizeof ( *eqe ) );
  1656. break;
  1657. }
  1658. /* Update event queue's index */
  1659. hermon_eq->next_idx++;
  1660. /* Ring doorbell */
  1661. MLX_FILL_1 ( &db_reg.event, 0,
  1662. ci, ( hermon_eq->next_idx & 0x00ffffffUL ) );
  1663. writel ( db_reg.dword[0], hermon_eq->doorbell );
  1664. }
  1665. }
  1666. /***************************************************************************
  1667. *
  1668. * Infiniband link-layer operations
  1669. *
  1670. ***************************************************************************
  1671. */
  1672. /**
  1673. * Sense port type
  1674. *
  1675. * @v ibdev Infiniband device
  1676. * @ret port_type Port type, or negative error
  1677. */
  1678. static int hermon_sense_port_type ( struct ib_device *ibdev ) {
  1679. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1680. struct hermonprm_sense_port sense_port;
  1681. int port_type;
  1682. int rc;
  1683. /* If DPDP is not supported, always assume Infiniband */
  1684. if ( ! hermon->cap.dpdp )
  1685. return HERMON_PORT_TYPE_IB;
  1686. /* Sense the port type */
  1687. if ( ( rc = hermon_cmd_sense_port ( hermon, ibdev->port,
  1688. &sense_port ) ) != 0 ) {
  1689. DBGC ( hermon, "Hermon %p port %d sense failed: %s\n",
  1690. hermon, ibdev->port, strerror ( rc ) );
  1691. return rc;
  1692. }
  1693. port_type = MLX_GET ( &sense_port, port_type );
  1694. DBGC ( hermon, "Hermon %p port %d type %d\n",
  1695. hermon, ibdev->port, port_type );
  1696. return port_type;
  1697. }
  1698. /**
  1699. * Initialise Infiniband link
  1700. *
  1701. * @v ibdev Infiniband device
  1702. * @ret rc Return status code
  1703. */
  1704. static int hermon_open ( struct ib_device *ibdev ) {
  1705. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1706. struct hermonprm_init_port init_port;
  1707. int port_type;
  1708. int rc;
  1709. /* Check we are connected to an Infiniband network */
  1710. if ( ( rc = port_type = hermon_sense_port_type ( ibdev ) ) < 0 )
  1711. return rc;
  1712. if ( port_type != HERMON_PORT_TYPE_IB ) {
  1713. DBGC ( hermon, "Hermon %p port %d not connected to an "
  1714. "Infiniband network", hermon, ibdev->port );
  1715. return -ENOTCONN;
  1716. }
  1717. /* Init Port */
  1718. memset ( &init_port, 0, sizeof ( init_port ) );
  1719. MLX_FILL_2 ( &init_port, 0,
  1720. port_width_cap, 3,
  1721. vl_cap, 1 );
  1722. MLX_FILL_2 ( &init_port, 1,
  1723. mtu, HERMON_MTU_2048,
  1724. max_gid, 1 );
  1725. MLX_FILL_1 ( &init_port, 2, max_pkey, 64 );
  1726. if ( ( rc = hermon_cmd_init_port ( hermon, ibdev->port,
  1727. &init_port ) ) != 0 ) {
  1728. DBGC ( hermon, "Hermon %p port %d could not intialise port: "
  1729. "%s\n", hermon, ibdev->port, strerror ( rc ) );
  1730. return rc;
  1731. }
  1732. /* Update MAD parameters */
  1733. ib_smc_update ( ibdev, hermon_mad );
  1734. return 0;
  1735. }
  1736. /**
  1737. * Close Infiniband link
  1738. *
  1739. * @v ibdev Infiniband device
  1740. */
  1741. static void hermon_close ( struct ib_device *ibdev ) {
  1742. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1743. int rc;
  1744. if ( ( rc = hermon_cmd_close_port ( hermon, ibdev->port ) ) != 0 ) {
  1745. DBGC ( hermon, "Hermon %p port %d could not close port: %s\n",
  1746. hermon, ibdev->port, strerror ( rc ) );
  1747. /* Nothing we can do about this */
  1748. }
  1749. }
  1750. /**
  1751. * Inform embedded subnet management agent of a received MAD
  1752. *
  1753. * @v ibdev Infiniband device
  1754. * @v mad MAD
  1755. * @ret rc Return status code
  1756. */
  1757. static int hermon_inform_sma ( struct ib_device *ibdev,
  1758. union ib_mad *mad ) {
  1759. int rc;
  1760. /* Send the MAD to the embedded SMA */
  1761. if ( ( rc = hermon_mad ( ibdev, mad ) ) != 0 )
  1762. return rc;
  1763. /* Update parameters held in software */
  1764. ib_smc_update ( ibdev, hermon_mad );
  1765. return 0;
  1766. }
  1767. /***************************************************************************
  1768. *
  1769. * Multicast group operations
  1770. *
  1771. ***************************************************************************
  1772. */
  1773. /**
  1774. * Attach to multicast group
  1775. *
  1776. * @v ibdev Infiniband device
  1777. * @v qp Queue pair
  1778. * @v gid Multicast GID
  1779. * @ret rc Return status code
  1780. */
  1781. static int hermon_mcast_attach ( struct ib_device *ibdev,
  1782. struct ib_queue_pair *qp,
  1783. struct ib_gid *gid ) {
  1784. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1785. struct hermonprm_mgm_hash hash;
  1786. struct hermonprm_mcg_entry mcg;
  1787. unsigned int index;
  1788. int rc;
  1789. /* Generate hash table index */
  1790. if ( ( rc = hermon_cmd_mgid_hash ( hermon, gid, &hash ) ) != 0 ) {
  1791. DBGC ( hermon, "Hermon %p could not hash GID: %s\n",
  1792. hermon, strerror ( rc ) );
  1793. return rc;
  1794. }
  1795. index = MLX_GET ( &hash, hash );
  1796. /* Check for existing hash table entry */
  1797. if ( ( rc = hermon_cmd_read_mcg ( hermon, index, &mcg ) ) != 0 ) {
  1798. DBGC ( hermon, "Hermon %p could not read MCG %#x: %s\n",
  1799. hermon, index, strerror ( rc ) );
  1800. return rc;
  1801. }
  1802. if ( MLX_GET ( &mcg, hdr.members_count ) != 0 ) {
  1803. /* FIXME: this implementation allows only a single QP
  1804. * per multicast group, and doesn't handle hash
  1805. * collisions. Sufficient for IPoIB but may need to
  1806. * be extended in future.
  1807. */
  1808. DBGC ( hermon, "Hermon %p MGID index %#x already in use\n",
  1809. hermon, index );
  1810. return -EBUSY;
  1811. }
  1812. /* Update hash table entry */
  1813. MLX_FILL_1 ( &mcg, 1, hdr.members_count, 1 );
  1814. MLX_FILL_1 ( &mcg, 8, qp[0].qpn, qp->qpn );
  1815. memcpy ( &mcg.u.dwords[4], gid, sizeof ( *gid ) );
  1816. if ( ( rc = hermon_cmd_write_mcg ( hermon, index, &mcg ) ) != 0 ) {
  1817. DBGC ( hermon, "Hermon %p could not write MCG %#x: %s\n",
  1818. hermon, index, strerror ( rc ) );
  1819. return rc;
  1820. }
  1821. return 0;
  1822. }
  1823. /**
  1824. * Detach from multicast group
  1825. *
  1826. * @v ibdev Infiniband device
  1827. * @v qp Queue pair
  1828. * @v gid Multicast GID
  1829. */
  1830. static void hermon_mcast_detach ( struct ib_device *ibdev,
  1831. struct ib_queue_pair *qp __unused,
  1832. struct ib_gid *gid ) {
  1833. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1834. struct hermonprm_mgm_hash hash;
  1835. struct hermonprm_mcg_entry mcg;
  1836. unsigned int index;
  1837. int rc;
  1838. /* Generate hash table index */
  1839. if ( ( rc = hermon_cmd_mgid_hash ( hermon, gid, &hash ) ) != 0 ) {
  1840. DBGC ( hermon, "Hermon %p could not hash GID: %s\n",
  1841. hermon, strerror ( rc ) );
  1842. return;
  1843. }
  1844. index = MLX_GET ( &hash, hash );
  1845. /* Clear hash table entry */
  1846. memset ( &mcg, 0, sizeof ( mcg ) );
  1847. if ( ( rc = hermon_cmd_write_mcg ( hermon, index, &mcg ) ) != 0 ) {
  1848. DBGC ( hermon, "Hermon %p could not write MCG %#x: %s\n",
  1849. hermon, index, strerror ( rc ) );
  1850. return;
  1851. }
  1852. }
  1853. /** Hermon Infiniband operations */
  1854. static struct ib_device_operations hermon_ib_operations = {
  1855. .create_cq = hermon_create_cq,
  1856. .destroy_cq = hermon_destroy_cq,
  1857. .create_qp = hermon_create_qp,
  1858. .modify_qp = hermon_modify_qp,
  1859. .destroy_qp = hermon_destroy_qp,
  1860. .post_send = hermon_post_send,
  1861. .post_recv = hermon_post_recv,
  1862. .poll_cq = hermon_poll_cq,
  1863. .poll_eq = hermon_poll_eq,
  1864. .open = hermon_open,
  1865. .close = hermon_close,
  1866. .mcast_attach = hermon_mcast_attach,
  1867. .mcast_detach = hermon_mcast_detach,
  1868. .set_port_info = hermon_inform_sma,
  1869. .set_pkey_table = hermon_inform_sma,
  1870. };
  1871. /***************************************************************************
  1872. *
  1873. * Firmware control
  1874. *
  1875. ***************************************************************************
  1876. */
  1877. /**
  1878. * Map virtual to physical address for firmware usage
  1879. *
  1880. * @v hermon Hermon device
  1881. * @v map Mapping function
  1882. * @v va Virtual address
  1883. * @v pa Physical address
  1884. * @v len Length of region
  1885. * @ret rc Return status code
  1886. */
  1887. static int hermon_map_vpm ( struct hermon *hermon,
  1888. int ( *map ) ( struct hermon *hermon,
  1889. const struct hermonprm_virtual_physical_mapping* ),
  1890. uint64_t va, physaddr_t pa, size_t len ) {
  1891. struct hermonprm_virtual_physical_mapping mapping;
  1892. int rc;
  1893. assert ( ( va & ( HERMON_PAGE_SIZE - 1 ) ) == 0 );
  1894. assert ( ( pa & ( HERMON_PAGE_SIZE - 1 ) ) == 0 );
  1895. assert ( ( len & ( HERMON_PAGE_SIZE - 1 ) ) == 0 );
  1896. /* These mappings tend to generate huge volumes of
  1897. * uninteresting debug data, which basically makes it
  1898. * impossible to use debugging otherwise.
  1899. */
  1900. DBG_DISABLE ( DBGLVL_LOG | DBGLVL_EXTRA );
  1901. while ( len ) {
  1902. memset ( &mapping, 0, sizeof ( mapping ) );
  1903. MLX_FILL_1 ( &mapping, 0, va_h, ( va >> 32 ) );
  1904. MLX_FILL_1 ( &mapping, 1, va_l, ( va >> 12 ) );
  1905. MLX_FILL_2 ( &mapping, 3,
  1906. log2size, 0,
  1907. pa_l, ( pa >> 12 ) );
  1908. if ( ( rc = map ( hermon, &mapping ) ) != 0 ) {
  1909. DBG_ENABLE ( DBGLVL_LOG | DBGLVL_EXTRA );
  1910. DBGC ( hermon, "Hermon %p could not map %llx => %lx: "
  1911. "%s\n", hermon, va, pa, strerror ( rc ) );
  1912. return rc;
  1913. }
  1914. pa += HERMON_PAGE_SIZE;
  1915. va += HERMON_PAGE_SIZE;
  1916. len -= HERMON_PAGE_SIZE;
  1917. }
  1918. DBG_ENABLE ( DBGLVL_LOG | DBGLVL_EXTRA );
  1919. return 0;
  1920. }
  1921. /**
  1922. * Start firmware running
  1923. *
  1924. * @v hermon Hermon device
  1925. * @ret rc Return status code
  1926. */
  1927. static int hermon_start_firmware ( struct hermon *hermon ) {
  1928. struct hermonprm_query_fw fw;
  1929. unsigned int fw_pages;
  1930. size_t fw_size;
  1931. physaddr_t fw_base;
  1932. int rc;
  1933. /* Get firmware parameters */
  1934. if ( ( rc = hermon_cmd_query_fw ( hermon, &fw ) ) != 0 ) {
  1935. DBGC ( hermon, "Hermon %p could not query firmware: %s\n",
  1936. hermon, strerror ( rc ) );
  1937. goto err_query_fw;
  1938. }
  1939. DBGC ( hermon, "Hermon %p firmware version %d.%d.%d\n", hermon,
  1940. MLX_GET ( &fw, fw_rev_major ), MLX_GET ( &fw, fw_rev_minor ),
  1941. MLX_GET ( &fw, fw_rev_subminor ) );
  1942. fw_pages = MLX_GET ( &fw, fw_pages );
  1943. DBGC ( hermon, "Hermon %p requires %d pages (%d kB) for firmware\n",
  1944. hermon, fw_pages, ( fw_pages * ( HERMON_PAGE_SIZE / 1024 ) ) );
  1945. /* Allocate firmware pages and map firmware area */
  1946. fw_size = ( fw_pages * HERMON_PAGE_SIZE );
  1947. hermon->firmware_area = umalloc ( fw_size );
  1948. if ( ! hermon->firmware_area ) {
  1949. rc = -ENOMEM;
  1950. goto err_alloc_fa;
  1951. }
  1952. fw_base = user_to_phys ( hermon->firmware_area, 0 );
  1953. DBGC ( hermon, "Hermon %p firmware area at physical [%08lx,%08lx)\n",
  1954. hermon, fw_base, ( fw_base + fw_size ) );
  1955. if ( ( rc = hermon_map_vpm ( hermon, hermon_cmd_map_fa,
  1956. 0, fw_base, fw_size ) ) != 0 ) {
  1957. DBGC ( hermon, "Hermon %p could not map firmware: %s\n",
  1958. hermon, strerror ( rc ) );
  1959. goto err_map_fa;
  1960. }
  1961. /* Start firmware */
  1962. if ( ( rc = hermon_cmd_run_fw ( hermon ) ) != 0 ) {
  1963. DBGC ( hermon, "Hermon %p could not run firmware: %s\n",
  1964. hermon, strerror ( rc ) );
  1965. goto err_run_fw;
  1966. }
  1967. DBGC ( hermon, "Hermon %p firmware started\n", hermon );
  1968. return 0;
  1969. err_run_fw:
  1970. err_map_fa:
  1971. hermon_cmd_unmap_fa ( hermon );
  1972. ufree ( hermon->firmware_area );
  1973. hermon->firmware_area = UNULL;
  1974. err_alloc_fa:
  1975. err_query_fw:
  1976. return rc;
  1977. }
  1978. /**
  1979. * Stop firmware running
  1980. *
  1981. * @v hermon Hermon device
  1982. */
  1983. static void hermon_stop_firmware ( struct hermon *hermon ) {
  1984. int rc;
  1985. if ( ( rc = hermon_cmd_unmap_fa ( hermon ) ) != 0 ) {
  1986. DBGC ( hermon, "Hermon %p FATAL could not stop firmware: %s\n",
  1987. hermon, strerror ( rc ) );
  1988. /* Leak memory and return; at least we avoid corruption */
  1989. return;
  1990. }
  1991. ufree ( hermon->firmware_area );
  1992. hermon->firmware_area = UNULL;
  1993. }
  1994. /***************************************************************************
  1995. *
  1996. * Infinihost Context Memory management
  1997. *
  1998. ***************************************************************************
  1999. */
  2000. /**
  2001. * Get device limits
  2002. *
  2003. * @v hermon Hermon device
  2004. * @ret rc Return status code
  2005. */
  2006. static int hermon_get_cap ( struct hermon *hermon ) {
  2007. struct hermonprm_query_dev_cap dev_cap;
  2008. int rc;
  2009. if ( ( rc = hermon_cmd_query_dev_cap ( hermon, &dev_cap ) ) != 0 ) {
  2010. DBGC ( hermon, "Hermon %p could not get device limits: %s\n",
  2011. hermon, strerror ( rc ) );
  2012. return rc;
  2013. }
  2014. hermon->cap.cmpt_entry_size = MLX_GET ( &dev_cap, c_mpt_entry_sz );
  2015. hermon->cap.reserved_qps =
  2016. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_qps ) );
  2017. hermon->cap.qpc_entry_size = MLX_GET ( &dev_cap, qpc_entry_sz );
  2018. hermon->cap.altc_entry_size = MLX_GET ( &dev_cap, altc_entry_sz );
  2019. hermon->cap.auxc_entry_size = MLX_GET ( &dev_cap, aux_entry_sz );
  2020. hermon->cap.reserved_srqs =
  2021. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_srqs ) );
  2022. hermon->cap.srqc_entry_size = MLX_GET ( &dev_cap, srq_entry_sz );
  2023. hermon->cap.reserved_cqs =
  2024. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_cqs ) );
  2025. hermon->cap.cqc_entry_size = MLX_GET ( &dev_cap, cqc_entry_sz );
  2026. hermon->cap.reserved_eqs = MLX_GET ( &dev_cap, num_rsvd_eqs );
  2027. hermon->cap.eqc_entry_size = MLX_GET ( &dev_cap, eqc_entry_sz );
  2028. hermon->cap.reserved_mtts =
  2029. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_mtts ) );
  2030. hermon->cap.mtt_entry_size = MLX_GET ( &dev_cap, mtt_entry_sz );
  2031. hermon->cap.reserved_mrws =
  2032. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_mrws ) );
  2033. hermon->cap.dmpt_entry_size = MLX_GET ( &dev_cap, d_mpt_entry_sz );
  2034. hermon->cap.reserved_uars = MLX_GET ( &dev_cap, num_rsvd_uars );
  2035. hermon->cap.num_ports = MLX_GET ( &dev_cap, num_ports );
  2036. hermon->cap.dpdp = MLX_GET ( &dev_cap, dpdp );
  2037. /* Sanity check */
  2038. if ( hermon->cap.num_ports > HERMON_MAX_PORTS ) {
  2039. DBGC ( hermon, "Hermon %p has %d ports (only %d supported)\n",
  2040. hermon, hermon->cap.num_ports, HERMON_MAX_PORTS );
  2041. hermon->cap.num_ports = HERMON_MAX_PORTS;
  2042. }
  2043. return 0;
  2044. }
  2045. /**
  2046. * Get ICM usage
  2047. *
  2048. * @v log_num_entries Log2 of the number of entries
  2049. * @v entry_size Entry size
  2050. * @ret usage Usage size in ICM
  2051. */
  2052. static size_t icm_usage ( unsigned int log_num_entries, size_t entry_size ) {
  2053. size_t usage;
  2054. usage = ( ( 1 << log_num_entries ) * entry_size );
  2055. usage = ( ( usage + HERMON_PAGE_SIZE - 1 ) &
  2056. ~( HERMON_PAGE_SIZE - 1 ) );
  2057. return usage;
  2058. }
  2059. /**
  2060. * Align ICM
  2061. *
  2062. * @v member_size Member size
  2063. * @v cur_icm_offset Current ICM offset
  2064. * @ret align_offset Align to offset
  2065. */
  2066. static size_t icm_align ( u32 member_size,
  2067. u64 cur_icm_offset ) {
  2068. size_t align_offset = 0;
  2069. member_size = member_size & 0xfffff000;
  2070. if ( member_size ) {
  2071. while ( ( cur_icm_offset + align_offset ) % member_size ) {
  2072. align_offset += HERMON_PAGE_SIZE;
  2073. }
  2074. }
  2075. return align_offset;
  2076. }
  2077. /**
  2078. * Allocate ICM
  2079. *
  2080. * @v hermon Hermon device
  2081. * @v init_hca INIT_HCA structure to fill in
  2082. * @ret rc Return status code
  2083. */
  2084. static int hermon_alloc_icm ( struct hermon *hermon,
  2085. struct hermonprm_init_hca *init_hca ) {
  2086. struct hermonprm_scalar_parameter icm_size;
  2087. struct hermonprm_scalar_parameter icm_aux_size;
  2088. uint64_t icm_offset = 0;
  2089. u32 icm_member_size = 0;
  2090. unsigned int log_num_qps, log_num_srqs, log_num_cqs, log_num_eqs;
  2091. unsigned int log_num_mtts, log_num_mpts;
  2092. size_t cmpt_max_len;
  2093. size_t qp_cmpt_len, srq_cmpt_len, cq_cmpt_len, eq_cmpt_len;
  2094. size_t icm_len, icm_aux_len;
  2095. physaddr_t icm_phys;
  2096. int i;
  2097. int rc;
  2098. /*
  2099. * Start by carving up the ICM virtual address space
  2100. *
  2101. */
  2102. /* Calculate number of each object type within ICM */
  2103. log_num_qps = fls ( hermon->cap.reserved_qps +
  2104. HERMON_RSVD_SPECIAL_QPS + HERMON_MAX_QPS - 1 );
  2105. log_num_srqs = fls ( hermon->cap.reserved_srqs - 1 );
  2106. log_num_cqs = fls ( hermon->cap.reserved_cqs + HERMON_MAX_CQS - 1 );
  2107. log_num_eqs = fls ( hermon->cap.reserved_eqs + HERMON_MAX_EQS - 1 );
  2108. log_num_mtts = fls ( hermon->cap.reserved_mtts + HERMON_MAX_MTTS - 1 );
  2109. /* ICM starts with the cMPT tables, which are sparse */
  2110. cmpt_max_len = ( HERMON_CMPT_MAX_ENTRIES *
  2111. ( ( uint64_t ) hermon->cap.cmpt_entry_size ) );
  2112. qp_cmpt_len = icm_usage ( log_num_qps, hermon->cap.cmpt_entry_size );
  2113. hermon->icm_map[HERMON_ICM_QP_CMPT].offset = icm_offset;
  2114. hermon->icm_map[HERMON_ICM_QP_CMPT].len = qp_cmpt_len;
  2115. icm_offset += cmpt_max_len;
  2116. srq_cmpt_len = icm_usage ( log_num_srqs, hermon->cap.cmpt_entry_size );
  2117. hermon->icm_map[HERMON_ICM_SRQ_CMPT].offset = icm_offset;
  2118. hermon->icm_map[HERMON_ICM_SRQ_CMPT].len = srq_cmpt_len;
  2119. icm_offset += cmpt_max_len;
  2120. cq_cmpt_len = icm_usage ( log_num_cqs, hermon->cap.cmpt_entry_size );
  2121. hermon->icm_map[HERMON_ICM_CQ_CMPT].offset = icm_offset;
  2122. hermon->icm_map[HERMON_ICM_CQ_CMPT].len = cq_cmpt_len;
  2123. icm_offset += cmpt_max_len;
  2124. eq_cmpt_len = icm_usage ( log_num_eqs, hermon->cap.cmpt_entry_size );
  2125. hermon->icm_map[HERMON_ICM_EQ_CMPT].offset = icm_offset;
  2126. hermon->icm_map[HERMON_ICM_EQ_CMPT].len = eq_cmpt_len;
  2127. icm_offset += cmpt_max_len;
  2128. hermon->icm_map[HERMON_ICM_OTHER].offset = icm_offset;
  2129. /* Queue pair contexts */
  2130. icm_member_size = icm_usage ( log_num_qps, hermon->cap.qpc_entry_size );
  2131. icm_offset += icm_align ( icm_member_size, icm_offset );
  2132. MLX_FILL_1 ( init_hca, 12,
  2133. qpc_eec_cqc_eqc_rdb_parameters.qpc_base_addr_h,
  2134. ( icm_offset >> 32 ) );
  2135. MLX_FILL_2 ( init_hca, 13,
  2136. qpc_eec_cqc_eqc_rdb_parameters.qpc_base_addr_l,
  2137. ( icm_offset >> 5 ),
  2138. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_qp,
  2139. log_num_qps );
  2140. DBGC ( hermon, "Hermon %p ICM QPC base = %llx\n", hermon, icm_offset );
  2141. icm_offset += icm_member_size;
  2142. /* Extended alternate path contexts */
  2143. icm_member_size = icm_usage ( log_num_qps,
  2144. hermon->cap.altc_entry_size );
  2145. icm_offset += icm_align ( icm_member_size, icm_offset );
  2146. MLX_FILL_1 ( init_hca, 24,
  2147. qpc_eec_cqc_eqc_rdb_parameters.altc_base_addr_h,
  2148. ( icm_offset >> 32 ) );
  2149. MLX_FILL_1 ( init_hca, 25,
  2150. qpc_eec_cqc_eqc_rdb_parameters.altc_base_addr_l,
  2151. icm_offset );
  2152. DBGC ( hermon, "Hermon %p ICM ALTC base = %llx\n", hermon, icm_offset);
  2153. icm_offset += icm_member_size;
  2154. /* Extended auxiliary contexts */
  2155. icm_member_size = icm_usage ( log_num_qps,
  2156. hermon->cap.auxc_entry_size );
  2157. icm_offset += icm_align ( icm_member_size, icm_offset );
  2158. MLX_FILL_1 ( init_hca, 28,
  2159. qpc_eec_cqc_eqc_rdb_parameters.auxc_base_addr_h,
  2160. ( icm_offset >> 32 ) );
  2161. MLX_FILL_1 ( init_hca, 29,
  2162. qpc_eec_cqc_eqc_rdb_parameters.auxc_base_addr_l,
  2163. icm_offset );
  2164. DBGC ( hermon, "Hermon %p ICM AUXC base = %llx\n", hermon, icm_offset);
  2165. icm_offset += icm_member_size;
  2166. /* Shared receive queue contexts */
  2167. icm_member_size = icm_usage ( log_num_srqs,
  2168. hermon->cap.srqc_entry_size );
  2169. icm_offset += icm_align ( icm_member_size, icm_offset );
  2170. MLX_FILL_1 ( init_hca, 18,
  2171. qpc_eec_cqc_eqc_rdb_parameters.srqc_base_addr_h,
  2172. ( icm_offset >> 32 ) );
  2173. MLX_FILL_2 ( init_hca, 19,
  2174. qpc_eec_cqc_eqc_rdb_parameters.srqc_base_addr_l,
  2175. ( icm_offset >> 5 ),
  2176. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_srq,
  2177. log_num_srqs );
  2178. DBGC ( hermon, "Hermon %p ICM SRQC base = %llx\n", hermon, icm_offset);
  2179. icm_offset += icm_member_size;
  2180. /* Completion queue contexts */
  2181. icm_member_size = icm_usage ( log_num_cqs, hermon->cap.cqc_entry_size );
  2182. icm_offset += icm_align ( icm_member_size, icm_offset );
  2183. MLX_FILL_1 ( init_hca, 20,
  2184. qpc_eec_cqc_eqc_rdb_parameters.cqc_base_addr_h,
  2185. ( icm_offset >> 32 ) );
  2186. MLX_FILL_2 ( init_hca, 21,
  2187. qpc_eec_cqc_eqc_rdb_parameters.cqc_base_addr_l,
  2188. ( icm_offset >> 5 ),
  2189. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_cq,
  2190. log_num_cqs );
  2191. DBGC ( hermon, "Hermon %p ICM CQC base = %llx\n", hermon, icm_offset );
  2192. icm_offset += icm_member_size;
  2193. /* Event queue contexts */
  2194. icm_member_size = icm_usage ( log_num_eqs, hermon->cap.eqc_entry_size );
  2195. icm_offset += icm_align ( icm_member_size, icm_offset );
  2196. MLX_FILL_1 ( init_hca, 32,
  2197. qpc_eec_cqc_eqc_rdb_parameters.eqc_base_addr_h,
  2198. ( icm_offset >> 32 ) );
  2199. MLX_FILL_2 ( init_hca, 33,
  2200. qpc_eec_cqc_eqc_rdb_parameters.eqc_base_addr_l,
  2201. ( icm_offset >> 5 ),
  2202. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_eq,
  2203. log_num_eqs );
  2204. DBGC ( hermon, "Hermon %p ICM EQC base = %llx\n", hermon, icm_offset );
  2205. icm_offset += icm_member_size;
  2206. /* Memory translation table */
  2207. icm_member_size = icm_usage ( log_num_mtts,
  2208. hermon->cap.mtt_entry_size );
  2209. icm_offset += icm_align ( icm_member_size, icm_offset );
  2210. MLX_FILL_1 ( init_hca, 64,
  2211. tpt_parameters.mtt_base_addr_h, ( icm_offset >> 32 ) );
  2212. MLX_FILL_1 ( init_hca, 65,
  2213. tpt_parameters.mtt_base_addr_l, icm_offset );
  2214. DBGC ( hermon, "Hermon %p ICM MTT base = %llx\n", hermon, icm_offset );
  2215. icm_offset += icm_member_size;
  2216. /* Memory protection table */
  2217. log_num_mpts = fls ( hermon->cap.reserved_mrws + 1 - 1 );
  2218. icm_member_size = icm_usage ( log_num_mpts,
  2219. hermon->cap.dmpt_entry_size );
  2220. icm_offset += icm_align ( icm_member_size, icm_offset );
  2221. MLX_FILL_1 ( init_hca, 60,
  2222. tpt_parameters.dmpt_base_adr_h, ( icm_offset >> 32 ) );
  2223. MLX_FILL_1 ( init_hca, 61,
  2224. tpt_parameters.dmpt_base_adr_l, icm_offset );
  2225. MLX_FILL_1 ( init_hca, 62,
  2226. tpt_parameters.log_dmpt_sz, log_num_mpts );
  2227. DBGC ( hermon, "Hermon %p ICM DMPT base = %llx\n", hermon, icm_offset);
  2228. icm_offset += icm_usage ( log_num_mpts,
  2229. hermon->cap.dmpt_entry_size );
  2230. /* Multicast table */
  2231. icm_member_size = ( ( 128 * sizeof ( struct hermonprm_mcg_entry ) +
  2232. HERMON_PAGE_SIZE - 1 ) & ~( HERMON_PAGE_SIZE - 1 ) );
  2233. icm_offset += icm_align ( icm_member_size, icm_offset );
  2234. MLX_FILL_1 ( init_hca, 48,
  2235. multicast_parameters.mc_base_addr_h,
  2236. ( icm_offset >> 32 ) );
  2237. MLX_FILL_1 ( init_hca, 49,
  2238. multicast_parameters.mc_base_addr_l, icm_offset );
  2239. MLX_FILL_1 ( init_hca, 52,
  2240. multicast_parameters.log_mc_table_entry_sz,
  2241. fls ( sizeof ( struct hermonprm_mcg_entry ) - 1 ) );
  2242. MLX_FILL_1 ( init_hca, 53,
  2243. multicast_parameters.log_mc_table_hash_sz, 7 );
  2244. MLX_FILL_1 ( init_hca, 54,
  2245. multicast_parameters.log_mc_table_sz, 7 );
  2246. DBGC ( hermon, "Hermon %p ICM MC base = %llx\n", hermon, icm_offset );
  2247. icm_offset += icm_member_size;
  2248. hermon->icm_map[HERMON_ICM_OTHER].len =
  2249. ( icm_offset - hermon->icm_map[HERMON_ICM_OTHER].offset );
  2250. /*
  2251. * Allocate and map physical memory for (portions of) ICM
  2252. *
  2253. * Map is:
  2254. * ICM AUX area (aligned to its own size)
  2255. * cMPT areas
  2256. * Other areas
  2257. */
  2258. /* Calculate physical memory required for ICM */
  2259. icm_len = 0;
  2260. for ( i = 0 ; i < HERMON_ICM_NUM_REGIONS ; i++ ) {
  2261. icm_len += hermon->icm_map[i].len;
  2262. }
  2263. /* Get ICM auxiliary area size */
  2264. memset ( &icm_size, 0, sizeof ( icm_size ) );
  2265. MLX_FILL_1 ( &icm_size, 0, value_hi, ( icm_offset >> 32 ) );
  2266. MLX_FILL_1 ( &icm_size, 1, value, icm_offset );
  2267. if ( ( rc = hermon_cmd_set_icm_size ( hermon, &icm_size,
  2268. &icm_aux_size ) ) != 0 ) {
  2269. DBGC ( hermon, "Hermon %p could not set ICM size: %s\n",
  2270. hermon, strerror ( rc ) );
  2271. goto err_set_icm_size;
  2272. }
  2273. icm_aux_len = ( MLX_GET ( &icm_aux_size, value ) * HERMON_PAGE_SIZE );
  2274. /* Allocate ICM data and auxiliary area */
  2275. DBGC ( hermon, "Hermon %p requires %zd kB ICM and %zd kB AUX ICM\n",
  2276. hermon, ( icm_len / 1024 ), ( icm_aux_len / 1024 ) );
  2277. hermon->icm = umalloc ( icm_aux_len + icm_len );
  2278. if ( ! hermon->icm ) {
  2279. rc = -ENOMEM;
  2280. goto err_alloc;
  2281. }
  2282. icm_phys = user_to_phys ( hermon->icm, 0 );
  2283. /* Map ICM auxiliary area */
  2284. DBGC ( hermon, "Hermon %p mapping ICM AUX => %08lx\n",
  2285. hermon, icm_phys );
  2286. if ( ( rc = hermon_map_vpm ( hermon, hermon_cmd_map_icm_aux,
  2287. 0, icm_phys, icm_aux_len ) ) != 0 ) {
  2288. DBGC ( hermon, "Hermon %p could not map AUX ICM: %s\n",
  2289. hermon, strerror ( rc ) );
  2290. goto err_map_icm_aux;
  2291. }
  2292. icm_phys += icm_aux_len;
  2293. /* MAP ICM area */
  2294. for ( i = 0 ; i < HERMON_ICM_NUM_REGIONS ; i++ ) {
  2295. DBGC ( hermon, "Hermon %p mapping ICM %llx+%zx => %08lx\n",
  2296. hermon, hermon->icm_map[i].offset,
  2297. hermon->icm_map[i].len, icm_phys );
  2298. if ( ( rc = hermon_map_vpm ( hermon, hermon_cmd_map_icm,
  2299. hermon->icm_map[i].offset,
  2300. icm_phys,
  2301. hermon->icm_map[i].len ) ) != 0 ){
  2302. DBGC ( hermon, "Hermon %p could not map ICM: %s\n",
  2303. hermon, strerror ( rc ) );
  2304. goto err_map_icm;
  2305. }
  2306. icm_phys += hermon->icm_map[i].len;
  2307. }
  2308. return 0;
  2309. err_map_icm:
  2310. assert ( i == 0 ); /* We don't handle partial failure at present */
  2311. err_map_icm_aux:
  2312. hermon_cmd_unmap_icm_aux ( hermon );
  2313. ufree ( hermon->icm );
  2314. hermon->icm = UNULL;
  2315. err_alloc:
  2316. err_set_icm_size:
  2317. return rc;
  2318. }
  2319. /**
  2320. * Free ICM
  2321. *
  2322. * @v hermon Hermon device
  2323. */
  2324. static void hermon_free_icm ( struct hermon *hermon ) {
  2325. struct hermonprm_scalar_parameter unmap_icm;
  2326. int i;
  2327. for ( i = ( HERMON_ICM_NUM_REGIONS - 1 ) ; i >= 0 ; i-- ) {
  2328. memset ( &unmap_icm, 0, sizeof ( unmap_icm ) );
  2329. MLX_FILL_1 ( &unmap_icm, 0, value_hi,
  2330. ( hermon->icm_map[i].offset >> 32 ) );
  2331. MLX_FILL_1 ( &unmap_icm, 1, value,
  2332. hermon->icm_map[i].offset );
  2333. hermon_cmd_unmap_icm ( hermon,
  2334. ( 1 << fls ( ( hermon->icm_map[i].len /
  2335. HERMON_PAGE_SIZE ) - 1)),
  2336. &unmap_icm );
  2337. }
  2338. hermon_cmd_unmap_icm_aux ( hermon );
  2339. ufree ( hermon->icm );
  2340. hermon->icm = UNULL;
  2341. }
  2342. /***************************************************************************
  2343. *
  2344. * PCI interface
  2345. *
  2346. ***************************************************************************
  2347. */
  2348. /**
  2349. * Set up memory protection table
  2350. *
  2351. * @v hermon Hermon device
  2352. * @ret rc Return status code
  2353. */
  2354. static int hermon_setup_mpt ( struct hermon *hermon ) {
  2355. struct hermonprm_mpt mpt;
  2356. uint32_t key;
  2357. int rc;
  2358. /* Derive key */
  2359. key = ( hermon->cap.reserved_mrws | HERMON_MKEY_PREFIX );
  2360. hermon->lkey = ( ( key << 8 ) | ( key >> 24 ) );
  2361. /* Initialise memory protection table */
  2362. memset ( &mpt, 0, sizeof ( mpt ) );
  2363. MLX_FILL_7 ( &mpt, 0,
  2364. atomic, 1,
  2365. rw, 1,
  2366. rr, 1,
  2367. lw, 1,
  2368. lr, 1,
  2369. pa, 1,
  2370. r_w, 1 );
  2371. MLX_FILL_1 ( &mpt, 2, mem_key, key );
  2372. MLX_FILL_1 ( &mpt, 3,
  2373. pd, HERMON_GLOBAL_PD );
  2374. MLX_FILL_1 ( &mpt, 10, len64, 1 );
  2375. if ( ( rc = hermon_cmd_sw2hw_mpt ( hermon,
  2376. hermon->cap.reserved_mrws,
  2377. &mpt ) ) != 0 ) {
  2378. DBGC ( hermon, "Hermon %p could not set up MPT: %s\n",
  2379. hermon, strerror ( rc ) );
  2380. return rc;
  2381. }
  2382. return 0;
  2383. }
  2384. /**
  2385. * Configure special queue pairs
  2386. *
  2387. * @v hermon Hermon device
  2388. * @ret rc Return status code
  2389. */
  2390. static int hermon_configure_special_qps ( struct hermon *hermon ) {
  2391. int rc;
  2392. /* Special QP block must be aligned on its own size */
  2393. hermon->special_qpn_base = ( ( hermon->cap.reserved_qps +
  2394. HERMON_NUM_SPECIAL_QPS - 1 )
  2395. & ~( HERMON_NUM_SPECIAL_QPS - 1 ) );
  2396. hermon->qpn_base = ( hermon->special_qpn_base +
  2397. HERMON_NUM_SPECIAL_QPS );
  2398. DBGC ( hermon, "Hermon %p special QPs at [%lx,%lx]\n", hermon,
  2399. hermon->special_qpn_base, ( hermon->qpn_base - 1 ) );
  2400. /* Issue command to configure special QPs */
  2401. if ( ( rc = hermon_cmd_conf_special_qp ( hermon, 0x00,
  2402. hermon->special_qpn_base ) ) != 0 ) {
  2403. DBGC ( hermon, "Hermon %p could not configure special QPs: "
  2404. "%s\n", hermon, strerror ( rc ) );
  2405. return rc;
  2406. }
  2407. return 0;
  2408. }
  2409. /**
  2410. * Reset device
  2411. *
  2412. * @v hermon Hermon device
  2413. * @v pci PCI device
  2414. */
  2415. static void hermon_reset ( struct hermon *hermon,
  2416. struct pci_device *pci ) {
  2417. struct pci_config_backup backup;
  2418. static const uint8_t backup_exclude[] =
  2419. PCI_CONFIG_BACKUP_EXCLUDE ( 0x58, 0x5c );
  2420. pci_backup ( pci, &backup, backup_exclude );
  2421. writel ( HERMON_RESET_MAGIC,
  2422. ( hermon->config + HERMON_RESET_OFFSET ) );
  2423. mdelay ( HERMON_RESET_WAIT_TIME_MS );
  2424. pci_restore ( pci, &backup, backup_exclude );
  2425. }
  2426. /**
  2427. * Probe PCI device
  2428. *
  2429. * @v pci PCI device
  2430. * @v id PCI ID
  2431. * @ret rc Return status code
  2432. */
  2433. static int hermon_probe ( struct pci_device *pci,
  2434. const struct pci_device_id *id __unused ) {
  2435. struct hermon *hermon;
  2436. struct ib_device *ibdev;
  2437. struct hermonprm_init_hca init_hca;
  2438. unsigned int i;
  2439. int rc;
  2440. /* Allocate Hermon device */
  2441. hermon = zalloc ( sizeof ( *hermon ) );
  2442. if ( ! hermon ) {
  2443. rc = -ENOMEM;
  2444. goto err_alloc_hermon;
  2445. }
  2446. pci_set_drvdata ( pci, hermon );
  2447. /* Fix up PCI device */
  2448. adjust_pci_device ( pci );
  2449. /* Get PCI BARs */
  2450. hermon->config = ioremap ( pci_bar_start ( pci, HERMON_PCI_CONFIG_BAR),
  2451. HERMON_PCI_CONFIG_BAR_SIZE );
  2452. hermon->uar = ioremap ( pci_bar_start ( pci, HERMON_PCI_UAR_BAR ),
  2453. HERMON_UAR_NON_EQ_PAGE * HERMON_PAGE_SIZE );
  2454. /* Reset device */
  2455. hermon_reset ( hermon, pci );
  2456. /* Allocate space for mailboxes */
  2457. hermon->mailbox_in = malloc_dma ( HERMON_MBOX_SIZE,
  2458. HERMON_MBOX_ALIGN );
  2459. if ( ! hermon->mailbox_in ) {
  2460. rc = -ENOMEM;
  2461. goto err_mailbox_in;
  2462. }
  2463. hermon->mailbox_out = malloc_dma ( HERMON_MBOX_SIZE,
  2464. HERMON_MBOX_ALIGN );
  2465. if ( ! hermon->mailbox_out ) {
  2466. rc = -ENOMEM;
  2467. goto err_mailbox_out;
  2468. }
  2469. /* Start firmware */
  2470. if ( ( rc = hermon_start_firmware ( hermon ) ) != 0 )
  2471. goto err_start_firmware;
  2472. /* Get device limits */
  2473. if ( ( rc = hermon_get_cap ( hermon ) ) != 0 )
  2474. goto err_get_cap;
  2475. /* Allocate Infiniband devices */
  2476. for ( i = 0 ; i < hermon->cap.num_ports ; i++ ) {
  2477. ibdev = alloc_ibdev ( 0 );
  2478. if ( ! ibdev ) {
  2479. rc = -ENOMEM;
  2480. goto err_alloc_ibdev;
  2481. }
  2482. hermon->ibdev[i] = ibdev;
  2483. ibdev->op = &hermon_ib_operations;
  2484. ibdev->dev = &pci->dev;
  2485. ibdev->port = ( HERMON_PORT_BASE + i );
  2486. ib_set_drvdata ( ibdev, hermon );
  2487. }
  2488. /* Allocate ICM */
  2489. memset ( &init_hca, 0, sizeof ( init_hca ) );
  2490. if ( ( rc = hermon_alloc_icm ( hermon, &init_hca ) ) != 0 )
  2491. goto err_alloc_icm;
  2492. /* Initialise HCA */
  2493. MLX_FILL_1 ( &init_hca, 0, version, 0x02 /* "Must be 0x02" */ );
  2494. MLX_FILL_1 ( &init_hca, 5, udp, 1 );
  2495. MLX_FILL_1 ( &init_hca, 74, uar_parameters.log_max_uars, 8 );
  2496. if ( ( rc = hermon_cmd_init_hca ( hermon, &init_hca ) ) != 0 ) {
  2497. DBGC ( hermon, "Hermon %p could not initialise HCA: %s\n",
  2498. hermon, strerror ( rc ) );
  2499. goto err_init_hca;
  2500. }
  2501. /* Set up memory protection */
  2502. if ( ( rc = hermon_setup_mpt ( hermon ) ) != 0 )
  2503. goto err_setup_mpt;
  2504. for ( i = 0 ; i < hermon->cap.num_ports ; i++ )
  2505. hermon->ibdev[i]->rdma_key = hermon->lkey;
  2506. /* Set up event queue */
  2507. if ( ( rc = hermon_create_eq ( hermon ) ) != 0 )
  2508. goto err_create_eq;
  2509. /* Configure special QPs */
  2510. if ( ( rc = hermon_configure_special_qps ( hermon ) ) != 0 )
  2511. goto err_conf_special_qps;
  2512. /* Update IPoIB MAC address */
  2513. for ( i = 0 ; i < hermon->cap.num_ports ; i++ ) {
  2514. ib_smc_update ( hermon->ibdev[i], hermon_mad );
  2515. }
  2516. /* Register Infiniband devices */
  2517. for ( i = 0 ; i < hermon->cap.num_ports ; i++ ) {
  2518. if ( ( rc = register_ibdev ( hermon->ibdev[i] ) ) != 0 ) {
  2519. DBGC ( hermon, "Hermon %p port %d could not register "
  2520. "IB device: %s\n", hermon,
  2521. hermon->ibdev[i]->port, strerror ( rc ) );
  2522. goto err_register_ibdev;
  2523. }
  2524. }
  2525. return 0;
  2526. i = hermon->cap.num_ports;
  2527. err_register_ibdev:
  2528. for ( i-- ; ( signed int ) i >= 0 ; i-- )
  2529. unregister_ibdev ( hermon->ibdev[i] );
  2530. err_conf_special_qps:
  2531. hermon_destroy_eq ( hermon );
  2532. err_create_eq:
  2533. err_setup_mpt:
  2534. hermon_cmd_close_hca ( hermon );
  2535. err_init_hca:
  2536. hermon_free_icm ( hermon );
  2537. err_alloc_icm:
  2538. i = hermon->cap.num_ports;
  2539. err_alloc_ibdev:
  2540. for ( i-- ; ( signed int ) i >= 0 ; i-- )
  2541. ibdev_put ( hermon->ibdev[i] );
  2542. err_get_cap:
  2543. hermon_stop_firmware ( hermon );
  2544. err_start_firmware:
  2545. free_dma ( hermon->mailbox_out, HERMON_MBOX_SIZE );
  2546. err_mailbox_out:
  2547. free_dma ( hermon->mailbox_in, HERMON_MBOX_SIZE );
  2548. err_mailbox_in:
  2549. free ( hermon );
  2550. err_alloc_hermon:
  2551. return rc;
  2552. }
  2553. /**
  2554. * Remove PCI device
  2555. *
  2556. * @v pci PCI device
  2557. */
  2558. static void hermon_remove ( struct pci_device *pci ) {
  2559. struct hermon *hermon = pci_get_drvdata ( pci );
  2560. int i;
  2561. for ( i = ( hermon->cap.num_ports - 1 ) ; i >= 0 ; i-- )
  2562. unregister_ibdev ( hermon->ibdev[i] );
  2563. hermon_destroy_eq ( hermon );
  2564. hermon_cmd_close_hca ( hermon );
  2565. hermon_free_icm ( hermon );
  2566. hermon_stop_firmware ( hermon );
  2567. hermon_stop_firmware ( hermon );
  2568. free_dma ( hermon->mailbox_out, HERMON_MBOX_SIZE );
  2569. free_dma ( hermon->mailbox_in, HERMON_MBOX_SIZE );
  2570. for ( i = ( hermon->cap.num_ports - 1 ) ; i >= 0 ; i-- )
  2571. ibdev_put ( hermon->ibdev[i] );
  2572. free ( hermon );
  2573. }
  2574. static struct pci_device_id hermon_nics[] = {
  2575. PCI_ROM ( 0x15b3, 0x6340, "mt25408", "MT25408 HCA driver", 0 ),
  2576. PCI_ROM ( 0x15b3, 0x634a, "mt25418", "MT25418 HCA driver", 0 ),
  2577. PCI_ROM ( 0x15b3, 0x6732, "mt26418", "MT26418 HCA driver", 0 ),
  2578. PCI_ROM ( 0x15b3, 0x673c, "mt26428", "MT26428 HCA driver", 0 ),
  2579. };
  2580. struct pci_driver hermon_driver __pci_driver = {
  2581. .ids = hermon_nics,
  2582. .id_count = ( sizeof ( hermon_nics ) / sizeof ( hermon_nics[0] ) ),
  2583. .probe = hermon_probe,
  2584. .remove = hermon_remove,
  2585. };