您最多选择25个主题 主题必须以字母或数字开头,可以包含连字符 (-),并且长度不得超过35个字符

qib_7322_regs.h 233KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839284028412842284328442845284628472848284928502851285228532854285528562857285828592860286128622863286428652866286728682869287028712872287328742875287628772878287928802881288228832884288528862887288828892890289128922893289428952896289728982899290029012902290329042905290629072908290929102911291229132914291529162917291829192920292129222923292429252926292729282929293029312932293329342935293629372938293929402941294229432944294529462947294829492950295129522953295429552956295729582959296029612962296329642965296629672968296929702971297229732974297529762977297829792980298129822983298429852986298729882989299029912992299329942995299629972998299930003001300230033004300530063007300830093010301130123013301430153016301730183019302030213022302330243025302630273028302930303031303230333034303530363037303830393040304130423043304430453046304730483049305030513052305330543055305630573058305930603061306230633064306530663067306830693070307130723073307430753076307730783079308030813082308330843085308630873088308930903091309230933094309530963097309830993100310131023103310431053106310731083109311031113112311331143115311631173118311931203121312231233124312531263127312831293130313131323133313431353136313731383139314031413142314331443145314631473148314931503151315231533154315531563157315831593160316131623163316431653166316731683169317031713172317331743175317631773178317931803181318231833184318531863187318831893190319131923193319431953196319731983199320032013202320332043205320632073208320932103211321232133214321532163217321832193220322132223223322432253226322732283229323032313232323332343235323632373238323932403241324232433244324532463247324832493250325132523253325432553256325732583259326032613262326332643265326632673268326932703271327232733274327532763277327832793280328132823283328432853286328732883289329032913292329332943295329632973298329933003301330233033304330533063307330833093310331133123313331433153316331733183319332033213322332333243325332633273328332933303331333233333334333533363337333833393340334133423343334433453346334733483349335033513352335333543355335633573358335933603361336233633364336533663367336833693370337133723373337433753376337733783379338033813382338333843385338633873388338933903391339233933394339533963397339833993400340134023403340434053406340734083409341034113412341334143415341634173418341934203421342234233424342534263427342834293430343134323433343434353436343734383439344034413442344334443445344634473448344934503451345234533454345534563457345834593460346134623463346434653466346734683469347034713472347334743475347634773478347934803481348234833484348534863487348834893490349134923493349434953496349734983499350035013502350335043505350635073508350935103511351235133514351535163517351835193520352135223523352435253526352735283529353035313532353335343535353635373538353935403541354235433544354535463547354835493550355135523553355435553556355735583559356035613562356335643565356635673568356935703571357235733574357535763577357835793580358135823583358435853586358735883589359035913592359335943595359635973598359936003601360236033604360536063607360836093610361136123613361436153616361736183619362036213622362336243625362636273628362936303631363236333634363536363637363836393640364136423643364436453646364736483649365036513652365336543655365636573658365936603661366236633664366536663667366836693670367136723673367436753676367736783679368036813682368336843685368636873688368936903691369236933694369536963697369836993700370137023703370437053706370737083709371037113712371337143715371637173718371937203721372237233724372537263727372837293730373137323733373437353736373737383739374037413742374337443745374637473748374937503751375237533754375537563757375837593760376137623763376437653766376737683769377037713772377337743775377637773778377937803781378237833784378537863787378837893790379137923793379437953796379737983799380038013802380338043805380638073808380938103811381238133814381538163817381838193820382138223823382438253826382738283829383038313832383338343835383638373838383938403841384238433844384538463847384838493850385138523853385438553856385738583859386038613862386338643865386638673868386938703871387238733874387538763877387838793880388138823883388438853886388738883889389038913892389338943895389638973898389939003901390239033904390539063907390839093910391139123913391439153916391739183919392039213922392339243925392639273928392939303931393239333934393539363937393839393940394139423943394439453946394739483949395039513952395339543955395639573958395939603961396239633964396539663967396839693970397139723973397439753976397739783979398039813982398339843985398639873988398939903991399239933994399539963997399839994000400140024003400440054006400740084009401040114012401340144015401640174018401940204021402240234024402540264027402840294030403140324033403440354036403740384039404040414042404340444045404640474048404940504051405240534054405540564057405840594060406140624063406440654066406740684069407040714072407340744075407640774078407940804081408240834084408540864087408840894090409140924093409440954096409740984099410041014102410341044105410641074108410941104111411241134114411541164117411841194120412141224123412441254126412741284129413041314132413341344135413641374138413941404141414241434144414541464147414841494150415141524153415441554156415741584159416041614162416341644165416641674168416941704171417241734174417541764177417841794180418141824183418441854186418741884189419041914192419341944195419641974198419942004201420242034204420542064207420842094210421142124213421442154216421742184219422042214222422342244225422642274228422942304231423242334234423542364237423842394240424142424243424442454246424742484249425042514252425342544255425642574258425942604261426242634264426542664267426842694270427142724273427442754276427742784279428042814282428342844285428642874288428942904291429242934294429542964297429842994300430143024303430443054306430743084309431043114312431343144315431643174318431943204321432243234324432543264327432843294330433143324333433443354336433743384339434043414342434343444345434643474348434943504351435243534354435543564357435843594360436143624363436443654366436743684369437043714372437343744375437643774378437943804381438243834384438543864387438843894390439143924393439443954396439743984399440044014402440344044405440644074408440944104411441244134414441544164417441844194420442144224423442444254426442744284429443044314432443344344435443644374438443944404441444244434444444544464447444844494450445144524453445444554456445744584459446044614462446344644465446644674468446944704471447244734474447544764477447844794480448144824483448444854486448744884489449044914492449344944495449644974498449945004501450245034504450545064507450845094510451145124513451445154516451745184519452045214522452345244525452645274528452945304531453245334534453545364537453845394540454145424543454445454546454745484549455045514552455345544555455645574558455945604561456245634564456545664567456845694570457145724573457445754576457745784579458045814582458345844585458645874588458945904591459245934594459545964597459845994600460146024603460446054606460746084609461046114612461346144615461646174618461946204621462246234624462546264627462846294630463146324633463446354636463746384639464046414642464346444645464646474648464946504651465246534654465546564657465846594660466146624663466446654666466746684669467046714672467346744675467646774678467946804681468246834684468546864687468846894690469146924693469446954696469746984699470047014702470347044705470647074708470947104711471247134714471547164717471847194720472147224723472447254726472747284729473047314732473347344735473647374738473947404741474247434744474547464747474847494750475147524753475447554756475747584759476047614762476347644765476647674768476947704771477247734774477547764777477847794780478147824783478447854786478747884789479047914792479347944795479647974798479948004801480248034804480548064807480848094810481148124813481448154816481748184819482048214822482348244825482648274828482948304831483248334834483548364837483848394840484148424843484448454846484748484849485048514852485348544855485648574858485948604861486248634864486548664867486848694870487148724873487448754876487748784879488048814882488348844885488648874888488948904891489248934894489548964897489848994900490149024903490449054906490749084909491049114912491349144915491649174918491949204921492249234924492549264927492849294930493149324933493449354936493749384939494049414942494349444945494649474948494949504951495249534954495549564957495849594960496149624963496449654966496749684969497049714972497349744975497649774978497949804981498249834984498549864987498849894990499149924993499449954996499749984999500050015002500350045005500650075008500950105011501250135014501550165017501850195020502150225023502450255026502750285029503050315032503350345035503650375038503950405041504250435044504550465047504850495050505150525053505450555056505750585059506050615062506350645065506650675068506950705071507250735074507550765077507850795080508150825083508450855086508750885089509050915092509350945095509650975098509951005101510251035104510551065107510851095110511151125113511451155116511751185119512051215122512351245125512651275128512951305131513251335134513551365137513851395140514151425143514451455146514751485149515051515152515351545155515651575158515951605161516251635164516551665167516851695170517151725173517451755176517751785179518051815182518351845185518651875188518951905191519251935194519551965197519851995200520152025203520452055206520752085209521052115212521352145215521652175218521952205221522252235224522552265227522852295230523152325233523452355236523752385239524052415242524352445245524652475248524952505251525252535254525552565257525852595260526152625263526452655266526752685269527052715272527352745275527652775278527952805281528252835284528552865287528852895290529152925293529452955296529752985299530053015302530353045305530653075308530953105311531253135314531553165317531853195320532153225323532453255326532753285329533053315332533353345335533653375338533953405341534253435344534553465347534853495350535153525353535453555356535753585359536053615362536353645365536653675368536953705371537253735374537553765377537853795380538153825383538453855386538753885389539053915392539353945395539653975398539954005401540254035404540554065407540854095410541154125413541454155416541754185419542054215422542354245425542654275428542954305431543254335434543554365437543854395440544154425443544454455446544754485449545054515452545354545455545654575458545954605461546254635464546554665467546854695470547154725473547454755476547754785479548054815482548354845485548654875488548954905491549254935494549554965497549854995500550155025503550455055506550755085509551055115512551355145515551655175518551955205521552255235524552555265527552855295530553155325533553455355536553755385539554055415542554355445545554655475548554955505551555255535554555555565557555855595560556155625563556455655566556755685569557055715572557355745575557655775578557955805581558255835584558555865587558855895590559155925593559455955596559755985599560056015602560356045605560656075608560956105611561256135614561556165617561856195620562156225623562456255626562756285629563056315632563356345635563656375638563956405641564256435644564556465647564856495650565156525653565456555656565756585659566056615662566356645665566656675668566956705671567256735674567556765677567856795680568156825683568456855686568756885689569056915692569356945695569656975698569957005701570257035704570557065707570857095710571157125713571457155716571757185719572057215722572357245725572657275728572957305731573257335734573557365737573857395740574157425743574457455746574757485749575057515752575357545755575657575758575957605761576257635764576557665767576857695770577157725773577457755776577757785779578057815782578357845785578657875788578957905791579257935794579557965797579857995800580158025803580458055806580758085809581058115812581358145815581658175818581958205821582258235824582558265827582858295830583158325833583458355836583758385839584058415842584358445845584658475848584958505851585258535854585558565857585858595860586158625863586458655866586758685869587058715872587358745875587658775878587958805881588258835884588558865887588858895890589158925893589458955896589758985899590059015902590359045905590659075908590959105911591259135914591559165917591859195920592159225923592459255926592759285929593059315932593359345935593659375938593959405941594259435944594559465947594859495950595159525953595459555956595759585959596059615962596359645965596659675968596959705971597259735974597559765977597859795980598159825983598459855986598759885989599059915992599359945995599659975998599960006001600260036004600560066007600860096010601160126013601460156016601760186019602060216022602360246025602660276028602960306031603260336034603560366037603860396040604160426043604460456046604760486049605060516052605360546055605660576058605960606061606260636064606560666067606860696070607160726073607460756076607760786079608060816082608360846085608660876088608960906091609260936094609560966097609860996100610161026103610461056106610761086109611061116112611361146115611661176118611961206121612261236124612561266127612861296130613161326133613461356136613761386139614061416142614361446145614661476148614961506151615261536154615561566157615861596160616161626163616461656166616761686169617061716172617361746175617661776178617961806181618261836184618561866187618861896190619161926193619461956196619761986199620062016202620362046205620662076208620962106211621262136214621562166217621862196220622162226223622462256226622762286229623062316232623362346235623662376238623962406241624262436244624562466247624862496250625162526253625462556256625762586259626062616262626362646265626662676268626962706271627262736274627562766277627862796280628162826283628462856286628762886289629062916292629362946295629662976298629963006301630263036304630563066307630863096310631163126313631463156316631763186319632063216322632363246325632663276328632963306331633263336334633563366337633863396340634163426343634463456346634763486349635063516352635363546355635663576358635963606361636263636364636563666367636863696370637163726373637463756376637763786379638063816382638363846385638663876388638963906391639263936394639563966397639863996400640164026403640464056406640764086409641064116412641364146415641664176418641964206421642264236424642564266427642864296430643164326433643464356436643764386439644064416442644364446445644664476448644964506451645264536454645564566457645864596460646164626463646464656466646764686469647064716472647364746475647664776478647964806481648264836484648564866487648864896490649164926493649464956496649764986499650065016502650365046505650665076508650965106511651265136514651565166517651865196520652165226523652465256526652765286529653065316532653365346535653665376538653965406541654265436544654565466547654865496550655165526553655465556556655765586559656065616562656365646565656665676568656965706571657265736574657565766577657865796580658165826583658465856586658765886589659065916592659365946595659665976598659966006601660266036604660566066607660866096610661166126613661466156616661766186619662066216622662366246625662666276628662966306631663266336634663566366637663866396640664166426643664466456646664766486649665066516652665366546655665666576658665966606661666266636664666566666667666866696670667166726673667466756676667766786679668066816682668366846685668666876688668966906691669266936694669566966697669866996700670167026703670467056706670767086709671067116712671367146715671667176718671967206721672267236724672567266727672867296730673167326733673467356736673767386739674067416742674367446745674667476748674967506751675267536754675567566757675867596760676167626763676467656766676767686769677067716772677367746775677667776778677967806781678267836784678567866787678867896790679167926793679467956796679767986799680068016802680368046805680668076808680968106811681268136814681568166817681868196820682168226823682468256826682768286829683068316832683368346835683668376838683968406841684268436844684568466847684868496850685168526853685468556856685768586859686068616862686368646865686668676868686968706871687268736874687568766877687868796880688168826883688468856886688768886889689068916892689368946895689668976898689969006901690269036904690569066907690869096910691169126913691469156916691769186919692069216922692369246925692669276928692969306931693269336934693569366937693869396940694169426943694469456946694769486949695069516952695369546955695669576958695969606961696269636964696569666967696869696970697169726973697469756976697769786979698069816982698369846985698669876988698969906991699269936994699569966997699869997000700170027003700470057006700770087009701070117012701370147015701670177018701970207021702270237024702570267027702870297030703170327033703470357036703770387039704070417042704370447045704670477048704970507051705270537054705570567057705870597060706170627063706470657066706770687069707070717072707370747075707670777078707970807081708270837084708570867087708870897090709170927093709470957096709770987099710071017102710371047105710671077108710971107111711271137114711571167117711871197120712171227123712471257126712771287129713071317132713371347135713671377138713971407141714271437144714571467147714871497150715171527153715471557156715771587159716071617162716371647165716671677168716971707171717271737174717571767177717871797180718171827183718471857186718771887189719071917192719371947195719671977198719972007201720272037204720572067207720872097210721172127213721472157216721772187219722072217222722372247225722672277228722972307231723272337234723572367237723872397240724172427243724472457246724772487249725072517252725372547255725672577258725972607261
  1. /*
  2. * Copyright (c) 2008, 2009 QLogic Corporation. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. /* This file is mechanically generated from RTL. Any hand-edits will be lost! */
  33. /* This file has been further processed by ./drivers/infiniband/qib_genbits.pl */
  34. FILE_LICENCE ( GPL2_ONLY );
  35. #define QIB_7322_Revision_offset 0x00000000UL
  36. struct QIB_7322_Revision_pb {
  37. pseudo_bit_t R_ChipRevMinor[8];
  38. pseudo_bit_t R_ChipRevMajor[8];
  39. pseudo_bit_t R_Arch[8];
  40. pseudo_bit_t R_SW[8];
  41. pseudo_bit_t BoardID[8];
  42. pseudo_bit_t R_Emulation_Revcode[22];
  43. pseudo_bit_t R_Emulation[1];
  44. pseudo_bit_t R_Simulator[1];
  45. };
  46. struct QIB_7322_Revision {
  47. PSEUDO_BIT_STRUCT ( struct QIB_7322_Revision_pb );
  48. };
  49. /* Default value: 0x0000000002010601 */
  50. #define QIB_7322_Control_offset 0x00000008UL
  51. struct QIB_7322_Control_pb {
  52. pseudo_bit_t SyncReset[1];
  53. pseudo_bit_t FreezeMode[1];
  54. pseudo_bit_t _unused_0[1];
  55. pseudo_bit_t PCIERetryBufDiagEn[1];
  56. pseudo_bit_t SDmaDescFetchPriorityEn[1];
  57. pseudo_bit_t PCIEPostQDiagEn[1];
  58. pseudo_bit_t PCIECplQDiagEn[1];
  59. pseudo_bit_t _unused_1[57];
  60. };
  61. struct QIB_7322_Control {
  62. PSEUDO_BIT_STRUCT ( struct QIB_7322_Control_pb );
  63. };
  64. /* Default value: 0x0000000000000000 */
  65. #define QIB_7322_PageAlign_offset 0x00000010UL
  66. /* Default value: 0x0000000000001000 */
  67. #define QIB_7322_ContextCnt_offset 0x00000018UL
  68. /* Default value: 0x0000000000000012 */
  69. #define QIB_7322_Scratch_offset 0x00000020UL
  70. /* Default value: 0x0000000000000000 */
  71. #define QIB_7322_CntrRegBase_offset 0x00000028UL
  72. /* Default value: 0x0000000000011000 */
  73. #define QIB_7322_SendRegBase_offset 0x00000030UL
  74. /* Default value: 0x0000000000003000 */
  75. #define QIB_7322_UserRegBase_offset 0x00000038UL
  76. /* Default value: 0x0000000000200000 */
  77. #define QIB_7322_DebugPortSel_offset 0x00000040UL
  78. struct QIB_7322_DebugPortSel_pb {
  79. pseudo_bit_t DebugOutMuxSel[2];
  80. pseudo_bit_t _unused_0[28];
  81. pseudo_bit_t SrcMuxSel0[8];
  82. pseudo_bit_t SrcMuxSel1[8];
  83. pseudo_bit_t DbgClkPortSel[5];
  84. pseudo_bit_t EnDbgPort[1];
  85. pseudo_bit_t EnEnhancedDebugMode[1];
  86. pseudo_bit_t EnhMode_SrcMuxSelIndex[10];
  87. pseudo_bit_t EnhMode_SrcMuxSelWrEn[1];
  88. };
  89. struct QIB_7322_DebugPortSel {
  90. PSEUDO_BIT_STRUCT ( struct QIB_7322_DebugPortSel_pb );
  91. };
  92. /* Default value: 0x0000000000000000 */
  93. #define QIB_7322_DebugPortNibbleSel_offset 0x00000048UL
  94. struct QIB_7322_DebugPortNibbleSel_pb {
  95. pseudo_bit_t NibbleSel0[4];
  96. pseudo_bit_t NibbleSel1[4];
  97. pseudo_bit_t NibbleSel2[4];
  98. pseudo_bit_t NibbleSel3[4];
  99. pseudo_bit_t NibbleSel4[4];
  100. pseudo_bit_t NibbleSel5[4];
  101. pseudo_bit_t NibbleSel6[4];
  102. pseudo_bit_t NibbleSel7[4];
  103. pseudo_bit_t NibbleSel8[4];
  104. pseudo_bit_t NibbleSel9[4];
  105. pseudo_bit_t NibbleSel10[4];
  106. pseudo_bit_t NibbleSel11[4];
  107. pseudo_bit_t NibbleSel12[4];
  108. pseudo_bit_t NibbleSel13[4];
  109. pseudo_bit_t NibbleSel14[4];
  110. pseudo_bit_t NibbleSel15[4];
  111. };
  112. struct QIB_7322_DebugPortNibbleSel {
  113. PSEUDO_BIT_STRUCT ( struct QIB_7322_DebugPortNibbleSel_pb );
  114. };
  115. /* Default value: 0xFEDCBA9876543210 */
  116. #define QIB_7322_DebugSigsIntSel_offset 0x00000050UL
  117. struct QIB_7322_DebugSigsIntSel_pb {
  118. pseudo_bit_t debug_port_sel_pcs_pipe_lane07[3];
  119. pseudo_bit_t debug_port_sel_pcs_pipe_lane815[3];
  120. pseudo_bit_t debug_port_sel_pcs_sdout[1];
  121. pseudo_bit_t debug_port_sel_pcs_symlock_elfifo_lane[4];
  122. pseudo_bit_t debug_port_sel_pcs_rxdet_encdec_lane[3];
  123. pseudo_bit_t EnableSDma_SelfDrain[1];
  124. pseudo_bit_t debug_port_sel_pcie_rx_tx[1];
  125. pseudo_bit_t _unused_0[1];
  126. pseudo_bit_t debug_port_sel_tx_ibport[1];
  127. pseudo_bit_t debug_port_sel_tx_sdma[1];
  128. pseudo_bit_t debug_port_sel_rx_ibport[1];
  129. pseudo_bit_t _unused_1[12];
  130. pseudo_bit_t debug_port_sel_xgxs_0[4];
  131. pseudo_bit_t debug_port_sel_credit_a_0[3];
  132. pseudo_bit_t debug_port_sel_credit_b_0[3];
  133. pseudo_bit_t debug_port_sel_xgxs_1[4];
  134. pseudo_bit_t debug_port_sel_credit_a_1[3];
  135. pseudo_bit_t debug_port_sel_credit_b_1[3];
  136. pseudo_bit_t _unused_2[12];
  137. };
  138. struct QIB_7322_DebugSigsIntSel {
  139. PSEUDO_BIT_STRUCT ( struct QIB_7322_DebugSigsIntSel_pb );
  140. };
  141. /* Default value: 0x0000000000000000 */
  142. #define QIB_7322_DebugPortValueReg_offset 0x00000058UL
  143. #define QIB_7322_IntBlocked_offset 0x00000060UL
  144. struct QIB_7322_IntBlocked_pb {
  145. pseudo_bit_t RcvAvail0IntBlocked[1];
  146. pseudo_bit_t RcvAvail1IntBlocked[1];
  147. pseudo_bit_t RcvAvail2IntBlocked[1];
  148. pseudo_bit_t RcvAvail3IntBlocked[1];
  149. pseudo_bit_t RcvAvail4IntBlocked[1];
  150. pseudo_bit_t RcvAvail5IntBlocked[1];
  151. pseudo_bit_t RcvAvail6IntBlocked[1];
  152. pseudo_bit_t RcvAvail7IntBlocked[1];
  153. pseudo_bit_t RcvAvail8IntBlocked[1];
  154. pseudo_bit_t RcvAvail9IntBlocked[1];
  155. pseudo_bit_t RcvAvail10IntBlocked[1];
  156. pseudo_bit_t RcvAvail11IntBlocked[1];
  157. pseudo_bit_t RcvAvail12IntBlocked[1];
  158. pseudo_bit_t RcvAvail13IntBlocked[1];
  159. pseudo_bit_t RcvAvail14IntBlocked[1];
  160. pseudo_bit_t RcvAvail15IntBlocked[1];
  161. pseudo_bit_t RcvAvail16IntBlocked[1];
  162. pseudo_bit_t RcvAvail17IntBlocked[1];
  163. pseudo_bit_t _unused_0[5];
  164. pseudo_bit_t SendBufAvailIntBlocked[1];
  165. pseudo_bit_t SendDoneIntBlocked_0[1];
  166. pseudo_bit_t SendDoneIntBlocked_1[1];
  167. pseudo_bit_t _unused_1[2];
  168. pseudo_bit_t AssertGPIOIntBlocked[1];
  169. pseudo_bit_t ErrIntBlocked[1];
  170. pseudo_bit_t ErrIntBlocked_0[1];
  171. pseudo_bit_t ErrIntBlocked_1[1];
  172. pseudo_bit_t RcvUrg0IntBlocked[1];
  173. pseudo_bit_t RcvUrg1IntBlocked[1];
  174. pseudo_bit_t RcvUrg2IntBlocked[1];
  175. pseudo_bit_t RcvUrg3IntBlocked[1];
  176. pseudo_bit_t RcvUrg4IntBlocked[1];
  177. pseudo_bit_t RcvUrg5IntBlocked[1];
  178. pseudo_bit_t RcvUrg6IntBlocked[1];
  179. pseudo_bit_t RcvUrg7IntBlocked[1];
  180. pseudo_bit_t RcvUrg8IntBlocked[1];
  181. pseudo_bit_t RcvUrg9IntBlocked[1];
  182. pseudo_bit_t RcvUrg10IntBlocked[1];
  183. pseudo_bit_t RcvUrg11IntBlocked[1];
  184. pseudo_bit_t RcvUrg12IntBlocked[1];
  185. pseudo_bit_t RcvUrg13IntBlocked[1];
  186. pseudo_bit_t RcvUrg14IntBlocked[1];
  187. pseudo_bit_t RcvUrg15IntBlocked[1];
  188. pseudo_bit_t RcvUrg16IntBlocked[1];
  189. pseudo_bit_t RcvUrg17IntBlocked[1];
  190. pseudo_bit_t _unused_2[6];
  191. pseudo_bit_t SDmaCleanupDoneBlocked_0[1];
  192. pseudo_bit_t SDmaCleanupDoneBlocked_1[1];
  193. pseudo_bit_t SDmaIdleIntBlocked_0[1];
  194. pseudo_bit_t SDmaIdleIntBlocked_1[1];
  195. pseudo_bit_t SDmaProgressIntBlocked_0[1];
  196. pseudo_bit_t SDmaProgressIntBlocked_1[1];
  197. pseudo_bit_t SDmaIntBlocked_0[1];
  198. pseudo_bit_t SDmaIntBlocked_1[1];
  199. };
  200. struct QIB_7322_IntBlocked {
  201. PSEUDO_BIT_STRUCT ( struct QIB_7322_IntBlocked_pb );
  202. };
  203. /* Default value: 0x0000000000000000 */
  204. #define QIB_7322_IntMask_offset 0x00000068UL
  205. struct QIB_7322_IntMask_pb {
  206. pseudo_bit_t RcvAvail0IntMask[1];
  207. pseudo_bit_t RcvAvail1IntMask[1];
  208. pseudo_bit_t RcvAvail2IntMask[1];
  209. pseudo_bit_t RcvAvail3IntMask[1];
  210. pseudo_bit_t RcvAvail4IntMask[1];
  211. pseudo_bit_t RcvAvail5IntMask[1];
  212. pseudo_bit_t RcvAvail6IntMask[1];
  213. pseudo_bit_t RcvAvail7IntMask[1];
  214. pseudo_bit_t RcvAvail8IntMask[1];
  215. pseudo_bit_t RcvAvail9IntMask[1];
  216. pseudo_bit_t RcvAvail10IntMask[1];
  217. pseudo_bit_t RcvAvail11IntMask[1];
  218. pseudo_bit_t RcvAvail12IntMask[1];
  219. pseudo_bit_t RcvAvail13IntMask[1];
  220. pseudo_bit_t RcvAvail14IntMask[1];
  221. pseudo_bit_t RcvAvail15IntMask[1];
  222. pseudo_bit_t RcvAvail16IntMask[1];
  223. pseudo_bit_t RcvAvail17IntMask[1];
  224. pseudo_bit_t _unused_0[5];
  225. pseudo_bit_t SendBufAvailIntMask[1];
  226. pseudo_bit_t SendDoneIntMask_0[1];
  227. pseudo_bit_t SendDoneIntMask_1[1];
  228. pseudo_bit_t _unused_1[2];
  229. pseudo_bit_t AssertGPIOIntMask[1];
  230. pseudo_bit_t ErrIntMask[1];
  231. pseudo_bit_t ErrIntMask_0[1];
  232. pseudo_bit_t ErrIntMask_1[1];
  233. pseudo_bit_t RcvUrg0IntMask[1];
  234. pseudo_bit_t RcvUrg1IntMask[1];
  235. pseudo_bit_t RcvUrg2IntMask[1];
  236. pseudo_bit_t RcvUrg3IntMask[1];
  237. pseudo_bit_t RcvUrg4IntMask[1];
  238. pseudo_bit_t RcvUrg5IntMask[1];
  239. pseudo_bit_t RcvUrg6IntMask[1];
  240. pseudo_bit_t RcvUrg7IntMask[1];
  241. pseudo_bit_t RcvUrg8IntMask[1];
  242. pseudo_bit_t RcvUrg9IntMask[1];
  243. pseudo_bit_t RcvUrg10IntMask[1];
  244. pseudo_bit_t RcvUrg11IntMask[1];
  245. pseudo_bit_t RcvUrg12IntMask[1];
  246. pseudo_bit_t RcvUrg13IntMask[1];
  247. pseudo_bit_t RcvUrg14IntMask[1];
  248. pseudo_bit_t RcvUrg15IntMask[1];
  249. pseudo_bit_t RcvUrg16IntMask[1];
  250. pseudo_bit_t RcvUrg17IntMask[1];
  251. pseudo_bit_t _unused_2[6];
  252. pseudo_bit_t SDmaCleanupDoneMask_0[1];
  253. pseudo_bit_t SDmaCleanupDoneMask_1[1];
  254. pseudo_bit_t SDmaIdleIntMask_0[1];
  255. pseudo_bit_t SDmaIdleIntMask_1[1];
  256. pseudo_bit_t SDmaProgressIntMask_0[1];
  257. pseudo_bit_t SDmaProgressIntMask_1[1];
  258. pseudo_bit_t SDmaIntMask_0[1];
  259. pseudo_bit_t SDmaIntMask_1[1];
  260. };
  261. struct QIB_7322_IntMask {
  262. PSEUDO_BIT_STRUCT ( struct QIB_7322_IntMask_pb );
  263. };
  264. /* Default value: 0x0000000000000000 */
  265. #define QIB_7322_IntStatus_offset 0x00000070UL
  266. struct QIB_7322_IntStatus_pb {
  267. pseudo_bit_t RcvAvail0[1];
  268. pseudo_bit_t RcvAvail1[1];
  269. pseudo_bit_t RcvAvail2[1];
  270. pseudo_bit_t RcvAvail3[1];
  271. pseudo_bit_t RcvAvail4[1];
  272. pseudo_bit_t RcvAvail5[1];
  273. pseudo_bit_t RcvAvail6[1];
  274. pseudo_bit_t RcvAvail7[1];
  275. pseudo_bit_t RcvAvail8[1];
  276. pseudo_bit_t RcvAvail9[1];
  277. pseudo_bit_t RcvAvail10[1];
  278. pseudo_bit_t RcvAvail11[1];
  279. pseudo_bit_t RcvAvail12[1];
  280. pseudo_bit_t RcvAvail13[1];
  281. pseudo_bit_t RcvAvail14[1];
  282. pseudo_bit_t RcvAvail15[1];
  283. pseudo_bit_t RcvAvail16[1];
  284. pseudo_bit_t RcvAvail17[1];
  285. pseudo_bit_t _unused_0[5];
  286. pseudo_bit_t SendBufAvail[1];
  287. pseudo_bit_t SendDone_0[1];
  288. pseudo_bit_t SendDone_1[1];
  289. pseudo_bit_t _unused_1[2];
  290. pseudo_bit_t AssertGPIO[1];
  291. pseudo_bit_t Err[1];
  292. pseudo_bit_t Err_0[1];
  293. pseudo_bit_t Err_1[1];
  294. pseudo_bit_t RcvUrg0[1];
  295. pseudo_bit_t RcvUrg1[1];
  296. pseudo_bit_t RcvUrg2[1];
  297. pseudo_bit_t RcvUrg3[1];
  298. pseudo_bit_t RcvUrg4[1];
  299. pseudo_bit_t RcvUrg5[1];
  300. pseudo_bit_t RcvUrg6[1];
  301. pseudo_bit_t RcvUrg7[1];
  302. pseudo_bit_t RcvUrg8[1];
  303. pseudo_bit_t RcvUrg9[1];
  304. pseudo_bit_t RcvUrg10[1];
  305. pseudo_bit_t RcvUrg11[1];
  306. pseudo_bit_t RcvUrg12[1];
  307. pseudo_bit_t RcvUrg13[1];
  308. pseudo_bit_t RcvUrg14[1];
  309. pseudo_bit_t RcvUrg15[1];
  310. pseudo_bit_t RcvUrg16[1];
  311. pseudo_bit_t RcvUrg17[1];
  312. pseudo_bit_t _unused_2[6];
  313. pseudo_bit_t SDmaCleanupDone_0[1];
  314. pseudo_bit_t SDmaCleanupDone_1[1];
  315. pseudo_bit_t SDmaIdleInt_0[1];
  316. pseudo_bit_t SDmaIdleInt_1[1];
  317. pseudo_bit_t SDmaProgressInt_0[1];
  318. pseudo_bit_t SDmaProgressInt_1[1];
  319. pseudo_bit_t SDmaInt_0[1];
  320. pseudo_bit_t SDmaInt_1[1];
  321. };
  322. struct QIB_7322_IntStatus {
  323. PSEUDO_BIT_STRUCT ( struct QIB_7322_IntStatus_pb );
  324. };
  325. /* Default value: 0x0000000000000000 */
  326. #define QIB_7322_IntClear_offset 0x00000078UL
  327. struct QIB_7322_IntClear_pb {
  328. pseudo_bit_t RcvAvail0IntClear[1];
  329. pseudo_bit_t RcvAvail1IntClear[1];
  330. pseudo_bit_t RcvAvail2IntClear[1];
  331. pseudo_bit_t RcvAvail3IntClear[1];
  332. pseudo_bit_t RcvAvail4IntClear[1];
  333. pseudo_bit_t RcvAvail5IntClear[1];
  334. pseudo_bit_t RcvAvail6IntClear[1];
  335. pseudo_bit_t RcvAvail7IntClear[1];
  336. pseudo_bit_t RcvAvail8IntClear[1];
  337. pseudo_bit_t RcvAvail9IntClear[1];
  338. pseudo_bit_t RcvAvail10IntClear[1];
  339. pseudo_bit_t RcvAvail11IntClear[1];
  340. pseudo_bit_t RcvAvail12IntClear[1];
  341. pseudo_bit_t RcvAvail13IntClear[1];
  342. pseudo_bit_t RcvAvail14IntClear[1];
  343. pseudo_bit_t RcvAvail15IntClear[1];
  344. pseudo_bit_t RcvAvail16IntClear[1];
  345. pseudo_bit_t RcvAvail17IntClear[1];
  346. pseudo_bit_t _unused_0[5];
  347. pseudo_bit_t SendBufAvailIntClear[1];
  348. pseudo_bit_t SendDoneIntClear_0[1];
  349. pseudo_bit_t SendDoneIntClear_1[1];
  350. pseudo_bit_t _unused_1[2];
  351. pseudo_bit_t AssertGPIOIntClear[1];
  352. pseudo_bit_t ErrIntClear[1];
  353. pseudo_bit_t ErrIntClear_0[1];
  354. pseudo_bit_t ErrIntClear_1[1];
  355. pseudo_bit_t RcvUrg0IntClear[1];
  356. pseudo_bit_t RcvUrg1IntClear[1];
  357. pseudo_bit_t RcvUrg2IntClear[1];
  358. pseudo_bit_t RcvUrg3IntClear[1];
  359. pseudo_bit_t RcvUrg4IntClear[1];
  360. pseudo_bit_t RcvUrg5IntClear[1];
  361. pseudo_bit_t RcvUrg6IntClear[1];
  362. pseudo_bit_t RcvUrg7IntClear[1];
  363. pseudo_bit_t RcvUrg8IntClear[1];
  364. pseudo_bit_t RcvUrg9IntClear[1];
  365. pseudo_bit_t RcvUrg10IntClear[1];
  366. pseudo_bit_t RcvUrg11IntClear[1];
  367. pseudo_bit_t RcvUrg12IntClear[1];
  368. pseudo_bit_t RcvUrg13IntClear[1];
  369. pseudo_bit_t RcvUrg14IntClear[1];
  370. pseudo_bit_t RcvUrg15IntClear[1];
  371. pseudo_bit_t RcvUrg16IntClear[1];
  372. pseudo_bit_t RcvUrg17IntClear[1];
  373. pseudo_bit_t _unused_2[6];
  374. pseudo_bit_t SDmaCleanupDoneClear_0[1];
  375. pseudo_bit_t SDmaCleanupDoneClear_1[1];
  376. pseudo_bit_t SDmaIdleIntClear_0[1];
  377. pseudo_bit_t SDmaIdleIntClear_1[1];
  378. pseudo_bit_t SDmaProgressIntClear_0[1];
  379. pseudo_bit_t SDmaProgressIntClear_1[1];
  380. pseudo_bit_t SDmaIntClear_0[1];
  381. pseudo_bit_t SDmaIntClear_1[1];
  382. };
  383. struct QIB_7322_IntClear {
  384. PSEUDO_BIT_STRUCT ( struct QIB_7322_IntClear_pb );
  385. };
  386. /* Default value: 0x0000000000000000 */
  387. #define QIB_7322_ErrMask_offset 0x00000080UL
  388. struct QIB_7322_ErrMask_pb {
  389. pseudo_bit_t _unused_0[12];
  390. pseudo_bit_t RcvEgrFullErrMask[1];
  391. pseudo_bit_t RcvHdrFullErrMask[1];
  392. pseudo_bit_t _unused_1[11];
  393. pseudo_bit_t SDmaBufMaskDuplicateErrMask[1];
  394. pseudo_bit_t SDmaWrongPortErrMask[1];
  395. pseudo_bit_t SendSpecialTriggerErrMask[1];
  396. pseudo_bit_t _unused_2[7];
  397. pseudo_bit_t SendArmLaunchErrMask[1];
  398. pseudo_bit_t SendVLMismatchErrMask[1];
  399. pseudo_bit_t _unused_3[15];
  400. pseudo_bit_t RcvContextShareErrMask[1];
  401. pseudo_bit_t InvalidEEPCmdMask[1];
  402. pseudo_bit_t _unused_4[1];
  403. pseudo_bit_t SBufVL15MisUseErrMask[1];
  404. pseudo_bit_t SDmaVL15ErrMask[1];
  405. pseudo_bit_t _unused_5[4];
  406. pseudo_bit_t InvalidAddrErrMask[1];
  407. pseudo_bit_t HardwareErrMask[1];
  408. pseudo_bit_t ResetNegatedMask[1];
  409. };
  410. struct QIB_7322_ErrMask {
  411. PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrMask_pb );
  412. };
  413. /* Default value: 0x0000000000000000 */
  414. #define QIB_7322_ErrStatus_offset 0x00000088UL
  415. struct QIB_7322_ErrStatus_pb {
  416. pseudo_bit_t _unused_0[12];
  417. pseudo_bit_t RcvEgrFullErr[1];
  418. pseudo_bit_t RcvHdrFullErr[1];
  419. pseudo_bit_t _unused_1[11];
  420. pseudo_bit_t SDmaBufMaskDuplicateErr[1];
  421. pseudo_bit_t SDmaWrongPortErr[1];
  422. pseudo_bit_t SendSpecialTriggerErr[1];
  423. pseudo_bit_t _unused_2[7];
  424. pseudo_bit_t SendArmLaunchErr[1];
  425. pseudo_bit_t SendVLMismatchErr[1];
  426. pseudo_bit_t _unused_3[15];
  427. pseudo_bit_t RcvContextShareErr[1];
  428. pseudo_bit_t InvalidEEPCmdErr[1];
  429. pseudo_bit_t _unused_4[1];
  430. pseudo_bit_t SBufVL15MisUseErr[1];
  431. pseudo_bit_t SDmaVL15Err[1];
  432. pseudo_bit_t _unused_5[4];
  433. pseudo_bit_t InvalidAddrErr[1];
  434. pseudo_bit_t HardwareErr[1];
  435. pseudo_bit_t ResetNegated[1];
  436. };
  437. struct QIB_7322_ErrStatus {
  438. PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrStatus_pb );
  439. };
  440. /* Default value: 0x0000000000000000 */
  441. #define QIB_7322_ErrClear_offset 0x00000090UL
  442. struct QIB_7322_ErrClear_pb {
  443. pseudo_bit_t _unused_0[12];
  444. pseudo_bit_t RcvEgrFullErrClear[1];
  445. pseudo_bit_t RcvHdrFullErrClear[1];
  446. pseudo_bit_t _unused_1[11];
  447. pseudo_bit_t SDmaBufMaskDuplicateErrClear[1];
  448. pseudo_bit_t SDmaWrongPortErrClear[1];
  449. pseudo_bit_t SendSpecialTriggerErrClear[1];
  450. pseudo_bit_t _unused_2[7];
  451. pseudo_bit_t SendArmLaunchErrClear[1];
  452. pseudo_bit_t SendVLMismatchErrMask[1];
  453. pseudo_bit_t _unused_3[15];
  454. pseudo_bit_t RcvContextShareErrClear[1];
  455. pseudo_bit_t InvalidEEPCmdErrClear[1];
  456. pseudo_bit_t _unused_4[1];
  457. pseudo_bit_t SBufVL15MisUseErrClear[1];
  458. pseudo_bit_t SDmaVL15ErrClear[1];
  459. pseudo_bit_t _unused_5[4];
  460. pseudo_bit_t InvalidAddrErrClear[1];
  461. pseudo_bit_t HardwareErrClear[1];
  462. pseudo_bit_t ResetNegatedClear[1];
  463. };
  464. struct QIB_7322_ErrClear {
  465. PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrClear_pb );
  466. };
  467. /* Default value: 0x0000000000000000 */
  468. #define QIB_7322_HwErrMask_offset 0x00000098UL
  469. struct QIB_7322_HwErrMask_pb {
  470. pseudo_bit_t _unused_0[11];
  471. pseudo_bit_t LATriggeredMask[1];
  472. pseudo_bit_t statusValidNoEopMask_0[1];
  473. pseudo_bit_t IBCBusFromSPCParityErrMask_0[1];
  474. pseudo_bit_t statusValidNoEopMask_1[1];
  475. pseudo_bit_t IBCBusFromSPCParityErrMask_1[1];
  476. pseudo_bit_t _unused_1[11];
  477. pseudo_bit_t SDmaMemReadErrMask_0[1];
  478. pseudo_bit_t SDmaMemReadErrMask_1[1];
  479. pseudo_bit_t PciePoisonedTLPMask[1];
  480. pseudo_bit_t PcieCplTimeoutMask[1];
  481. pseudo_bit_t PCIeBusParityErrMask[3];
  482. pseudo_bit_t pcie_phy_txParityErr[1];
  483. pseudo_bit_t _unused_2[13];
  484. pseudo_bit_t MemoryErrMask[1];
  485. pseudo_bit_t _unused_3[4];
  486. pseudo_bit_t TempsenseTholdReachedMask[1];
  487. pseudo_bit_t PowerOnBISTFailedMask[1];
  488. pseudo_bit_t PCIESerdesPClkNotDetectMask[1];
  489. pseudo_bit_t _unused_4[6];
  490. pseudo_bit_t IBSerdesPClkNotDetectMask_0[1];
  491. pseudo_bit_t IBSerdesPClkNotDetectMask_1[1];
  492. };
  493. struct QIB_7322_HwErrMask {
  494. PSEUDO_BIT_STRUCT ( struct QIB_7322_HwErrMask_pb );
  495. };
  496. /* Default value: 0x0000000000000000 */
  497. #define QIB_7322_HwErrStatus_offset 0x000000a0UL
  498. struct QIB_7322_HwErrStatus_pb {
  499. pseudo_bit_t _unused_0[11];
  500. pseudo_bit_t LATriggered[1];
  501. pseudo_bit_t statusValidNoEop_0[1];
  502. pseudo_bit_t IBCBusFromSPCParityErr_0[1];
  503. pseudo_bit_t statusValidNoEop_1[1];
  504. pseudo_bit_t IBCBusFromSPCParityErr_1[1];
  505. pseudo_bit_t _unused_1[11];
  506. pseudo_bit_t SDmaMemReadErr_0[1];
  507. pseudo_bit_t SDmaMemReadErr_1[1];
  508. pseudo_bit_t PciePoisonedTLP[1];
  509. pseudo_bit_t PcieCplTimeout[1];
  510. pseudo_bit_t PCIeBusParity[3];
  511. pseudo_bit_t pcie_phy_txParityErr[1];
  512. pseudo_bit_t _unused_2[13];
  513. pseudo_bit_t MemoryErr[1];
  514. pseudo_bit_t _unused_3[4];
  515. pseudo_bit_t TempsenseTholdReached[1];
  516. pseudo_bit_t PowerOnBISTFailed[1];
  517. pseudo_bit_t PCIESerdesPClkNotDetect[1];
  518. pseudo_bit_t _unused_4[6];
  519. pseudo_bit_t IBSerdesPClkNotDetect_0[1];
  520. pseudo_bit_t IBSerdesPClkNotDetect_1[1];
  521. };
  522. struct QIB_7322_HwErrStatus {
  523. PSEUDO_BIT_STRUCT ( struct QIB_7322_HwErrStatus_pb );
  524. };
  525. /* Default value: 0x0000000000000000 */
  526. #define QIB_7322_HwErrClear_offset 0x000000a8UL
  527. struct QIB_7322_HwErrClear_pb {
  528. pseudo_bit_t _unused_0[11];
  529. pseudo_bit_t LATriggeredClear[1];
  530. pseudo_bit_t IBCBusToSPCparityErrClear_0[1];
  531. pseudo_bit_t IBCBusFromSPCParityErrClear_0[1];
  532. pseudo_bit_t IBCBusToSPCparityErrClear_1[1];
  533. pseudo_bit_t IBCBusFromSPCParityErrClear_1[1];
  534. pseudo_bit_t _unused_1[11];
  535. pseudo_bit_t SDmaMemReadErrClear_0[1];
  536. pseudo_bit_t SDmaMemReadErrClear_1[1];
  537. pseudo_bit_t PciePoisonedTLPClear[1];
  538. pseudo_bit_t PcieCplTimeoutClear[1];
  539. pseudo_bit_t PCIeBusParityClear[3];
  540. pseudo_bit_t pcie_phy_txParityErr[1];
  541. pseudo_bit_t _unused_2[13];
  542. pseudo_bit_t MemoryErrClear[1];
  543. pseudo_bit_t _unused_3[4];
  544. pseudo_bit_t TempsenseTholdReachedClear[1];
  545. pseudo_bit_t PowerOnBISTFailedClear[1];
  546. pseudo_bit_t PCIESerdesPClkNotDetectClear[1];
  547. pseudo_bit_t _unused_4[6];
  548. pseudo_bit_t IBSerdesPClkNotDetectClear_0[1];
  549. pseudo_bit_t IBSerdesPClkNotDetectClear_1[1];
  550. };
  551. struct QIB_7322_HwErrClear {
  552. PSEUDO_BIT_STRUCT ( struct QIB_7322_HwErrClear_pb );
  553. };
  554. /* Default value: 0x0000000000000000 */
  555. #define QIB_7322_HwDiagCtrl_offset 0x000000b0UL
  556. struct QIB_7322_HwDiagCtrl_pb {
  557. pseudo_bit_t _unused_0[12];
  558. pseudo_bit_t ForcestatusValidNoEop_0[1];
  559. pseudo_bit_t ForceIBCBusFromSPCParityErr_0[1];
  560. pseudo_bit_t ForcestatusValidNoEop_1[1];
  561. pseudo_bit_t ForceIBCBusFromSPCParityErr_1[1];
  562. pseudo_bit_t _unused_1[15];
  563. pseudo_bit_t forcePCIeBusParity[4];
  564. pseudo_bit_t _unused_2[25];
  565. pseudo_bit_t CounterDisable[1];
  566. pseudo_bit_t CounterWrEnable[1];
  567. pseudo_bit_t _unused_3[1];
  568. pseudo_bit_t Diagnostic[1];
  569. };
  570. struct QIB_7322_HwDiagCtrl {
  571. PSEUDO_BIT_STRUCT ( struct QIB_7322_HwDiagCtrl_pb );
  572. };
  573. /* Default value: 0x0000000000000000 */
  574. #define QIB_7322_EXTStatus_offset 0x000000c0UL
  575. struct QIB_7322_EXTStatus_pb {
  576. pseudo_bit_t _unused_0[14];
  577. pseudo_bit_t MemBISTEndTest[1];
  578. pseudo_bit_t MemBISTDisabled[1];
  579. pseudo_bit_t _unused_1[32];
  580. pseudo_bit_t GPIOIn[16];
  581. };
  582. struct QIB_7322_EXTStatus {
  583. PSEUDO_BIT_STRUCT ( struct QIB_7322_EXTStatus_pb );
  584. };
  585. /* Default value: 0x000000000000X000 */
  586. #define QIB_7322_EXTCtrl_offset 0x000000c8UL
  587. struct QIB_7322_EXTCtrl_pb {
  588. pseudo_bit_t LEDPort0YellowOn[1];
  589. pseudo_bit_t LEDPort0GreenOn[1];
  590. pseudo_bit_t LEDPort1YellowOn[1];
  591. pseudo_bit_t LEDPort1GreenOn[1];
  592. pseudo_bit_t _unused_0[28];
  593. pseudo_bit_t GPIOInvert[16];
  594. pseudo_bit_t GPIOOe[16];
  595. };
  596. struct QIB_7322_EXTCtrl {
  597. PSEUDO_BIT_STRUCT ( struct QIB_7322_EXTCtrl_pb );
  598. };
  599. /* Default value: 0x0000000000000000 */
  600. #define QIB_7322_GPIODebugSelReg_offset 0x000000d8UL
  601. struct QIB_7322_GPIODebugSelReg_pb {
  602. pseudo_bit_t GPIOSourceSelDebug[16];
  603. pseudo_bit_t SelPulse[16];
  604. pseudo_bit_t _unused_0[32];
  605. };
  606. struct QIB_7322_GPIODebugSelReg {
  607. PSEUDO_BIT_STRUCT ( struct QIB_7322_GPIODebugSelReg_pb );
  608. };
  609. /* Default value: 0x0000000000000000 */
  610. #define QIB_7322_GPIOOut_offset 0x000000e0UL
  611. /* Default value: 0x0000000000000000 */
  612. #define QIB_7322_GPIOMask_offset 0x000000e8UL
  613. /* Default value: 0x0000000000000000 */
  614. #define QIB_7322_GPIOStatus_offset 0x000000f0UL
  615. /* Default value: 0x0000000000000000 */
  616. #define QIB_7322_GPIOClear_offset 0x000000f8UL
  617. /* Default value: 0x0000000000000000 */
  618. #define QIB_7322_RcvCtrl_offset 0x00000100UL
  619. struct QIB_7322_RcvCtrl_pb {
  620. pseudo_bit_t dontDropRHQFull[18];
  621. pseudo_bit_t _unused_0[2];
  622. pseudo_bit_t IntrAvail[18];
  623. pseudo_bit_t _unused_1[3];
  624. pseudo_bit_t ContextCfg[2];
  625. pseudo_bit_t TidFlowEnable[1];
  626. pseudo_bit_t XrcTypeCode[3];
  627. pseudo_bit_t TailUpd[1];
  628. pseudo_bit_t TidReDirect[16];
  629. };
  630. struct QIB_7322_RcvCtrl {
  631. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvCtrl_pb );
  632. };
  633. /* Default value: 0x0000000000000000 */
  634. #define QIB_7322_RcvHdrSize_offset 0x00000110UL
  635. /* Default value: 0x0000000000000000 */
  636. #define QIB_7322_RcvHdrCnt_offset 0x00000118UL
  637. /* Default value: 0x0000000000000000 */
  638. #define QIB_7322_RcvHdrEntSize_offset 0x00000120UL
  639. /* Default value: 0x0000000000000000 */
  640. #define QIB_7322_RcvTIDBase_offset 0x00000128UL
  641. /* Default value: 0x0000000000050000 */
  642. #define QIB_7322_RcvTIDCnt_offset 0x00000130UL
  643. /* Default value: 0x0000000000000200 */
  644. #define QIB_7322_RcvEgrBase_offset 0x00000138UL
  645. /* Default value: 0x0000000000014000 */
  646. #define QIB_7322_RcvEgrCnt_offset 0x00000140UL
  647. /* Default value: 0x0000000000001000 */
  648. #define QIB_7322_RcvBufBase_offset 0x00000148UL
  649. /* Default value: 0x0000000000080000 */
  650. #define QIB_7322_RcvBufSize_offset 0x00000150UL
  651. /* Default value: 0x0000000000005000 */
  652. #define QIB_7322_RxIntMemBase_offset 0x00000158UL
  653. /* Default value: 0x0000000000077000 */
  654. #define QIB_7322_RxIntMemSize_offset 0x00000160UL
  655. /* Default value: 0x0000000000007000 */
  656. #define QIB_7322_encryption_key_low_offset 0x00000180UL
  657. /* Default value: 0x0000000000000000 */
  658. #define QIB_7322_encryption_key_high_offset 0x00000188UL
  659. /* Default value: 0x0000000000000000 */
  660. #define QIB_7322_feature_mask_offset 0x00000190UL
  661. /* Default value: 0x00000000000000XX */
  662. #define QIB_7322_active_feature_mask_offset 0x00000198UL
  663. struct QIB_7322_active_feature_mask_pb {
  664. pseudo_bit_t Port0_SDR_Enabled[1];
  665. pseudo_bit_t Port0_DDR_Enabled[1];
  666. pseudo_bit_t Port0_QDR_Enabled[1];
  667. pseudo_bit_t Port1_SDR_Enabled[1];
  668. pseudo_bit_t Port1_DDR_Enabled[1];
  669. pseudo_bit_t Port1_QDR_Enabled[1];
  670. pseudo_bit_t _unused_0[58];
  671. };
  672. struct QIB_7322_active_feature_mask {
  673. PSEUDO_BIT_STRUCT ( struct QIB_7322_active_feature_mask_pb );
  674. };
  675. /* Default value: 0x00000000000000XX */
  676. #define QIB_7322_SendCtrl_offset 0x000001c0UL
  677. struct QIB_7322_SendCtrl_pb {
  678. pseudo_bit_t _unused_0[1];
  679. pseudo_bit_t SendIntBufAvail[1];
  680. pseudo_bit_t SendBufAvailUpd[1];
  681. pseudo_bit_t _unused_1[1];
  682. pseudo_bit_t SpecialTriggerEn[1];
  683. pseudo_bit_t _unused_2[11];
  684. pseudo_bit_t DisarmSendBuf[8];
  685. pseudo_bit_t AvailUpdThld[5];
  686. pseudo_bit_t SendBufAvailPad64Byte[1];
  687. pseudo_bit_t _unused_3[1];
  688. pseudo_bit_t Disarm[1];
  689. pseudo_bit_t _unused_4[32];
  690. };
  691. struct QIB_7322_SendCtrl {
  692. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendCtrl_pb );
  693. };
  694. /* Default value: 0x0000000000000000 */
  695. #define QIB_7322_SendBufBase_offset 0x000001c8UL
  696. struct QIB_7322_SendBufBase_pb {
  697. pseudo_bit_t BaseAddr_SmallPIO[21];
  698. pseudo_bit_t _unused_0[11];
  699. pseudo_bit_t BaseAddr_LargePIO[21];
  700. pseudo_bit_t _unused_1[11];
  701. };
  702. struct QIB_7322_SendBufBase {
  703. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufBase_pb );
  704. };
  705. /* Default value: 0x0018000000100000 */
  706. #define QIB_7322_SendBufSize_offset 0x000001d0UL
  707. struct QIB_7322_SendBufSize_pb {
  708. pseudo_bit_t Size_SmallPIO[12];
  709. pseudo_bit_t _unused_0[20];
  710. pseudo_bit_t Size_LargePIO[13];
  711. pseudo_bit_t _unused_1[19];
  712. };
  713. struct QIB_7322_SendBufSize {
  714. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufSize_pb );
  715. };
  716. /* Default value: 0x0000108000000880 */
  717. #define QIB_7322_SendBufCnt_offset 0x000001d8UL
  718. struct QIB_7322_SendBufCnt_pb {
  719. pseudo_bit_t Num_SmallBuffers[9];
  720. pseudo_bit_t _unused_0[23];
  721. pseudo_bit_t Num_LargeBuffers[6];
  722. pseudo_bit_t _unused_1[26];
  723. };
  724. struct QIB_7322_SendBufCnt {
  725. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufCnt_pb );
  726. };
  727. /* Default value: 0x0000002000000080 */
  728. #define QIB_7322_SendBufAvailAddr_offset 0x000001e0UL
  729. struct QIB_7322_SendBufAvailAddr_pb {
  730. pseudo_bit_t _unused_0[6];
  731. pseudo_bit_t SendBufAvailAddr[34];
  732. pseudo_bit_t _unused_1[24];
  733. };
  734. struct QIB_7322_SendBufAvailAddr {
  735. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufAvailAddr_pb );
  736. };
  737. /* Default value: 0x0000000000000000 */
  738. #define QIB_7322_TxIntMemBase_offset 0x000001e8UL
  739. /* Default value: 0x0000000000064000 */
  740. #define QIB_7322_TxIntMemSize_offset 0x000001f0UL
  741. /* Default value: 0x000000000000C000 */
  742. #define QIB_7322_SendBufErr0_offset 0x00000240UL
  743. struct QIB_7322_SendBufErr0_pb {
  744. pseudo_bit_t SendBufErr_63_0[64];
  745. };
  746. struct QIB_7322_SendBufErr0 {
  747. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufErr0_pb );
  748. };
  749. /* Default value: 0x0000000000000000 */
  750. #define QIB_7322_AvailUpdCount_offset 0x00000268UL
  751. struct QIB_7322_AvailUpdCount_pb {
  752. pseudo_bit_t AvailUpdCount[5];
  753. pseudo_bit_t _unused_0[59];
  754. };
  755. struct QIB_7322_AvailUpdCount {
  756. PSEUDO_BIT_STRUCT ( struct QIB_7322_AvailUpdCount_pb );
  757. };
  758. /* Default value: 0x0000000000000000 */
  759. #define QIB_7322_RcvHdrAddr0_offset 0x00000280UL
  760. struct QIB_7322_RcvHdrAddr0_pb {
  761. pseudo_bit_t _unused_0[2];
  762. pseudo_bit_t RcvHdrAddr[38];
  763. pseudo_bit_t _unused_1[24];
  764. };
  765. struct QIB_7322_RcvHdrAddr0 {
  766. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrAddr0_pb );
  767. };
  768. /* Default value: 0x0000000000000000 */
  769. #define QIB_7322_RcvHdrTailAddr0_offset 0x00000340UL
  770. struct QIB_7322_RcvHdrTailAddr0_pb {
  771. pseudo_bit_t _unused_0[2];
  772. pseudo_bit_t RcvHdrTailAddr[38];
  773. pseudo_bit_t _unused_1[24];
  774. };
  775. struct QIB_7322_RcvHdrTailAddr0 {
  776. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrTailAddr0_pb );
  777. };
  778. /* Default value: 0x0000000000000000 */
  779. #define QIB_7322_EEPCtlStat_offset 0x000003e8UL
  780. struct QIB_7322_EEPCtlStat_pb {
  781. pseudo_bit_t EPAccEn[2];
  782. pseudo_bit_t EPReset[1];
  783. pseudo_bit_t ByteProg[1];
  784. pseudo_bit_t PageMode[1];
  785. pseudo_bit_t LstDatWr[1];
  786. pseudo_bit_t CmdWrErr[1];
  787. pseudo_bit_t _unused_0[24];
  788. pseudo_bit_t CtlrStat[1];
  789. pseudo_bit_t _unused_1[32];
  790. };
  791. struct QIB_7322_EEPCtlStat {
  792. PSEUDO_BIT_STRUCT ( struct QIB_7322_EEPCtlStat_pb );
  793. };
  794. /* Default value: 0x0000000000000002 */
  795. #define QIB_7322_EEPAddrCmd_offset 0x000003f0UL
  796. struct QIB_7322_EEPAddrCmd_pb {
  797. pseudo_bit_t EPAddr[24];
  798. pseudo_bit_t EPCmd[8];
  799. pseudo_bit_t _unused_0[32];
  800. };
  801. struct QIB_7322_EEPAddrCmd {
  802. PSEUDO_BIT_STRUCT ( struct QIB_7322_EEPAddrCmd_pb );
  803. };
  804. /* Default value: 0x0000000000000000 */
  805. #define QIB_7322_EEPData_offset 0x000003f8UL
  806. /* Default value: 0x0000000000000000 */
  807. #define QIB_7322_efuse_control_reg_offset 0x00000410UL
  808. struct QIB_7322_efuse_control_reg_pb {
  809. pseudo_bit_t address[11];
  810. pseudo_bit_t last_program_address[11];
  811. pseudo_bit_t operation[2];
  812. pseudo_bit_t start_operation[1];
  813. pseudo_bit_t _unused_0[4];
  814. pseudo_bit_t req_err[1];
  815. pseudo_bit_t read_data_valid[1];
  816. pseudo_bit_t rdy[1];
  817. pseudo_bit_t _unused_1[32];
  818. };
  819. struct QIB_7322_efuse_control_reg {
  820. PSEUDO_BIT_STRUCT ( struct QIB_7322_efuse_control_reg_pb );
  821. };
  822. /* Default value: 0x0000000080000000 */
  823. #define QIB_7322_efuse_data_reg_offset 0x00000418UL
  824. /* Default value: 0x0000000000000000 */
  825. #define QIB_7322_voltage_margin_reg_offset 0x00000428UL
  826. struct QIB_7322_voltage_margin_reg_pb {
  827. pseudo_bit_t voltage_margin_settings_enable[1];
  828. pseudo_bit_t voltage_margin_settings[2];
  829. pseudo_bit_t _unused_0[61];
  830. };
  831. struct QIB_7322_voltage_margin_reg {
  832. PSEUDO_BIT_STRUCT ( struct QIB_7322_voltage_margin_reg_pb );
  833. };
  834. /* Default value: 0x0000000000000000 */
  835. #define QIB_7322_VTSense_reg_offset 0x00000430UL
  836. struct QIB_7322_VTSense_reg_pb {
  837. pseudo_bit_t temp_sense_select[3];
  838. pseudo_bit_t adc_mode[1];
  839. pseudo_bit_t start_busy[1];
  840. pseudo_bit_t power_down[1];
  841. pseudo_bit_t threshold[10];
  842. pseudo_bit_t sensor_output_data[10];
  843. pseudo_bit_t _unused_0[1];
  844. pseudo_bit_t threshold_limbit[1];
  845. pseudo_bit_t _unused_1[3];
  846. pseudo_bit_t output_valid[1];
  847. pseudo_bit_t _unused_2[32];
  848. };
  849. struct QIB_7322_VTSense_reg {
  850. PSEUDO_BIT_STRUCT ( struct QIB_7322_VTSense_reg_pb );
  851. };
  852. /* Default value: 0x0000000000000020 */
  853. #define QIB_7322_procmon_reg_offset 0x00000438UL
  854. struct QIB_7322_procmon_reg_pb {
  855. pseudo_bit_t ring_osc_select[3];
  856. pseudo_bit_t _unused_0[12];
  857. pseudo_bit_t start_counter[1];
  858. pseudo_bit_t procmon_count[12];
  859. pseudo_bit_t _unused_1[3];
  860. pseudo_bit_t procmon_count_valid[1];
  861. pseudo_bit_t _unused_2[32];
  862. };
  863. struct QIB_7322_procmon_reg {
  864. PSEUDO_BIT_STRUCT ( struct QIB_7322_procmon_reg_pb );
  865. };
  866. /* Default value: 0x0000000000000000 */
  867. #define QIB_7322_PcieRbufTestReg0_offset 0x00000440UL
  868. /* Default value: 0x0000000000000000 */
  869. #define QIB_7322_ahb_access_ctrl_offset 0x00000460UL
  870. struct QIB_7322_ahb_access_ctrl_pb {
  871. pseudo_bit_t sw_ahb_sel[1];
  872. pseudo_bit_t sw_sel_ahb_trgt[2];
  873. pseudo_bit_t _unused_0[61];
  874. };
  875. struct QIB_7322_ahb_access_ctrl {
  876. PSEUDO_BIT_STRUCT ( struct QIB_7322_ahb_access_ctrl_pb );
  877. };
  878. /* Default value: 0x0000000000000000 */
  879. #define QIB_7322_ahb_transaction_reg_offset 0x00000468UL
  880. struct QIB_7322_ahb_transaction_reg_pb {
  881. pseudo_bit_t _unused_0[16];
  882. pseudo_bit_t ahb_address[11];
  883. pseudo_bit_t write_not_read[1];
  884. pseudo_bit_t _unused_1[2];
  885. pseudo_bit_t ahb_req_err[1];
  886. pseudo_bit_t ahb_rdy[1];
  887. pseudo_bit_t ahb_data[32];
  888. };
  889. struct QIB_7322_ahb_transaction_reg {
  890. PSEUDO_BIT_STRUCT ( struct QIB_7322_ahb_transaction_reg_pb );
  891. };
  892. /* Default value: 0x0000000080000000 */
  893. #define QIB_7322_SPC_JTAG_ACCESS_REG_offset 0x00000470UL
  894. struct QIB_7322_SPC_JTAG_ACCESS_REG_pb {
  895. pseudo_bit_t rdy[1];
  896. pseudo_bit_t tdo[1];
  897. pseudo_bit_t tdi[1];
  898. pseudo_bit_t opcode[2];
  899. pseudo_bit_t bist_en[5];
  900. pseudo_bit_t SPC_JTAG_ACCESS_EN[1];
  901. pseudo_bit_t _unused_0[53];
  902. };
  903. struct QIB_7322_SPC_JTAG_ACCESS_REG {
  904. PSEUDO_BIT_STRUCT ( struct QIB_7322_SPC_JTAG_ACCESS_REG_pb );
  905. };
  906. /* Default value: 0x0000000000000001 */
  907. #define QIB_7322_LAControlReg_offset 0x00000478UL
  908. struct QIB_7322_LAControlReg_pb {
  909. pseudo_bit_t Finished[1];
  910. pseudo_bit_t Address[9];
  911. pseudo_bit_t Mode[2];
  912. pseudo_bit_t Delay[20];
  913. pseudo_bit_t Finished_sc[1];
  914. pseudo_bit_t Address_sc[9];
  915. pseudo_bit_t Mode_sc[2];
  916. pseudo_bit_t Delay_sc[20];
  917. };
  918. struct QIB_7322_LAControlReg {
  919. PSEUDO_BIT_STRUCT ( struct QIB_7322_LAControlReg_pb );
  920. };
  921. /* Default value: 0x0000000100000001 */
  922. #define QIB_7322_PcieRhdrTestReg0_offset 0x00000480UL
  923. /* Default value: 0x0000000000000000 */
  924. #define QIB_7322_SendCheckMask0_offset 0x000004c0UL
  925. struct QIB_7322_SendCheckMask0_pb {
  926. pseudo_bit_t SendCheckMask_63_32[64];
  927. };
  928. struct QIB_7322_SendCheckMask0 {
  929. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendCheckMask0_pb );
  930. };
  931. /* Default value: 0x0000000000000000 */
  932. #define QIB_7322_SendGRHCheckMask0_offset 0x000004e0UL
  933. struct QIB_7322_SendGRHCheckMask0_pb {
  934. pseudo_bit_t SendGRHCheckMask_63_32[64];
  935. };
  936. struct QIB_7322_SendGRHCheckMask0 {
  937. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendGRHCheckMask0_pb );
  938. };
  939. /* Default value: 0x0000000000000000 */
  940. #define QIB_7322_SendIBPacketMask0_offset 0x00000500UL
  941. struct QIB_7322_SendIBPacketMask0_pb {
  942. pseudo_bit_t SendIBPacketMask_63_32[64];
  943. };
  944. struct QIB_7322_SendIBPacketMask0 {
  945. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendIBPacketMask0_pb );
  946. };
  947. /* Default value: 0x0000000000000000 */
  948. #define QIB_7322_IntRedirect0_offset 0x00000540UL
  949. struct QIB_7322_IntRedirect0_pb {
  950. pseudo_bit_t vec0[5];
  951. pseudo_bit_t vec1[5];
  952. pseudo_bit_t vec2[5];
  953. pseudo_bit_t vec3[5];
  954. pseudo_bit_t vec4[5];
  955. pseudo_bit_t vec5[5];
  956. pseudo_bit_t vec6[5];
  957. pseudo_bit_t vec7[5];
  958. pseudo_bit_t vec8[5];
  959. pseudo_bit_t vec9[5];
  960. pseudo_bit_t vec10[5];
  961. pseudo_bit_t vec11[5];
  962. pseudo_bit_t _unused_0[4];
  963. };
  964. struct QIB_7322_IntRedirect0 {
  965. PSEUDO_BIT_STRUCT ( struct QIB_7322_IntRedirect0_pb );
  966. };
  967. /* Default value: 0x0000000000000000 */
  968. #define QIB_7322_Int_Granted_offset 0x00000570UL
  969. /* Default value: 0x0000000000000000 */
  970. #define QIB_7322_vec_clr_without_int_offset 0x00000578UL
  971. /* Default value: 0x0000000000000000 */
  972. #define QIB_7322_DCACtrlA_offset 0x00000580UL
  973. struct QIB_7322_DCACtrlA_pb {
  974. pseudo_bit_t RcvHdrqDCAEnable[1];
  975. pseudo_bit_t EagerDCAEnable[1];
  976. pseudo_bit_t RcvTailUpdDCAEnable[1];
  977. pseudo_bit_t SendDMAHead0DCAEnable[1];
  978. pseudo_bit_t SendDMAHead1DCAEnable[1];
  979. pseudo_bit_t _unused_0[59];
  980. };
  981. struct QIB_7322_DCACtrlA {
  982. PSEUDO_BIT_STRUCT ( struct QIB_7322_DCACtrlA_pb );
  983. };
  984. /* Default value: 0x0000000000000000 */
  985. #define QIB_7322_DCACtrlB_offset 0x00000588UL
  986. struct QIB_7322_DCACtrlB_pb {
  987. pseudo_bit_t RcvHdrq0DCAOPH[8];
  988. pseudo_bit_t RcvHdrq0DCAXfrCnt[6];
  989. pseudo_bit_t RcvHdrq1DCAOPH[8];
  990. pseudo_bit_t RcvHdrq1DCAXfrCnt[6];
  991. pseudo_bit_t _unused_0[4];
  992. pseudo_bit_t RcvHdrq2DCAOPH[8];
  993. pseudo_bit_t RcvHdrq2DCAXfrCnt[6];
  994. pseudo_bit_t RcvHdrq3DCAOPH[8];
  995. pseudo_bit_t RcvHdrq3DCAXfrCnt[6];
  996. pseudo_bit_t _unused_1[4];
  997. };
  998. struct QIB_7322_DCACtrlB {
  999. PSEUDO_BIT_STRUCT ( struct QIB_7322_DCACtrlB_pb );
  1000. };
  1001. /* Default value: 0x0000000000000000 */
  1002. #define QIB_7322_DCACtrlC_offset 0x00000590UL
  1003. struct QIB_7322_DCACtrlC_pb {
  1004. pseudo_bit_t RcvHdrq4DCAOPH[8];
  1005. pseudo_bit_t RcvHdrq4DCAXfrCnt[6];
  1006. pseudo_bit_t RcvHdrq5DCAOPH[8];
  1007. pseudo_bit_t RcvHdrq5DCAXfrCnt[6];
  1008. pseudo_bit_t _unused_0[4];
  1009. pseudo_bit_t RcvHdrq6DCAOPH[8];
  1010. pseudo_bit_t RcvHdrq6DCAXfrCnt[6];
  1011. pseudo_bit_t RcvHdrq7DCAOPH[8];
  1012. pseudo_bit_t RcvHdrq7DCAXfrCnt[6];
  1013. pseudo_bit_t _unused_1[4];
  1014. };
  1015. struct QIB_7322_DCACtrlC {
  1016. PSEUDO_BIT_STRUCT ( struct QIB_7322_DCACtrlC_pb );
  1017. };
  1018. /* Default value: 0x0000000000000000 */
  1019. #define QIB_7322_DCACtrlD_offset 0x00000598UL
  1020. struct QIB_7322_DCACtrlD_pb {
  1021. pseudo_bit_t RcvHdrq8DCAOPH[8];
  1022. pseudo_bit_t RcvHdrq8DCAXfrCnt[6];
  1023. pseudo_bit_t RcvHdrq9DCAOPH[8];
  1024. pseudo_bit_t RcvHdrq9DCAXfrCnt[6];
  1025. pseudo_bit_t _unused_0[4];
  1026. pseudo_bit_t RcvHdrq10DCAOPH[8];
  1027. pseudo_bit_t RcvHdrq10DCAXfrCnt[6];
  1028. pseudo_bit_t RcvHdrq11DCAOPH[8];
  1029. pseudo_bit_t RcvHdrq11DCAXfrCnt[6];
  1030. pseudo_bit_t _unused_1[4];
  1031. };
  1032. struct QIB_7322_DCACtrlD {
  1033. PSEUDO_BIT_STRUCT ( struct QIB_7322_DCACtrlD_pb );
  1034. };
  1035. /* Default value: 0x0000000000000000 */
  1036. #define QIB_7322_DCACtrlE_offset 0x000005a0UL
  1037. struct QIB_7322_DCACtrlE_pb {
  1038. pseudo_bit_t RcvHdrq12DCAOPH[8];
  1039. pseudo_bit_t RcvHdrq12DCAXfrCnt[6];
  1040. pseudo_bit_t RcvHdrq13DCAOPH[8];
  1041. pseudo_bit_t RcvHdrq13DCAXfrCnt[6];
  1042. pseudo_bit_t _unused_0[4];
  1043. pseudo_bit_t RcvHdrq14DCAOPH[8];
  1044. pseudo_bit_t RcvHdrq14DCAXfrCnt[6];
  1045. pseudo_bit_t RcvHdrq15DCAOPH[8];
  1046. pseudo_bit_t RcvHdrq15DCAXfrCnt[6];
  1047. pseudo_bit_t _unused_1[4];
  1048. };
  1049. struct QIB_7322_DCACtrlE {
  1050. PSEUDO_BIT_STRUCT ( struct QIB_7322_DCACtrlE_pb );
  1051. };
  1052. /* Default value: 0x0000000000000000 */
  1053. #define QIB_7322_DCACtrlF_offset 0x000005a8UL
  1054. struct QIB_7322_DCACtrlF_pb {
  1055. pseudo_bit_t RcvHdrq16DCAOPH[8];
  1056. pseudo_bit_t RcvHdrq16DCAXfrCnt[6];
  1057. pseudo_bit_t RcvHdrq17DCAOPH[8];
  1058. pseudo_bit_t RcvHdrq17DCAXfrCnt[6];
  1059. pseudo_bit_t _unused_0[4];
  1060. pseudo_bit_t SendDma0DCAOPH[8];
  1061. pseudo_bit_t SendDma1DCAOPH[8];
  1062. pseudo_bit_t _unused_1[16];
  1063. };
  1064. struct QIB_7322_DCACtrlF {
  1065. PSEUDO_BIT_STRUCT ( struct QIB_7322_DCACtrlF_pb );
  1066. };
  1067. /* Default value: 0x0000000000000000 */
  1068. #define QIB_7322_MemErrCtrlA_offset 0x00000600UL
  1069. struct QIB_7322_MemErrCtrlA_pb {
  1070. pseudo_bit_t FSSUncErrRcvBuf_0[1];
  1071. pseudo_bit_t FSSUncErrRcvFlags_0[1];
  1072. pseudo_bit_t FSSUncErrLookupiqBuf_0[1];
  1073. pseudo_bit_t FSSUncErrRcvDMAHdrBuf_0[1];
  1074. pseudo_bit_t FSSUncErrRcvDMADataBuf_0[1];
  1075. pseudo_bit_t FSSUncErrRcvBuf_1[1];
  1076. pseudo_bit_t FSSUncErrRcvFlags_1[1];
  1077. pseudo_bit_t FSSUncErrLookupiqBuf_1[1];
  1078. pseudo_bit_t FSSUncErrRcvDMAHdrBuf_1[1];
  1079. pseudo_bit_t FSSUncErrRcvDMADataBuf_1[1];
  1080. pseudo_bit_t FSSUncErrRcvTIDArray[1];
  1081. pseudo_bit_t FSSUncErrRcvEgrArray[1];
  1082. pseudo_bit_t _unused_0[3];
  1083. pseudo_bit_t FSSUncErrSendBufVL15[1];
  1084. pseudo_bit_t FSSUncErrSendBufMain[1];
  1085. pseudo_bit_t FSSUncErrSendBufExtra[1];
  1086. pseudo_bit_t FSSUncErrSendPbcArray[1];
  1087. pseudo_bit_t FSSUncErrSendLaFIFO0_0[1];
  1088. pseudo_bit_t FSSUncErrSendLaFIFO1_0[1];
  1089. pseudo_bit_t FSSUncErrSendLaFIFO2_0[1];
  1090. pseudo_bit_t FSSUncErrSendLaFIFO3_0[1];
  1091. pseudo_bit_t FSSUncErrSendLaFIFO4_0[1];
  1092. pseudo_bit_t FSSUncErrSendLaFIFO5_0[1];
  1093. pseudo_bit_t FSSUncErrSendLaFIFO6_0[1];
  1094. pseudo_bit_t FSSUncErrSendLaFIFO7_0[1];
  1095. pseudo_bit_t FSSUncErrSendLaFIFO0_1[1];
  1096. pseudo_bit_t FSSUncErrSendLaFIFO1_1[1];
  1097. pseudo_bit_t FSSUncErrSendLaFIFO2_1[1];
  1098. pseudo_bit_t FSSUncErrSendLaFIFO3_1[1];
  1099. pseudo_bit_t FSSUncErrSendLaFIFO4_1[1];
  1100. pseudo_bit_t FSSUncErrSendLaFIFO5_1[1];
  1101. pseudo_bit_t FSSUncErrSendLaFIFO6_1[1];
  1102. pseudo_bit_t FSSUncErrSendLaFIFO7_1[1];
  1103. pseudo_bit_t FSSUncErrSendRmFIFO_0[1];
  1104. pseudo_bit_t FSSUncErrSendRmFIFO_1[1];
  1105. pseudo_bit_t _unused_1[11];
  1106. pseudo_bit_t FSSUncErrPCIeRetryBuf[1];
  1107. pseudo_bit_t FSSUncErrPCIePostHdrBuf[1];
  1108. pseudo_bit_t FSSUncErrPCIePostDataBuf[1];
  1109. pseudo_bit_t FSSUncErrPCIeCompHdrBuf[1];
  1110. pseudo_bit_t FSSUncErrPCIeCompDataBuf[1];
  1111. pseudo_bit_t FSSUncErrMsixTable0[1];
  1112. pseudo_bit_t FSSUncErrMsixTable1[1];
  1113. pseudo_bit_t FSSUncErrMsixTable2[1];
  1114. pseudo_bit_t _unused_2[4];
  1115. pseudo_bit_t SwapEccDataMsixBits[1];
  1116. pseudo_bit_t SwapEccDataExtraBits[1];
  1117. pseudo_bit_t DisableEccCorrection[1];
  1118. pseudo_bit_t SwapEccDataBits[1];
  1119. };
  1120. struct QIB_7322_MemErrCtrlA {
  1121. PSEUDO_BIT_STRUCT ( struct QIB_7322_MemErrCtrlA_pb );
  1122. };
  1123. /* Default value: 0x0000000000000000 */
  1124. #define QIB_7322_MemErrCtrlB_offset 0x00000608UL
  1125. struct QIB_7322_MemErrCtrlB_pb {
  1126. pseudo_bit_t FSSCorErrRcvBuf_0[1];
  1127. pseudo_bit_t FSSCorErrRcvFlags_0[1];
  1128. pseudo_bit_t FSSCorErrLookupiqBuf_0[1];
  1129. pseudo_bit_t FSSCorErrRcvDMAHdrBuf_0[1];
  1130. pseudo_bit_t FSSCorErrRcvDMADataBuf_0[1];
  1131. pseudo_bit_t FSSCorErrRcvBuf_1[1];
  1132. pseudo_bit_t FSSCorErrRcvFlags_1[1];
  1133. pseudo_bit_t FSSCorErrLookupiqBuf_1[1];
  1134. pseudo_bit_t FSSCorErrRcvDMAHdrBuf_1[1];
  1135. pseudo_bit_t FSSCorErrRcvDMADataBuf_1[1];
  1136. pseudo_bit_t FSSCorErrRcvTIDArray[1];
  1137. pseudo_bit_t FSSCorErrRcvEgrArray[1];
  1138. pseudo_bit_t _unused_0[3];
  1139. pseudo_bit_t FSSCorErrSendBufVL15[1];
  1140. pseudo_bit_t FSSCorErrSendBufMain[1];
  1141. pseudo_bit_t FSSCorErrSendBufExtra[1];
  1142. pseudo_bit_t FSSCorErrSendPbcArray[1];
  1143. pseudo_bit_t FSSCorErrSendLaFIFO0_0[1];
  1144. pseudo_bit_t FSSCorErrSendLaFIFO1_0[1];
  1145. pseudo_bit_t FSSCorErrSendLaFIFO2_0[1];
  1146. pseudo_bit_t FSSCorErrSendLaFIFO3_0[1];
  1147. pseudo_bit_t FSSCorErrSendLaFIFO4_0[1];
  1148. pseudo_bit_t FSSCorErrSendLaFIFO5_0[1];
  1149. pseudo_bit_t FSSCorErrSendLaFIFO6_0[1];
  1150. pseudo_bit_t FSSCorErrSendLaFIFO7_0[1];
  1151. pseudo_bit_t FSSCorErrSendLaFIFO0_1[1];
  1152. pseudo_bit_t FSSCorErrSendLaFIFO1_1[1];
  1153. pseudo_bit_t FSSCorErrSendLaFIFO2_1[1];
  1154. pseudo_bit_t FSSCorErrSendLaFIFO3_1[1];
  1155. pseudo_bit_t FSSCorErrSendLaFIFO4_1[1];
  1156. pseudo_bit_t FSSCorErrSendLaFIFO5_1[1];
  1157. pseudo_bit_t FSSCorErrSendLaFIFO6_1[1];
  1158. pseudo_bit_t FSSCorErrSendLaFIFO7_1[1];
  1159. pseudo_bit_t FSSCorErrSendRmFIFO_0[1];
  1160. pseudo_bit_t FSSCorErrSendRmFIFO_1[1];
  1161. pseudo_bit_t _unused_1[11];
  1162. pseudo_bit_t FSSCorErrPCIeRetryBuf[1];
  1163. pseudo_bit_t FSSCorErrPCIePostHdrBuf[1];
  1164. pseudo_bit_t FSSCorErrPCIePostDataBuf[1];
  1165. pseudo_bit_t FSSCorErrPCIeCompHdrBuf[1];
  1166. pseudo_bit_t FSSCorErrPCIeCompDataBuf[1];
  1167. pseudo_bit_t FSSCorErrMsixTable0[1];
  1168. pseudo_bit_t FSSCorErrMsixTable1[1];
  1169. pseudo_bit_t FSSCorErrMsixTable2[1];
  1170. pseudo_bit_t _unused_2[8];
  1171. };
  1172. struct QIB_7322_MemErrCtrlB {
  1173. PSEUDO_BIT_STRUCT ( struct QIB_7322_MemErrCtrlB_pb );
  1174. };
  1175. /* Default value: 0x0000000000000000 */
  1176. #define QIB_7322_MemMultiUnCorErrMask_offset 0x00000610UL
  1177. struct QIB_7322_MemMultiUnCorErrMask_pb {
  1178. pseudo_bit_t MulUncErrMskRcvBuf_0[1];
  1179. pseudo_bit_t MulUncErrMskRcvFlags_0[1];
  1180. pseudo_bit_t MulUncErrMskLookupiqBuf_0[1];
  1181. pseudo_bit_t MulUncErrMskRcvDMAHdrBuf_0[1];
  1182. pseudo_bit_t MulUncErrMskRcvDMADataBuf_0[1];
  1183. pseudo_bit_t MulUncErrMskRcvBuf_1[1];
  1184. pseudo_bit_t MulUncErrMskRcvFlags_1[1];
  1185. pseudo_bit_t MulUncErrMskLookupiqBuf_1[1];
  1186. pseudo_bit_t MulUncErrMskRcvDMAHdrBuf_1[1];
  1187. pseudo_bit_t MulUncErrMskRcvDMADataBuf_1[1];
  1188. pseudo_bit_t MulUncErrMskRcvTIDArray[1];
  1189. pseudo_bit_t MulUncErrMskRcvEgrArray[1];
  1190. pseudo_bit_t _unused_0[3];
  1191. pseudo_bit_t MulUncErrMskSendBufVL15[1];
  1192. pseudo_bit_t MulUncErrMskSendBufMain[1];
  1193. pseudo_bit_t MulUncErrMskSendBufExtra[1];
  1194. pseudo_bit_t MulUncErrMskSendPbcArray[1];
  1195. pseudo_bit_t MulUncErrMskSendLaFIFO0_0[1];
  1196. pseudo_bit_t MulUncErrMskSendLaFIFO1_0[1];
  1197. pseudo_bit_t MulUncErrMskSendLaFIFO2_0[1];
  1198. pseudo_bit_t MulUncErrMskSendLaFIFO3_0[1];
  1199. pseudo_bit_t MulUncErrMskSendLaFIFO4_0[1];
  1200. pseudo_bit_t MulUncErrMskSendLaFIFO5_0[1];
  1201. pseudo_bit_t MulUncErrMskSendLaFIFO6_0[1];
  1202. pseudo_bit_t MulUncErrMskSendLaFIFO7_0[1];
  1203. pseudo_bit_t MulUncErrMskSendLaFIFO0_1[1];
  1204. pseudo_bit_t MulUncErrMskSendLaFIFO1_1[1];
  1205. pseudo_bit_t MulUncErrMskSendLaFIFO2_1[1];
  1206. pseudo_bit_t MulUncErrMskSendLaFIFO3_1[1];
  1207. pseudo_bit_t MulUncErrMskSendLaFIFO4_1[1];
  1208. pseudo_bit_t MulUncErrMskSendLaFIFO5_1[1];
  1209. pseudo_bit_t MulUncErrMskSendLaFIFO6_1[1];
  1210. pseudo_bit_t MulUncErrMskSendLaFIFO7_1[1];
  1211. pseudo_bit_t MulUncErrMskSendRmFIFO_0[1];
  1212. pseudo_bit_t MulUncErrMskSendRmFIFO_1[1];
  1213. pseudo_bit_t _unused_1[11];
  1214. pseudo_bit_t MulUncErrMskPCIeRetryBuf[1];
  1215. pseudo_bit_t MulUncErrMskPCIePostHdrBuf[1];
  1216. pseudo_bit_t MulUncErrMskPCIePostDataBuf[1];
  1217. pseudo_bit_t MulUncErrMskPCIeCompHdrBuf[1];
  1218. pseudo_bit_t MulUncErrMskPCIeCompDataBuf[1];
  1219. pseudo_bit_t MulUncErrMskMsixTable0[1];
  1220. pseudo_bit_t MulUncErrMskMsixTable1[1];
  1221. pseudo_bit_t MulUncErrMskMsixTable2[1];
  1222. pseudo_bit_t _unused_2[8];
  1223. };
  1224. struct QIB_7322_MemMultiUnCorErrMask {
  1225. PSEUDO_BIT_STRUCT ( struct QIB_7322_MemMultiUnCorErrMask_pb );
  1226. };
  1227. /* Default value: 0x0000000000000000 */
  1228. #define QIB_7322_MemMultiUnCorErrStatus_offset 0x00000618UL
  1229. struct QIB_7322_MemMultiUnCorErrStatus_pb {
  1230. pseudo_bit_t MulUncErrStatusRcvBuf_0[1];
  1231. pseudo_bit_t MulUncErrStatusRcvFlags_0[1];
  1232. pseudo_bit_t MulUncErrStatusLookupiqBuf_0[1];
  1233. pseudo_bit_t MulUncErrStatusRcvDMAHdrBuf_0[1];
  1234. pseudo_bit_t MulUncErrStatusRcvDMADataBuf_0[1];
  1235. pseudo_bit_t MulUncErrStatusRcvBuf_1[1];
  1236. pseudo_bit_t MulUncErrStatusRcvFlags_1[1];
  1237. pseudo_bit_t MulUncErrStatusLookupiqBuf_1[1];
  1238. pseudo_bit_t MulUncErrStatusRcvDMAHdrBuf_1[1];
  1239. pseudo_bit_t MulUncErrStatusRcvDMADataBuf_1[1];
  1240. pseudo_bit_t MulUncErrStatusRcvTIDArray[1];
  1241. pseudo_bit_t MulUncErrStatusRcvEgrArray[1];
  1242. pseudo_bit_t _unused_0[3];
  1243. pseudo_bit_t MulUncErrStatusSendBufVL15[1];
  1244. pseudo_bit_t MulUncErrStatusSendBufMain[1];
  1245. pseudo_bit_t MulUncErrStatusSendBufExtra[1];
  1246. pseudo_bit_t MulUncErrStatusSendPbcArray[1];
  1247. pseudo_bit_t MulUncErrStatusSendLaFIFO0_0[1];
  1248. pseudo_bit_t MulUncErrStatusSendLaFIFO1_0[1];
  1249. pseudo_bit_t MulUncErrStatusSendLaFIFO2_0[1];
  1250. pseudo_bit_t MulUncErrStatusSendLaFIFO3_0[1];
  1251. pseudo_bit_t MulUncErrStatusSendLaFIFO4_0[1];
  1252. pseudo_bit_t MulUncErrStatusSendLaFIFO5_0[1];
  1253. pseudo_bit_t MulUncErrStatusSendLaFIFO6_0[1];
  1254. pseudo_bit_t MulUncErrStatusSendLaFIFO7_0[1];
  1255. pseudo_bit_t MulUncErrStatusSendLaFIFO0_1[1];
  1256. pseudo_bit_t MulUncErrStatusSendLaFIFO1_1[1];
  1257. pseudo_bit_t MulUncErrStatusSendLaFIFO2_1[1];
  1258. pseudo_bit_t MulUncErrStatusSendLaFIFO3_1[1];
  1259. pseudo_bit_t MulUncErrStatusSendLaFIFO4_1[1];
  1260. pseudo_bit_t MulUncErrStatusSendLaFIFO5_1[1];
  1261. pseudo_bit_t MulUncErrStatusSendLaFIFO6_1[1];
  1262. pseudo_bit_t MulUncErrStatusSendLaFIFO7_1[1];
  1263. pseudo_bit_t MulUncErrStatusSendRmFIFO_0[1];
  1264. pseudo_bit_t MulUncErrStatusSendRmFIFO_1[1];
  1265. pseudo_bit_t _unused_1[11];
  1266. pseudo_bit_t MulUncErrStatusPCIeRetryBuf[1];
  1267. pseudo_bit_t MulUncErrStatusPCIePostHdrBuf[1];
  1268. pseudo_bit_t MulUncErrStatusPCIePostDataBuf[1];
  1269. pseudo_bit_t MulUncErrStatusPCIeCompHdrBuf[1];
  1270. pseudo_bit_t MulUncErrStatusPCIeCompDataBuf[1];
  1271. pseudo_bit_t MulUncErrStatusMsixTable0[1];
  1272. pseudo_bit_t MulUncErrStatusMsixTable1[1];
  1273. pseudo_bit_t MulUncErrStatusMsixTable2[1];
  1274. pseudo_bit_t _unused_2[8];
  1275. };
  1276. struct QIB_7322_MemMultiUnCorErrStatus {
  1277. PSEUDO_BIT_STRUCT ( struct QIB_7322_MemMultiUnCorErrStatus_pb );
  1278. };
  1279. /* Default value: 0x0000000000000000 */
  1280. #define QIB_7322_MemMultiUnCorErrClear_offset 0x00000620UL
  1281. struct QIB_7322_MemMultiUnCorErrClear_pb {
  1282. pseudo_bit_t MulUncErrClearRcvBuf_0[1];
  1283. pseudo_bit_t MulUncErrClearRcvFlags_0[1];
  1284. pseudo_bit_t MulUncErrClearLookupiqBuf_0[1];
  1285. pseudo_bit_t MulUncErrClearRcvDMAHdrBuf_0[1];
  1286. pseudo_bit_t MulUncErrClearRcvDMADataBuf_0[1];
  1287. pseudo_bit_t MulUncErrClearRcvBuf_1[1];
  1288. pseudo_bit_t MulUncErrClearRcvFlags_1[1];
  1289. pseudo_bit_t MulUncErrClearLookupiqBuf_1[1];
  1290. pseudo_bit_t MulUncErrClearRcvDMAHdrBuf_1[1];
  1291. pseudo_bit_t MulUncErrClearRcvDMADataBuf_1[1];
  1292. pseudo_bit_t MulUncErrClearRcvTIDArray[1];
  1293. pseudo_bit_t MulUncErrClearRcvEgrArray[1];
  1294. pseudo_bit_t _unused_0[3];
  1295. pseudo_bit_t MulUncErrClearSendBufVL15[1];
  1296. pseudo_bit_t MulUncErrClearSendBufMain[1];
  1297. pseudo_bit_t MulUncErrClearSendBufExtra[1];
  1298. pseudo_bit_t MulUncErrClearSendPbcArray[1];
  1299. pseudo_bit_t MulUncErrClearSendLaFIFO0_0[1];
  1300. pseudo_bit_t MulUncErrClearSendLaFIFO1_0[1];
  1301. pseudo_bit_t MulUncErrClearSendLaFIFO2_0[1];
  1302. pseudo_bit_t MulUncErrClearSendLaFIFO3_0[1];
  1303. pseudo_bit_t MulUncErrClearSendLaFIFO4_0[1];
  1304. pseudo_bit_t MulUncErrClearSendLaFIFO5_0[1];
  1305. pseudo_bit_t MulUncErrClearSendLaFIFO6_0[1];
  1306. pseudo_bit_t MulUncErrClearSendLaFIFO7_0[1];
  1307. pseudo_bit_t MulUncErrClearSendLaFIFO0_1[1];
  1308. pseudo_bit_t MulUncErrClearSendLaFIFO1_1[1];
  1309. pseudo_bit_t MulUncErrClearSendLaFIFO2_1[1];
  1310. pseudo_bit_t MulUncErrClearSendLaFIFO3_1[1];
  1311. pseudo_bit_t MulUncErrClearSendLaFIFO4_1[1];
  1312. pseudo_bit_t MulUncErrClearSendLaFIFO5_1[1];
  1313. pseudo_bit_t MulUncErrClearSendLaFIFO6_1[1];
  1314. pseudo_bit_t MulUncErrClearSendLaFIFO7_1[1];
  1315. pseudo_bit_t MulUncErrClearSendRmFIFO_0[1];
  1316. pseudo_bit_t MulUncErrClearSendRmFIFO_1[1];
  1317. pseudo_bit_t _unused_1[11];
  1318. pseudo_bit_t MulUncErrClearPCIeRetryBuf[1];
  1319. pseudo_bit_t MulUncErrClearPCIePostHdrBuf[1];
  1320. pseudo_bit_t MulUncErrClearPCIePostDataBuf[1];
  1321. pseudo_bit_t MulUncErrClearPCIeCompHdrBuf[1];
  1322. pseudo_bit_t MulUncErrClearPCIeCompDataBuf[1];
  1323. pseudo_bit_t MulUncErrClearMsixTable0[1];
  1324. pseudo_bit_t MulUncErrClearMsixTable1[1];
  1325. pseudo_bit_t MulUncErrClearMsixTable2[1];
  1326. pseudo_bit_t _unused_2[8];
  1327. };
  1328. struct QIB_7322_MemMultiUnCorErrClear {
  1329. PSEUDO_BIT_STRUCT ( struct QIB_7322_MemMultiUnCorErrClear_pb );
  1330. };
  1331. /* Default value: 0x0000000000000000 */
  1332. #define QIB_7322_MemUnCorErrMask_offset 0x00000628UL
  1333. struct QIB_7322_MemUnCorErrMask_pb {
  1334. pseudo_bit_t UncErrMskRcvBuf_0[1];
  1335. pseudo_bit_t UncErrMskRcvFlags_0[1];
  1336. pseudo_bit_t UncErrMskLookupiqBuf_0[1];
  1337. pseudo_bit_t UncErrMskRcvDMAHdrBuf_0[1];
  1338. pseudo_bit_t UncErrMskRcvDMADataBuf_0[1];
  1339. pseudo_bit_t UncErrMskRcvBuf_1[1];
  1340. pseudo_bit_t UncErrMskRcvFlags_1[1];
  1341. pseudo_bit_t UncErrMskLookupiqBuf_1[1];
  1342. pseudo_bit_t UncErrMskRcvDMAHdrBuf_1[1];
  1343. pseudo_bit_t UncErrMskRcvDMADataBuf_1[1];
  1344. pseudo_bit_t UncErrMskRcvTIDArray[1];
  1345. pseudo_bit_t UncErrMskRcvEgrArray[1];
  1346. pseudo_bit_t _unused_0[3];
  1347. pseudo_bit_t UncErrMskSendBufVL15[1];
  1348. pseudo_bit_t UncErrMskSendBufMain[1];
  1349. pseudo_bit_t UncErrMskSendBufExtra[1];
  1350. pseudo_bit_t UncErrMskSendPbcArray[1];
  1351. pseudo_bit_t UncErrMskSendLaFIFO0_0[1];
  1352. pseudo_bit_t UncErrMskSendLaFIFO1_0[1];
  1353. pseudo_bit_t UncErrMskSendLaFIFO2_0[1];
  1354. pseudo_bit_t UncErrMskSendLaFIFO3_0[1];
  1355. pseudo_bit_t UncErrMskSendLaFIFO4_0[1];
  1356. pseudo_bit_t UncErrMskSendLaFIFO5_0[1];
  1357. pseudo_bit_t UncErrMskSendLaFIFO6_0[1];
  1358. pseudo_bit_t UncErrMskSendLaFIFO7_0[1];
  1359. pseudo_bit_t UncErrMskSendLaFIFO0_1[1];
  1360. pseudo_bit_t UncErrMskSendLaFIFO1_1[1];
  1361. pseudo_bit_t UncErrMskSendLaFIFO2_1[1];
  1362. pseudo_bit_t UncErrMskSendLaFIFO3_1[1];
  1363. pseudo_bit_t UncErrMskSendLaFIFO4_1[1];
  1364. pseudo_bit_t UncErrMskSendLaFIFO5_1[1];
  1365. pseudo_bit_t UncErrMskSendLaFIFO6_1[1];
  1366. pseudo_bit_t UncErrMskSendLaFIFO7_1[1];
  1367. pseudo_bit_t UncErrMskSendRmFIFO_0[1];
  1368. pseudo_bit_t UncErrMskSendRmFIFO_1[1];
  1369. pseudo_bit_t _unused_1[11];
  1370. pseudo_bit_t UncErrMskPCIeRetryBuf[1];
  1371. pseudo_bit_t UncErrMskPCIePostHdrBuf[1];
  1372. pseudo_bit_t UncErrMskPCIePostDataBuf[1];
  1373. pseudo_bit_t UncErrMskPCIeCompHdrBuf[1];
  1374. pseudo_bit_t UncErrMskPCIeCompDataBuf[1];
  1375. pseudo_bit_t UncErrMskMsixTable0[1];
  1376. pseudo_bit_t UncErrMskMsixTable1[1];
  1377. pseudo_bit_t UncErrMskMsixTable2[1];
  1378. pseudo_bit_t _unused_2[8];
  1379. };
  1380. struct QIB_7322_MemUnCorErrMask {
  1381. PSEUDO_BIT_STRUCT ( struct QIB_7322_MemUnCorErrMask_pb );
  1382. };
  1383. /* Default value: 0x0000000000000000 */
  1384. #define QIB_7322_MemUnCorErrStatus_offset 0x00000630UL
  1385. struct QIB_7322_MemUnCorErrStatus_pb {
  1386. pseudo_bit_t UncErrStatusRcvBuf_0[1];
  1387. pseudo_bit_t UncErrStatusRcvFlags_0[1];
  1388. pseudo_bit_t UncErrStatusLookupiqBuf_0[1];
  1389. pseudo_bit_t UncErrStatusRcvDMAHdrBuf_0[1];
  1390. pseudo_bit_t UncErrStatusRcvDMADataBuf_0[1];
  1391. pseudo_bit_t UncErrStatusRcvBuf_1[1];
  1392. pseudo_bit_t UncErrStatusRcvFlags_1[1];
  1393. pseudo_bit_t UncErrStatusLookupiqBuf_1[1];
  1394. pseudo_bit_t UncErrStatusRcvDMAHdrBuf_1[1];
  1395. pseudo_bit_t UncErrStatusRcvDMADataBuf_1[1];
  1396. pseudo_bit_t UncErrStatusRcvTIDArray[1];
  1397. pseudo_bit_t UncErrStatusRcvEgrArray[1];
  1398. pseudo_bit_t _unused_0[3];
  1399. pseudo_bit_t UncErrStatusSendBufVL15[1];
  1400. pseudo_bit_t UncErrStatusSendBufMain[1];
  1401. pseudo_bit_t UncErrStatusSendBufExtra[1];
  1402. pseudo_bit_t UncErrStatusSendPbcArray[1];
  1403. pseudo_bit_t UncErrStatusSendLaFIFO0_0[1];
  1404. pseudo_bit_t UncErrStatusSendLaFIFO1_0[1];
  1405. pseudo_bit_t UncErrStatusSendLaFIFO2_0[1];
  1406. pseudo_bit_t UncErrStatusSendLaFIFO3_0[1];
  1407. pseudo_bit_t UncErrStatusSendLaFIFO4_0[1];
  1408. pseudo_bit_t UncErrStatusSendLaFIFO5_0[1];
  1409. pseudo_bit_t UncErrStatusSendLaFIFO6_0[1];
  1410. pseudo_bit_t UncErrStatusSendLaFIFO7_0[1];
  1411. pseudo_bit_t UncErrStatusSendLaFIFO0_1[1];
  1412. pseudo_bit_t UncErrStatusSendLaFIFO1_1[1];
  1413. pseudo_bit_t UncErrStatusSendLaFIFO2_1[1];
  1414. pseudo_bit_t UncErrStatusSendLaFIFO3_1[1];
  1415. pseudo_bit_t UncErrStatusSendLaFIFO4_1[1];
  1416. pseudo_bit_t UncErrStatusSendLaFIFO5_1[1];
  1417. pseudo_bit_t UncErrStatusSendLaFIFO6_1[1];
  1418. pseudo_bit_t UncErrStatusSendLaFIFO7_1[1];
  1419. pseudo_bit_t UncErrStatusSendRmFIFO_0[1];
  1420. pseudo_bit_t UncErrStatusSendRmFIFO_1[1];
  1421. pseudo_bit_t _unused_1[11];
  1422. pseudo_bit_t UncErrStatusPCIeRetryBuf[1];
  1423. pseudo_bit_t UncErrStatusPCIePostHdrBuf[1];
  1424. pseudo_bit_t UncErrStatusPCIePostDataBuf[1];
  1425. pseudo_bit_t UncErrStatusPCIeCompHdrBuf[1];
  1426. pseudo_bit_t UncErrStatusPCIeCompDataBuf[1];
  1427. pseudo_bit_t UncErrStatusMsixTable0[1];
  1428. pseudo_bit_t UncErrStatusMsixTable1[1];
  1429. pseudo_bit_t UncErrStatusMsixTable2[1];
  1430. pseudo_bit_t _unused_2[8];
  1431. };
  1432. struct QIB_7322_MemUnCorErrStatus {
  1433. PSEUDO_BIT_STRUCT ( struct QIB_7322_MemUnCorErrStatus_pb );
  1434. };
  1435. /* Default value: 0x0000000000000000 */
  1436. #define QIB_7322_MemUnCorErrClear_offset 0x00000638UL
  1437. struct QIB_7322_MemUnCorErrClear_pb {
  1438. pseudo_bit_t UncErrClearRcvBuf_0[1];
  1439. pseudo_bit_t UncErrClearRcvFlags_0[1];
  1440. pseudo_bit_t UncErrClearLookupiqBuf_0[1];
  1441. pseudo_bit_t UncErrClearRcvDMAHdrBuf_0[1];
  1442. pseudo_bit_t UncErrClearRcvDMADataBuf_0[1];
  1443. pseudo_bit_t UncErrClearRcvBuf_1[1];
  1444. pseudo_bit_t UncErrClearRcvFlags_1[1];
  1445. pseudo_bit_t UncErrClearLookupiqBuf_1[1];
  1446. pseudo_bit_t UncErrClearRcvDMAHdrBuf_1[1];
  1447. pseudo_bit_t UncErrClearRcvDMADataBuf_1[1];
  1448. pseudo_bit_t UncErrClearRcvTIDArray[1];
  1449. pseudo_bit_t UncErrClearRcvEgrArray[1];
  1450. pseudo_bit_t _unused_0[3];
  1451. pseudo_bit_t UncErrClearSendBufVL15[1];
  1452. pseudo_bit_t UncErrClearSendBufMain[1];
  1453. pseudo_bit_t UncErrClearSendBufExtra[1];
  1454. pseudo_bit_t UncErrClearSendPbcArray[1];
  1455. pseudo_bit_t UncErrClearSendLaFIFO0_0[1];
  1456. pseudo_bit_t UncErrClearSendLaFIFO1_0[1];
  1457. pseudo_bit_t UncErrClearSendLaFIFO2_0[1];
  1458. pseudo_bit_t UncErrClearSendLaFIFO3_0[1];
  1459. pseudo_bit_t UncErrClearSendLaFIFO4_0[1];
  1460. pseudo_bit_t UncErrClearSendLaFIFO5_0[1];
  1461. pseudo_bit_t UncErrClearSendLaFIFO6_0[1];
  1462. pseudo_bit_t UncErrClearSendLaFIFO7_0[1];
  1463. pseudo_bit_t UncErrClearSendLaFIFO0_1[1];
  1464. pseudo_bit_t UncErrClearSendLaFIFO1_1[1];
  1465. pseudo_bit_t UncErrClearSendLaFIFO2_1[1];
  1466. pseudo_bit_t UncErrClearSendLaFIFO3_1[1];
  1467. pseudo_bit_t UncErrClearSendLaFIFO4_1[1];
  1468. pseudo_bit_t UncErrClearSendLaFIFO5_1[1];
  1469. pseudo_bit_t UncErrClearSendLaFIFO6_1[1];
  1470. pseudo_bit_t UncErrClearSendLaFIFO7_1[1];
  1471. pseudo_bit_t UncErrClearSendRmFIFO_0[1];
  1472. pseudo_bit_t UncErrClearSendRmFIFO_1[1];
  1473. pseudo_bit_t _unused_1[11];
  1474. pseudo_bit_t UncErrClearPCIeRetryBuf[1];
  1475. pseudo_bit_t UncErrClearPCIePostHdrBuf[1];
  1476. pseudo_bit_t UncErrClearPCIePostDataBuf[1];
  1477. pseudo_bit_t UncErrClearPCIeCompHdrBuf[1];
  1478. pseudo_bit_t UncErrClearPCIeCompDataBuf[1];
  1479. pseudo_bit_t UncErrClearMsixTable0[1];
  1480. pseudo_bit_t UncErrClearMsixTable1[1];
  1481. pseudo_bit_t UncErrClearMsixTable2[1];
  1482. pseudo_bit_t _unused_2[8];
  1483. };
  1484. struct QIB_7322_MemUnCorErrClear {
  1485. PSEUDO_BIT_STRUCT ( struct QIB_7322_MemUnCorErrClear_pb );
  1486. };
  1487. /* Default value: 0x0000000000000000 */
  1488. #define QIB_7322_MemMultiCorErrMask_offset 0x00000640UL
  1489. struct QIB_7322_MemMultiCorErrMask_pb {
  1490. pseudo_bit_t MulCorErrMskRcvBuf_0[1];
  1491. pseudo_bit_t MulCorErrMskRcvFlags_0[1];
  1492. pseudo_bit_t MulCorErrMskLookupiqBuf_0[1];
  1493. pseudo_bit_t MulCorErrMskRcvDMAHdrBuf_0[1];
  1494. pseudo_bit_t MulCorErrMskRcvDMADataBuf_0[1];
  1495. pseudo_bit_t MulCorErrMskRcvBuf_1[1];
  1496. pseudo_bit_t MulCorErrMskRcvFlags_1[1];
  1497. pseudo_bit_t MulCorErrMskLookupiqBuf_1[1];
  1498. pseudo_bit_t MulCorErrMskRcvDMAHdrBuf_1[1];
  1499. pseudo_bit_t MulCorErrMskRcvDMADataBuf_1[1];
  1500. pseudo_bit_t MulCorErrMskRcvTIDArray[1];
  1501. pseudo_bit_t MulCorErrMskRcvEgrArray[1];
  1502. pseudo_bit_t _unused_0[3];
  1503. pseudo_bit_t MulCorErrMskSendBufVL15[1];
  1504. pseudo_bit_t MulCorErrMskSendBufMain[1];
  1505. pseudo_bit_t MulCorErrMskSendBufExtra[1];
  1506. pseudo_bit_t MulCorErrMskSendPbcArray[1];
  1507. pseudo_bit_t MulCorErrMskSendLaFIFO0_0[1];
  1508. pseudo_bit_t MulCorErrMskSendLaFIFO1_0[1];
  1509. pseudo_bit_t MulCorErrMskSendLaFIFO2_0[1];
  1510. pseudo_bit_t MulCorErrMskSendLaFIFO3_0[1];
  1511. pseudo_bit_t MulCorErrMskSendLaFIFO4_0[1];
  1512. pseudo_bit_t MulCorErrMskSendLaFIFO5_0[1];
  1513. pseudo_bit_t MulCorErrMskSendLaFIFO6_0[1];
  1514. pseudo_bit_t MulCorErrMskSendLaFIFO7_0[1];
  1515. pseudo_bit_t MulCorErrMskSendLaFIFO0_1[1];
  1516. pseudo_bit_t MulCorErrMskSendLaFIFO1_1[1];
  1517. pseudo_bit_t MulCorErrMskSendLaFIFO2_1[1];
  1518. pseudo_bit_t MulCorErrMskSendLaFIFO3_1[1];
  1519. pseudo_bit_t MulCorErrMskSendLaFIFO4_1[1];
  1520. pseudo_bit_t MulCorErrMskSendLaFIFO5_1[1];
  1521. pseudo_bit_t MulCorErrMskSendLaFIFO6_1[1];
  1522. pseudo_bit_t MulCorErrMskSendLaFIFO7_1[1];
  1523. pseudo_bit_t MulCorErrMskSendRmFIFO_0[1];
  1524. pseudo_bit_t MulCorErrMskSendRmFIFO_1[1];
  1525. pseudo_bit_t _unused_1[11];
  1526. pseudo_bit_t MulCorErrMskPCIeRetryBuf[1];
  1527. pseudo_bit_t MulCorErrMskPCIePostHdrBuf[1];
  1528. pseudo_bit_t MulCorErrMskPCIePostDataBuf[1];
  1529. pseudo_bit_t MulCorErrMskPCIeCompHdrBuf[1];
  1530. pseudo_bit_t MulCorErrMskPCIeCompDataBuf[1];
  1531. pseudo_bit_t MulCorErrMskMsixTable0[1];
  1532. pseudo_bit_t MulCorErrMskMsixTable1[1];
  1533. pseudo_bit_t MulCorErrMskMsixTable2[1];
  1534. pseudo_bit_t _unused_2[8];
  1535. };
  1536. struct QIB_7322_MemMultiCorErrMask {
  1537. PSEUDO_BIT_STRUCT ( struct QIB_7322_MemMultiCorErrMask_pb );
  1538. };
  1539. /* Default value: 0x0000000000000000 */
  1540. #define QIB_7322_MemMultiCorErrStatus_offset 0x00000648UL
  1541. struct QIB_7322_MemMultiCorErrStatus_pb {
  1542. pseudo_bit_t MulCorErrStatusRcvBuf_0[1];
  1543. pseudo_bit_t MulCorErrStatusRcvFlags_0[1];
  1544. pseudo_bit_t MulCorErrStatusLookupiqBuf_0[1];
  1545. pseudo_bit_t MulCorErrStatusRcvDMAHdrBuf_0[1];
  1546. pseudo_bit_t MulCorErrStatusRcvDMADataBuf_0[1];
  1547. pseudo_bit_t MulCorErrStatusRcvBuf_1[1];
  1548. pseudo_bit_t MulCorErrStatusRcvFlags_1[1];
  1549. pseudo_bit_t MulCorErrStatusLookupiqBuf_1[1];
  1550. pseudo_bit_t MulCorErrStatusRcvDMAHdrBuf_1[1];
  1551. pseudo_bit_t MulCorErrStatusRcvDMADataBuf_1[1];
  1552. pseudo_bit_t MulCorErrStatusRcvTIDArray[1];
  1553. pseudo_bit_t MulCorErrStatusRcvEgrArray[1];
  1554. pseudo_bit_t _unused_0[3];
  1555. pseudo_bit_t MulCorErrStatusSendBufVL15[1];
  1556. pseudo_bit_t MulCorErrStatusSendBufMain[1];
  1557. pseudo_bit_t MulCorErrStatusSendBufExtra[1];
  1558. pseudo_bit_t MulCorErrStatusSendPbcArray[1];
  1559. pseudo_bit_t MulCorErrStatusSendLaFIFO0_0[1];
  1560. pseudo_bit_t MulCorErrStatusSendLaFIFO1_0[1];
  1561. pseudo_bit_t MulCorErrStatusSendLaFIFO2_0[1];
  1562. pseudo_bit_t MulCorErrStatusSendLaFIFO3_0[1];
  1563. pseudo_bit_t MulCorErrStatusSendLaFIFO4_0[1];
  1564. pseudo_bit_t MulCorErrStatusSendLaFIFO5_0[1];
  1565. pseudo_bit_t MulCorErrStatusSendLaFIFO6_0[1];
  1566. pseudo_bit_t MulCorErrStatusSendLaFIFO7_0[1];
  1567. pseudo_bit_t MulCorErrStatusSendLaFIFO0_1[1];
  1568. pseudo_bit_t MulCorErrStatusSendLaFIFO1_1[1];
  1569. pseudo_bit_t MulCorErrStatusSendLaFIFO2_1[1];
  1570. pseudo_bit_t MulCorErrStatusSendLaFIFO3_1[1];
  1571. pseudo_bit_t MulCorErrStatusSendLaFIFO4_1[1];
  1572. pseudo_bit_t MulCorErrStatusSendLaFIFO5_1[1];
  1573. pseudo_bit_t MulCorErrStatusSendLaFIFO6_1[1];
  1574. pseudo_bit_t MulCorErrStatusSendLaFIFO7_1[1];
  1575. pseudo_bit_t MulCorErrStatusSendRmFIFO_0[1];
  1576. pseudo_bit_t MulCorErrStatusSendRmFIFO_1[1];
  1577. pseudo_bit_t _unused_1[11];
  1578. pseudo_bit_t MulCorErrStatusPCIeRetryBuf[1];
  1579. pseudo_bit_t MulCorErrStatusPCIePostHdrBuf[1];
  1580. pseudo_bit_t MulCorErrStatusPCIePostDataBuf[1];
  1581. pseudo_bit_t MulCorErrStatusPCIeCompHdrBuf[1];
  1582. pseudo_bit_t MulCorErrStatusPCIeCompDataBuf[1];
  1583. pseudo_bit_t MulCorErrStatusMsixTable0[1];
  1584. pseudo_bit_t MulCorErrStatusMsixTable1[1];
  1585. pseudo_bit_t MulCorErrStatusMsixTable2[1];
  1586. pseudo_bit_t _unused_2[8];
  1587. };
  1588. struct QIB_7322_MemMultiCorErrStatus {
  1589. PSEUDO_BIT_STRUCT ( struct QIB_7322_MemMultiCorErrStatus_pb );
  1590. };
  1591. /* Default value: 0x0000000000000000 */
  1592. #define QIB_7322_MemMultiCorErrClear_offset 0x00000650UL
  1593. struct QIB_7322_MemMultiCorErrClear_pb {
  1594. pseudo_bit_t MulCorErrClearRcvBuf_0[1];
  1595. pseudo_bit_t MulCorErrClearRcvFlags_0[1];
  1596. pseudo_bit_t MulCorErrClearLookupiqBuf_0[1];
  1597. pseudo_bit_t MulCorErrClearRcvDMAHdrBuf_0[1];
  1598. pseudo_bit_t MulCorErrClearRcvDMADataBuf_0[1];
  1599. pseudo_bit_t MulCorErrClearRcvBuf_1[1];
  1600. pseudo_bit_t MulCorErrClearRcvFlags_1[1];
  1601. pseudo_bit_t MulCorErrClearLookupiqBuf_1[1];
  1602. pseudo_bit_t MulCorErrClearRcvDMAHdrBuf_1[1];
  1603. pseudo_bit_t MulCorErrClearRcvDMADataBuf_1[1];
  1604. pseudo_bit_t MulCorErrClearRcvTIDArray[1];
  1605. pseudo_bit_t MulCorErrClearRcvEgrArray[1];
  1606. pseudo_bit_t _unused_0[3];
  1607. pseudo_bit_t MulCorErrClearSendBufVL15[1];
  1608. pseudo_bit_t MulCorErrClearSendBufMain[1];
  1609. pseudo_bit_t MulCorErrClearSendBufExtra[1];
  1610. pseudo_bit_t MulCorErrClearSendPbcArray[1];
  1611. pseudo_bit_t MulCorErrClearSendLaFIFO0_0[1];
  1612. pseudo_bit_t MulCorErrClearSendLaFIFO1_0[1];
  1613. pseudo_bit_t MulCorErrClearSendLaFIFO2_0[1];
  1614. pseudo_bit_t MulCorErrClearSendLaFIFO3_0[1];
  1615. pseudo_bit_t MulCorErrClearSendLaFIFO4_0[1];
  1616. pseudo_bit_t MulCorErrClearSendLaFIFO5_0[1];
  1617. pseudo_bit_t MulCorErrClearSendLaFIFO6_0[1];
  1618. pseudo_bit_t MulCorErrClearSendLaFIFO7_0[1];
  1619. pseudo_bit_t MulCorErrClearSendLaFIFO0_1[1];
  1620. pseudo_bit_t MulCorErrClearSendLaFIFO1_1[1];
  1621. pseudo_bit_t MulCorErrClearSendLaFIFO2_1[1];
  1622. pseudo_bit_t MulCorErrClearSendLaFIFO3_1[1];
  1623. pseudo_bit_t MulCorErrClearSendLaFIFO4_1[1];
  1624. pseudo_bit_t MulCorErrClearSendLaFIFO5_1[1];
  1625. pseudo_bit_t MulCorErrClearSendLaFIFO6_1[1];
  1626. pseudo_bit_t MulCorErrClearSendLaFIFO7_1[1];
  1627. pseudo_bit_t MulCorErrClearSendRmFIFO_0[1];
  1628. pseudo_bit_t MulCorErrClearSendRmFIFO_1[1];
  1629. pseudo_bit_t _unused_1[11];
  1630. pseudo_bit_t MulCorErrClearPCIeRetryBuf[1];
  1631. pseudo_bit_t MulCorErrClearPCIePostHdrBuf[1];
  1632. pseudo_bit_t MulCorErrClearPCIePostDataBuf[1];
  1633. pseudo_bit_t MulCorErrClearPCIeCompHdrBuf[1];
  1634. pseudo_bit_t MulCorErrClearPCIeCompDataBuf[1];
  1635. pseudo_bit_t MulCorErrClearMsixTable0[1];
  1636. pseudo_bit_t MulCorErrClearMsixTable1[1];
  1637. pseudo_bit_t MulCorErrClearMsixTable2[1];
  1638. pseudo_bit_t _unused_2[8];
  1639. };
  1640. struct QIB_7322_MemMultiCorErrClear {
  1641. PSEUDO_BIT_STRUCT ( struct QIB_7322_MemMultiCorErrClear_pb );
  1642. };
  1643. /* Default value: 0x0000000000000000 */
  1644. #define QIB_7322_MemCorErrMask_offset 0x00000658UL
  1645. struct QIB_7322_MemCorErrMask_pb {
  1646. pseudo_bit_t CorErrMskRcvBuf_0[1];
  1647. pseudo_bit_t CorErrMskRcvFlags_0[1];
  1648. pseudo_bit_t CorErrMskLookupiqBuf_0[1];
  1649. pseudo_bit_t CorErrMskRcvDMAHdrBuf_0[1];
  1650. pseudo_bit_t CorErrMskRcvDMADataBuf_0[1];
  1651. pseudo_bit_t CorErrMskRcvBuf_1[1];
  1652. pseudo_bit_t CorErrMskRcvFlags_1[1];
  1653. pseudo_bit_t CorErrMskLookupiqBuf_1[1];
  1654. pseudo_bit_t CorErrMskRcvDMAHdrBuf_1[1];
  1655. pseudo_bit_t CorErrMskRcvDMADataBuf_1[1];
  1656. pseudo_bit_t CorErrMskRcvTIDArray[1];
  1657. pseudo_bit_t CorErrMskRcvEgrArray[1];
  1658. pseudo_bit_t _unused_0[3];
  1659. pseudo_bit_t CorErrMskSendBufVL15[1];
  1660. pseudo_bit_t CorErrMskSendBufMain[1];
  1661. pseudo_bit_t CorErrMskSendBufExtra[1];
  1662. pseudo_bit_t CorErrMskSendPbcArray[1];
  1663. pseudo_bit_t CorErrMskSendLaFIFO0_0[1];
  1664. pseudo_bit_t CorErrMskSendLaFIFO1_0[1];
  1665. pseudo_bit_t CorErrMskSendLaFIFO2_0[1];
  1666. pseudo_bit_t CorErrMskSendLaFIFO3_0[1];
  1667. pseudo_bit_t CorErrMskSendLaFIFO4_0[1];
  1668. pseudo_bit_t CorErrMskSendLaFIFO5_0[1];
  1669. pseudo_bit_t CorErrMskSendLaFIFO6_0[1];
  1670. pseudo_bit_t CorErrMskSendLaFIFO7_0[1];
  1671. pseudo_bit_t CorErrMskSendLaFIFO0_1[1];
  1672. pseudo_bit_t CorErrMskSendLaFIFO1_1[1];
  1673. pseudo_bit_t CorErrMskSendLaFIFO2_1[1];
  1674. pseudo_bit_t CorErrMskSendLaFIFO3_1[1];
  1675. pseudo_bit_t CorErrMskSendLaFIFO4_1[1];
  1676. pseudo_bit_t CorErrMskSendLaFIFO5_1[1];
  1677. pseudo_bit_t CorErrMskSendLaFIFO6_1[1];
  1678. pseudo_bit_t CorErrMskSendLaFIFO7_1[1];
  1679. pseudo_bit_t CorErrMskSendRmFIFO_0[1];
  1680. pseudo_bit_t CorErrMskSendRmFIFO_1[1];
  1681. pseudo_bit_t _unused_1[11];
  1682. pseudo_bit_t CorErrMskPCIeRetryBuf[1];
  1683. pseudo_bit_t CorErrMskPCIePostHdrBuf[1];
  1684. pseudo_bit_t CorErrMskPCIePostDataBuf[1];
  1685. pseudo_bit_t CorErrMskPCIeCompHdrBuf[1];
  1686. pseudo_bit_t CorErrMskPCIeCompDataBuf[1];
  1687. pseudo_bit_t CorErrMskMsixTable0[1];
  1688. pseudo_bit_t CorErrMskMsixTable1[1];
  1689. pseudo_bit_t CorErrMskMsixTable2[1];
  1690. pseudo_bit_t _unused_2[8];
  1691. };
  1692. struct QIB_7322_MemCorErrMask {
  1693. PSEUDO_BIT_STRUCT ( struct QIB_7322_MemCorErrMask_pb );
  1694. };
  1695. /* Default value: 0x0000000000000000 */
  1696. #define QIB_7322_MemCorErrStatus_offset 0x00000660UL
  1697. struct QIB_7322_MemCorErrStatus_pb {
  1698. pseudo_bit_t CorErrStatusRcvBuf_0[1];
  1699. pseudo_bit_t CorErrStatusRcvFlags_0[1];
  1700. pseudo_bit_t CorErrStatusLookupiqBuf_0[1];
  1701. pseudo_bit_t CorErrStatusRcvDMAHdrBuf_0[1];
  1702. pseudo_bit_t CorErrStatusRcvDMADataBuf_0[1];
  1703. pseudo_bit_t CorErrStatusRcvBuf_1[1];
  1704. pseudo_bit_t CorErrStatusRcvFlags_1[1];
  1705. pseudo_bit_t CorErrStatusLookupiqBuf_1[1];
  1706. pseudo_bit_t CorErrStatusRcvDMAHdrBuf_1[1];
  1707. pseudo_bit_t CorErrStatusRcvDMADataBuf_1[1];
  1708. pseudo_bit_t CorErrStatusRcvTIDArray[1];
  1709. pseudo_bit_t CorErrStatusRcvEgrArray[1];
  1710. pseudo_bit_t _unused_0[3];
  1711. pseudo_bit_t CorErrStatusSendBufVL15[1];
  1712. pseudo_bit_t CorErrStatusSendBufMain[1];
  1713. pseudo_bit_t CorErrStatusSendBufExtra[1];
  1714. pseudo_bit_t CorErrStatusSendPbcArray[1];
  1715. pseudo_bit_t CorErrStatusSendLaFIFO0_0[1];
  1716. pseudo_bit_t CorErrStatusSendLaFIFO1_0[1];
  1717. pseudo_bit_t CorErrStatusSendLaFIFO2_0[1];
  1718. pseudo_bit_t CorErrStatusSendLaFIFO3_0[1];
  1719. pseudo_bit_t CorErrStatusSendLaFIFO4_0[1];
  1720. pseudo_bit_t CorErrStatusSendLaFIFO5_0[1];
  1721. pseudo_bit_t CorErrStatusSendLaFIFO6_0[1];
  1722. pseudo_bit_t CorErrStatusSendLaFIFO7_0[1];
  1723. pseudo_bit_t CorErrStatusSendLaFIFO0_1[1];
  1724. pseudo_bit_t CorErrStatusSendLaFIFO1_1[1];
  1725. pseudo_bit_t CorErrStatusSendLaFIFO2_1[1];
  1726. pseudo_bit_t CorErrStatusSendLaFIFO3_1[1];
  1727. pseudo_bit_t CorErrStatusSendLaFIFO4_1[1];
  1728. pseudo_bit_t CorErrStatusSendLaFIFO5_1[1];
  1729. pseudo_bit_t CorErrStatusSendLaFIFO6_1[1];
  1730. pseudo_bit_t CorErrStatusSendLaFIFO7_1[1];
  1731. pseudo_bit_t CorErrStatusSendRmFIFO_0[1];
  1732. pseudo_bit_t CorErrStatusSendRmFIFO_1[1];
  1733. pseudo_bit_t _unused_1[11];
  1734. pseudo_bit_t CorErrStatusPCIeRetryBuf[1];
  1735. pseudo_bit_t CorErrStatusPCIePostHdrBuf[1];
  1736. pseudo_bit_t CorErrStatusPCIePostDataBuf[1];
  1737. pseudo_bit_t CorErrStatusPCIeCompHdrBuf[1];
  1738. pseudo_bit_t CorErrStatusPCIeCompDataBuf[1];
  1739. pseudo_bit_t CorErrStatusMsixTable0[1];
  1740. pseudo_bit_t CorErrStatusMsixTable1[1];
  1741. pseudo_bit_t CorErrStatusMsixTable2[1];
  1742. pseudo_bit_t _unused_2[8];
  1743. };
  1744. struct QIB_7322_MemCorErrStatus {
  1745. PSEUDO_BIT_STRUCT ( struct QIB_7322_MemCorErrStatus_pb );
  1746. };
  1747. /* Default value: 0x0000000000000000 */
  1748. #define QIB_7322_MemCorErrClear_offset 0x00000668UL
  1749. struct QIB_7322_MemCorErrClear_pb {
  1750. pseudo_bit_t CorErrClearRcvBuf_0[1];
  1751. pseudo_bit_t CorErrClearRcvFlags_0[1];
  1752. pseudo_bit_t CorErrClearLookupiqBuf_0[1];
  1753. pseudo_bit_t CorErrClearRcvDMAHdrBuf_0[1];
  1754. pseudo_bit_t CorErrClearRcvDMADataBuf_0[1];
  1755. pseudo_bit_t CorErrClearRcvBuf_1[1];
  1756. pseudo_bit_t CorErrClearRcvFlags_1[1];
  1757. pseudo_bit_t CorErrClearLookupiqBuf_1[1];
  1758. pseudo_bit_t CorErrClearRcvDMAHdrBuf_1[1];
  1759. pseudo_bit_t CorErrClearRcvDMADataBuf_1[1];
  1760. pseudo_bit_t CorErrClearRcvTIDArray[1];
  1761. pseudo_bit_t CorErrClearRcvEgrArray[1];
  1762. pseudo_bit_t _unused_0[3];
  1763. pseudo_bit_t CorErrClearSendBufVL15[1];
  1764. pseudo_bit_t CorErrClearSendBufMain[1];
  1765. pseudo_bit_t CorErrClearSendBufExtra[1];
  1766. pseudo_bit_t CorErrClearSendPbcArray[1];
  1767. pseudo_bit_t CorErrClearSendLaFIFO0_0[1];
  1768. pseudo_bit_t CorErrClearSendLaFIFO1_0[1];
  1769. pseudo_bit_t CorErrClearSendLaFIFO2_0[1];
  1770. pseudo_bit_t CorErrClearSendLaFIFO3_0[1];
  1771. pseudo_bit_t CorErrClearSendLaFIFO4_0[1];
  1772. pseudo_bit_t CorErrClearSendLaFIFO5_0[1];
  1773. pseudo_bit_t CorErrClearSendLaFIFO6_0[1];
  1774. pseudo_bit_t CorErrClearSendLaFIFO7_0[1];
  1775. pseudo_bit_t CorErrClearSendLaFIFO0_1[1];
  1776. pseudo_bit_t CorErrClearSendLaFIFO1_1[1];
  1777. pseudo_bit_t CorErrClearSendLaFIFO2_1[1];
  1778. pseudo_bit_t CorErrClearSendLaFIFO3_1[1];
  1779. pseudo_bit_t CorErrClearSendLaFIFO4_1[1];
  1780. pseudo_bit_t CorErrClearSendLaFIFO5_1[1];
  1781. pseudo_bit_t CorErrClearSendLaFIFO6_1[1];
  1782. pseudo_bit_t CorErrClearSendLaFIFO7_1[1];
  1783. pseudo_bit_t CorErrClearSendRmFIFO_0[1];
  1784. pseudo_bit_t CorErrClearSendRmFIFO_1[1];
  1785. pseudo_bit_t _unused_1[11];
  1786. pseudo_bit_t CorErrClearPCIeRetryBuf[1];
  1787. pseudo_bit_t CorErrClearPCIePostHdrBuf[1];
  1788. pseudo_bit_t CorErrClearPCIePostDataBuf[1];
  1789. pseudo_bit_t CorErrClearPCIeCompHdrBuf[1];
  1790. pseudo_bit_t CorErrClearPCIeCompDataBuf[1];
  1791. pseudo_bit_t CorErrClearMsixTable0[1];
  1792. pseudo_bit_t CorErrClearMsixTable1[1];
  1793. pseudo_bit_t CorErrClearMsixTable2[1];
  1794. pseudo_bit_t _unused_2[8];
  1795. };
  1796. struct QIB_7322_MemCorErrClear {
  1797. PSEUDO_BIT_STRUCT ( struct QIB_7322_MemCorErrClear_pb );
  1798. };
  1799. /* Default value: 0x0000000000000000 */
  1800. #define QIB_7322_MsixTableUnCorErrLogA_offset 0x00000680UL
  1801. struct QIB_7322_MsixTableUnCorErrLogA_pb {
  1802. pseudo_bit_t MsixTable_1_0_UnCorErrData[64];
  1803. };
  1804. struct QIB_7322_MsixTableUnCorErrLogA {
  1805. PSEUDO_BIT_STRUCT ( struct QIB_7322_MsixTableUnCorErrLogA_pb );
  1806. };
  1807. /* Default value: 0x0000000000000000 */
  1808. #define QIB_7322_MsixTableUnCorErrLogB_offset 0x00000688UL
  1809. struct QIB_7322_MsixTableUnCorErrLogB_pb {
  1810. pseudo_bit_t MsixTable_2_UnCorErrData[32];
  1811. pseudo_bit_t MsixTable_0_UnCorErrCheckBits[7];
  1812. pseudo_bit_t MsixTable_1_UnCorErrCheckBits[7];
  1813. pseudo_bit_t MsixTable_2_UnCorErrCheckBits[7];
  1814. pseudo_bit_t _unused_0[11];
  1815. };
  1816. struct QIB_7322_MsixTableUnCorErrLogB {
  1817. PSEUDO_BIT_STRUCT ( struct QIB_7322_MsixTableUnCorErrLogB_pb );
  1818. };
  1819. /* Default value: 0x0000000000000000 */
  1820. #define QIB_7322_MsixTableUnCorErrLogC_offset 0x00000690UL
  1821. struct QIB_7322_MsixTableUnCorErrLogC_pb {
  1822. pseudo_bit_t MsixTable_0_UnCorErrAddr[7];
  1823. pseudo_bit_t MsixTable_1_UnCorErrAddr[7];
  1824. pseudo_bit_t MsixTable_2_UnCorErrAddr[7];
  1825. pseudo_bit_t _unused_0[43];
  1826. };
  1827. struct QIB_7322_MsixTableUnCorErrLogC {
  1828. PSEUDO_BIT_STRUCT ( struct QIB_7322_MsixTableUnCorErrLogC_pb );
  1829. };
  1830. /* Default value: 0x0000000000000000 */
  1831. #define QIB_7322_MsixEntryWithUncorErr_offset 0x00000698UL
  1832. /* Default value: 0x0000000000000000 */
  1833. #define QIB_7322_MsixTableCorErrLogA_offset 0x000006a0UL
  1834. struct QIB_7322_MsixTableCorErrLogA_pb {
  1835. pseudo_bit_t MsixTable_1_0_CorErrData[64];
  1836. };
  1837. struct QIB_7322_MsixTableCorErrLogA {
  1838. PSEUDO_BIT_STRUCT ( struct QIB_7322_MsixTableCorErrLogA_pb );
  1839. };
  1840. /* Default value: 0x0000000000000000 */
  1841. #define QIB_7322_MsixTableCorErrLogB_offset 0x000006a8UL
  1842. struct QIB_7322_MsixTableCorErrLogB_pb {
  1843. pseudo_bit_t MsixTable_2_CorErrData[32];
  1844. pseudo_bit_t MsixTable_0_CorErrCheckBits[7];
  1845. pseudo_bit_t MsixTable_1_CorErrCheckBits[7];
  1846. pseudo_bit_t MsixTable_2_CorErrCheckBits[7];
  1847. pseudo_bit_t _unused_0[11];
  1848. };
  1849. struct QIB_7322_MsixTableCorErrLogB {
  1850. PSEUDO_BIT_STRUCT ( struct QIB_7322_MsixTableCorErrLogB_pb );
  1851. };
  1852. /* Default value: 0x0000000000000000 */
  1853. #define QIB_7322_MsixTableCorErrLogC_offset 0x000006b0UL
  1854. struct QIB_7322_MsixTableCorErrLogC_pb {
  1855. pseudo_bit_t MsixTable_0_CorErrAddr[7];
  1856. pseudo_bit_t MsixTable_1_CorErrAddr[7];
  1857. pseudo_bit_t MsixTable_2_CorErrAddr[7];
  1858. pseudo_bit_t _unused_0[43];
  1859. };
  1860. struct QIB_7322_MsixTableCorErrLogC {
  1861. PSEUDO_BIT_STRUCT ( struct QIB_7322_MsixTableCorErrLogC_pb );
  1862. };
  1863. /* Default value: 0x0000000000000000 */
  1864. #define QIB_7322_PcieCplDataBufrUnCorErrLogA_offset 0x00000700UL
  1865. struct QIB_7322_PcieCplDataBufrUnCorErrLogA_pb {
  1866. pseudo_bit_t PcieCplDataBufrUnCorErrData_63_0[64];
  1867. };
  1868. struct QIB_7322_PcieCplDataBufrUnCorErrLogA {
  1869. PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplDataBufrUnCorErrLogA_pb );
  1870. };
  1871. /* Default value: 0x0000000000000000 */
  1872. #define QIB_7322_PcieCplDataBufrUnCorErrLogB_offset 0x00000708UL
  1873. struct QIB_7322_PcieCplDataBufrUnCorErrLogB_pb {
  1874. pseudo_bit_t PcieCplDataBufrUnCorErrData_127_64[64];
  1875. };
  1876. struct QIB_7322_PcieCplDataBufrUnCorErrLogB {
  1877. PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplDataBufrUnCorErrLogB_pb );
  1878. };
  1879. /* Default value: 0x0000000000000000 */
  1880. #define QIB_7322_PcieCplDataBufrUnCorErrLogC_offset 0x00000710UL
  1881. struct QIB_7322_PcieCplDataBufrUnCorErrLogC_pb {
  1882. pseudo_bit_t PcieCplDataBufrUnCorErrData_136_128[9];
  1883. pseudo_bit_t PcieCplDataBufrUnCorErrCheckBit_21_0[22];
  1884. pseudo_bit_t PcieCplDataBufrUnCorErrAddr_13_0[14];
  1885. pseudo_bit_t _unused_0[19];
  1886. };
  1887. struct QIB_7322_PcieCplDataBufrUnCorErrLogC {
  1888. PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplDataBufrUnCorErrLogC_pb );
  1889. };
  1890. /* Default value: 0x0000000000000000 */
  1891. #define QIB_7322_PcieCplHdrBufrUnCorErrLogA_offset 0x00000720UL
  1892. struct QIB_7322_PcieCplHdrBufrUnCorErrLogA_pb {
  1893. pseudo_bit_t PcieCplHdrBufrUnCorErrHdr_63_0[64];
  1894. };
  1895. struct QIB_7322_PcieCplHdrBufrUnCorErrLogA {
  1896. PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplHdrBufrUnCorErrLogA_pb );
  1897. };
  1898. /* Default value: 0x0000000000000000 */
  1899. #define QIB_7322_PcieCplHdrBufrUnCorErrLogB_offset 0x00000728UL
  1900. struct QIB_7322_PcieCplHdrBufrUnCorErrLogB_pb {
  1901. pseudo_bit_t PcieCplHdrBufrUnCorErrHdr_103_64[40];
  1902. pseudo_bit_t _unused_0[24];
  1903. };
  1904. struct QIB_7322_PcieCplHdrBufrUnCorErrLogB {
  1905. PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplHdrBufrUnCorErrLogB_pb );
  1906. };
  1907. /* Default value: 0x0000000000000000 */
  1908. #define QIB_7322_PcieCplHdrBufrUnCorErrLogC_offset 0x00000730UL
  1909. struct QIB_7322_PcieCplHdrBufrUnCorErrLogC_pb {
  1910. pseudo_bit_t PcieCplHdrBufrUnCorErrCheckBit_15_0[16];
  1911. pseudo_bit_t PcieCplHdrBufrUnCorErrAddr_8_0[9];
  1912. pseudo_bit_t _unused_0[39];
  1913. };
  1914. struct QIB_7322_PcieCplHdrBufrUnCorErrLogC {
  1915. PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplHdrBufrUnCorErrLogC_pb );
  1916. };
  1917. /* Default value: 0x0000000000000000 */
  1918. #define QIB_7322_PciePDataBufrUnCorErrLogA_offset 0x00000740UL
  1919. struct QIB_7322_PciePDataBufrUnCorErrLogA_pb {
  1920. pseudo_bit_t PciePDataBufrUnCorErrData_63_0[64];
  1921. };
  1922. struct QIB_7322_PciePDataBufrUnCorErrLogA {
  1923. PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePDataBufrUnCorErrLogA_pb );
  1924. };
  1925. /* Default value: 0x0000000000000000 */
  1926. #define QIB_7322_PciePDataBufrUnCorErrLogB_offset 0x00000748UL
  1927. struct QIB_7322_PciePDataBufrUnCorErrLogB_pb {
  1928. pseudo_bit_t PciePDataBufrUnCorErrData_127_64[64];
  1929. };
  1930. struct QIB_7322_PciePDataBufrUnCorErrLogB {
  1931. PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePDataBufrUnCorErrLogB_pb );
  1932. };
  1933. /* Default value: 0x0000000000000000 */
  1934. #define QIB_7322_PciePDataBufrUnCorErrLogC_offset 0x00000750UL
  1935. struct QIB_7322_PciePDataBufrUnCorErrLogC_pb {
  1936. pseudo_bit_t PciePDataBufrUnCorErrData_136_128[9];
  1937. pseudo_bit_t PciePDataBufrUnCorErrCheckBit_21_0[22];
  1938. pseudo_bit_t PciePDataBufrUnCorErrAddr_13_0[14];
  1939. pseudo_bit_t _unused_0[19];
  1940. };
  1941. struct QIB_7322_PciePDataBufrUnCorErrLogC {
  1942. PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePDataBufrUnCorErrLogC_pb );
  1943. };
  1944. /* Default value: 0x0000000000000000 */
  1945. #define QIB_7322_PciePHdrBufrUnCorErrLogA_offset 0x00000760UL
  1946. struct QIB_7322_PciePHdrBufrUnCorErrLogA_pb {
  1947. pseudo_bit_t PciePHdrBufrUnCorErrData_63_0[64];
  1948. };
  1949. struct QIB_7322_PciePHdrBufrUnCorErrLogA {
  1950. PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePHdrBufrUnCorErrLogA_pb );
  1951. };
  1952. /* Default value: 0x0000000000000000 */
  1953. #define QIB_7322_PciePHdrBufrUnCorErrLogB_offset 0x00000768UL
  1954. struct QIB_7322_PciePHdrBufrUnCorErrLogB_pb {
  1955. pseudo_bit_t PciePHdrBufrUnCorErrData_107_64[44];
  1956. pseudo_bit_t _unused_0[20];
  1957. };
  1958. struct QIB_7322_PciePHdrBufrUnCorErrLogB {
  1959. PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePHdrBufrUnCorErrLogB_pb );
  1960. };
  1961. /* Default value: 0x0000000000000000 */
  1962. #define QIB_7322_PciePHdrBufrUnCorErrLogC_offset 0x00000770UL
  1963. struct QIB_7322_PciePHdrBufrUnCorErrLogC_pb {
  1964. pseudo_bit_t PciePHdrBufrUnCorErrCheckBit_15_0[16];
  1965. pseudo_bit_t PciePHdrBufrUnCorErrAddr_8_0[9];
  1966. pseudo_bit_t _unused_0[39];
  1967. };
  1968. struct QIB_7322_PciePHdrBufrUnCorErrLogC {
  1969. PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePHdrBufrUnCorErrLogC_pb );
  1970. };
  1971. /* Default value: 0x0000000000000000 */
  1972. #define QIB_7322_PcieRetryBufrUnCorErrLogA_offset 0x00000780UL
  1973. struct QIB_7322_PcieRetryBufrUnCorErrLogA_pb {
  1974. pseudo_bit_t PcieRetryBufrUnCorErrData_63_0[64];
  1975. };
  1976. struct QIB_7322_PcieRetryBufrUnCorErrLogA {
  1977. PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieRetryBufrUnCorErrLogA_pb );
  1978. };
  1979. /* Default value: 0x0000000000000000 */
  1980. #define QIB_7322_PcieRetryBufrUnCorErrLogB_offset 0x00000788UL
  1981. struct QIB_7322_PcieRetryBufrUnCorErrLogB_pb {
  1982. pseudo_bit_t PcieRetryBufrUnCorErrData_127_64[64];
  1983. };
  1984. struct QIB_7322_PcieRetryBufrUnCorErrLogB {
  1985. PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieRetryBufrUnCorErrLogB_pb );
  1986. };
  1987. /* Default value: 0x0000000000000000 */
  1988. #define QIB_7322_PcieRetryBufrUnCorErrLogC_offset 0x00000790UL
  1989. struct QIB_7322_PcieRetryBufrUnCorErrLogC_pb {
  1990. pseudo_bit_t PcieRetryBufrUnCorErrData_133_128[6];
  1991. pseudo_bit_t PcieRetryBufrUnCorErrCheckBit_20_0[21];
  1992. pseudo_bit_t PcieRetryBufrUnCorErrAddr_13_0[14];
  1993. pseudo_bit_t _unused_0[23];
  1994. };
  1995. struct QIB_7322_PcieRetryBufrUnCorErrLogC {
  1996. PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieRetryBufrUnCorErrLogC_pb );
  1997. };
  1998. /* Default value: 0x0000000000000000 */
  1999. #define QIB_7322_RxTIDArrayUnCorErrLogA_offset 0x00000800UL
  2000. struct QIB_7322_RxTIDArrayUnCorErrLogA_pb {
  2001. pseudo_bit_t RxTIDArrayUnCorErrData_39_0[40];
  2002. pseudo_bit_t RxTIDArrayUnCorErrCheckBit_11_0[12];
  2003. pseudo_bit_t _unused_0[12];
  2004. };
  2005. struct QIB_7322_RxTIDArrayUnCorErrLogA {
  2006. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxTIDArrayUnCorErrLogA_pb );
  2007. };
  2008. /* Default value: 0x0000000000000000 */
  2009. #define QIB_7322_RxTIDArrayUnCorErrLogB_offset 0x00000808UL
  2010. struct QIB_7322_RxTIDArrayUnCorErrLogB_pb {
  2011. pseudo_bit_t RxTIDArrayUnCorErrAddr_16_0[17];
  2012. pseudo_bit_t _unused_0[47];
  2013. };
  2014. struct QIB_7322_RxTIDArrayUnCorErrLogB {
  2015. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxTIDArrayUnCorErrLogB_pb );
  2016. };
  2017. /* Default value: 0x0000000000000000 */
  2018. #define QIB_7322_RxEagerArrayUnCorErrLogA_offset 0x00000810UL
  2019. struct QIB_7322_RxEagerArrayUnCorErrLogA_pb {
  2020. pseudo_bit_t RxEagerArrayUnCorErrData_39_0[40];
  2021. pseudo_bit_t RxEagerArrayUnCorErrCheckBit_11_0[12];
  2022. pseudo_bit_t _unused_0[12];
  2023. };
  2024. struct QIB_7322_RxEagerArrayUnCorErrLogA {
  2025. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxEagerArrayUnCorErrLogA_pb );
  2026. };
  2027. /* Default value: 0x0000000000000000 */
  2028. #define QIB_7322_RxEagerArrayUnCorErrLogB_offset 0x00000818UL
  2029. struct QIB_7322_RxEagerArrayUnCorErrLogB_pb {
  2030. pseudo_bit_t RxEagerArrayUnCorErrAddr_17_0[18];
  2031. pseudo_bit_t _unused_0[46];
  2032. };
  2033. struct QIB_7322_RxEagerArrayUnCorErrLogB {
  2034. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxEagerArrayUnCorErrLogB_pb );
  2035. };
  2036. /* Default value: 0x0000000000000000 */
  2037. #define QIB_7322_SBufMainArrayUnCorErrLogA_offset 0x00000880UL
  2038. struct QIB_7322_SBufMainArrayUnCorErrLogA_pb {
  2039. pseudo_bit_t SBufMainArrayUnCorErrData_63_0[64];
  2040. };
  2041. struct QIB_7322_SBufMainArrayUnCorErrLogA {
  2042. PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufMainArrayUnCorErrLogA_pb );
  2043. };
  2044. /* Default value: 0x0000000000000000 */
  2045. #define QIB_7322_SBufMainArrayUnCorErrLogB_offset 0x00000888UL
  2046. struct QIB_7322_SBufMainArrayUnCorErrLogB_pb {
  2047. pseudo_bit_t SBufMainArrayUnCorErrData_127_64[64];
  2048. };
  2049. struct QIB_7322_SBufMainArrayUnCorErrLogB {
  2050. PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufMainArrayUnCorErrLogB_pb );
  2051. };
  2052. /* Default value: 0x0000000000000000 */
  2053. #define QIB_7322_SBufMainArrayUnCorErrLogC_offset 0x00000890UL
  2054. struct QIB_7322_SBufMainArrayUnCorErrLogC_pb {
  2055. pseudo_bit_t SBufMainArrayUnCorErrCheckBit_27_0[28];
  2056. pseudo_bit_t SBufMainArrayUnCorErrAddr_18_0[19];
  2057. pseudo_bit_t _unused_0[13];
  2058. pseudo_bit_t SBufMainArrayUnCorErrDword_3_0[4];
  2059. };
  2060. struct QIB_7322_SBufMainArrayUnCorErrLogC {
  2061. PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufMainArrayUnCorErrLogC_pb );
  2062. };
  2063. /* Default value: 0x0000000000000000 */
  2064. #define QIB_7322_SBufExtraArrayUnCorErrLogA_offset 0x00000898UL
  2065. struct QIB_7322_SBufExtraArrayUnCorErrLogA_pb {
  2066. pseudo_bit_t SBufExtraArrayUnCorErrData_63_0[64];
  2067. };
  2068. struct QIB_7322_SBufExtraArrayUnCorErrLogA {
  2069. PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufExtraArrayUnCorErrLogA_pb );
  2070. };
  2071. /* Default value: 0x0000000000000000 */
  2072. #define QIB_7322_SBufExtraArrayUnCorErrLogB_offset 0x000008a0UL
  2073. struct QIB_7322_SBufExtraArrayUnCorErrLogB_pb {
  2074. pseudo_bit_t SBufExtraArrayUnCorErrData_127_64[64];
  2075. };
  2076. struct QIB_7322_SBufExtraArrayUnCorErrLogB {
  2077. PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufExtraArrayUnCorErrLogB_pb );
  2078. };
  2079. /* Default value: 0x0000000000000000 */
  2080. #define QIB_7322_SBufExtraArrayUnCorErrLogC_offset 0x000008a8UL
  2081. struct QIB_7322_SBufExtraArrayUnCorErrLogC_pb {
  2082. pseudo_bit_t SBufExtraArrayUnCorErrCheckBit_27_0[28];
  2083. pseudo_bit_t SBufExtraArrayUnCorErrAddr_14_0[15];
  2084. pseudo_bit_t _unused_0[17];
  2085. pseudo_bit_t SBufExtraArrayUnCorErrAdd_3_0[4];
  2086. };
  2087. struct QIB_7322_SBufExtraArrayUnCorErrLogC {
  2088. PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufExtraArrayUnCorErrLogC_pb );
  2089. };
  2090. /* Default value: 0x0000000000000000 */
  2091. #define QIB_7322_SendPbcArrayUnCorErrLog_offset 0x000008b0UL
  2092. struct QIB_7322_SendPbcArrayUnCorErrLog_pb {
  2093. pseudo_bit_t SendPbcArrayUnCorErrData_21_0[22];
  2094. pseudo_bit_t SendPbcArrayUnCorErrCheckBit_6_0[7];
  2095. pseudo_bit_t SendPbcArrayUnCorErrAddr_9_0[10];
  2096. pseudo_bit_t _unused_0[25];
  2097. };
  2098. struct QIB_7322_SendPbcArrayUnCorErrLog {
  2099. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendPbcArrayUnCorErrLog_pb );
  2100. };
  2101. /* Default value: 0x0000000000000000 */
  2102. #define QIB_7322_SBufVL15ArrayUnCorErrLogA_offset 0x000008c0UL
  2103. struct QIB_7322_SBufVL15ArrayUnCorErrLogA_pb {
  2104. pseudo_bit_t SBufVL15ArrayUnCorErrData_63_0[64];
  2105. };
  2106. struct QIB_7322_SBufVL15ArrayUnCorErrLogA {
  2107. PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufVL15ArrayUnCorErrLogA_pb );
  2108. };
  2109. /* Default value: 0x0000000000000000 */
  2110. #define QIB_7322_PcieCplDataBufrCorErrLogA_offset 0x00000900UL
  2111. struct QIB_7322_PcieCplDataBufrCorErrLogA_pb {
  2112. pseudo_bit_t PcieCplDataBufrCorErrData_63_0[64];
  2113. };
  2114. struct QIB_7322_PcieCplDataBufrCorErrLogA {
  2115. PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplDataBufrCorErrLogA_pb );
  2116. };
  2117. /* Default value: 0x0000000000000000 */
  2118. #define QIB_7322_PcieCplDataBufrCorErrLogB_offset 0x00000908UL
  2119. struct QIB_7322_PcieCplDataBufrCorErrLogB_pb {
  2120. pseudo_bit_t PcieCplDataBufrCorErrData_127_64[64];
  2121. };
  2122. struct QIB_7322_PcieCplDataBufrCorErrLogB {
  2123. PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplDataBufrCorErrLogB_pb );
  2124. };
  2125. /* Default value: 0x0000000000000000 */
  2126. #define QIB_7322_PcieCplDataBufrCorErrLogC_offset 0x00000910UL
  2127. struct QIB_7322_PcieCplDataBufrCorErrLogC_pb {
  2128. pseudo_bit_t PcieCplDataBufrCorErrData_136_128[9];
  2129. pseudo_bit_t PcieCplDataBufrCorErrCheckBit_21_0[22];
  2130. pseudo_bit_t PcieCplDataBufrCorErrAddr_13_0[14];
  2131. pseudo_bit_t _unused_0[19];
  2132. };
  2133. struct QIB_7322_PcieCplDataBufrCorErrLogC {
  2134. PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplDataBufrCorErrLogC_pb );
  2135. };
  2136. /* Default value: 0x0000000000000000 */
  2137. #define QIB_7322_PcieCplHdrBufrCorErrLogA_offset 0x00000920UL
  2138. struct QIB_7322_PcieCplHdrBufrCorErrLogA_pb {
  2139. pseudo_bit_t PcieCplHdrBufrCorErrHdr_63_0[64];
  2140. };
  2141. struct QIB_7322_PcieCplHdrBufrCorErrLogA {
  2142. PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplHdrBufrCorErrLogA_pb );
  2143. };
  2144. /* Default value: 0x0000000000000000 */
  2145. #define QIB_7322_PcieCplHdrBufrCorErrLogB_offset 0x00000928UL
  2146. struct QIB_7322_PcieCplHdrBufrCorErrLogB_pb {
  2147. pseudo_bit_t PcieCplHdrBufrCorErrHdr_103_64[40];
  2148. pseudo_bit_t _unused_0[24];
  2149. };
  2150. struct QIB_7322_PcieCplHdrBufrCorErrLogB {
  2151. PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplHdrBufrCorErrLogB_pb );
  2152. };
  2153. /* Default value: 0x0000000000000000 */
  2154. #define QIB_7322_PcieCplHdrBufrCorErrLogC_offset 0x00000930UL
  2155. struct QIB_7322_PcieCplHdrBufrCorErrLogC_pb {
  2156. pseudo_bit_t PcieCplHdrBufrCorErrCheckBit_15_0[16];
  2157. pseudo_bit_t PcieCplHdrBufrCorErrAddr_8_0[9];
  2158. pseudo_bit_t _unused_0[39];
  2159. };
  2160. struct QIB_7322_PcieCplHdrBufrCorErrLogC {
  2161. PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieCplHdrBufrCorErrLogC_pb );
  2162. };
  2163. /* Default value: 0x0000000000000000 */
  2164. #define QIB_7322_PciePDataBufrCorErrLogA_offset 0x00000940UL
  2165. struct QIB_7322_PciePDataBufrCorErrLogA_pb {
  2166. pseudo_bit_t PciePDataBufrCorErrData_63_0[64];
  2167. };
  2168. struct QIB_7322_PciePDataBufrCorErrLogA {
  2169. PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePDataBufrCorErrLogA_pb );
  2170. };
  2171. /* Default value: 0x0000000000000000 */
  2172. #define QIB_7322_PciePDataBufrCorErrLogB_offset 0x00000948UL
  2173. struct QIB_7322_PciePDataBufrCorErrLogB_pb {
  2174. pseudo_bit_t PciePDataBufrCorErrData_127_64[64];
  2175. };
  2176. struct QIB_7322_PciePDataBufrCorErrLogB {
  2177. PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePDataBufrCorErrLogB_pb );
  2178. };
  2179. /* Default value: 0x0000000000000000 */
  2180. #define QIB_7322_PciePDataBufrCorErrLogC_offset 0x00000950UL
  2181. struct QIB_7322_PciePDataBufrCorErrLogC_pb {
  2182. pseudo_bit_t PciePDataBufrCorErrData_136_128[9];
  2183. pseudo_bit_t PciePDataBufrCorErrCheckBit_21_0[22];
  2184. pseudo_bit_t PciePDataBufrCorErrAddr_13_0[14];
  2185. pseudo_bit_t _unused_0[19];
  2186. };
  2187. struct QIB_7322_PciePDataBufrCorErrLogC {
  2188. PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePDataBufrCorErrLogC_pb );
  2189. };
  2190. /* Default value: 0x0000000000000000 */
  2191. #define QIB_7322_PciePHdrBufrCorErrLogA_offset 0x00000960UL
  2192. struct QIB_7322_PciePHdrBufrCorErrLogA_pb {
  2193. pseudo_bit_t PciePHdrBufrCorErrData_63_0[64];
  2194. };
  2195. struct QIB_7322_PciePHdrBufrCorErrLogA {
  2196. PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePHdrBufrCorErrLogA_pb );
  2197. };
  2198. /* Default value: 0x0000000000000000 */
  2199. #define QIB_7322_PciePHdrBufrCorErrLogB_offset 0x00000968UL
  2200. struct QIB_7322_PciePHdrBufrCorErrLogB_pb {
  2201. pseudo_bit_t PciePHdrBufrCorErrData_107_64[44];
  2202. pseudo_bit_t _unused_0[20];
  2203. };
  2204. struct QIB_7322_PciePHdrBufrCorErrLogB {
  2205. PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePHdrBufrCorErrLogB_pb );
  2206. };
  2207. /* Default value: 0x0000000000000000 */
  2208. #define QIB_7322_PciePHdrBufrCorErrLogC_offset 0x00000970UL
  2209. struct QIB_7322_PciePHdrBufrCorErrLogC_pb {
  2210. pseudo_bit_t PciePHdrBufrCorErrCheckBit_15_0[16];
  2211. pseudo_bit_t PciePHdrBufrCorErrAddr_8_0[9];
  2212. pseudo_bit_t _unused_0[39];
  2213. };
  2214. struct QIB_7322_PciePHdrBufrCorErrLogC {
  2215. PSEUDO_BIT_STRUCT ( struct QIB_7322_PciePHdrBufrCorErrLogC_pb );
  2216. };
  2217. /* Default value: 0x0000000000000000 */
  2218. #define QIB_7322_PcieRetryBufrCorErrLogA_offset 0x00000980UL
  2219. struct QIB_7322_PcieRetryBufrCorErrLogA_pb {
  2220. pseudo_bit_t PcieRetryBufrCorErrData_63_0[64];
  2221. };
  2222. struct QIB_7322_PcieRetryBufrCorErrLogA {
  2223. PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieRetryBufrCorErrLogA_pb );
  2224. };
  2225. /* Default value: 0x0000000000000000 */
  2226. #define QIB_7322_PcieRetryBufrCorErrLogB_offset 0x00000988UL
  2227. struct QIB_7322_PcieRetryBufrCorErrLogB_pb {
  2228. pseudo_bit_t PcieRetryBufrCorErrData_127_64[64];
  2229. };
  2230. struct QIB_7322_PcieRetryBufrCorErrLogB {
  2231. PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieRetryBufrCorErrLogB_pb );
  2232. };
  2233. /* Default value: 0x0000000000000000 */
  2234. #define QIB_7322_PcieRetryBufrCorErrLogC_offset 0x00000990UL
  2235. struct QIB_7322_PcieRetryBufrCorErrLogC_pb {
  2236. pseudo_bit_t PcieRetryBufrCorErrData_133_128[6];
  2237. pseudo_bit_t PcieRetryBufrCorErrCheckBit_20_0[21];
  2238. pseudo_bit_t PcieRetryBufrCorErrAddr_13_0[14];
  2239. pseudo_bit_t _unused_0[23];
  2240. };
  2241. struct QIB_7322_PcieRetryBufrCorErrLogC {
  2242. PSEUDO_BIT_STRUCT ( struct QIB_7322_PcieRetryBufrCorErrLogC_pb );
  2243. };
  2244. /* Default value: 0x0000000000000000 */
  2245. #define QIB_7322_RxTIDArrayCorErrLogA_offset 0x00000a00UL
  2246. struct QIB_7322_RxTIDArrayCorErrLogA_pb {
  2247. pseudo_bit_t RxTIDArrayCorErrData_39_0[40];
  2248. pseudo_bit_t RxTIDArrayCorErrCheckBit_11_0[12];
  2249. pseudo_bit_t _unused_0[12];
  2250. };
  2251. struct QIB_7322_RxTIDArrayCorErrLogA {
  2252. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxTIDArrayCorErrLogA_pb );
  2253. };
  2254. /* Default value: 0x0000000000000000 */
  2255. #define QIB_7322_RxTIDArrayCorErrLogB_offset 0x00000a08UL
  2256. struct QIB_7322_RxTIDArrayCorErrLogB_pb {
  2257. pseudo_bit_t RxTIDArrayCorErrAddr_16_0[17];
  2258. pseudo_bit_t _unused_0[47];
  2259. };
  2260. struct QIB_7322_RxTIDArrayCorErrLogB {
  2261. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxTIDArrayCorErrLogB_pb );
  2262. };
  2263. /* Default value: 0x0000000000000000 */
  2264. #define QIB_7322_RxEagerArrayCorErrLogA_offset 0x00000a10UL
  2265. struct QIB_7322_RxEagerArrayCorErrLogA_pb {
  2266. pseudo_bit_t RxEagerArrayCorErrData_39_0[40];
  2267. pseudo_bit_t RxEagerArrayCorErrCheckBit_11_0[12];
  2268. pseudo_bit_t _unused_0[12];
  2269. };
  2270. struct QIB_7322_RxEagerArrayCorErrLogA {
  2271. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxEagerArrayCorErrLogA_pb );
  2272. };
  2273. /* Default value: 0x0000000000000000 */
  2274. #define QIB_7322_RxEagerArrayCorErrLogB_offset 0x00000a18UL
  2275. struct QIB_7322_RxEagerArrayCorErrLogB_pb {
  2276. pseudo_bit_t RxEagerArrayCorErrAddr_17_0[18];
  2277. pseudo_bit_t _unused_0[46];
  2278. };
  2279. struct QIB_7322_RxEagerArrayCorErrLogB {
  2280. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxEagerArrayCorErrLogB_pb );
  2281. };
  2282. /* Default value: 0x0000000000000000 */
  2283. #define QIB_7322_SBufMainArrayCorErrLogA_offset 0x00000a80UL
  2284. struct QIB_7322_SBufMainArrayCorErrLogA_pb {
  2285. pseudo_bit_t SBufMainArrayCorErrData_63_0[64];
  2286. };
  2287. struct QIB_7322_SBufMainArrayCorErrLogA {
  2288. PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufMainArrayCorErrLogA_pb );
  2289. };
  2290. /* Default value: 0x0000000000000000 */
  2291. #define QIB_7322_SBufMainArrayCorErrLogB_offset 0x00000a88UL
  2292. struct QIB_7322_SBufMainArrayCorErrLogB_pb {
  2293. pseudo_bit_t SBufMainArrayCorErrData_127_64[64];
  2294. };
  2295. struct QIB_7322_SBufMainArrayCorErrLogB {
  2296. PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufMainArrayCorErrLogB_pb );
  2297. };
  2298. /* Default value: 0x0000000000000000 */
  2299. #define QIB_7322_SBufMainArrayCorErrLogC_offset 0x00000a90UL
  2300. struct QIB_7322_SBufMainArrayCorErrLogC_pb {
  2301. pseudo_bit_t SBufMainArrayCorErrCheckBit_27_0[28];
  2302. pseudo_bit_t SBufMainArrayCorErrAddr_18_0[19];
  2303. pseudo_bit_t _unused_0[13];
  2304. pseudo_bit_t SBufMainArrayCorErrDword_3_0[4];
  2305. };
  2306. struct QIB_7322_SBufMainArrayCorErrLogC {
  2307. PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufMainArrayCorErrLogC_pb );
  2308. };
  2309. /* Default value: 0x0000000000000000 */
  2310. #define QIB_7322_SBufExtraArrayCorErrLogA_offset 0x00000a98UL
  2311. struct QIB_7322_SBufExtraArrayCorErrLogA_pb {
  2312. pseudo_bit_t SBufExtraArrayCorErrData_63_0[64];
  2313. };
  2314. struct QIB_7322_SBufExtraArrayCorErrLogA {
  2315. PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufExtraArrayCorErrLogA_pb );
  2316. };
  2317. /* Default value: 0x0000000000000000 */
  2318. #define QIB_7322_SBufExtraArrayCorErrLogB_offset 0x00000aa0UL
  2319. struct QIB_7322_SBufExtraArrayCorErrLogB_pb {
  2320. pseudo_bit_t SBufExtraArrayCorErrData_127_64[64];
  2321. };
  2322. struct QIB_7322_SBufExtraArrayCorErrLogB {
  2323. PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufExtraArrayCorErrLogB_pb );
  2324. };
  2325. /* Default value: 0x0000000000000000 */
  2326. #define QIB_7322_SBufExtraArrayCorErrLogC_offset 0x00000aa8UL
  2327. struct QIB_7322_SBufExtraArrayCorErrLogC_pb {
  2328. pseudo_bit_t SBufExtraArrayCorErrCheckBit_27_0[28];
  2329. pseudo_bit_t SBufExtraArrayCorErrAddr_14_0[15];
  2330. pseudo_bit_t _unused_0[17];
  2331. pseudo_bit_t SBufExtraArrayCorErrAdd_3_0[4];
  2332. };
  2333. struct QIB_7322_SBufExtraArrayCorErrLogC {
  2334. PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufExtraArrayCorErrLogC_pb );
  2335. };
  2336. /* Default value: 0x0000000000000000 */
  2337. #define QIB_7322_SendPbcArrayCorErrLog_offset 0x00000ab0UL
  2338. struct QIB_7322_SendPbcArrayCorErrLog_pb {
  2339. pseudo_bit_t SendPbcArrayCorErrData_21_0[22];
  2340. pseudo_bit_t SendPbcArrayCorErrCheckBit_6_0[7];
  2341. pseudo_bit_t SendPbcArrayCorErrAddr_9_0[10];
  2342. pseudo_bit_t _unused_0[25];
  2343. };
  2344. struct QIB_7322_SendPbcArrayCorErrLog {
  2345. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendPbcArrayCorErrLog_pb );
  2346. };
  2347. /* Default value: 0x0000000000000000 */
  2348. #define QIB_7322_SBufVL15ArrayCorErrLogA_offset 0x00000ac0UL
  2349. struct QIB_7322_SBufVL15ArrayCorErrLogA_pb {
  2350. pseudo_bit_t SBufVL15ArrayCorErrData_63_0[64];
  2351. };
  2352. struct QIB_7322_SBufVL15ArrayCorErrLogA {
  2353. PSEUDO_BIT_STRUCT ( struct QIB_7322_SBufVL15ArrayCorErrLogA_pb );
  2354. };
  2355. /* Default value: 0x0000000000000000 */
  2356. #define QIB_7322_RcvAvailTimeOut0_offset 0x00000c00UL
  2357. struct QIB_7322_RcvAvailTimeOut0_pb {
  2358. pseudo_bit_t RcvAvailTOReload[16];
  2359. pseudo_bit_t RcvAvailTOCount[16];
  2360. pseudo_bit_t _unused_0[32];
  2361. };
  2362. struct QIB_7322_RcvAvailTimeOut0 {
  2363. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvAvailTimeOut0_pb );
  2364. };
  2365. /* Default value: 0x0000000000000000 */
  2366. #define QIB_7322_CntrRegBase_0_offset 0x00001028UL
  2367. /* Default value: 0x0000000000012000 */
  2368. #define QIB_7322_ErrMask_0_offset 0x00001080UL
  2369. struct QIB_7322_ErrMask_0_pb {
  2370. pseudo_bit_t RcvFormatErrMask[1];
  2371. pseudo_bit_t RcvVCRCErrMask[1];
  2372. pseudo_bit_t RcvICRCErrMask[1];
  2373. pseudo_bit_t RcvMinPktLenErrMask[1];
  2374. pseudo_bit_t RcvMaxPktLenErrMask[1];
  2375. pseudo_bit_t RcvLongPktLenErrMask[1];
  2376. pseudo_bit_t RcvShortPktLenErrMask[1];
  2377. pseudo_bit_t RcvUnexpectedCharErrMask[1];
  2378. pseudo_bit_t RcvUnsupportedVLErrMask[1];
  2379. pseudo_bit_t RcvEBPErrMask[1];
  2380. pseudo_bit_t RcvIBFlowErrMask[1];
  2381. pseudo_bit_t RcvBadVersionErrMask[1];
  2382. pseudo_bit_t _unused_0[2];
  2383. pseudo_bit_t RcvBadTidErrMask[1];
  2384. pseudo_bit_t RcvHdrLenErrMask[1];
  2385. pseudo_bit_t RcvHdrErrMask[1];
  2386. pseudo_bit_t RcvIBLostLinkErrMask[1];
  2387. pseudo_bit_t _unused_1[11];
  2388. pseudo_bit_t SendMinPktLenErrMask[1];
  2389. pseudo_bit_t SendMaxPktLenErrMask[1];
  2390. pseudo_bit_t SendUnderRunErrMask[1];
  2391. pseudo_bit_t SendPktLenErrMask[1];
  2392. pseudo_bit_t SendDroppedSmpPktErrMask[1];
  2393. pseudo_bit_t SendDroppedDataPktErrMask[1];
  2394. pseudo_bit_t _unused_2[1];
  2395. pseudo_bit_t SendUnexpectedPktNumErrMask[1];
  2396. pseudo_bit_t SendUnsupportedVLErrMask[1];
  2397. pseudo_bit_t SendBufMisuseErrMask[1];
  2398. pseudo_bit_t SDmaGenMismatchErrMask[1];
  2399. pseudo_bit_t SDmaOutOfBoundErrMask[1];
  2400. pseudo_bit_t SDmaTailOutOfBoundErrMask[1];
  2401. pseudo_bit_t SDmaBaseErrMask[1];
  2402. pseudo_bit_t SDma1stDescErrMask[1];
  2403. pseudo_bit_t SDmaRpyTagErrMask[1];
  2404. pseudo_bit_t SDmaDwEnErrMask[1];
  2405. pseudo_bit_t SDmaMissingDwErrMask[1];
  2406. pseudo_bit_t SDmaUnexpDataErrMask[1];
  2407. pseudo_bit_t SDmaDescAddrMisalignErrMask[1];
  2408. pseudo_bit_t SDmaHaltErrMask[1];
  2409. pseudo_bit_t _unused_3[4];
  2410. pseudo_bit_t VL15BufMisuseErrMask[1];
  2411. pseudo_bit_t _unused_4[2];
  2412. pseudo_bit_t SHeadersErrMask[1];
  2413. pseudo_bit_t IBStatusChangedMask[1];
  2414. pseudo_bit_t _unused_5[5];
  2415. };
  2416. struct QIB_7322_ErrMask_0 {
  2417. PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrMask_0_pb );
  2418. };
  2419. /* Default value: 0x0000000000000000 */
  2420. #define QIB_7322_ErrStatus_0_offset 0x00001088UL
  2421. struct QIB_7322_ErrStatus_0_pb {
  2422. pseudo_bit_t RcvFormatErr[1];
  2423. pseudo_bit_t RcvVCRCErr[1];
  2424. pseudo_bit_t RcvICRCErr[1];
  2425. pseudo_bit_t RcvMinPktLenErr[1];
  2426. pseudo_bit_t RcvMaxPktLenErr[1];
  2427. pseudo_bit_t RcvLongPktLenErr[1];
  2428. pseudo_bit_t RcvShortPktLenErr[1];
  2429. pseudo_bit_t RcvUnexpectedCharErr[1];
  2430. pseudo_bit_t RcvUnsupportedVLErr[1];
  2431. pseudo_bit_t RcvEBPErr[1];
  2432. pseudo_bit_t RcvIBFlowErr[1];
  2433. pseudo_bit_t RcvBadVersionErr[1];
  2434. pseudo_bit_t _unused_0[2];
  2435. pseudo_bit_t RcvBadTidErr[1];
  2436. pseudo_bit_t RcvHdrLenErr[1];
  2437. pseudo_bit_t RcvHdrErr[1];
  2438. pseudo_bit_t RcvIBLostLinkErr[1];
  2439. pseudo_bit_t _unused_1[11];
  2440. pseudo_bit_t SendMinPktLenErr[1];
  2441. pseudo_bit_t SendMaxPktLenErr[1];
  2442. pseudo_bit_t SendUnderRunErr[1];
  2443. pseudo_bit_t SendPktLenErr[1];
  2444. pseudo_bit_t SendDroppedSmpPktErr[1];
  2445. pseudo_bit_t SendDroppedDataPktErr[1];
  2446. pseudo_bit_t _unused_2[1];
  2447. pseudo_bit_t SendUnexpectedPktNumErr[1];
  2448. pseudo_bit_t SendUnsupportedVLErr[1];
  2449. pseudo_bit_t SendBufMisuseErr[1];
  2450. pseudo_bit_t SDmaGenMismatchErr[1];
  2451. pseudo_bit_t SDmaOutOfBoundErr[1];
  2452. pseudo_bit_t SDmaTailOutOfBoundErr[1];
  2453. pseudo_bit_t SDmaBaseErr[1];
  2454. pseudo_bit_t SDma1stDescErr[1];
  2455. pseudo_bit_t SDmaRpyTagErr[1];
  2456. pseudo_bit_t SDmaDwEnErr[1];
  2457. pseudo_bit_t SDmaMissingDwErr[1];
  2458. pseudo_bit_t SDmaUnexpDataErr[1];
  2459. pseudo_bit_t SDmaDescAddrMisalignErr[1];
  2460. pseudo_bit_t SDmaHaltErr[1];
  2461. pseudo_bit_t _unused_3[4];
  2462. pseudo_bit_t VL15BufMisuseErr[1];
  2463. pseudo_bit_t _unused_4[2];
  2464. pseudo_bit_t SHeadersErr[1];
  2465. pseudo_bit_t IBStatusChanged[1];
  2466. pseudo_bit_t _unused_5[5];
  2467. };
  2468. struct QIB_7322_ErrStatus_0 {
  2469. PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrStatus_0_pb );
  2470. };
  2471. /* Default value: 0x0000000000000000 */
  2472. #define QIB_7322_ErrClear_0_offset 0x00001090UL
  2473. struct QIB_7322_ErrClear_0_pb {
  2474. pseudo_bit_t RcvFormatErrClear[1];
  2475. pseudo_bit_t RcvVCRCErrClear[1];
  2476. pseudo_bit_t RcvICRCErrClear[1];
  2477. pseudo_bit_t RcvMinPktLenErrClear[1];
  2478. pseudo_bit_t RcvMaxPktLenErrClear[1];
  2479. pseudo_bit_t RcvLongPktLenErrClear[1];
  2480. pseudo_bit_t RcvShortPktLenErrClear[1];
  2481. pseudo_bit_t RcvUnexpectedCharErrClear[1];
  2482. pseudo_bit_t RcvUnsupportedVLErrClear[1];
  2483. pseudo_bit_t RcvEBPErrClear[1];
  2484. pseudo_bit_t RcvIBFlowErrClear[1];
  2485. pseudo_bit_t RcvBadVersionErrClear[1];
  2486. pseudo_bit_t _unused_0[2];
  2487. pseudo_bit_t RcvBadTidErrClear[1];
  2488. pseudo_bit_t RcvHdrLenErrClear[1];
  2489. pseudo_bit_t RcvHdrErrClear[1];
  2490. pseudo_bit_t RcvIBLostLinkErrClear[1];
  2491. pseudo_bit_t _unused_1[11];
  2492. pseudo_bit_t SendMinPktLenErrClear[1];
  2493. pseudo_bit_t SendMaxPktLenErrClear[1];
  2494. pseudo_bit_t SendUnderRunErrClear[1];
  2495. pseudo_bit_t SendPktLenErrClear[1];
  2496. pseudo_bit_t SendDroppedSmpPktErrClear[1];
  2497. pseudo_bit_t SendDroppedDataPktErrClear[1];
  2498. pseudo_bit_t _unused_2[1];
  2499. pseudo_bit_t SendUnexpectedPktNumErrClear[1];
  2500. pseudo_bit_t SendUnsupportedVLErrClear[1];
  2501. pseudo_bit_t SendBufMisuseErrClear[1];
  2502. pseudo_bit_t SDmaGenMismatchErrClear[1];
  2503. pseudo_bit_t SDmaOutOfBoundErrClear[1];
  2504. pseudo_bit_t SDmaTailOutOfBoundErrClear[1];
  2505. pseudo_bit_t SDmaBaseErrClear[1];
  2506. pseudo_bit_t SDma1stDescErrClear[1];
  2507. pseudo_bit_t SDmaRpyTagErrClear[1];
  2508. pseudo_bit_t SDmaDwEnErrClear[1];
  2509. pseudo_bit_t SDmaMissingDwErrClear[1];
  2510. pseudo_bit_t SDmaUnexpDataErrClear[1];
  2511. pseudo_bit_t SDmaDescAddrMisalignErrClear[1];
  2512. pseudo_bit_t SDmaHaltErrClear[1];
  2513. pseudo_bit_t _unused_3[4];
  2514. pseudo_bit_t VL15BufMisuseErrClear[1];
  2515. pseudo_bit_t _unused_4[2];
  2516. pseudo_bit_t SHeadersErrClear[1];
  2517. pseudo_bit_t IBStatusChangedClear[1];
  2518. pseudo_bit_t _unused_5[5];
  2519. };
  2520. struct QIB_7322_ErrClear_0 {
  2521. PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrClear_0_pb );
  2522. };
  2523. /* Default value: 0x0000000000000000 */
  2524. #define QIB_7322_TXEStatus_0_offset 0x000010b8UL
  2525. struct QIB_7322_TXEStatus_0_pb {
  2526. pseudo_bit_t LaFifoEmpty_VL0[1];
  2527. pseudo_bit_t LaFifoEmpty_VL1[1];
  2528. pseudo_bit_t LaFifoEmpty_VL2[1];
  2529. pseudo_bit_t LaFifoEmpty_VL3[1];
  2530. pseudo_bit_t LaFifoEmpty_VL4[1];
  2531. pseudo_bit_t LaFifoEmpty_VL5[1];
  2532. pseudo_bit_t LaFifoEmpty_VL6[1];
  2533. pseudo_bit_t LaFifoEmpty_VL7[1];
  2534. pseudo_bit_t _unused_0[7];
  2535. pseudo_bit_t LaFifoEmpty_VL15[1];
  2536. pseudo_bit_t _unused_1[14];
  2537. pseudo_bit_t RmFifoEmpty[1];
  2538. pseudo_bit_t TXE_IBC_Idle[1];
  2539. pseudo_bit_t _unused_2[32];
  2540. };
  2541. struct QIB_7322_TXEStatus_0 {
  2542. PSEUDO_BIT_STRUCT ( struct QIB_7322_TXEStatus_0_pb );
  2543. };
  2544. /* Default value: 0x0000000XC00080FF */
  2545. #define QIB_7322_RcvCtrl_0_offset 0x00001100UL
  2546. struct QIB_7322_RcvCtrl_0_pb {
  2547. pseudo_bit_t ContextEnableKernel[1];
  2548. pseudo_bit_t _unused_0[1];
  2549. pseudo_bit_t ContextEnableUser[16];
  2550. pseudo_bit_t _unused_1[21];
  2551. pseudo_bit_t RcvIBPortEnable[1];
  2552. pseudo_bit_t RcvQPMapEnable[1];
  2553. pseudo_bit_t RcvPartitionKeyDisable[1];
  2554. pseudo_bit_t RcvResetCredit[1];
  2555. pseudo_bit_t _unused_2[21];
  2556. };
  2557. struct QIB_7322_RcvCtrl_0 {
  2558. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvCtrl_0_pb );
  2559. };
  2560. /* Default value: 0x0000000000000000 */
  2561. #define QIB_7322_RcvBTHQP_0_offset 0x00001108UL
  2562. struct QIB_7322_RcvBTHQP_0_pb {
  2563. pseudo_bit_t RcvBTHQP[24];
  2564. pseudo_bit_t _unused_0[40];
  2565. };
  2566. struct QIB_7322_RcvBTHQP_0 {
  2567. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvBTHQP_0_pb );
  2568. };
  2569. /* Default value: 0x0000000000000000 */
  2570. #define QIB_7322_RcvQPMapTableA_0_offset 0x00001110UL
  2571. struct QIB_7322_RcvQPMapTableA_0_pb {
  2572. pseudo_bit_t RcvQPMapContext0[5];
  2573. pseudo_bit_t RcvQPMapContext1[5];
  2574. pseudo_bit_t RcvQPMapContext2[5];
  2575. pseudo_bit_t RcvQPMapContext3[5];
  2576. pseudo_bit_t RcvQPMapContext4[5];
  2577. pseudo_bit_t RcvQPMapContext5[5];
  2578. pseudo_bit_t _unused_0[34];
  2579. };
  2580. struct QIB_7322_RcvQPMapTableA_0 {
  2581. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableA_0_pb );
  2582. };
  2583. /* Default value: 0x0000000000000000 */
  2584. #define QIB_7322_RcvQPMapTableB_0_offset 0x00001118UL
  2585. struct QIB_7322_RcvQPMapTableB_0_pb {
  2586. pseudo_bit_t RcvQPMapContext6[5];
  2587. pseudo_bit_t RcvQPMapContext7[5];
  2588. pseudo_bit_t RcvQPMapContext8[5];
  2589. pseudo_bit_t RcvQPMapContext9[5];
  2590. pseudo_bit_t RcvQPMapContext10[5];
  2591. pseudo_bit_t RcvQPMapContext11[5];
  2592. pseudo_bit_t _unused_0[34];
  2593. };
  2594. struct QIB_7322_RcvQPMapTableB_0 {
  2595. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableB_0_pb );
  2596. };
  2597. /* Default value: 0x0000000000000000 */
  2598. #define QIB_7322_RcvQPMapTableC_0_offset 0x00001120UL
  2599. struct QIB_7322_RcvQPMapTableC_0_pb {
  2600. pseudo_bit_t RcvQPMapContext12[5];
  2601. pseudo_bit_t RcvQPMapContext13[5];
  2602. pseudo_bit_t RcvQPMapContext14[5];
  2603. pseudo_bit_t RcvQPMapContext15[5];
  2604. pseudo_bit_t RcvQPMapContext16[5];
  2605. pseudo_bit_t RcvQPMapContext17[5];
  2606. pseudo_bit_t _unused_0[34];
  2607. };
  2608. struct QIB_7322_RcvQPMapTableC_0 {
  2609. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableC_0_pb );
  2610. };
  2611. /* Default value: 0x0000000000000000 */
  2612. #define QIB_7322_RcvQPMapTableD_0_offset 0x00001128UL
  2613. struct QIB_7322_RcvQPMapTableD_0_pb {
  2614. pseudo_bit_t RcvQPMapContext18[5];
  2615. pseudo_bit_t RcvQPMapContext19[5];
  2616. pseudo_bit_t RcvQPMapContext20[5];
  2617. pseudo_bit_t RcvQPMapContext21[5];
  2618. pseudo_bit_t RcvQPMapContext22[5];
  2619. pseudo_bit_t RcvQPMapContext23[5];
  2620. pseudo_bit_t _unused_0[34];
  2621. };
  2622. struct QIB_7322_RcvQPMapTableD_0 {
  2623. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableD_0_pb );
  2624. };
  2625. /* Default value: 0x0000000000000000 */
  2626. #define QIB_7322_RcvQPMapTableE_0_offset 0x00001130UL
  2627. struct QIB_7322_RcvQPMapTableE_0_pb {
  2628. pseudo_bit_t RcvQPMapContext24[5];
  2629. pseudo_bit_t RcvQPMapContext25[5];
  2630. pseudo_bit_t RcvQPMapContext26[5];
  2631. pseudo_bit_t RcvQPMapContext27[5];
  2632. pseudo_bit_t RcvQPMapContext28[5];
  2633. pseudo_bit_t RcvQPMapContext29[5];
  2634. pseudo_bit_t _unused_0[34];
  2635. };
  2636. struct QIB_7322_RcvQPMapTableE_0 {
  2637. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableE_0_pb );
  2638. };
  2639. /* Default value: 0x0000000000000000 */
  2640. #define QIB_7322_RcvQPMapTableF_0_offset 0x00001138UL
  2641. struct QIB_7322_RcvQPMapTableF_0_pb {
  2642. pseudo_bit_t RcvQPMapContext30[5];
  2643. pseudo_bit_t RcvQPMapContext31[5];
  2644. pseudo_bit_t _unused_0[54];
  2645. };
  2646. struct QIB_7322_RcvQPMapTableF_0 {
  2647. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableF_0_pb );
  2648. };
  2649. /* Default value: 0x0000000000000000 */
  2650. #define QIB_7322_PSStat_0_offset 0x00001140UL
  2651. /* Default value: 0x0000000000000000 */
  2652. #define QIB_7322_PSStart_0_offset 0x00001148UL
  2653. /* Default value: 0x0000000000000000 */
  2654. #define QIB_7322_PSInterval_0_offset 0x00001150UL
  2655. /* Default value: 0x0000000000000000 */
  2656. #define QIB_7322_RcvStatus_0_offset 0x00001160UL
  2657. struct QIB_7322_RcvStatus_0_pb {
  2658. pseudo_bit_t RxPktInProgress[1];
  2659. pseudo_bit_t DmaeqBlockingContext[5];
  2660. pseudo_bit_t _unused_0[58];
  2661. };
  2662. struct QIB_7322_RcvStatus_0 {
  2663. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvStatus_0_pb );
  2664. };
  2665. /* Default value: 0x0000000000000000 */
  2666. #define QIB_7322_RcvPartitionKey_0_offset 0x00001168UL
  2667. /* Default value: 0x0000000000000000 */
  2668. #define QIB_7322_RcvQPMulticastContext_0_offset 0x00001170UL
  2669. struct QIB_7322_RcvQPMulticastContext_0_pb {
  2670. pseudo_bit_t RcvQpMcContext[5];
  2671. pseudo_bit_t _unused_0[59];
  2672. };
  2673. struct QIB_7322_RcvQPMulticastContext_0 {
  2674. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMulticastContext_0_pb );
  2675. };
  2676. /* Default value: 0x0000000000000000 */
  2677. #define QIB_7322_RcvPktLEDCnt_0_offset 0x00001178UL
  2678. struct QIB_7322_RcvPktLEDCnt_0_pb {
  2679. pseudo_bit_t OFFperiod[32];
  2680. pseudo_bit_t ONperiod[32];
  2681. };
  2682. struct QIB_7322_RcvPktLEDCnt_0 {
  2683. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvPktLEDCnt_0_pb );
  2684. };
  2685. /* Default value: 0x0000000000000000 */
  2686. #define QIB_7322_SendDmaIdleCnt_0_offset 0x00001180UL
  2687. struct QIB_7322_SendDmaIdleCnt_0_pb {
  2688. pseudo_bit_t SendDmaIdleCnt[16];
  2689. pseudo_bit_t _unused_0[48];
  2690. };
  2691. struct QIB_7322_SendDmaIdleCnt_0 {
  2692. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaIdleCnt_0_pb );
  2693. };
  2694. /* Default value: 0x0000000000000000 */
  2695. #define QIB_7322_SendDmaReloadCnt_0_offset 0x00001188UL
  2696. struct QIB_7322_SendDmaReloadCnt_0_pb {
  2697. pseudo_bit_t SendDmaReloadCnt[16];
  2698. pseudo_bit_t _unused_0[48];
  2699. };
  2700. struct QIB_7322_SendDmaReloadCnt_0 {
  2701. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaReloadCnt_0_pb );
  2702. };
  2703. /* Default value: 0x0000000000000000 */
  2704. #define QIB_7322_SendDmaDescCnt_0_offset 0x00001190UL
  2705. struct QIB_7322_SendDmaDescCnt_0_pb {
  2706. pseudo_bit_t SendDmaDescCnt[16];
  2707. pseudo_bit_t _unused_0[48];
  2708. };
  2709. struct QIB_7322_SendDmaDescCnt_0 {
  2710. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaDescCnt_0_pb );
  2711. };
  2712. /* Default value: 0x0000000000000000 */
  2713. #define QIB_7322_SendCtrl_0_offset 0x000011c0UL
  2714. struct QIB_7322_SendCtrl_0_pb {
  2715. pseudo_bit_t TxeAbortIbc[1];
  2716. pseudo_bit_t TxeBypassIbc[1];
  2717. pseudo_bit_t _unused_0[1];
  2718. pseudo_bit_t SendEnable[1];
  2719. pseudo_bit_t _unused_1[3];
  2720. pseudo_bit_t ForceCreditUpToDate[1];
  2721. pseudo_bit_t SDmaCleanup[1];
  2722. pseudo_bit_t SDmaIntEnable[1];
  2723. pseudo_bit_t SDmaSingleDescriptor[1];
  2724. pseudo_bit_t SDmaEnable[1];
  2725. pseudo_bit_t SDmaHalt[1];
  2726. pseudo_bit_t TxeDrainLaFifo[1];
  2727. pseudo_bit_t TxeDrainRmFifo[1];
  2728. pseudo_bit_t IBVLArbiterEn[1];
  2729. pseudo_bit_t _unused_2[48];
  2730. };
  2731. struct QIB_7322_SendCtrl_0 {
  2732. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendCtrl_0_pb );
  2733. };
  2734. /* Default value: 0x0000000000000000 */
  2735. #define QIB_7322_SendDmaBase_0_offset 0x000011f8UL
  2736. struct QIB_7322_SendDmaBase_0_pb {
  2737. pseudo_bit_t SendDmaBase[48];
  2738. pseudo_bit_t _unused_0[16];
  2739. };
  2740. struct QIB_7322_SendDmaBase_0 {
  2741. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaBase_0_pb );
  2742. };
  2743. /* Default value: 0x0000000000000000 */
  2744. #define QIB_7322_SendDmaLenGen_0_offset 0x00001200UL
  2745. struct QIB_7322_SendDmaLenGen_0_pb {
  2746. pseudo_bit_t Length[16];
  2747. pseudo_bit_t Generation[3];
  2748. pseudo_bit_t _unused_0[45];
  2749. };
  2750. struct QIB_7322_SendDmaLenGen_0 {
  2751. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaLenGen_0_pb );
  2752. };
  2753. /* Default value: 0x0000000000000000 */
  2754. #define QIB_7322_SendDmaTail_0_offset 0x00001208UL
  2755. struct QIB_7322_SendDmaTail_0_pb {
  2756. pseudo_bit_t SendDmaTail[16];
  2757. pseudo_bit_t _unused_0[48];
  2758. };
  2759. struct QIB_7322_SendDmaTail_0 {
  2760. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaTail_0_pb );
  2761. };
  2762. /* Default value: 0x0000000000000000 */
  2763. #define QIB_7322_SendDmaHead_0_offset 0x00001210UL
  2764. struct QIB_7322_SendDmaHead_0_pb {
  2765. pseudo_bit_t SendDmaHead[16];
  2766. pseudo_bit_t _unused_0[16];
  2767. pseudo_bit_t InternalSendDmaHead[16];
  2768. pseudo_bit_t _unused_1[16];
  2769. };
  2770. struct QIB_7322_SendDmaHead_0 {
  2771. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaHead_0_pb );
  2772. };
  2773. /* Default value: 0x0000000000000000 */
  2774. #define QIB_7322_SendDmaHeadAddr_0_offset 0x00001218UL
  2775. struct QIB_7322_SendDmaHeadAddr_0_pb {
  2776. pseudo_bit_t SendDmaHeadAddr[48];
  2777. pseudo_bit_t _unused_0[16];
  2778. };
  2779. struct QIB_7322_SendDmaHeadAddr_0 {
  2780. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaHeadAddr_0_pb );
  2781. };
  2782. /* Default value: 0x0000000000000000 */
  2783. #define QIB_7322_SendDmaBufMask0_0_offset 0x00001220UL
  2784. struct QIB_7322_SendDmaBufMask0_0_pb {
  2785. pseudo_bit_t BufMask_63_0[64];
  2786. };
  2787. struct QIB_7322_SendDmaBufMask0_0 {
  2788. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaBufMask0_0_pb );
  2789. };
  2790. /* Default value: 0x0000000000000000 */
  2791. #define QIB_7322_SendDmaStatus_0_offset 0x00001238UL
  2792. struct QIB_7322_SendDmaStatus_0_pb {
  2793. pseudo_bit_t SplFifoDescIndex[16];
  2794. pseudo_bit_t SplFifoBufNum[8];
  2795. pseudo_bit_t SplFifoFull[1];
  2796. pseudo_bit_t SplFifoEmpty[1];
  2797. pseudo_bit_t SplFifoDisarmed[1];
  2798. pseudo_bit_t SplFifoReadyToGo[1];
  2799. pseudo_bit_t ScbFetchDescFlag[1];
  2800. pseudo_bit_t ScbEntryValid[1];
  2801. pseudo_bit_t ScbEmpty[1];
  2802. pseudo_bit_t ScbFull[1];
  2803. pseudo_bit_t RpyTag_7_0[8];
  2804. pseudo_bit_t RpyLowAddr_6_0[7];
  2805. pseudo_bit_t ScbDescIndex_13_0[14];
  2806. pseudo_bit_t InternalSDmaHalt[1];
  2807. pseudo_bit_t HaltInProg[1];
  2808. pseudo_bit_t ScoreBoardDrainInProg[1];
  2809. };
  2810. struct QIB_7322_SendDmaStatus_0 {
  2811. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaStatus_0_pb );
  2812. };
  2813. /* Default value: 0x0000000042000000 */
  2814. #define QIB_7322_SendDmaPriorityThld_0_offset 0x00001258UL
  2815. struct QIB_7322_SendDmaPriorityThld_0_pb {
  2816. pseudo_bit_t PriorityThreshold[4];
  2817. pseudo_bit_t _unused_0[60];
  2818. };
  2819. struct QIB_7322_SendDmaPriorityThld_0 {
  2820. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaPriorityThld_0_pb );
  2821. };
  2822. /* Default value: 0x0000000000000000 */
  2823. #define QIB_7322_SendHdrErrSymptom_0_offset 0x00001260UL
  2824. struct QIB_7322_SendHdrErrSymptom_0_pb {
  2825. pseudo_bit_t PacketTooSmall[1];
  2826. pseudo_bit_t RawIPV6[1];
  2827. pseudo_bit_t SLIDFail[1];
  2828. pseudo_bit_t QPFail[1];
  2829. pseudo_bit_t PkeyFail[1];
  2830. pseudo_bit_t GRHFail[1];
  2831. pseudo_bit_t NonKeyPacket[1];
  2832. pseudo_bit_t _unused_0[57];
  2833. };
  2834. struct QIB_7322_SendHdrErrSymptom_0 {
  2835. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendHdrErrSymptom_0_pb );
  2836. };
  2837. /* Default value: 0x0000000000000000 */
  2838. #define QIB_7322_RxCreditVL0_0_offset 0x00001280UL
  2839. struct QIB_7322_RxCreditVL0_0_pb {
  2840. pseudo_bit_t RxMaxCreditVL[12];
  2841. pseudo_bit_t _unused_0[4];
  2842. pseudo_bit_t RxBufrConsumedVL[12];
  2843. pseudo_bit_t _unused_1[36];
  2844. };
  2845. struct QIB_7322_RxCreditVL0_0 {
  2846. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxCreditVL0_0_pb );
  2847. };
  2848. /* Default value: 0x0000000000000000 */
  2849. #define QIB_7322_SendDmaBufUsed0_0_offset 0x00001480UL
  2850. struct QIB_7322_SendDmaBufUsed0_0_pb {
  2851. pseudo_bit_t BufUsed_63_0[64];
  2852. };
  2853. struct QIB_7322_SendDmaBufUsed0_0 {
  2854. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaBufUsed0_0_pb );
  2855. };
  2856. /* Default value: 0x0000000000000000 */
  2857. #define QIB_7322_SendDmaReqTagUsed_0_offset 0x00001498UL
  2858. struct QIB_7322_SendDmaReqTagUsed_0_pb {
  2859. pseudo_bit_t ReqTagUsed_7_0[8];
  2860. pseudo_bit_t _unused_0[56];
  2861. };
  2862. struct QIB_7322_SendDmaReqTagUsed_0 {
  2863. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaReqTagUsed_0_pb );
  2864. };
  2865. /* Default value: 0x0000000000000000 */
  2866. #define QIB_7322_SendCheckControl_0_offset 0x000014a8UL
  2867. struct QIB_7322_SendCheckControl_0_pb {
  2868. pseudo_bit_t PacketTooSmall_En[1];
  2869. pseudo_bit_t RawIPV6_En[1];
  2870. pseudo_bit_t SLID_En[1];
  2871. pseudo_bit_t BTHQP_En[1];
  2872. pseudo_bit_t PKey_En[1];
  2873. pseudo_bit_t _unused_0[59];
  2874. };
  2875. struct QIB_7322_SendCheckControl_0 {
  2876. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendCheckControl_0_pb );
  2877. };
  2878. /* Default value: 0x0000000000000000 */
  2879. #define QIB_7322_SendIBSLIDMask_0_offset 0x000014b0UL
  2880. struct QIB_7322_SendIBSLIDMask_0_pb {
  2881. pseudo_bit_t SendIBSLIDMask_15_0[16];
  2882. pseudo_bit_t _unused_0[48];
  2883. };
  2884. struct QIB_7322_SendIBSLIDMask_0 {
  2885. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendIBSLIDMask_0_pb );
  2886. };
  2887. /* Default value: 0x0000000000000000 */
  2888. #define QIB_7322_SendIBSLIDAssign_0_offset 0x000014b8UL
  2889. struct QIB_7322_SendIBSLIDAssign_0_pb {
  2890. pseudo_bit_t SendIBSLIDAssign_15_0[16];
  2891. pseudo_bit_t _unused_0[48];
  2892. };
  2893. struct QIB_7322_SendIBSLIDAssign_0 {
  2894. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendIBSLIDAssign_0_pb );
  2895. };
  2896. /* Default value: 0x0000000000000000 */
  2897. #define QIB_7322_IBCStatusA_0_offset 0x00001540UL
  2898. struct QIB_7322_IBCStatusA_0_pb {
  2899. pseudo_bit_t LinkTrainingState[5];
  2900. pseudo_bit_t LinkState[3];
  2901. pseudo_bit_t LinkSpeedActive[1];
  2902. pseudo_bit_t LinkWidthActive[1];
  2903. pseudo_bit_t DDS_RXEQ_FAIL[1];
  2904. pseudo_bit_t _unused_0[1];
  2905. pseudo_bit_t IBRxLaneReversed[1];
  2906. pseudo_bit_t IBTxLaneReversed[1];
  2907. pseudo_bit_t ScrambleEn[1];
  2908. pseudo_bit_t ScrambleCapRemote[1];
  2909. pseudo_bit_t _unused_1[13];
  2910. pseudo_bit_t LinkSpeedQDR[1];
  2911. pseudo_bit_t TxReady[1];
  2912. pseudo_bit_t _unused_2[1];
  2913. pseudo_bit_t TxCreditOk_VL0[1];
  2914. pseudo_bit_t TxCreditOk_VL1[1];
  2915. pseudo_bit_t TxCreditOk_VL2[1];
  2916. pseudo_bit_t TxCreditOk_VL3[1];
  2917. pseudo_bit_t TxCreditOk_VL4[1];
  2918. pseudo_bit_t TxCreditOk_VL5[1];
  2919. pseudo_bit_t TxCreditOk_VL6[1];
  2920. pseudo_bit_t TxCreditOk_VL7[1];
  2921. pseudo_bit_t _unused_3[24];
  2922. };
  2923. struct QIB_7322_IBCStatusA_0 {
  2924. PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCStatusA_0_pb );
  2925. };
  2926. /* Default value: 0x0000000000000X02 */
  2927. #define QIB_7322_IBCStatusB_0_offset 0x00001548UL
  2928. struct QIB_7322_IBCStatusB_0_pb {
  2929. pseudo_bit_t LinkRoundTripLatency[26];
  2930. pseudo_bit_t ReqDDSLocalFromRmt[4];
  2931. pseudo_bit_t RxEqLocalDevice[2];
  2932. pseudo_bit_t heartbeat_crosstalk[4];
  2933. pseudo_bit_t heartbeat_timed_out[1];
  2934. pseudo_bit_t ibsd_adaptation_timer_started[1];
  2935. pseudo_bit_t ibsd_adaptation_timer_reached_threshold[1];
  2936. pseudo_bit_t ibsd_adaptation_timer_debug[1];
  2937. pseudo_bit_t _unused_0[24];
  2938. };
  2939. struct QIB_7322_IBCStatusB_0 {
  2940. PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCStatusB_0_pb );
  2941. };
  2942. /* Default value: 0x00000000XXXXXXXX */
  2943. #define QIB_7322_IBCCtrlA_0_offset 0x00001560UL
  2944. struct QIB_7322_IBCCtrlA_0_pb {
  2945. pseudo_bit_t FlowCtrlPeriod[8];
  2946. pseudo_bit_t FlowCtrlWaterMark[8];
  2947. pseudo_bit_t LinkInitCmd[3];
  2948. pseudo_bit_t LinkCmd[2];
  2949. pseudo_bit_t MaxPktLen[11];
  2950. pseudo_bit_t PhyerrThreshold[4];
  2951. pseudo_bit_t OverrunThreshold[4];
  2952. pseudo_bit_t _unused_0[8];
  2953. pseudo_bit_t NumVLane[3];
  2954. pseudo_bit_t _unused_1[9];
  2955. pseudo_bit_t IBStatIntReductionEn[1];
  2956. pseudo_bit_t IBLinkEn[1];
  2957. pseudo_bit_t LinkDownDefaultState[1];
  2958. pseudo_bit_t Loopback[1];
  2959. };
  2960. struct QIB_7322_IBCCtrlA_0 {
  2961. PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCCtrlA_0_pb );
  2962. };
  2963. /* Default value: 0x0000000000000000 */
  2964. #define QIB_7322_IBCCtrlB_0_offset 0x00001568UL
  2965. struct QIB_7322_IBCCtrlB_0_pb {
  2966. pseudo_bit_t IB_ENHANCED_MODE[1];
  2967. pseudo_bit_t SD_SPEED[1];
  2968. pseudo_bit_t SD_SPEED_SDR[1];
  2969. pseudo_bit_t SD_SPEED_DDR[1];
  2970. pseudo_bit_t SD_SPEED_QDR[1];
  2971. pseudo_bit_t IB_NUM_CHANNELS[2];
  2972. pseudo_bit_t IB_POLARITY_REV_SUPP[1];
  2973. pseudo_bit_t IB_LANE_REV_SUPPORTED[1];
  2974. pseudo_bit_t SD_RX_EQUAL_ENABLE[1];
  2975. pseudo_bit_t SD_ADD_ENB[1];
  2976. pseudo_bit_t SD_DDSV[1];
  2977. pseudo_bit_t SD_DDS[4];
  2978. pseudo_bit_t HRTBT_ENB[1];
  2979. pseudo_bit_t HRTBT_AUTO[1];
  2980. pseudo_bit_t HRTBT_PORT[8];
  2981. pseudo_bit_t HRTBT_REQ[1];
  2982. pseudo_bit_t IB_ENABLE_FILT_DPKT[1];
  2983. pseudo_bit_t _unused_0[4];
  2984. pseudo_bit_t IB_DLID[16];
  2985. pseudo_bit_t IB_DLID_MASK[16];
  2986. };
  2987. struct QIB_7322_IBCCtrlB_0 {
  2988. PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCCtrlB_0_pb );
  2989. };
  2990. /* Default value: 0x00000000000305FF */
  2991. #define QIB_7322_IBCCtrlC_0_offset 0x00001570UL
  2992. struct QIB_7322_IBCCtrlC_0_pb {
  2993. pseudo_bit_t IB_FRONT_PORCH[5];
  2994. pseudo_bit_t IB_BACK_PORCH[5];
  2995. pseudo_bit_t _unused_0[54];
  2996. };
  2997. struct QIB_7322_IBCCtrlC_0 {
  2998. PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCCtrlC_0_pb );
  2999. };
  3000. /* Default value: 0x0000000000000301 */
  3001. #define QIB_7322_HRTBT_GUID_0_offset 0x00001588UL
  3002. /* Default value: 0x0000000000000000 */
  3003. #define QIB_7322_IB_SDTEST_IF_TX_0_offset 0x00001590UL
  3004. struct QIB_7322_IB_SDTEST_IF_TX_0_pb {
  3005. pseudo_bit_t TS_T_TX_VALID[1];
  3006. pseudo_bit_t TS_3_TX_VALID[1];
  3007. pseudo_bit_t VL_CAP[2];
  3008. pseudo_bit_t CREDIT_CHANGE[1];
  3009. pseudo_bit_t _unused_0[6];
  3010. pseudo_bit_t TS_TX_OPCODE[2];
  3011. pseudo_bit_t TS_TX_SPEED[3];
  3012. pseudo_bit_t _unused_1[16];
  3013. pseudo_bit_t TS_TX_TX_CFG[16];
  3014. pseudo_bit_t TS_TX_RX_CFG[16];
  3015. };
  3016. struct QIB_7322_IB_SDTEST_IF_TX_0 {
  3017. PSEUDO_BIT_STRUCT ( struct QIB_7322_IB_SDTEST_IF_TX_0_pb );
  3018. };
  3019. /* Default value: 0x0000000000000000 */
  3020. #define QIB_7322_IB_SDTEST_IF_RX_0_offset 0x00001598UL
  3021. struct QIB_7322_IB_SDTEST_IF_RX_0_pb {
  3022. pseudo_bit_t TS_T_RX_VALID[1];
  3023. pseudo_bit_t TS_3_RX_VALID[1];
  3024. pseudo_bit_t _unused_0[14];
  3025. pseudo_bit_t TS_RX_A[8];
  3026. pseudo_bit_t TS_RX_B[8];
  3027. pseudo_bit_t TS_RX_TX_CFG[16];
  3028. pseudo_bit_t TS_RX_RX_CFG[16];
  3029. };
  3030. struct QIB_7322_IB_SDTEST_IF_RX_0 {
  3031. PSEUDO_BIT_STRUCT ( struct QIB_7322_IB_SDTEST_IF_RX_0_pb );
  3032. };
  3033. /* Default value: 0x0000000000000000 */
  3034. #define QIB_7322_IBNCModeCtrl_0_offset 0x000015b8UL
  3035. struct QIB_7322_IBNCModeCtrl_0_pb {
  3036. pseudo_bit_t TSMEnable_send_TS1[1];
  3037. pseudo_bit_t TSMEnable_send_TS2[1];
  3038. pseudo_bit_t TSMEnable_ignore_TSM_on_rx[1];
  3039. pseudo_bit_t _unused_0[5];
  3040. pseudo_bit_t TSMCode_TS1[9];
  3041. pseudo_bit_t TSMCode_TS2[9];
  3042. pseudo_bit_t _unused_1[6];
  3043. pseudo_bit_t ScrambleCapLocal[1];
  3044. pseudo_bit_t ScrambleCapRemoteMask[1];
  3045. pseudo_bit_t ScrambleCapRemoteForce[1];
  3046. pseudo_bit_t _unused_2[29];
  3047. };
  3048. struct QIB_7322_IBNCModeCtrl_0 {
  3049. PSEUDO_BIT_STRUCT ( struct QIB_7322_IBNCModeCtrl_0_pb );
  3050. };
  3051. /* Default value: 0x0000000000000000 */
  3052. #define QIB_7322_IBSerdesStatus_0_offset 0x000015d0UL
  3053. /* Default value: 0x0000000000000000 */
  3054. #define QIB_7322_IBPCSConfig_0_offset 0x000015d8UL
  3055. struct QIB_7322_IBPCSConfig_0_pb {
  3056. pseudo_bit_t tx_rx_reset[1];
  3057. pseudo_bit_t xcv_treset[1];
  3058. pseudo_bit_t xcv_rreset[1];
  3059. pseudo_bit_t _unused_0[6];
  3060. pseudo_bit_t link_sync_mask[10];
  3061. pseudo_bit_t _unused_1[45];
  3062. };
  3063. struct QIB_7322_IBPCSConfig_0 {
  3064. PSEUDO_BIT_STRUCT ( struct QIB_7322_IBPCSConfig_0_pb );
  3065. };
  3066. /* Default value: 0x0000000000000007 */
  3067. #define QIB_7322_IBSerdesCtrl_0_offset 0x000015e0UL
  3068. struct QIB_7322_IBSerdesCtrl_0_pb {
  3069. pseudo_bit_t CMODE[7];
  3070. pseudo_bit_t _unused_0[1];
  3071. pseudo_bit_t TXIDLE[1];
  3072. pseudo_bit_t RXPD[1];
  3073. pseudo_bit_t TXPD[1];
  3074. pseudo_bit_t PLLPD[1];
  3075. pseudo_bit_t LPEN[1];
  3076. pseudo_bit_t RXLOSEN[1];
  3077. pseudo_bit_t _unused_1[1];
  3078. pseudo_bit_t IB_LAT_MODE[1];
  3079. pseudo_bit_t CGMODE[4];
  3080. pseudo_bit_t CHANNEL_RESET_N[4];
  3081. pseudo_bit_t DISABLE_RXLATOFF_SDR[1];
  3082. pseudo_bit_t DISABLE_RXLATOFF_DDR[1];
  3083. pseudo_bit_t DISABLE_RXLATOFF_QDR[1];
  3084. pseudo_bit_t _unused_2[37];
  3085. };
  3086. struct QIB_7322_IBSerdesCtrl_0 {
  3087. PSEUDO_BIT_STRUCT ( struct QIB_7322_IBSerdesCtrl_0_pb );
  3088. };
  3089. /* Default value: 0x0000000000FFA00F */
  3090. #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_offset 0x00001600UL
  3091. struct QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_pb {
  3092. pseudo_bit_t txcn1_ena[3];
  3093. pseudo_bit_t txcn1_xtra_emph0[2];
  3094. pseudo_bit_t txcp1_ena[4];
  3095. pseudo_bit_t txc0_ena[5];
  3096. pseudo_bit_t txampcntl_d2a[4];
  3097. pseudo_bit_t _unused_0[12];
  3098. pseudo_bit_t reset_tx_deemphasis_override[1];
  3099. pseudo_bit_t tx_override_deemphasis_select[1];
  3100. pseudo_bit_t _unused_1[32];
  3101. };
  3102. struct QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0 {
  3103. PSEUDO_BIT_STRUCT ( struct QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_0_pb );
  3104. };
  3105. /* Default value: 0x0000000000000000 */
  3106. #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_offset 0x00001640UL
  3107. struct QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_pb {
  3108. pseudo_bit_t static_disable_rxenadfe_sdr_ch0[8];
  3109. pseudo_bit_t static_disable_rxenadfe_sdr_ch1[8];
  3110. pseudo_bit_t static_disable_rxenadfe_sdr_ch2[8];
  3111. pseudo_bit_t static_disable_rxenadfe_sdr_ch3[8];
  3112. pseudo_bit_t static_disable_rxenale_sdr_ch0[1];
  3113. pseudo_bit_t static_disable_rxenale_sdr_ch1[1];
  3114. pseudo_bit_t static_disable_rxenale_sdr_ch2[1];
  3115. pseudo_bit_t static_disable_rxenale_sdr_ch3[1];
  3116. pseudo_bit_t static_disable_rxenagain_sdr_ch0[1];
  3117. pseudo_bit_t static_disable_rxenagain_sdr_ch1[1];
  3118. pseudo_bit_t static_disable_rxenagain_sdr_ch2[1];
  3119. pseudo_bit_t static_disable_rxenagain_sdr_ch3[1];
  3120. pseudo_bit_t _unused_0[24];
  3121. };
  3122. struct QIB_7322_ADAPT_DISABLE_STATIC_SDR_0 {
  3123. PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_STATIC_SDR_0_pb );
  3124. };
  3125. /* Default value: 0x0000000000000000 */
  3126. #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_offset 0x00001648UL
  3127. struct QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_pb {
  3128. pseudo_bit_t dyn_disable_rxenadfe_sdr_ch0[8];
  3129. pseudo_bit_t dyn_disable_rxenadfe_sdr_ch1[8];
  3130. pseudo_bit_t dyn_disable_rxenadfe_sdr_ch2[8];
  3131. pseudo_bit_t dyn_disable_rxenadfe_sdr_ch3[8];
  3132. pseudo_bit_t dyn_disable_rxenale_sdr_ch0[1];
  3133. pseudo_bit_t dyn_disable_rxenale_sdr_ch1[1];
  3134. pseudo_bit_t dyn_disable_rxenale_sdr_ch2[1];
  3135. pseudo_bit_t dyn_disable_rxenale_sdr_ch3[1];
  3136. pseudo_bit_t dyn_disable_rxenagain_sdr_ch0[1];
  3137. pseudo_bit_t dyn_disable_rxenagain_sdr_ch1[1];
  3138. pseudo_bit_t dyn_disable_rxenagain_sdr_ch2[1];
  3139. pseudo_bit_t dyn_disable_rxenagain_sdr_ch3[1];
  3140. pseudo_bit_t _unused_0[24];
  3141. };
  3142. struct QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0 {
  3143. PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_0_pb );
  3144. };
  3145. /* Default value: 0x0000000000000000 */
  3146. #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_offset 0x00001650UL
  3147. struct QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_pb {
  3148. pseudo_bit_t static_disable_rxenadfe_ddr_ch0[8];
  3149. pseudo_bit_t static_disable_rxenadfe_ddr_ch1[8];
  3150. pseudo_bit_t static_disable_rxenadfe_ddr_ch2[8];
  3151. pseudo_bit_t static_disable_rxenadfe_ddr_ch3[8];
  3152. pseudo_bit_t static_disable_rxenale_ddr_ch0[1];
  3153. pseudo_bit_t static_disable_rxenale_ddr_ch1[1];
  3154. pseudo_bit_t static_disable_rxenale_ddr_ch2[1];
  3155. pseudo_bit_t static_disable_rxenale_ddr_ch3[1];
  3156. pseudo_bit_t static_disable_rxenagain_ddr_ch0[1];
  3157. pseudo_bit_t static_disable_rxenagain_ddr_ch1[1];
  3158. pseudo_bit_t static_disable_rxenagain_ddr_ch2[1];
  3159. pseudo_bit_t static_disable_rxenagain_ddr_ch3[1];
  3160. pseudo_bit_t _unused_0[24];
  3161. };
  3162. struct QIB_7322_ADAPT_DISABLE_STATIC_DDR_0 {
  3163. PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_STATIC_DDR_0_pb );
  3164. };
  3165. /* Default value: 0x0000000000000000 */
  3166. #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_offset 0x00001658UL
  3167. struct QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_pb {
  3168. pseudo_bit_t dyn_disable_rxenadfe_ddr_ch0[8];
  3169. pseudo_bit_t dyn_disable_rxenadfe_ddr_ch1[8];
  3170. pseudo_bit_t dyn_disable_rxenadfe_ddr_ch2[8];
  3171. pseudo_bit_t dyn_disable_rxenadfe_ddr_ch3[8];
  3172. pseudo_bit_t dyn_disable_rxenale_ddr_ch0[1];
  3173. pseudo_bit_t dyn_disable_rxenale_ddr_ch1[1];
  3174. pseudo_bit_t dyn_disable_rxenale_ddr_ch2[1];
  3175. pseudo_bit_t dyn_disable_rxenale_ddr_ch3[1];
  3176. pseudo_bit_t dyn_disable_rxenagain_ddr_ch0[1];
  3177. pseudo_bit_t dyn_disable_rxenagain_ddr_ch1[1];
  3178. pseudo_bit_t dyn_disable_rxenagain_ddr_ch2[1];
  3179. pseudo_bit_t dyn_disable_rxenagain_ddr_ch3[1];
  3180. pseudo_bit_t _unused_0[24];
  3181. };
  3182. struct QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0 {
  3183. PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_0_pb );
  3184. };
  3185. /* Default value: 0x0000000000000000 */
  3186. #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_offset 0x00001660UL
  3187. struct QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_pb {
  3188. pseudo_bit_t static_disable_rxenadfe_qdr_ch0[8];
  3189. pseudo_bit_t static_disable_rxenadfe_qdr_ch1[8];
  3190. pseudo_bit_t static_disable_rxenadfe_qdr_ch2[8];
  3191. pseudo_bit_t static_disable_rxenadfe_qdr_ch3[8];
  3192. pseudo_bit_t static_disable_rxenale_qdr_ch0[1];
  3193. pseudo_bit_t static_disable_rxenale_qdr_ch1[1];
  3194. pseudo_bit_t static_disable_rxenale_qdr_ch2[1];
  3195. pseudo_bit_t static_disable_rxenale_qdr_ch3[1];
  3196. pseudo_bit_t static_disable_rxenagain_qdr_ch0[1];
  3197. pseudo_bit_t static_disable_rxenagain_qdr_ch1[1];
  3198. pseudo_bit_t static_disable_rxenagain_qdr_ch2[1];
  3199. pseudo_bit_t static_disable_rxenagain_qdr_ch3[1];
  3200. pseudo_bit_t _unused_0[24];
  3201. };
  3202. struct QIB_7322_ADAPT_DISABLE_STATIC_QDR_0 {
  3203. PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_STATIC_QDR_0_pb );
  3204. };
  3205. /* Default value: 0x0000000000000000 */
  3206. #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_offset 0x00001668UL
  3207. struct QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_pb {
  3208. pseudo_bit_t dyn_disable_rxenadfe_qdr_ch0[8];
  3209. pseudo_bit_t dyn_disable_rxenadfe_qdr_ch1[8];
  3210. pseudo_bit_t dyn_disable_rxenadfe_qdr_ch2[8];
  3211. pseudo_bit_t dyn_disable_rxenadfe_qdr_ch3[8];
  3212. pseudo_bit_t dyn_disable_rxenale_qdr_ch0[1];
  3213. pseudo_bit_t dyn_disable_rxenale_qdr_ch1[1];
  3214. pseudo_bit_t dyn_disable_rxenale_qdr_ch2[1];
  3215. pseudo_bit_t dyn_disable_rxenale_qdr_ch3[1];
  3216. pseudo_bit_t dyn_disable_rxenagain_qdr_ch0[1];
  3217. pseudo_bit_t dyn_disable_rxenagain_qdr_ch1[1];
  3218. pseudo_bit_t dyn_disable_rxenagain_qdr_ch2[1];
  3219. pseudo_bit_t dyn_disable_rxenagain_qdr_ch3[1];
  3220. pseudo_bit_t _unused_0[24];
  3221. };
  3222. struct QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0 {
  3223. PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_0_pb );
  3224. };
  3225. /* Default value: 0x0000000000000000 */
  3226. #define QIB_7322_ADAPT_DISABLE_TIMER_THRESHOLD_0_offset 0x00001670UL
  3227. /* Default value: 0x0000000000000000 */
  3228. #define QIB_7322_RxBufrUnCorErrLogA_0_offset 0x00001800UL
  3229. struct QIB_7322_RxBufrUnCorErrLogA_0_pb {
  3230. pseudo_bit_t RxBufrUnCorErrData_63_0[64];
  3231. };
  3232. struct QIB_7322_RxBufrUnCorErrLogA_0 {
  3233. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrUnCorErrLogA_0_pb );
  3234. };
  3235. /* Default value: 0x0000000000000000 */
  3236. #define QIB_7322_RxBufrUnCorErrLogB_0_offset 0x00001808UL
  3237. struct QIB_7322_RxBufrUnCorErrLogB_0_pb {
  3238. pseudo_bit_t RxBufrUnCorErrData_127_64[64];
  3239. };
  3240. struct QIB_7322_RxBufrUnCorErrLogB_0 {
  3241. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrUnCorErrLogB_0_pb );
  3242. };
  3243. /* Default value: 0x0000000000000000 */
  3244. #define QIB_7322_RxBufrUnCorErrLogC_0_offset 0x00001810UL
  3245. struct QIB_7322_RxBufrUnCorErrLogC_0_pb {
  3246. pseudo_bit_t RxBufrUnCorErrData_191_128[64];
  3247. };
  3248. struct QIB_7322_RxBufrUnCorErrLogC_0 {
  3249. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrUnCorErrLogC_0_pb );
  3250. };
  3251. /* Default value: 0x0000000000000000 */
  3252. #define QIB_7322_RxBufrUnCorErrLogD_0_offset 0x00001818UL
  3253. struct QIB_7322_RxBufrUnCorErrLogD_0_pb {
  3254. pseudo_bit_t RxBufrUnCorErrData_255_192[64];
  3255. };
  3256. struct QIB_7322_RxBufrUnCorErrLogD_0 {
  3257. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrUnCorErrLogD_0_pb );
  3258. };
  3259. /* Default value: 0x0000000000000000 */
  3260. #define QIB_7322_RxBufrUnCorErrLogE_0_offset 0x00001820UL
  3261. struct QIB_7322_RxBufrUnCorErrLogE_0_pb {
  3262. pseudo_bit_t RxBufrUnCorErrData_258_256[3];
  3263. pseudo_bit_t RxBufrUnCorErrCheckBit_36_0[37];
  3264. pseudo_bit_t RxBufrUnCorErrAddr_15_0[16];
  3265. pseudo_bit_t _unused_0[8];
  3266. };
  3267. struct QIB_7322_RxBufrUnCorErrLogE_0 {
  3268. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrUnCorErrLogE_0_pb );
  3269. };
  3270. /* Default value: 0x0000000000000000 */
  3271. #define QIB_7322_RxFlagUnCorErrLogA_0_offset 0x00001828UL
  3272. struct QIB_7322_RxFlagUnCorErrLogA_0_pb {
  3273. pseudo_bit_t RxFlagUnCorErrData_63_0[64];
  3274. };
  3275. struct QIB_7322_RxFlagUnCorErrLogA_0 {
  3276. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxFlagUnCorErrLogA_0_pb );
  3277. };
  3278. /* Default value: 0x0000000000000000 */
  3279. #define QIB_7322_RxFlagUnCorErrLogB_0_offset 0x00001830UL
  3280. struct QIB_7322_RxFlagUnCorErrLogB_0_pb {
  3281. pseudo_bit_t RxFlagUnCorErrCheckBit_7_0[8];
  3282. pseudo_bit_t RxFlagUnCorErrAddr_12_0[13];
  3283. pseudo_bit_t _unused_0[43];
  3284. };
  3285. struct QIB_7322_RxFlagUnCorErrLogB_0 {
  3286. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxFlagUnCorErrLogB_0_pb );
  3287. };
  3288. /* Default value: 0x0000000000000000 */
  3289. #define QIB_7322_RxLkupiqUnCorErrLogA_0_offset 0x00001840UL
  3290. struct QIB_7322_RxLkupiqUnCorErrLogA_0_pb {
  3291. pseudo_bit_t RxLkupiqUnCorErrData_45_0[46];
  3292. pseudo_bit_t RxLkupiqUnCorErrCheckBit_7_0[8];
  3293. pseudo_bit_t _unused_0[10];
  3294. };
  3295. struct QIB_7322_RxLkupiqUnCorErrLogA_0 {
  3296. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxLkupiqUnCorErrLogA_0_pb );
  3297. };
  3298. /* Default value: 0x0000000000000000 */
  3299. #define QIB_7322_RxLkupiqUnCorErrLogB_0_offset 0x00001848UL
  3300. struct QIB_7322_RxLkupiqUnCorErrLogB_0_pb {
  3301. pseudo_bit_t RxLkupiqUnCorErrAddr_12_0[13];
  3302. pseudo_bit_t _unused_0[51];
  3303. };
  3304. struct QIB_7322_RxLkupiqUnCorErrLogB_0 {
  3305. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxLkupiqUnCorErrLogB_0_pb );
  3306. };
  3307. /* Default value: 0x0000000000000000 */
  3308. #define QIB_7322_RxHdrFifoUnCorErrLogA_0_offset 0x00001850UL
  3309. struct QIB_7322_RxHdrFifoUnCorErrLogA_0_pb {
  3310. pseudo_bit_t RxHdrFifoUnCorErrData_63_0[64];
  3311. };
  3312. struct QIB_7322_RxHdrFifoUnCorErrLogA_0 {
  3313. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoUnCorErrLogA_0_pb );
  3314. };
  3315. /* Default value: 0x0000000000000000 */
  3316. #define QIB_7322_RxHdrFifoUnCorErrLogB_0_offset 0x00001858UL
  3317. struct QIB_7322_RxHdrFifoUnCorErrLogB_0_pb {
  3318. pseudo_bit_t RxHdrFifoUnCorErrData_127_64[64];
  3319. };
  3320. struct QIB_7322_RxHdrFifoUnCorErrLogB_0 {
  3321. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoUnCorErrLogB_0_pb );
  3322. };
  3323. /* Default value: 0x0000000000000000 */
  3324. #define QIB_7322_RxHdrFifoUnCorErrLogC_0_offset 0x00001860UL
  3325. struct QIB_7322_RxHdrFifoUnCorErrLogC_0_pb {
  3326. pseudo_bit_t RxHdrFifoUnCorErrCheckBit_15_0[16];
  3327. pseudo_bit_t RxHdrFifoUnCorErrAddr_10_0[11];
  3328. pseudo_bit_t _unused_0[37];
  3329. };
  3330. struct QIB_7322_RxHdrFifoUnCorErrLogC_0 {
  3331. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoUnCorErrLogC_0_pb );
  3332. };
  3333. /* Default value: 0x0000000000000000 */
  3334. #define QIB_7322_RxDataFifoUnCorErrLogA_0_offset 0x00001868UL
  3335. struct QIB_7322_RxDataFifoUnCorErrLogA_0_pb {
  3336. pseudo_bit_t RxDataFifoUnCorErrData_63_0[64];
  3337. };
  3338. struct QIB_7322_RxDataFifoUnCorErrLogA_0 {
  3339. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxDataFifoUnCorErrLogA_0_pb );
  3340. };
  3341. /* Default value: 0x0000000000000000 */
  3342. #define QIB_7322_RxDataFifoUnCorErrLogB_0_offset 0x00001870UL
  3343. struct QIB_7322_RxDataFifoUnCorErrLogB_0_pb {
  3344. pseudo_bit_t RxDataFifoUnCorErrData_127_64[64];
  3345. };
  3346. struct QIB_7322_RxDataFifoUnCorErrLogB_0 {
  3347. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxDataFifoUnCorErrLogB_0_pb );
  3348. };
  3349. /* Default value: 0x0000000000000000 */
  3350. #define QIB_7322_RxDataFifoUnCorErrLogC_0_offset 0x00001878UL
  3351. struct QIB_7322_RxDataFifoUnCorErrLogC_0_pb {
  3352. pseudo_bit_t RxDataFifoUnCorErrCheckBit_15_0[16];
  3353. pseudo_bit_t RxDataFifoUnCorErrAddr_10_0[11];
  3354. pseudo_bit_t _unused_0[37];
  3355. };
  3356. struct QIB_7322_RxDataFifoUnCorErrLogC_0 {
  3357. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxDataFifoUnCorErrLogC_0_pb );
  3358. };
  3359. /* Default value: 0x0000000000000000 */
  3360. #define QIB_7322_LaFifoArray0UnCorErrLog_0_offset 0x00001880UL
  3361. struct QIB_7322_LaFifoArray0UnCorErrLog_0_pb {
  3362. pseudo_bit_t LaFifoArray0UnCorErrData_34_0[35];
  3363. pseudo_bit_t LaFifoArray0UnCorErrCheckBit_10_0[11];
  3364. pseudo_bit_t LaFifoArray0UnCorErrAddr_10_0[11];
  3365. pseudo_bit_t _unused_0[7];
  3366. };
  3367. struct QIB_7322_LaFifoArray0UnCorErrLog_0 {
  3368. PSEUDO_BIT_STRUCT ( struct QIB_7322_LaFifoArray0UnCorErrLog_0_pb );
  3369. };
  3370. /* Default value: 0x0000000000000000 */
  3371. #define QIB_7322_RmFifoArrayUnCorErrLogA_0_offset 0x000018c0UL
  3372. struct QIB_7322_RmFifoArrayUnCorErrLogA_0_pb {
  3373. pseudo_bit_t RmFifoArrayUnCorErrData_63_0[64];
  3374. };
  3375. struct QIB_7322_RmFifoArrayUnCorErrLogA_0 {
  3376. PSEUDO_BIT_STRUCT ( struct QIB_7322_RmFifoArrayUnCorErrLogA_0_pb );
  3377. };
  3378. /* Default value: 0x0000000000000000 */
  3379. #define QIB_7322_RmFifoArrayUnCorErrLogB_0_offset 0x000018c8UL
  3380. struct QIB_7322_RmFifoArrayUnCorErrLogB_0_pb {
  3381. pseudo_bit_t RmFifoArrayUnCorErrData_127_64[64];
  3382. };
  3383. struct QIB_7322_RmFifoArrayUnCorErrLogB_0 {
  3384. PSEUDO_BIT_STRUCT ( struct QIB_7322_RmFifoArrayUnCorErrLogB_0_pb );
  3385. };
  3386. /* Default value: 0x0000000000000000 */
  3387. #define QIB_7322_RmFifoArrayUnCorErrLogC_0_offset 0x000018d0UL
  3388. struct QIB_7322_RmFifoArrayUnCorErrLogC_0_pb {
  3389. pseudo_bit_t RmFifoArrayUnCorErrCheckBit_27_0[28];
  3390. pseudo_bit_t RmFifoArrayUnCorErrAddr_13_0[14];
  3391. pseudo_bit_t _unused_0[18];
  3392. pseudo_bit_t RmFifoArrayUnCorErrDword_3_0[4];
  3393. };
  3394. struct QIB_7322_RmFifoArrayUnCorErrLogC_0 {
  3395. PSEUDO_BIT_STRUCT ( struct QIB_7322_RmFifoArrayUnCorErrLogC_0_pb );
  3396. };
  3397. /* Default value: 0x0000000000000000 */
  3398. #define QIB_7322_RxBufrCorErrLogA_0_offset 0x00001900UL
  3399. struct QIB_7322_RxBufrCorErrLogA_0_pb {
  3400. pseudo_bit_t RxBufrCorErrData_63_0[64];
  3401. };
  3402. struct QIB_7322_RxBufrCorErrLogA_0 {
  3403. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrCorErrLogA_0_pb );
  3404. };
  3405. /* Default value: 0x0000000000000000 */
  3406. #define QIB_7322_RxBufrCorErrLogB_0_offset 0x00001908UL
  3407. struct QIB_7322_RxBufrCorErrLogB_0_pb {
  3408. pseudo_bit_t RxBufrCorErrData_127_64[64];
  3409. };
  3410. struct QIB_7322_RxBufrCorErrLogB_0 {
  3411. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrCorErrLogB_0_pb );
  3412. };
  3413. /* Default value: 0x0000000000000000 */
  3414. #define QIB_7322_RxBufrCorErrLogC_0_offset 0x00001910UL
  3415. struct QIB_7322_RxBufrCorErrLogC_0_pb {
  3416. pseudo_bit_t RxBufrCorErrData_191_128[64];
  3417. };
  3418. struct QIB_7322_RxBufrCorErrLogC_0 {
  3419. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrCorErrLogC_0_pb );
  3420. };
  3421. /* Default value: 0x0000000000000000 */
  3422. #define QIB_7322_RxBufrCorErrLogD_0_offset 0x00001918UL
  3423. struct QIB_7322_RxBufrCorErrLogD_0_pb {
  3424. pseudo_bit_t RxBufrCorErrData_255_192[64];
  3425. };
  3426. struct QIB_7322_RxBufrCorErrLogD_0 {
  3427. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrCorErrLogD_0_pb );
  3428. };
  3429. /* Default value: 0x0000000000000000 */
  3430. #define QIB_7322_RxBufrCorErrLogE_0_offset 0x00001920UL
  3431. struct QIB_7322_RxBufrCorErrLogE_0_pb {
  3432. pseudo_bit_t RxBufrCorErrData_258_256[3];
  3433. pseudo_bit_t RxBufrCorErrCheckBit_36_0[37];
  3434. pseudo_bit_t RxBufrCorErrAddr_15_0[16];
  3435. pseudo_bit_t _unused_0[8];
  3436. };
  3437. struct QIB_7322_RxBufrCorErrLogE_0 {
  3438. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrCorErrLogE_0_pb );
  3439. };
  3440. /* Default value: 0x0000000000000000 */
  3441. #define QIB_7322_RxFlagCorErrLogA_0_offset 0x00001928UL
  3442. struct QIB_7322_RxFlagCorErrLogA_0_pb {
  3443. pseudo_bit_t RxFlagCorErrData_63_0[64];
  3444. };
  3445. struct QIB_7322_RxFlagCorErrLogA_0 {
  3446. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxFlagCorErrLogA_0_pb );
  3447. };
  3448. /* Default value: 0x0000000000000000 */
  3449. #define QIB_7322_RxFlagCorErrLogB_0_offset 0x00001930UL
  3450. struct QIB_7322_RxFlagCorErrLogB_0_pb {
  3451. pseudo_bit_t RxFlagCorErrCheckBit_7_0[8];
  3452. pseudo_bit_t RxFlagCorErrAddr_12_0[13];
  3453. pseudo_bit_t _unused_0[43];
  3454. };
  3455. struct QIB_7322_RxFlagCorErrLogB_0 {
  3456. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxFlagCorErrLogB_0_pb );
  3457. };
  3458. /* Default value: 0x0000000000000000 */
  3459. #define QIB_7322_RxLkupiqCorErrLogA_0_offset 0x00001940UL
  3460. struct QIB_7322_RxLkupiqCorErrLogA_0_pb {
  3461. pseudo_bit_t RxLkupiqCorErrData_45_0[46];
  3462. pseudo_bit_t RxLkupiqCorErrCheckBit_7_0[8];
  3463. pseudo_bit_t _unused_0[10];
  3464. };
  3465. struct QIB_7322_RxLkupiqCorErrLogA_0 {
  3466. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxLkupiqCorErrLogA_0_pb );
  3467. };
  3468. /* Default value: 0x0000000000000000 */
  3469. #define QIB_7322_RxLkupiqCorErrLogB_0_offset 0x00001948UL
  3470. struct QIB_7322_RxLkupiqCorErrLogB_0_pb {
  3471. pseudo_bit_t RxLkupiqCorErrAddr_12_0[13];
  3472. pseudo_bit_t _unused_0[51];
  3473. };
  3474. struct QIB_7322_RxLkupiqCorErrLogB_0 {
  3475. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxLkupiqCorErrLogB_0_pb );
  3476. };
  3477. /* Default value: 0x0000000000000000 */
  3478. #define QIB_7322_RxHdrFifoCorErrLogA_0_offset 0x00001950UL
  3479. struct QIB_7322_RxHdrFifoCorErrLogA_0_pb {
  3480. pseudo_bit_t RxHdrFifoCorErrData_63_0[64];
  3481. };
  3482. struct QIB_7322_RxHdrFifoCorErrLogA_0 {
  3483. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoCorErrLogA_0_pb );
  3484. };
  3485. /* Default value: 0x0000000000000000 */
  3486. #define QIB_7322_RxHdrFifoCorErrLogB_0_offset 0x00001958UL
  3487. struct QIB_7322_RxHdrFifoCorErrLogB_0_pb {
  3488. pseudo_bit_t RxHdrFifoCorErrData_127_64[64];
  3489. };
  3490. struct QIB_7322_RxHdrFifoCorErrLogB_0 {
  3491. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoCorErrLogB_0_pb );
  3492. };
  3493. /* Default value: 0x0000000000000000 */
  3494. #define QIB_7322_RxHdrFifoCorErrLogC_0_offset 0x00001960UL
  3495. struct QIB_7322_RxHdrFifoCorErrLogC_0_pb {
  3496. pseudo_bit_t RxHdrFifoCorErrCheckBit_15_0[16];
  3497. pseudo_bit_t RxHdrFifoCorErrAddr_10_0[11];
  3498. pseudo_bit_t _unused_0[37];
  3499. };
  3500. struct QIB_7322_RxHdrFifoCorErrLogC_0 {
  3501. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoCorErrLogC_0_pb );
  3502. };
  3503. /* Default value: 0x0000000000000000 */
  3504. #define QIB_7322_RxDataFifoCorErrLogA_0_offset 0x00001968UL
  3505. struct QIB_7322_RxDataFifoCorErrLogA_0_pb {
  3506. pseudo_bit_t RxDataFifoCorErrData_63_0[64];
  3507. };
  3508. struct QIB_7322_RxDataFifoCorErrLogA_0 {
  3509. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxDataFifoCorErrLogA_0_pb );
  3510. };
  3511. /* Default value: 0x0000000000000000 */
  3512. #define QIB_7322_RxDataFifoCorErrLogB_0_offset 0x00001970UL
  3513. struct QIB_7322_RxDataFifoCorErrLogB_0_pb {
  3514. pseudo_bit_t RxDataFifoCorErrData_127_64[64];
  3515. };
  3516. struct QIB_7322_RxDataFifoCorErrLogB_0 {
  3517. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxDataFifoCorErrLogB_0_pb );
  3518. };
  3519. /* Default value: 0x0000000000000000 */
  3520. #define QIB_7322_RxDataFifoCorErrLogC_0_offset 0x00001978UL
  3521. struct QIB_7322_RxDataFifoCorErrLogC_0_pb {
  3522. pseudo_bit_t RxDataFifoCorErrCheckBit_15_0[16];
  3523. pseudo_bit_t RxDataFifoCorErrAddr_10_0[11];
  3524. pseudo_bit_t _unused_0[37];
  3525. };
  3526. struct QIB_7322_RxDataFifoCorErrLogC_0 {
  3527. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxDataFifoCorErrLogC_0_pb );
  3528. };
  3529. /* Default value: 0x0000000000000000 */
  3530. #define QIB_7322_LaFifoArray0CorErrLog_0_offset 0x00001980UL
  3531. struct QIB_7322_LaFifoArray0CorErrLog_0_pb {
  3532. pseudo_bit_t LaFifoArray0CorErrData_34_0[35];
  3533. pseudo_bit_t LaFifoArray0CorErrCheckBit_10_0[11];
  3534. pseudo_bit_t LaFifoArray0CorErrAddr_10_0[11];
  3535. pseudo_bit_t _unused_0[7];
  3536. };
  3537. struct QIB_7322_LaFifoArray0CorErrLog_0 {
  3538. PSEUDO_BIT_STRUCT ( struct QIB_7322_LaFifoArray0CorErrLog_0_pb );
  3539. };
  3540. /* Default value: 0x0000000000000000 */
  3541. #define QIB_7322_RmFifoArrayCorErrLogA_0_offset 0x000019c0UL
  3542. struct QIB_7322_RmFifoArrayCorErrLogA_0_pb {
  3543. pseudo_bit_t RmFifoArrayCorErrData_63_0[64];
  3544. };
  3545. struct QIB_7322_RmFifoArrayCorErrLogA_0 {
  3546. PSEUDO_BIT_STRUCT ( struct QIB_7322_RmFifoArrayCorErrLogA_0_pb );
  3547. };
  3548. /* Default value: 0x0000000000000000 */
  3549. #define QIB_7322_RmFifoArrayCorErrLogB_0_offset 0x000019c8UL
  3550. struct QIB_7322_RmFifoArrayCorErrLogB_0_pb {
  3551. pseudo_bit_t RmFifoArrayCorErrData_127_64[64];
  3552. };
  3553. struct QIB_7322_RmFifoArrayCorErrLogB_0 {
  3554. PSEUDO_BIT_STRUCT ( struct QIB_7322_RmFifoArrayCorErrLogB_0_pb );
  3555. };
  3556. /* Default value: 0x0000000000000000 */
  3557. #define QIB_7322_RmFifoArrayCorErrLogC_0_offset 0x000019d0UL
  3558. struct QIB_7322_RmFifoArrayCorErrLogC_0_pb {
  3559. pseudo_bit_t RmFifoArrayCorErrCheckBit_27_0[28];
  3560. pseudo_bit_t RmFifoArrayCorErrAddr_13_0[14];
  3561. pseudo_bit_t _unused_0[18];
  3562. pseudo_bit_t RmFifoArrayCorErrDword_3_0[4];
  3563. };
  3564. struct QIB_7322_RmFifoArrayCorErrLogC_0 {
  3565. PSEUDO_BIT_STRUCT ( struct QIB_7322_RmFifoArrayCorErrLogC_0_pb );
  3566. };
  3567. /* Default value: 0x0000000000000000 */
  3568. #define QIB_7322_HighPriorityLimit_0_offset 0x00001bc0UL
  3569. struct QIB_7322_HighPriorityLimit_0_pb {
  3570. pseudo_bit_t Limit[8];
  3571. pseudo_bit_t _unused_0[56];
  3572. };
  3573. struct QIB_7322_HighPriorityLimit_0 {
  3574. PSEUDO_BIT_STRUCT ( struct QIB_7322_HighPriorityLimit_0_pb );
  3575. };
  3576. /* Default value: 0x0000000000000000 */
  3577. #define QIB_7322_LowPriority0_0_offset 0x00001c00UL
  3578. struct QIB_7322_LowPriority0_0_pb {
  3579. pseudo_bit_t Weight[8];
  3580. pseudo_bit_t _unused_0[8];
  3581. pseudo_bit_t VirtualLane[3];
  3582. pseudo_bit_t _unused_1[45];
  3583. };
  3584. struct QIB_7322_LowPriority0_0 {
  3585. PSEUDO_BIT_STRUCT ( struct QIB_7322_LowPriority0_0_pb );
  3586. };
  3587. /* Default value: 0x0000000000000000 */
  3588. #define QIB_7322_HighPriority0_0_offset 0x00001e00UL
  3589. struct QIB_7322_HighPriority0_0_pb {
  3590. pseudo_bit_t Weight[8];
  3591. pseudo_bit_t _unused_0[8];
  3592. pseudo_bit_t VirtualLane[3];
  3593. pseudo_bit_t _unused_1[45];
  3594. };
  3595. struct QIB_7322_HighPriority0_0 {
  3596. PSEUDO_BIT_STRUCT ( struct QIB_7322_HighPriority0_0_pb );
  3597. };
  3598. /* Default value: 0x0000000000000000 */
  3599. #define QIB_7322_CntrRegBase_1_offset 0x00002028UL
  3600. /* Default value: 0x0000000000013000 */
  3601. #define QIB_7322_ErrMask_1_offset 0x00002080UL
  3602. struct QIB_7322_ErrMask_1_pb {
  3603. pseudo_bit_t RcvFormatErrMask[1];
  3604. pseudo_bit_t RcvVCRCErrMask[1];
  3605. pseudo_bit_t RcvICRCErrMask[1];
  3606. pseudo_bit_t RcvMinPktLenErrMask[1];
  3607. pseudo_bit_t RcvMaxPktLenErrMask[1];
  3608. pseudo_bit_t RcvLongPktLenErrMask[1];
  3609. pseudo_bit_t RcvShortPktLenErrMask[1];
  3610. pseudo_bit_t RcvUnexpectedCharErrMask[1];
  3611. pseudo_bit_t RcvUnsupportedVLErrMask[1];
  3612. pseudo_bit_t RcvEBPErrMask[1];
  3613. pseudo_bit_t RcvIBFlowErrMask[1];
  3614. pseudo_bit_t RcvBadVersionErrMask[1];
  3615. pseudo_bit_t _unused_0[2];
  3616. pseudo_bit_t RcvBadTidErrMask[1];
  3617. pseudo_bit_t RcvHdrLenErrMask[1];
  3618. pseudo_bit_t RcvHdrErrMask[1];
  3619. pseudo_bit_t RcvIBLostLinkErrMask[1];
  3620. pseudo_bit_t _unused_1[11];
  3621. pseudo_bit_t SendMinPktLenErrMask[1];
  3622. pseudo_bit_t SendMaxPktLenErrMask[1];
  3623. pseudo_bit_t SendUnderRunErrMask[1];
  3624. pseudo_bit_t SendPktLenErrMask[1];
  3625. pseudo_bit_t SendDroppedSmpPktErrMask[1];
  3626. pseudo_bit_t SendDroppedDataPktErrMask[1];
  3627. pseudo_bit_t _unused_2[1];
  3628. pseudo_bit_t SendUnexpectedPktNumErrMask[1];
  3629. pseudo_bit_t SendUnsupportedVLErrMask[1];
  3630. pseudo_bit_t SendBufMisuseErrMask[1];
  3631. pseudo_bit_t SDmaGenMismatchErrMask[1];
  3632. pseudo_bit_t SDmaOutOfBoundErrMask[1];
  3633. pseudo_bit_t SDmaTailOutOfBoundErrMask[1];
  3634. pseudo_bit_t SDmaBaseErrMask[1];
  3635. pseudo_bit_t SDma1stDescErrMask[1];
  3636. pseudo_bit_t SDmaRpyTagErrMask[1];
  3637. pseudo_bit_t SDmaDwEnErrMask[1];
  3638. pseudo_bit_t SDmaMissingDwErrMask[1];
  3639. pseudo_bit_t SDmaUnexpDataErrMask[1];
  3640. pseudo_bit_t SDmaDescAddrMisalignErrMask[1];
  3641. pseudo_bit_t SDmaHaltErrMask[1];
  3642. pseudo_bit_t _unused_3[4];
  3643. pseudo_bit_t VL15BufMisuseErrMask[1];
  3644. pseudo_bit_t _unused_4[2];
  3645. pseudo_bit_t SHeadersErrMask[1];
  3646. pseudo_bit_t IBStatusChangedMask[1];
  3647. pseudo_bit_t _unused_5[5];
  3648. };
  3649. struct QIB_7322_ErrMask_1 {
  3650. PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrMask_1_pb );
  3651. };
  3652. /* Default value: 0x0000000000000000 */
  3653. #define QIB_7322_ErrStatus_1_offset 0x00002088UL
  3654. struct QIB_7322_ErrStatus_1_pb {
  3655. pseudo_bit_t RcvFormatErr[1];
  3656. pseudo_bit_t RcvVCRCErr[1];
  3657. pseudo_bit_t RcvICRCErr[1];
  3658. pseudo_bit_t RcvMinPktLenErr[1];
  3659. pseudo_bit_t RcvMaxPktLenErr[1];
  3660. pseudo_bit_t RcvLongPktLenErr[1];
  3661. pseudo_bit_t RcvShortPktLenErr[1];
  3662. pseudo_bit_t RcvUnexpectedCharErr[1];
  3663. pseudo_bit_t RcvUnsupportedVLErr[1];
  3664. pseudo_bit_t RcvEBPErr[1];
  3665. pseudo_bit_t RcvIBFlowErr[1];
  3666. pseudo_bit_t RcvBadVersionErr[1];
  3667. pseudo_bit_t _unused_0[2];
  3668. pseudo_bit_t RcvBadTidErr[1];
  3669. pseudo_bit_t RcvHdrLenErr[1];
  3670. pseudo_bit_t RcvHdrErr[1];
  3671. pseudo_bit_t RcvIBLostLinkErr[1];
  3672. pseudo_bit_t _unused_1[11];
  3673. pseudo_bit_t SendMinPktLenErr[1];
  3674. pseudo_bit_t SendMaxPktLenErr[1];
  3675. pseudo_bit_t SendUnderRunErr[1];
  3676. pseudo_bit_t SendPktLenErr[1];
  3677. pseudo_bit_t SendDroppedSmpPktErr[1];
  3678. pseudo_bit_t SendDroppedDataPktErr[1];
  3679. pseudo_bit_t _unused_2[1];
  3680. pseudo_bit_t SendUnexpectedPktNumErr[1];
  3681. pseudo_bit_t SendUnsupportedVLErr[1];
  3682. pseudo_bit_t SendBufMisuseErr[1];
  3683. pseudo_bit_t SDmaGenMismatchErr[1];
  3684. pseudo_bit_t SDmaOutOfBoundErr[1];
  3685. pseudo_bit_t SDmaTailOutOfBoundErr[1];
  3686. pseudo_bit_t SDmaBaseErr[1];
  3687. pseudo_bit_t SDma1stDescErr[1];
  3688. pseudo_bit_t SDmaRpyTagErr[1];
  3689. pseudo_bit_t SDmaDwEnErr[1];
  3690. pseudo_bit_t SDmaMissingDwErr[1];
  3691. pseudo_bit_t SDmaUnexpDataErr[1];
  3692. pseudo_bit_t SDmaDescAddrMisalignErr[1];
  3693. pseudo_bit_t SDmaHaltErr[1];
  3694. pseudo_bit_t _unused_3[4];
  3695. pseudo_bit_t VL15BufMisuseErr[1];
  3696. pseudo_bit_t _unused_4[2];
  3697. pseudo_bit_t SHeadersErr[1];
  3698. pseudo_bit_t IBStatusChanged[1];
  3699. pseudo_bit_t _unused_5[5];
  3700. };
  3701. struct QIB_7322_ErrStatus_1 {
  3702. PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrStatus_1_pb );
  3703. };
  3704. /* Default value: 0x0000000000000000 */
  3705. #define QIB_7322_ErrClear_1_offset 0x00002090UL
  3706. struct QIB_7322_ErrClear_1_pb {
  3707. pseudo_bit_t RcvFormatErrClear[1];
  3708. pseudo_bit_t RcvVCRCErrClear[1];
  3709. pseudo_bit_t RcvICRCErrClear[1];
  3710. pseudo_bit_t RcvMinPktLenErrClear[1];
  3711. pseudo_bit_t RcvMaxPktLenErrClear[1];
  3712. pseudo_bit_t RcvLongPktLenErrClear[1];
  3713. pseudo_bit_t RcvShortPktLenErrClear[1];
  3714. pseudo_bit_t RcvUnexpectedCharErrClear[1];
  3715. pseudo_bit_t RcvUnsupportedVLErrClear[1];
  3716. pseudo_bit_t RcvEBPErrClear[1];
  3717. pseudo_bit_t RcvIBFlowErrClear[1];
  3718. pseudo_bit_t RcvBadVersionErrClear[1];
  3719. pseudo_bit_t _unused_0[2];
  3720. pseudo_bit_t RcvBadTidErrClear[1];
  3721. pseudo_bit_t RcvHdrLenErrClear[1];
  3722. pseudo_bit_t RcvHdrErrClear[1];
  3723. pseudo_bit_t RcvIBLostLinkErrClear[1];
  3724. pseudo_bit_t _unused_1[11];
  3725. pseudo_bit_t SendMinPktLenErrClear[1];
  3726. pseudo_bit_t SendMaxPktLenErrClear[1];
  3727. pseudo_bit_t SendUnderRunErrClear[1];
  3728. pseudo_bit_t SendPktLenErrClear[1];
  3729. pseudo_bit_t SendDroppedSmpPktErrClear[1];
  3730. pseudo_bit_t SendDroppedDataPktErrClear[1];
  3731. pseudo_bit_t _unused_2[1];
  3732. pseudo_bit_t SendUnexpectedPktNumErrClear[1];
  3733. pseudo_bit_t SendUnsupportedVLErrClear[1];
  3734. pseudo_bit_t SendBufMisuseErrClear[1];
  3735. pseudo_bit_t SDmaGenMismatchErrClear[1];
  3736. pseudo_bit_t SDmaOutOfBoundErrClear[1];
  3737. pseudo_bit_t SDmaTailOutOfBoundErrClear[1];
  3738. pseudo_bit_t SDmaBaseErrClear[1];
  3739. pseudo_bit_t SDma1stDescErrClear[1];
  3740. pseudo_bit_t SDmaRpyTagErrClear[1];
  3741. pseudo_bit_t SDmaDwEnErrClear[1];
  3742. pseudo_bit_t SDmaMissingDwErrClear[1];
  3743. pseudo_bit_t SDmaUnexpDataErrClear[1];
  3744. pseudo_bit_t SDmaDescAddrMisalignErrClear[1];
  3745. pseudo_bit_t SDmaHaltErrClear[1];
  3746. pseudo_bit_t _unused_3[4];
  3747. pseudo_bit_t VL15BufMisuseErrClear[1];
  3748. pseudo_bit_t _unused_4[2];
  3749. pseudo_bit_t SHeadersErrClear[1];
  3750. pseudo_bit_t IBStatusChangedClear[1];
  3751. pseudo_bit_t _unused_5[5];
  3752. };
  3753. struct QIB_7322_ErrClear_1 {
  3754. PSEUDO_BIT_STRUCT ( struct QIB_7322_ErrClear_1_pb );
  3755. };
  3756. /* Default value: 0x0000000000000000 */
  3757. #define QIB_7322_TXEStatus_1_offset 0x000020b8UL
  3758. struct QIB_7322_TXEStatus_1_pb {
  3759. pseudo_bit_t LaFifoEmpty_VL0[1];
  3760. pseudo_bit_t LaFifoEmpty_VL1[1];
  3761. pseudo_bit_t LaFifoEmpty_VL2[1];
  3762. pseudo_bit_t LaFifoEmpty_VL3[1];
  3763. pseudo_bit_t LaFifoEmpty_VL4[1];
  3764. pseudo_bit_t LaFifoEmpty_VL5[1];
  3765. pseudo_bit_t LaFifoEmpty_VL6[1];
  3766. pseudo_bit_t LaFifoEmpty_VL7[1];
  3767. pseudo_bit_t _unused_0[7];
  3768. pseudo_bit_t LaFifoEmpty_VL15[1];
  3769. pseudo_bit_t _unused_1[14];
  3770. pseudo_bit_t RmFifoEmpty[1];
  3771. pseudo_bit_t TXE_IBC_Idle[1];
  3772. pseudo_bit_t _unused_2[32];
  3773. };
  3774. struct QIB_7322_TXEStatus_1 {
  3775. PSEUDO_BIT_STRUCT ( struct QIB_7322_TXEStatus_1_pb );
  3776. };
  3777. /* Default value: 0x0000000XC00080FF */
  3778. #define QIB_7322_RcvCtrl_1_offset 0x00002100UL
  3779. struct QIB_7322_RcvCtrl_1_pb {
  3780. pseudo_bit_t _unused_0[1];
  3781. pseudo_bit_t ContextEnableKernel[1];
  3782. pseudo_bit_t ContextEnableUser[16];
  3783. pseudo_bit_t _unused_1[21];
  3784. pseudo_bit_t RcvIBPortEnable[1];
  3785. pseudo_bit_t RcvQPMapEnable[1];
  3786. pseudo_bit_t RcvPartitionKeyDisable[1];
  3787. pseudo_bit_t RcvResetCredit[1];
  3788. pseudo_bit_t _unused_2[21];
  3789. };
  3790. struct QIB_7322_RcvCtrl_1 {
  3791. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvCtrl_1_pb );
  3792. };
  3793. /* Default value: 0x0000000000000000 */
  3794. #define QIB_7322_RcvBTHQP_1_offset 0x00002108UL
  3795. struct QIB_7322_RcvBTHQP_1_pb {
  3796. pseudo_bit_t RcvBTHQP[24];
  3797. pseudo_bit_t _unused_0[40];
  3798. };
  3799. struct QIB_7322_RcvBTHQP_1 {
  3800. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvBTHQP_1_pb );
  3801. };
  3802. /* Default value: 0x0000000000000000 */
  3803. #define QIB_7322_RcvQPMapTableA_1_offset 0x00002110UL
  3804. struct QIB_7322_RcvQPMapTableA_1_pb {
  3805. pseudo_bit_t RcvQPMapContext0[5];
  3806. pseudo_bit_t RcvQPMapContext1[5];
  3807. pseudo_bit_t RcvQPMapContext2[5];
  3808. pseudo_bit_t RcvQPMapContext3[5];
  3809. pseudo_bit_t RcvQPMapContext4[5];
  3810. pseudo_bit_t RcvQPMapContext5[5];
  3811. pseudo_bit_t _unused_0[34];
  3812. };
  3813. struct QIB_7322_RcvQPMapTableA_1 {
  3814. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableA_1_pb );
  3815. };
  3816. /* Default value: 0x0000000000000000 */
  3817. #define QIB_7322_RcvQPMapTableB_1_offset 0x00002118UL
  3818. struct QIB_7322_RcvQPMapTableB_1_pb {
  3819. pseudo_bit_t RcvQPMapContext6[5];
  3820. pseudo_bit_t RcvQPMapContext7[5];
  3821. pseudo_bit_t RcvQPMapContext8[5];
  3822. pseudo_bit_t RcvQPMapContext9[5];
  3823. pseudo_bit_t RcvQPMapContext10[5];
  3824. pseudo_bit_t RcvQPMapContext11[5];
  3825. pseudo_bit_t _unused_0[34];
  3826. };
  3827. struct QIB_7322_RcvQPMapTableB_1 {
  3828. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableB_1_pb );
  3829. };
  3830. /* Default value: 0x0000000000000000 */
  3831. #define QIB_7322_RcvQPMapTableC_1_offset 0x00002120UL
  3832. struct QIB_7322_RcvQPMapTableC_1_pb {
  3833. pseudo_bit_t RcvQPMapContext12[5];
  3834. pseudo_bit_t RcvQPMapContext13[5];
  3835. pseudo_bit_t RcvQPMapContext14[5];
  3836. pseudo_bit_t RcvQPMapContext15[5];
  3837. pseudo_bit_t RcvQPMapContext16[5];
  3838. pseudo_bit_t RcvQPMapContext17[5];
  3839. pseudo_bit_t _unused_0[34];
  3840. };
  3841. struct QIB_7322_RcvQPMapTableC_1 {
  3842. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableC_1_pb );
  3843. };
  3844. /* Default value: 0x0000000000000000 */
  3845. #define QIB_7322_RcvQPMapTableD_1_offset 0x00002128UL
  3846. struct QIB_7322_RcvQPMapTableD_1_pb {
  3847. pseudo_bit_t RcvQPMapContext18[5];
  3848. pseudo_bit_t RcvQPMapContext19[5];
  3849. pseudo_bit_t RcvQPMapContext20[5];
  3850. pseudo_bit_t RcvQPMapContext21[5];
  3851. pseudo_bit_t RcvQPMapContext22[5];
  3852. pseudo_bit_t RcvQPMapContext23[5];
  3853. pseudo_bit_t _unused_0[34];
  3854. };
  3855. struct QIB_7322_RcvQPMapTableD_1 {
  3856. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableD_1_pb );
  3857. };
  3858. /* Default value: 0x0000000000000000 */
  3859. #define QIB_7322_RcvQPMapTableE_1_offset 0x00002130UL
  3860. struct QIB_7322_RcvQPMapTableE_1_pb {
  3861. pseudo_bit_t RcvQPMapContext24[5];
  3862. pseudo_bit_t RcvQPMapContext25[5];
  3863. pseudo_bit_t RcvQPMapContext26[5];
  3864. pseudo_bit_t RcvQPMapContext27[5];
  3865. pseudo_bit_t RcvQPMapContext28[5];
  3866. pseudo_bit_t RcvQPMapContext29[5];
  3867. pseudo_bit_t _unused_0[34];
  3868. };
  3869. struct QIB_7322_RcvQPMapTableE_1 {
  3870. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableE_1_pb );
  3871. };
  3872. /* Default value: 0x0000000000000000 */
  3873. #define QIB_7322_RcvQPMapTableF_1_offset 0x00002138UL
  3874. struct QIB_7322_RcvQPMapTableF_1_pb {
  3875. pseudo_bit_t RcvQPMapContext30[5];
  3876. pseudo_bit_t RcvQPMapContext31[5];
  3877. pseudo_bit_t _unused_0[54];
  3878. };
  3879. struct QIB_7322_RcvQPMapTableF_1 {
  3880. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMapTableF_1_pb );
  3881. };
  3882. /* Default value: 0x0000000000000000 */
  3883. #define QIB_7322_PSStat_1_offset 0x00002140UL
  3884. /* Default value: 0x0000000000000000 */
  3885. #define QIB_7322_PSStart_1_offset 0x00002148UL
  3886. /* Default value: 0x0000000000000000 */
  3887. #define QIB_7322_PSInterval_1_offset 0x00002150UL
  3888. /* Default value: 0x0000000000000000 */
  3889. #define QIB_7322_RcvStatus_1_offset 0x00002160UL
  3890. struct QIB_7322_RcvStatus_1_pb {
  3891. pseudo_bit_t RxPktInProgress[1];
  3892. pseudo_bit_t DmaeqBlockingContext[5];
  3893. pseudo_bit_t _unused_0[58];
  3894. };
  3895. struct QIB_7322_RcvStatus_1 {
  3896. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvStatus_1_pb );
  3897. };
  3898. /* Default value: 0x0000000000000000 */
  3899. #define QIB_7322_RcvPartitionKey_1_offset 0x00002168UL
  3900. /* Default value: 0x0000000000000000 */
  3901. #define QIB_7322_RcvQPMulticastContext_1_offset 0x00002170UL
  3902. struct QIB_7322_RcvQPMulticastContext_1_pb {
  3903. pseudo_bit_t RcvQpMcContext[5];
  3904. pseudo_bit_t _unused_0[59];
  3905. };
  3906. struct QIB_7322_RcvQPMulticastContext_1 {
  3907. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvQPMulticastContext_1_pb );
  3908. };
  3909. /* Default value: 0x0000000000000000 */
  3910. #define QIB_7322_RcvPktLEDCnt_1_offset 0x00002178UL
  3911. struct QIB_7322_RcvPktLEDCnt_1_pb {
  3912. pseudo_bit_t OFFperiod[32];
  3913. pseudo_bit_t ONperiod[32];
  3914. };
  3915. struct QIB_7322_RcvPktLEDCnt_1 {
  3916. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvPktLEDCnt_1_pb );
  3917. };
  3918. /* Default value: 0x0000000000000000 */
  3919. #define QIB_7322_SendDmaIdleCnt_1_offset 0x00002180UL
  3920. struct QIB_7322_SendDmaIdleCnt_1_pb {
  3921. pseudo_bit_t SendDmaIdleCnt[16];
  3922. pseudo_bit_t _unused_0[48];
  3923. };
  3924. struct QIB_7322_SendDmaIdleCnt_1 {
  3925. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaIdleCnt_1_pb );
  3926. };
  3927. /* Default value: 0x0000000000000000 */
  3928. #define QIB_7322_SendDmaReloadCnt_1_offset 0x00002188UL
  3929. struct QIB_7322_SendDmaReloadCnt_1_pb {
  3930. pseudo_bit_t SendDmaReloadCnt[16];
  3931. pseudo_bit_t _unused_0[48];
  3932. };
  3933. struct QIB_7322_SendDmaReloadCnt_1 {
  3934. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaReloadCnt_1_pb );
  3935. };
  3936. /* Default value: 0x0000000000000000 */
  3937. #define QIB_7322_SendDmaDescCnt_1_offset 0x00002190UL
  3938. struct QIB_7322_SendDmaDescCnt_1_pb {
  3939. pseudo_bit_t SendDmaDescCnt[16];
  3940. pseudo_bit_t _unused_0[48];
  3941. };
  3942. struct QIB_7322_SendDmaDescCnt_1 {
  3943. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaDescCnt_1_pb );
  3944. };
  3945. /* Default value: 0x0000000000000000 */
  3946. #define QIB_7322_SendCtrl_1_offset 0x000021c0UL
  3947. struct QIB_7322_SendCtrl_1_pb {
  3948. pseudo_bit_t TxeAbortIbc[1];
  3949. pseudo_bit_t TxeBypassIbc[1];
  3950. pseudo_bit_t _unused_0[1];
  3951. pseudo_bit_t SendEnable[1];
  3952. pseudo_bit_t _unused_1[3];
  3953. pseudo_bit_t ForceCreditUpToDate[1];
  3954. pseudo_bit_t SDmaCleanup[1];
  3955. pseudo_bit_t SDmaIntEnable[1];
  3956. pseudo_bit_t SDmaSingleDescriptor[1];
  3957. pseudo_bit_t SDmaEnable[1];
  3958. pseudo_bit_t SDmaHalt[1];
  3959. pseudo_bit_t TxeDrainLaFifo[1];
  3960. pseudo_bit_t TxeDrainRmFifo[1];
  3961. pseudo_bit_t IBVLArbiterEn[1];
  3962. pseudo_bit_t _unused_2[48];
  3963. };
  3964. struct QIB_7322_SendCtrl_1 {
  3965. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendCtrl_1_pb );
  3966. };
  3967. /* Default value: 0x0000000000000000 */
  3968. #define QIB_7322_SendDmaBase_1_offset 0x000021f8UL
  3969. struct QIB_7322_SendDmaBase_1_pb {
  3970. pseudo_bit_t SendDmaBase[48];
  3971. pseudo_bit_t _unused_0[16];
  3972. };
  3973. struct QIB_7322_SendDmaBase_1 {
  3974. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaBase_1_pb );
  3975. };
  3976. /* Default value: 0x0000000000000000 */
  3977. #define QIB_7322_SendDmaLenGen_1_offset 0x00002200UL
  3978. struct QIB_7322_SendDmaLenGen_1_pb {
  3979. pseudo_bit_t Length[16];
  3980. pseudo_bit_t Generation[3];
  3981. pseudo_bit_t _unused_0[45];
  3982. };
  3983. struct QIB_7322_SendDmaLenGen_1 {
  3984. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaLenGen_1_pb );
  3985. };
  3986. /* Default value: 0x0000000000000000 */
  3987. #define QIB_7322_SendDmaTail_1_offset 0x00002208UL
  3988. struct QIB_7322_SendDmaTail_1_pb {
  3989. pseudo_bit_t SendDmaTail[16];
  3990. pseudo_bit_t _unused_0[48];
  3991. };
  3992. struct QIB_7322_SendDmaTail_1 {
  3993. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaTail_1_pb );
  3994. };
  3995. /* Default value: 0x0000000000000000 */
  3996. #define QIB_7322_SendDmaHead_1_offset 0x00002210UL
  3997. struct QIB_7322_SendDmaHead_1_pb {
  3998. pseudo_bit_t SendDmaHead[16];
  3999. pseudo_bit_t _unused_0[16];
  4000. pseudo_bit_t InternalSendDmaHead[16];
  4001. pseudo_bit_t _unused_1[16];
  4002. };
  4003. struct QIB_7322_SendDmaHead_1 {
  4004. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaHead_1_pb );
  4005. };
  4006. /* Default value: 0x0000000000000000 */
  4007. #define QIB_7322_SendDmaHeadAddr_1_offset 0x00002218UL
  4008. struct QIB_7322_SendDmaHeadAddr_1_pb {
  4009. pseudo_bit_t SendDmaHeadAddr[48];
  4010. pseudo_bit_t _unused_0[16];
  4011. };
  4012. struct QIB_7322_SendDmaHeadAddr_1 {
  4013. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaHeadAddr_1_pb );
  4014. };
  4015. /* Default value: 0x0000000000000000 */
  4016. #define QIB_7322_SendDmaBufMask0_1_offset 0x00002220UL
  4017. struct QIB_7322_SendDmaBufMask0_1_pb {
  4018. pseudo_bit_t BufMask_63_0[64];
  4019. };
  4020. struct QIB_7322_SendDmaBufMask0_1 {
  4021. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaBufMask0_1_pb );
  4022. };
  4023. /* Default value: 0x0000000000000000 */
  4024. #define QIB_7322_SendDmaStatus_1_offset 0x00002238UL
  4025. struct QIB_7322_SendDmaStatus_1_pb {
  4026. pseudo_bit_t SplFifoDescIndex[16];
  4027. pseudo_bit_t SplFifoBufNum[8];
  4028. pseudo_bit_t SplFifoFull[1];
  4029. pseudo_bit_t SplFifoEmpty[1];
  4030. pseudo_bit_t SplFifoDisarmed[1];
  4031. pseudo_bit_t SplFifoReadyToGo[1];
  4032. pseudo_bit_t ScbFetchDescFlag[1];
  4033. pseudo_bit_t ScbEntryValid[1];
  4034. pseudo_bit_t ScbEmpty[1];
  4035. pseudo_bit_t ScbFull[1];
  4036. pseudo_bit_t RpyTag_7_0[8];
  4037. pseudo_bit_t RpyLowAddr_6_0[7];
  4038. pseudo_bit_t ScbDescIndex_13_0[14];
  4039. pseudo_bit_t InternalSDmaHalt[1];
  4040. pseudo_bit_t HaltInProg[1];
  4041. pseudo_bit_t ScoreBoardDrainInProg[1];
  4042. };
  4043. struct QIB_7322_SendDmaStatus_1 {
  4044. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaStatus_1_pb );
  4045. };
  4046. /* Default value: 0x0000000042000000 */
  4047. #define QIB_7322_SendDmaPriorityThld_1_offset 0x00002258UL
  4048. struct QIB_7322_SendDmaPriorityThld_1_pb {
  4049. pseudo_bit_t PriorityThreshold[4];
  4050. pseudo_bit_t _unused_0[60];
  4051. };
  4052. struct QIB_7322_SendDmaPriorityThld_1 {
  4053. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaPriorityThld_1_pb );
  4054. };
  4055. /* Default value: 0x0000000000000000 */
  4056. #define QIB_7322_SendHdrErrSymptom_1_offset 0x00002260UL
  4057. struct QIB_7322_SendHdrErrSymptom_1_pb {
  4058. pseudo_bit_t PacketTooSmall[1];
  4059. pseudo_bit_t RawIPV6[1];
  4060. pseudo_bit_t SLIDFail[1];
  4061. pseudo_bit_t QPFail[1];
  4062. pseudo_bit_t PkeyFail[1];
  4063. pseudo_bit_t GRHFail[1];
  4064. pseudo_bit_t NonKeyPacket[1];
  4065. pseudo_bit_t _unused_0[57];
  4066. };
  4067. struct QIB_7322_SendHdrErrSymptom_1 {
  4068. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendHdrErrSymptom_1_pb );
  4069. };
  4070. /* Default value: 0x0000000000000000 */
  4071. #define QIB_7322_RxCreditVL0_1_offset 0x00002280UL
  4072. struct QIB_7322_RxCreditVL0_1_pb {
  4073. pseudo_bit_t RxMaxCreditVL[12];
  4074. pseudo_bit_t _unused_0[4];
  4075. pseudo_bit_t RxBufrConsumedVL[12];
  4076. pseudo_bit_t _unused_1[36];
  4077. };
  4078. struct QIB_7322_RxCreditVL0_1 {
  4079. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxCreditVL0_1_pb );
  4080. };
  4081. /* Default value: 0x0000000000000000 */
  4082. #define QIB_7322_SendDmaBufUsed0_1_offset 0x00002480UL
  4083. struct QIB_7322_SendDmaBufUsed0_1_pb {
  4084. pseudo_bit_t BufUsed_63_0[64];
  4085. };
  4086. struct QIB_7322_SendDmaBufUsed0_1 {
  4087. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaBufUsed0_1_pb );
  4088. };
  4089. /* Default value: 0x0000000000000000 */
  4090. #define QIB_7322_SendDmaReqTagUsed_1_offset 0x00002498UL
  4091. struct QIB_7322_SendDmaReqTagUsed_1_pb {
  4092. pseudo_bit_t ReqTagUsed_7_0[8];
  4093. pseudo_bit_t _unused_0[56];
  4094. };
  4095. struct QIB_7322_SendDmaReqTagUsed_1 {
  4096. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendDmaReqTagUsed_1_pb );
  4097. };
  4098. /* Default value: 0x0000000000000000 */
  4099. #define QIB_7322_SendCheckControl_1_offset 0x000024a8UL
  4100. struct QIB_7322_SendCheckControl_1_pb {
  4101. pseudo_bit_t PacketTooSmall_En[1];
  4102. pseudo_bit_t RawIPV6_En[1];
  4103. pseudo_bit_t SLID_En[1];
  4104. pseudo_bit_t BTHQP_En[1];
  4105. pseudo_bit_t PKey_En[1];
  4106. pseudo_bit_t _unused_0[59];
  4107. };
  4108. struct QIB_7322_SendCheckControl_1 {
  4109. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendCheckControl_1_pb );
  4110. };
  4111. /* Default value: 0x0000000000000000 */
  4112. #define QIB_7322_SendIBSLIDMask_1_offset 0x000024b0UL
  4113. struct QIB_7322_SendIBSLIDMask_1_pb {
  4114. pseudo_bit_t SendIBSLIDMask_15_0[16];
  4115. pseudo_bit_t _unused_0[48];
  4116. };
  4117. struct QIB_7322_SendIBSLIDMask_1 {
  4118. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendIBSLIDMask_1_pb );
  4119. };
  4120. /* Default value: 0x0000000000000000 */
  4121. #define QIB_7322_SendIBSLIDAssign_1_offset 0x000024b8UL
  4122. struct QIB_7322_SendIBSLIDAssign_1_pb {
  4123. pseudo_bit_t SendIBSLIDAssign_15_0[16];
  4124. pseudo_bit_t _unused_0[48];
  4125. };
  4126. struct QIB_7322_SendIBSLIDAssign_1 {
  4127. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendIBSLIDAssign_1_pb );
  4128. };
  4129. /* Default value: 0x0000000000000000 */
  4130. #define QIB_7322_IBCStatusA_1_offset 0x00002540UL
  4131. struct QIB_7322_IBCStatusA_1_pb {
  4132. pseudo_bit_t LinkTrainingState[5];
  4133. pseudo_bit_t LinkState[3];
  4134. pseudo_bit_t LinkSpeedActive[1];
  4135. pseudo_bit_t LinkWidthActive[1];
  4136. pseudo_bit_t DDS_RXEQ_FAIL[1];
  4137. pseudo_bit_t _unused_0[1];
  4138. pseudo_bit_t IBRxLaneReversed[1];
  4139. pseudo_bit_t IBTxLaneReversed[1];
  4140. pseudo_bit_t ScrambleEn[1];
  4141. pseudo_bit_t ScrambleCapRemote[1];
  4142. pseudo_bit_t _unused_1[13];
  4143. pseudo_bit_t LinkSpeedQDR[1];
  4144. pseudo_bit_t TxReady[1];
  4145. pseudo_bit_t _unused_2[1];
  4146. pseudo_bit_t TxCreditOk_VL0[1];
  4147. pseudo_bit_t TxCreditOk_VL1[1];
  4148. pseudo_bit_t TxCreditOk_VL2[1];
  4149. pseudo_bit_t TxCreditOk_VL3[1];
  4150. pseudo_bit_t TxCreditOk_VL4[1];
  4151. pseudo_bit_t TxCreditOk_VL5[1];
  4152. pseudo_bit_t TxCreditOk_VL6[1];
  4153. pseudo_bit_t TxCreditOk_VL7[1];
  4154. pseudo_bit_t _unused_3[24];
  4155. };
  4156. struct QIB_7322_IBCStatusA_1 {
  4157. PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCStatusA_1_pb );
  4158. };
  4159. /* Default value: 0x0000000000000X02 */
  4160. #define QIB_7322_IBCStatusB_1_offset 0x00002548UL
  4161. struct QIB_7322_IBCStatusB_1_pb {
  4162. pseudo_bit_t LinkRoundTripLatency[26];
  4163. pseudo_bit_t ReqDDSLocalFromRmt[4];
  4164. pseudo_bit_t RxEqLocalDevice[2];
  4165. pseudo_bit_t heartbeat_crosstalk[4];
  4166. pseudo_bit_t heartbeat_timed_out[1];
  4167. pseudo_bit_t _unused_0[27];
  4168. };
  4169. struct QIB_7322_IBCStatusB_1 {
  4170. PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCStatusB_1_pb );
  4171. };
  4172. /* Default value: 0x00000000XXXXXXXX */
  4173. #define QIB_7322_IBCCtrlA_1_offset 0x00002560UL
  4174. struct QIB_7322_IBCCtrlA_1_pb {
  4175. pseudo_bit_t FlowCtrlPeriod[8];
  4176. pseudo_bit_t FlowCtrlWaterMark[8];
  4177. pseudo_bit_t LinkInitCmd[3];
  4178. pseudo_bit_t LinkCmd[2];
  4179. pseudo_bit_t MaxPktLen[11];
  4180. pseudo_bit_t PhyerrThreshold[4];
  4181. pseudo_bit_t OverrunThreshold[4];
  4182. pseudo_bit_t _unused_0[8];
  4183. pseudo_bit_t NumVLane[3];
  4184. pseudo_bit_t _unused_1[9];
  4185. pseudo_bit_t IBStatIntReductionEn[1];
  4186. pseudo_bit_t IBLinkEn[1];
  4187. pseudo_bit_t LinkDownDefaultState[1];
  4188. pseudo_bit_t Loopback[1];
  4189. };
  4190. struct QIB_7322_IBCCtrlA_1 {
  4191. PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCCtrlA_1_pb );
  4192. };
  4193. /* Default value: 0x0000000000000000 */
  4194. #define QIB_7322_IBCCtrlB_1_offset 0x00002568UL
  4195. struct QIB_7322_IBCCtrlB_1_pb {
  4196. pseudo_bit_t IB_ENHANCED_MODE[1];
  4197. pseudo_bit_t SD_SPEED[1];
  4198. pseudo_bit_t SD_SPEED_SDR[1];
  4199. pseudo_bit_t SD_SPEED_DDR[1];
  4200. pseudo_bit_t SD_SPEED_QDR[1];
  4201. pseudo_bit_t IB_NUM_CHANNELS[2];
  4202. pseudo_bit_t IB_POLARITY_REV_SUPP[1];
  4203. pseudo_bit_t IB_LANE_REV_SUPPORTED[1];
  4204. pseudo_bit_t SD_RX_EQUAL_ENABLE[1];
  4205. pseudo_bit_t SD_ADD_ENB[1];
  4206. pseudo_bit_t SD_DDSV[1];
  4207. pseudo_bit_t SD_DDS[4];
  4208. pseudo_bit_t HRTBT_ENB[1];
  4209. pseudo_bit_t HRTBT_AUTO[1];
  4210. pseudo_bit_t HRTBT_PORT[8];
  4211. pseudo_bit_t HRTBT_REQ[1];
  4212. pseudo_bit_t IB_ENABLE_FILT_DPKT[1];
  4213. pseudo_bit_t _unused_0[4];
  4214. pseudo_bit_t IB_DLID[16];
  4215. pseudo_bit_t IB_DLID_MASK[16];
  4216. };
  4217. struct QIB_7322_IBCCtrlB_1 {
  4218. PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCCtrlB_1_pb );
  4219. };
  4220. /* Default value: 0x00000000000305FF */
  4221. #define QIB_7322_IBCCtrlC_1_offset 0x00002570UL
  4222. struct QIB_7322_IBCCtrlC_1_pb {
  4223. pseudo_bit_t IB_FRONT_PORCH[5];
  4224. pseudo_bit_t IB_BACK_PORCH[5];
  4225. pseudo_bit_t _unused_0[54];
  4226. };
  4227. struct QIB_7322_IBCCtrlC_1 {
  4228. PSEUDO_BIT_STRUCT ( struct QIB_7322_IBCCtrlC_1_pb );
  4229. };
  4230. /* Default value: 0x0000000000000301 */
  4231. #define QIB_7322_HRTBT_GUID_1_offset 0x00002588UL
  4232. /* Default value: 0x0000000000000000 */
  4233. #define QIB_7322_IB_SDTEST_IF_TX_1_offset 0x00002590UL
  4234. struct QIB_7322_IB_SDTEST_IF_TX_1_pb {
  4235. pseudo_bit_t TS_T_TX_VALID[1];
  4236. pseudo_bit_t TS_3_TX_VALID[1];
  4237. pseudo_bit_t VL_CAP[2];
  4238. pseudo_bit_t CREDIT_CHANGE[1];
  4239. pseudo_bit_t _unused_0[6];
  4240. pseudo_bit_t TS_TX_OPCODE[2];
  4241. pseudo_bit_t TS_TX_SPEED[3];
  4242. pseudo_bit_t _unused_1[16];
  4243. pseudo_bit_t TS_TX_TX_CFG[16];
  4244. pseudo_bit_t TS_TX_RX_CFG[16];
  4245. };
  4246. struct QIB_7322_IB_SDTEST_IF_TX_1 {
  4247. PSEUDO_BIT_STRUCT ( struct QIB_7322_IB_SDTEST_IF_TX_1_pb );
  4248. };
  4249. /* Default value: 0x0000000000000000 */
  4250. #define QIB_7322_IB_SDTEST_IF_RX_1_offset 0x00002598UL
  4251. struct QIB_7322_IB_SDTEST_IF_RX_1_pb {
  4252. pseudo_bit_t TS_T_RX_VALID[1];
  4253. pseudo_bit_t TS_3_RX_VALID[1];
  4254. pseudo_bit_t _unused_0[14];
  4255. pseudo_bit_t TS_RX_A[8];
  4256. pseudo_bit_t TS_RX_B[8];
  4257. pseudo_bit_t TS_RX_TX_CFG[16];
  4258. pseudo_bit_t TS_RX_RX_CFG[16];
  4259. };
  4260. struct QIB_7322_IB_SDTEST_IF_RX_1 {
  4261. PSEUDO_BIT_STRUCT ( struct QIB_7322_IB_SDTEST_IF_RX_1_pb );
  4262. };
  4263. /* Default value: 0x0000000000000000 */
  4264. #define QIB_7322_IBNCModeCtrl_1_offset 0x000025b8UL
  4265. struct QIB_7322_IBNCModeCtrl_1_pb {
  4266. pseudo_bit_t TSMEnable_send_TS1[1];
  4267. pseudo_bit_t TSMEnable_send_TS2[1];
  4268. pseudo_bit_t TSMEnable_ignore_TSM_on_rx[1];
  4269. pseudo_bit_t _unused_0[5];
  4270. pseudo_bit_t TSMCode_TS1[9];
  4271. pseudo_bit_t TSMCode_TS2[9];
  4272. pseudo_bit_t _unused_1[6];
  4273. pseudo_bit_t ScrambleCapLocal[1];
  4274. pseudo_bit_t ScrambleCapRemoteMask[1];
  4275. pseudo_bit_t ScrambleCapRemoteForce[1];
  4276. pseudo_bit_t _unused_2[29];
  4277. };
  4278. struct QIB_7322_IBNCModeCtrl_1 {
  4279. PSEUDO_BIT_STRUCT ( struct QIB_7322_IBNCModeCtrl_1_pb );
  4280. };
  4281. /* Default value: 0x0000000000000000 */
  4282. #define QIB_7322_IBSerdesStatus_1_offset 0x000025d0UL
  4283. /* Default value: 0x0000000000000000 */
  4284. #define QIB_7322_IBPCSConfig_1_offset 0x000025d8UL
  4285. struct QIB_7322_IBPCSConfig_1_pb {
  4286. pseudo_bit_t tx_rx_reset[1];
  4287. pseudo_bit_t xcv_treset[1];
  4288. pseudo_bit_t xcv_rreset[1];
  4289. pseudo_bit_t _unused_0[6];
  4290. pseudo_bit_t link_sync_mask[10];
  4291. pseudo_bit_t _unused_1[45];
  4292. };
  4293. struct QIB_7322_IBPCSConfig_1 {
  4294. PSEUDO_BIT_STRUCT ( struct QIB_7322_IBPCSConfig_1_pb );
  4295. };
  4296. /* Default value: 0x0000000000000007 */
  4297. #define QIB_7322_IBSerdesCtrl_1_offset 0x000025e0UL
  4298. struct QIB_7322_IBSerdesCtrl_1_pb {
  4299. pseudo_bit_t CMODE[7];
  4300. pseudo_bit_t _unused_0[1];
  4301. pseudo_bit_t TXIDLE[1];
  4302. pseudo_bit_t RXPD[1];
  4303. pseudo_bit_t TXPD[1];
  4304. pseudo_bit_t PLLPD[1];
  4305. pseudo_bit_t LPEN[1];
  4306. pseudo_bit_t RXLOSEN[1];
  4307. pseudo_bit_t _unused_1[1];
  4308. pseudo_bit_t IB_LAT_MODE[1];
  4309. pseudo_bit_t CGMODE[4];
  4310. pseudo_bit_t CHANNEL_RESET_N[4];
  4311. pseudo_bit_t DISABLE_RXLATOFF_SDR[1];
  4312. pseudo_bit_t DISABLE_RXLATOFF_DDR[1];
  4313. pseudo_bit_t DISABLE_RXLATOFF_QDR[1];
  4314. pseudo_bit_t _unused_2[37];
  4315. };
  4316. struct QIB_7322_IBSerdesCtrl_1 {
  4317. PSEUDO_BIT_STRUCT ( struct QIB_7322_IBSerdesCtrl_1_pb );
  4318. };
  4319. /* Default value: 0x0000000000FFA00F */
  4320. #define QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_offset 0x00002600UL
  4321. struct QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_pb {
  4322. pseudo_bit_t txcn1_ena[3];
  4323. pseudo_bit_t txcn1_xtra_emph0[2];
  4324. pseudo_bit_t txcp1_ena[4];
  4325. pseudo_bit_t txc0_ena[5];
  4326. pseudo_bit_t txampcntl_d2a[4];
  4327. pseudo_bit_t _unused_0[12];
  4328. pseudo_bit_t reset_tx_deemphasis_override[1];
  4329. pseudo_bit_t tx_override_deemphasis_select[1];
  4330. pseudo_bit_t _unused_1[32];
  4331. };
  4332. struct QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1 {
  4333. PSEUDO_BIT_STRUCT ( struct QIB_7322_IBSD_TX_DEEMPHASIS_OVERRIDE_1_pb );
  4334. };
  4335. /* Default value: 0x0000000000000000 */
  4336. #define QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_offset 0x00002640UL
  4337. struct QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_pb {
  4338. pseudo_bit_t static_disable_rxenadfe_sdr_ch0[8];
  4339. pseudo_bit_t static_disable_rxenadfe_sdr_ch1[8];
  4340. pseudo_bit_t static_disable_rxenadfe_sdr_ch2[8];
  4341. pseudo_bit_t static_disable_rxenadfe_sdr_ch3[8];
  4342. pseudo_bit_t static_disable_rxenale_sdr_ch0[1];
  4343. pseudo_bit_t static_disable_rxenale_sdr_ch1[1];
  4344. pseudo_bit_t static_disable_rxenale_sdr_ch2[1];
  4345. pseudo_bit_t static_disable_rxenale_sdr_ch3[1];
  4346. pseudo_bit_t static_disable_rxenagain_sdr_ch0[1];
  4347. pseudo_bit_t static_disable_rxenagain_sdr_ch1[1];
  4348. pseudo_bit_t static_disable_rxenagain_sdr_ch2[1];
  4349. pseudo_bit_t static_disable_rxenagain_sdr_ch3[1];
  4350. pseudo_bit_t _unused_0[24];
  4351. };
  4352. struct QIB_7322_ADAPT_DISABLE_STATIC_SDR_1 {
  4353. PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_STATIC_SDR_1_pb );
  4354. };
  4355. /* Default value: 0x0000000000000000 */
  4356. #define QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_offset 0x00002648UL
  4357. struct QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_pb {
  4358. pseudo_bit_t dyn_disable_rxenadfe_sdr_ch0[8];
  4359. pseudo_bit_t dyn_disable_rxenadfe_sdr_ch1[8];
  4360. pseudo_bit_t dyn_disable_rxenadfe_sdr_ch2[8];
  4361. pseudo_bit_t dyn_disable_rxenadfe_sdr_ch3[8];
  4362. pseudo_bit_t dyn_disable_rxenale_sdr_ch0[1];
  4363. pseudo_bit_t dyn_disable_rxenale_sdr_ch1[1];
  4364. pseudo_bit_t dyn_disable_rxenale_sdr_ch2[1];
  4365. pseudo_bit_t dyn_disable_rxenale_sdr_ch3[1];
  4366. pseudo_bit_t dyn_disable_rxenagain_sdr_ch0[1];
  4367. pseudo_bit_t dyn_disable_rxenagain_sdr_ch1[1];
  4368. pseudo_bit_t dyn_disable_rxenagain_sdr_ch2[1];
  4369. pseudo_bit_t dyn_disable_rxenagain_sdr_ch3[1];
  4370. pseudo_bit_t _unused_0[24];
  4371. };
  4372. struct QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1 {
  4373. PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_DYNAMIC_SDR_1_pb );
  4374. };
  4375. /* Default value: 0x0000000000000000 */
  4376. #define QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_offset 0x00002650UL
  4377. struct QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_pb {
  4378. pseudo_bit_t static_disable_rxenadfe_ddr_ch0[8];
  4379. pseudo_bit_t static_disable_rxenadfe_ddr_ch1[8];
  4380. pseudo_bit_t static_disable_rxenadfe_ddr_ch2[8];
  4381. pseudo_bit_t static_disable_rxenadfe_ddr_ch3[8];
  4382. pseudo_bit_t static_disable_rxenale_ddr_ch0[1];
  4383. pseudo_bit_t static_disable_rxenale_ddr_ch1[1];
  4384. pseudo_bit_t static_disable_rxenale_ddr_ch2[1];
  4385. pseudo_bit_t static_disable_rxenale_ddr_ch3[1];
  4386. pseudo_bit_t static_disable_rxenagain_ddr_ch0[1];
  4387. pseudo_bit_t static_disable_rxenagain_ddr_ch1[1];
  4388. pseudo_bit_t static_disable_rxenagain_ddr_ch2[1];
  4389. pseudo_bit_t static_disable_rxenagain_ddr_ch3[1];
  4390. pseudo_bit_t _unused_0[24];
  4391. };
  4392. struct QIB_7322_ADAPT_DISABLE_STATIC_DDR_1 {
  4393. PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_STATIC_DDR_1_pb );
  4394. };
  4395. /* Default value: 0x0000000000000000 */
  4396. #define QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_offset 0x00002658UL
  4397. struct QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_pb {
  4398. pseudo_bit_t dyn_disable_rxenadfe_ddr_ch0[8];
  4399. pseudo_bit_t dyn_disable_rxenadfe_ddr_ch1[8];
  4400. pseudo_bit_t dyn_disable_rxenadfe_ddr_ch2[8];
  4401. pseudo_bit_t dyn_disable_rxenadfe_ddr_ch3[8];
  4402. pseudo_bit_t dyn_disable_rxenale_ddr_ch0[1];
  4403. pseudo_bit_t dyn_disable_rxenale_ddr_ch1[1];
  4404. pseudo_bit_t dyn_disable_rxenale_ddr_ch2[1];
  4405. pseudo_bit_t dyn_disable_rxenale_ddr_ch3[1];
  4406. pseudo_bit_t dyn_disable_rxenagain_ddr_ch0[1];
  4407. pseudo_bit_t dyn_disable_rxenagain_ddr_ch1[1];
  4408. pseudo_bit_t dyn_disable_rxenagain_ddr_ch2[1];
  4409. pseudo_bit_t dyn_disable_rxenagain_ddr_ch3[1];
  4410. pseudo_bit_t _unused_0[24];
  4411. };
  4412. struct QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1 {
  4413. PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_DYNAMIC_DDR_1_pb );
  4414. };
  4415. /* Default value: 0x0000000000000000 */
  4416. #define QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_offset 0x00002660UL
  4417. struct QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_pb {
  4418. pseudo_bit_t static_disable_rxenadfe_qdr_ch0[8];
  4419. pseudo_bit_t static_disable_rxenadfe_qdr_ch1[8];
  4420. pseudo_bit_t static_disable_rxenadfe_qdr_ch2[8];
  4421. pseudo_bit_t static_disable_rxenadfe_qdr_ch3[8];
  4422. pseudo_bit_t static_disable_rxenale_qdr_ch0[1];
  4423. pseudo_bit_t static_disable_rxenale_qdr_ch1[1];
  4424. pseudo_bit_t static_disable_rxenale_qdr_ch2[1];
  4425. pseudo_bit_t static_disable_rxenale_qdr_ch3[1];
  4426. pseudo_bit_t static_disable_rxenagain_qdr_ch0[1];
  4427. pseudo_bit_t static_disable_rxenagain_qdr_ch1[1];
  4428. pseudo_bit_t static_disable_rxenagain_qdr_ch2[1];
  4429. pseudo_bit_t static_disable_rxenagain_qdr_ch3[1];
  4430. pseudo_bit_t _unused_0[24];
  4431. };
  4432. struct QIB_7322_ADAPT_DISABLE_STATIC_QDR_1 {
  4433. PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_STATIC_QDR_1_pb );
  4434. };
  4435. /* Default value: 0x0000000000000000 */
  4436. #define QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_offset 0x00002668UL
  4437. struct QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_pb {
  4438. pseudo_bit_t dyn_disable_rxenadfe_qdr_ch0[8];
  4439. pseudo_bit_t dyn_disable_rxenadfe_qdr_ch1[8];
  4440. pseudo_bit_t dyn_disable_rxenadfe_qdr_ch2[8];
  4441. pseudo_bit_t dyn_disable_rxenadfe_qdr_ch3[8];
  4442. pseudo_bit_t dyn_disable_rxenale_qdr_ch0[1];
  4443. pseudo_bit_t dyn_disable_rxenale_qdr_ch1[1];
  4444. pseudo_bit_t dyn_disable_rxenale_qdr_ch2[1];
  4445. pseudo_bit_t dyn_disable_rxenale_qdr_ch3[1];
  4446. pseudo_bit_t dyn_disable_rxenagain_qdr_ch0[1];
  4447. pseudo_bit_t dyn_disable_rxenagain_qdr_ch1[1];
  4448. pseudo_bit_t dyn_disable_rxenagain_qdr_ch2[1];
  4449. pseudo_bit_t dyn_disable_rxenagain_qdr_ch3[1];
  4450. pseudo_bit_t _unused_0[24];
  4451. };
  4452. struct QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1 {
  4453. PSEUDO_BIT_STRUCT ( struct QIB_7322_ADAPT_DISABLE_DYNAMIC_QDR_1_pb );
  4454. };
  4455. /* Default value: 0x0000000000000000 */
  4456. #define QIB_7322_ADAPT_DISABLE_TIMER_THRESHOLD_1_offset 0x00002670UL
  4457. /* Default value: 0x0000000000000000 */
  4458. #define QIB_7322_RxBufrUnCorErrLogA_1_offset 0x00002800UL
  4459. struct QIB_7322_RxBufrUnCorErrLogA_1_pb {
  4460. pseudo_bit_t RxBufrUnCorErrData_63_0[64];
  4461. };
  4462. struct QIB_7322_RxBufrUnCorErrLogA_1 {
  4463. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrUnCorErrLogA_1_pb );
  4464. };
  4465. /* Default value: 0x0000000000000000 */
  4466. #define QIB_7322_RxBufrUnCorErrLogB_1_offset 0x00002808UL
  4467. struct QIB_7322_RxBufrUnCorErrLogB_1_pb {
  4468. pseudo_bit_t RxBufrUnCorErrData_127_64[64];
  4469. };
  4470. struct QIB_7322_RxBufrUnCorErrLogB_1 {
  4471. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrUnCorErrLogB_1_pb );
  4472. };
  4473. /* Default value: 0x0000000000000000 */
  4474. #define QIB_7322_RxBufrUnCorErrLogC_1_offset 0x00002810UL
  4475. struct QIB_7322_RxBufrUnCorErrLogC_1_pb {
  4476. pseudo_bit_t RxBufrUnCorErrData_191_128[64];
  4477. };
  4478. struct QIB_7322_RxBufrUnCorErrLogC_1 {
  4479. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrUnCorErrLogC_1_pb );
  4480. };
  4481. /* Default value: 0x0000000000000000 */
  4482. #define QIB_7322_RxBufrUnCorErrLogD_1_offset 0x00002818UL
  4483. struct QIB_7322_RxBufrUnCorErrLogD_1_pb {
  4484. pseudo_bit_t RxBufrUnCorErrData_255_192[64];
  4485. };
  4486. struct QIB_7322_RxBufrUnCorErrLogD_1 {
  4487. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrUnCorErrLogD_1_pb );
  4488. };
  4489. /* Default value: 0x0000000000000000 */
  4490. #define QIB_7322_RxBufrUnCorErrLogE_1_offset 0x00002820UL
  4491. struct QIB_7322_RxBufrUnCorErrLogE_1_pb {
  4492. pseudo_bit_t RxBufrUnCorErrData_258_256[3];
  4493. pseudo_bit_t RxBufrUnCorErrCheckBit_36_0[37];
  4494. pseudo_bit_t RxBufrUnCorErrAddr_15_0[16];
  4495. pseudo_bit_t _unused_0[8];
  4496. };
  4497. struct QIB_7322_RxBufrUnCorErrLogE_1 {
  4498. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrUnCorErrLogE_1_pb );
  4499. };
  4500. /* Default value: 0x0000000000000000 */
  4501. #define QIB_7322_RxFlagUnCorErrLogA_1_offset 0x00002828UL
  4502. struct QIB_7322_RxFlagUnCorErrLogA_1_pb {
  4503. pseudo_bit_t RxFlagUnCorErrData_63_0[64];
  4504. };
  4505. struct QIB_7322_RxFlagUnCorErrLogA_1 {
  4506. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxFlagUnCorErrLogA_1_pb );
  4507. };
  4508. /* Default value: 0x0000000000000000 */
  4509. #define QIB_7322_RxFlagUnCorErrLogB_1_offset 0x00002830UL
  4510. struct QIB_7322_RxFlagUnCorErrLogB_1_pb {
  4511. pseudo_bit_t RxFlagUnCorErrCheckBit_7_0[8];
  4512. pseudo_bit_t RxFlagUnCorErrAddr_12_0[13];
  4513. pseudo_bit_t _unused_0[43];
  4514. };
  4515. struct QIB_7322_RxFlagUnCorErrLogB_1 {
  4516. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxFlagUnCorErrLogB_1_pb );
  4517. };
  4518. /* Default value: 0x0000000000000000 */
  4519. #define QIB_7322_RxLkupiqUnCorErrLogA_1_offset 0x00002840UL
  4520. struct QIB_7322_RxLkupiqUnCorErrLogA_1_pb {
  4521. pseudo_bit_t RxLkupiqUnCorErrData_45_0[46];
  4522. pseudo_bit_t RxLkupiqUnCorErrCheckBit_7_0[8];
  4523. pseudo_bit_t _unused_0[10];
  4524. };
  4525. struct QIB_7322_RxLkupiqUnCorErrLogA_1 {
  4526. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxLkupiqUnCorErrLogA_1_pb );
  4527. };
  4528. /* Default value: 0x0000000000000000 */
  4529. #define QIB_7322_RxLkupiqUnCorErrLogB_1_offset 0x00002848UL
  4530. struct QIB_7322_RxLkupiqUnCorErrLogB_1_pb {
  4531. pseudo_bit_t RxLkupiqUnCorErrAddr_12_0[13];
  4532. pseudo_bit_t _unused_0[51];
  4533. };
  4534. struct QIB_7322_RxLkupiqUnCorErrLogB_1 {
  4535. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxLkupiqUnCorErrLogB_1_pb );
  4536. };
  4537. /* Default value: 0x0000000000000000 */
  4538. #define QIB_7322_RxHdrFifoUnCorErrLogA_1_offset 0x00002850UL
  4539. struct QIB_7322_RxHdrFifoUnCorErrLogA_1_pb {
  4540. pseudo_bit_t RxHdrFifoUnCorErrData_63_0[64];
  4541. };
  4542. struct QIB_7322_RxHdrFifoUnCorErrLogA_1 {
  4543. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoUnCorErrLogA_1_pb );
  4544. };
  4545. /* Default value: 0x0000000000000000 */
  4546. #define QIB_7322_RxHdrFifoUnCorErrLogB_1_offset 0x00002858UL
  4547. struct QIB_7322_RxHdrFifoUnCorErrLogB_1_pb {
  4548. pseudo_bit_t RxHdrFifoUnCorErrData_127_64[64];
  4549. };
  4550. struct QIB_7322_RxHdrFifoUnCorErrLogB_1 {
  4551. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoUnCorErrLogB_1_pb );
  4552. };
  4553. /* Default value: 0x0000000000000000 */
  4554. #define QIB_7322_RxHdrFifoUnCorErrLogC_1_offset 0x00002860UL
  4555. struct QIB_7322_RxHdrFifoUnCorErrLogC_1_pb {
  4556. pseudo_bit_t RxHdrFifoUnCorErrCheckBit_15_0[16];
  4557. pseudo_bit_t RxHdrFifoUnCorErrAddr_10_0[11];
  4558. pseudo_bit_t _unused_0[37];
  4559. };
  4560. struct QIB_7322_RxHdrFifoUnCorErrLogC_1 {
  4561. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoUnCorErrLogC_1_pb );
  4562. };
  4563. /* Default value: 0x0000000000000000 */
  4564. #define QIB_7322_RxDataFifoUnCorErrLogA_1_offset 0x00002868UL
  4565. struct QIB_7322_RxDataFifoUnCorErrLogA_1_pb {
  4566. pseudo_bit_t RxDataFifoUnCorErrData_63_0[64];
  4567. };
  4568. struct QIB_7322_RxDataFifoUnCorErrLogA_1 {
  4569. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxDataFifoUnCorErrLogA_1_pb );
  4570. };
  4571. /* Default value: 0x0000000000000000 */
  4572. #define QIB_7322_RxDataFifoUnCorErrLogB_1_offset 0x00002870UL
  4573. struct QIB_7322_RxDataFifoUnCorErrLogB_1_pb {
  4574. pseudo_bit_t RxDataFifoUnCorErrData_127_64[64];
  4575. };
  4576. struct QIB_7322_RxDataFifoUnCorErrLogB_1 {
  4577. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxDataFifoUnCorErrLogB_1_pb );
  4578. };
  4579. /* Default value: 0x0000000000000000 */
  4580. #define QIB_7322_RxDataFifoUnCorErrLogC_1_offset 0x00002878UL
  4581. struct QIB_7322_RxDataFifoUnCorErrLogC_1_pb {
  4582. pseudo_bit_t RxDataFifoUnCorErrCheckBit_15_0[16];
  4583. pseudo_bit_t RxDataFifoUnCorErrAddr_10_0[11];
  4584. pseudo_bit_t _unused_0[37];
  4585. };
  4586. struct QIB_7322_RxDataFifoUnCorErrLogC_1 {
  4587. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxDataFifoUnCorErrLogC_1_pb );
  4588. };
  4589. /* Default value: 0x0000000000000000 */
  4590. #define QIB_7322_LaFifoArray0UnCorErrLog_1_offset 0x00002880UL
  4591. struct QIB_7322_LaFifoArray0UnCorErrLog_1_pb {
  4592. pseudo_bit_t LaFifoArray0UnCorErrData_34_0[35];
  4593. pseudo_bit_t LaFifoArray0UnCorErrCheckBit_10_0[11];
  4594. pseudo_bit_t LaFifoArray0UnCorErrAddr_10_0[11];
  4595. pseudo_bit_t _unused_0[7];
  4596. };
  4597. struct QIB_7322_LaFifoArray0UnCorErrLog_1 {
  4598. PSEUDO_BIT_STRUCT ( struct QIB_7322_LaFifoArray0UnCorErrLog_1_pb );
  4599. };
  4600. /* Default value: 0x0000000000000000 */
  4601. #define QIB_7322_RmFifoArrayUnCorErrLogA_1_offset 0x000028c0UL
  4602. struct QIB_7322_RmFifoArrayUnCorErrLogA_1_pb {
  4603. pseudo_bit_t RmFifoArrayUnCorErrData_63_0[64];
  4604. };
  4605. struct QIB_7322_RmFifoArrayUnCorErrLogA_1 {
  4606. PSEUDO_BIT_STRUCT ( struct QIB_7322_RmFifoArrayUnCorErrLogA_1_pb );
  4607. };
  4608. /* Default value: 0x0000000000000000 */
  4609. #define QIB_7322_RmFifoArrayUnCorErrLogB_1_offset 0x000028c8UL
  4610. struct QIB_7322_RmFifoArrayUnCorErrLogB_1_pb {
  4611. pseudo_bit_t RmFifoArrayUnCorErrData_127_64[64];
  4612. };
  4613. struct QIB_7322_RmFifoArrayUnCorErrLogB_1 {
  4614. PSEUDO_BIT_STRUCT ( struct QIB_7322_RmFifoArrayUnCorErrLogB_1_pb );
  4615. };
  4616. /* Default value: 0x0000000000000000 */
  4617. #define QIB_7322_RmFifoArrayUnCorErrLogC_1_offset 0x000028d0UL
  4618. struct QIB_7322_RmFifoArrayUnCorErrLogC_1_pb {
  4619. pseudo_bit_t RmFifoArrayUnCorErrCheckBit_27_0[28];
  4620. pseudo_bit_t RmFifoArrayUnCorErrAddr_13_0[14];
  4621. pseudo_bit_t _unused_0[18];
  4622. pseudo_bit_t RmFifoArrayUnCorErrDword_3_0[4];
  4623. };
  4624. struct QIB_7322_RmFifoArrayUnCorErrLogC_1 {
  4625. PSEUDO_BIT_STRUCT ( struct QIB_7322_RmFifoArrayUnCorErrLogC_1_pb );
  4626. };
  4627. /* Default value: 0x0000000000000000 */
  4628. #define QIB_7322_RxBufrCorErrLogA_1_offset 0x00002900UL
  4629. struct QIB_7322_RxBufrCorErrLogA_1_pb {
  4630. pseudo_bit_t RxBufrCorErrData_63_0[64];
  4631. };
  4632. struct QIB_7322_RxBufrCorErrLogA_1 {
  4633. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrCorErrLogA_1_pb );
  4634. };
  4635. /* Default value: 0x0000000000000000 */
  4636. #define QIB_7322_RxBufrCorErrLogB_1_offset 0x00002908UL
  4637. struct QIB_7322_RxBufrCorErrLogB_1_pb {
  4638. pseudo_bit_t RxBufrCorErrData_127_64[64];
  4639. };
  4640. struct QIB_7322_RxBufrCorErrLogB_1 {
  4641. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrCorErrLogB_1_pb );
  4642. };
  4643. /* Default value: 0x0000000000000000 */
  4644. #define QIB_7322_RxBufrCorErrLogC_1_offset 0x00002910UL
  4645. struct QIB_7322_RxBufrCorErrLogC_1_pb {
  4646. pseudo_bit_t RxBufrCorErrData_191_128[64];
  4647. };
  4648. struct QIB_7322_RxBufrCorErrLogC_1 {
  4649. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrCorErrLogC_1_pb );
  4650. };
  4651. /* Default value: 0x0000000000000000 */
  4652. #define QIB_7322_RxBufrCorErrLogD_1_offset 0x00002918UL
  4653. struct QIB_7322_RxBufrCorErrLogD_1_pb {
  4654. pseudo_bit_t RxBufrCorErrData_255_192[64];
  4655. };
  4656. struct QIB_7322_RxBufrCorErrLogD_1 {
  4657. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrCorErrLogD_1_pb );
  4658. };
  4659. /* Default value: 0x0000000000000000 */
  4660. #define QIB_7322_RxBufrCorErrLogE_1_offset 0x00002920UL
  4661. struct QIB_7322_RxBufrCorErrLogE_1_pb {
  4662. pseudo_bit_t RxBufrCorErrData_258_256[3];
  4663. pseudo_bit_t RxBufrCorErrCheckBit_36_0[37];
  4664. pseudo_bit_t RxBufrCorErrAddr_15_0[16];
  4665. pseudo_bit_t _unused_0[8];
  4666. };
  4667. struct QIB_7322_RxBufrCorErrLogE_1 {
  4668. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxBufrCorErrLogE_1_pb );
  4669. };
  4670. /* Default value: 0x0000000000000000 */
  4671. #define QIB_7322_RxFlagCorErrLogA_1_offset 0x00002928UL
  4672. struct QIB_7322_RxFlagCorErrLogA_1_pb {
  4673. pseudo_bit_t RxFlagCorErrData_63_0[64];
  4674. };
  4675. struct QIB_7322_RxFlagCorErrLogA_1 {
  4676. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxFlagCorErrLogA_1_pb );
  4677. };
  4678. /* Default value: 0x0000000000000000 */
  4679. #define QIB_7322_RxFlagCorErrLogB_1_offset 0x00002930UL
  4680. struct QIB_7322_RxFlagCorErrLogB_1_pb {
  4681. pseudo_bit_t RxFlagCorErrCheckBit_7_0[8];
  4682. pseudo_bit_t RxFlagCorErrAddr_12_0[13];
  4683. pseudo_bit_t _unused_0[43];
  4684. };
  4685. struct QIB_7322_RxFlagCorErrLogB_1 {
  4686. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxFlagCorErrLogB_1_pb );
  4687. };
  4688. /* Default value: 0x0000000000000000 */
  4689. #define QIB_7322_RxLkupiqCorErrLogA_1_offset 0x00002940UL
  4690. struct QIB_7322_RxLkupiqCorErrLogA_1_pb {
  4691. pseudo_bit_t RxLkupiqCorErrData_45_0[46];
  4692. pseudo_bit_t RxLkupiqCorErrCheckBit_7_0[8];
  4693. pseudo_bit_t _unused_0[10];
  4694. };
  4695. struct QIB_7322_RxLkupiqCorErrLogA_1 {
  4696. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxLkupiqCorErrLogA_1_pb );
  4697. };
  4698. /* Default value: 0x0000000000000000 */
  4699. #define QIB_7322_RxLkupiqCorErrLogB_1_offset 0x00002948UL
  4700. struct QIB_7322_RxLkupiqCorErrLogB_1_pb {
  4701. pseudo_bit_t RxLkupiqCorErrAddr_12_0[13];
  4702. pseudo_bit_t _unused_0[51];
  4703. };
  4704. struct QIB_7322_RxLkupiqCorErrLogB_1 {
  4705. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxLkupiqCorErrLogB_1_pb );
  4706. };
  4707. /* Default value: 0x0000000000000000 */
  4708. #define QIB_7322_RxHdrFifoCorErrLogA_1_offset 0x00002950UL
  4709. struct QIB_7322_RxHdrFifoCorErrLogA_1_pb {
  4710. pseudo_bit_t RxHdrFifoCorErrData_63_0[64];
  4711. };
  4712. struct QIB_7322_RxHdrFifoCorErrLogA_1 {
  4713. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoCorErrLogA_1_pb );
  4714. };
  4715. /* Default value: 0x0000000000000000 */
  4716. #define QIB_7322_RxHdrFifoCorErrLogB_1_offset 0x00002958UL
  4717. struct QIB_7322_RxHdrFifoCorErrLogB_1_pb {
  4718. pseudo_bit_t RxHdrFifoCorErrData_127_64[64];
  4719. };
  4720. struct QIB_7322_RxHdrFifoCorErrLogB_1 {
  4721. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoCorErrLogB_1_pb );
  4722. };
  4723. /* Default value: 0x0000000000000000 */
  4724. #define QIB_7322_RxHdrFifoCorErrLogC_1_offset 0x00002960UL
  4725. struct QIB_7322_RxHdrFifoCorErrLogC_1_pb {
  4726. pseudo_bit_t RxHdrFifoCorErrCheckBit_15_0[16];
  4727. pseudo_bit_t RxHdrFifoCorErrAddr_10_0[11];
  4728. pseudo_bit_t _unused_0[37];
  4729. };
  4730. struct QIB_7322_RxHdrFifoCorErrLogC_1 {
  4731. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxHdrFifoCorErrLogC_1_pb );
  4732. };
  4733. /* Default value: 0x0000000000000000 */
  4734. #define QIB_7322_RxDataFifoCorErrLogA_1_offset 0x00002968UL
  4735. struct QIB_7322_RxDataFifoCorErrLogA_1_pb {
  4736. pseudo_bit_t RxDataFifoCorErrData_63_0[64];
  4737. };
  4738. struct QIB_7322_RxDataFifoCorErrLogA_1 {
  4739. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxDataFifoCorErrLogA_1_pb );
  4740. };
  4741. /* Default value: 0x0000000000000000 */
  4742. #define QIB_7322_RxDataFifoCorErrLogB_1_offset 0x00002970UL
  4743. struct QIB_7322_RxDataFifoCorErrLogB_1_pb {
  4744. pseudo_bit_t RxDataFifoCorErrData_127_64[64];
  4745. };
  4746. struct QIB_7322_RxDataFifoCorErrLogB_1 {
  4747. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxDataFifoCorErrLogB_1_pb );
  4748. };
  4749. /* Default value: 0x0000000000000000 */
  4750. #define QIB_7322_RxDataFifoCorErrLogC_1_offset 0x00002978UL
  4751. struct QIB_7322_RxDataFifoCorErrLogC_1_pb {
  4752. pseudo_bit_t RxDataFifoCorErrCheckBit_15_0[16];
  4753. pseudo_bit_t RxDataFifoCorErrAddr_10_0[11];
  4754. pseudo_bit_t _unused_0[37];
  4755. };
  4756. struct QIB_7322_RxDataFifoCorErrLogC_1 {
  4757. PSEUDO_BIT_STRUCT ( struct QIB_7322_RxDataFifoCorErrLogC_1_pb );
  4758. };
  4759. /* Default value: 0x0000000000000000 */
  4760. #define QIB_7322_LaFifoArray0CorErrLog_1_offset 0x00002980UL
  4761. struct QIB_7322_LaFifoArray0CorErrLog_1_pb {
  4762. pseudo_bit_t LaFifoArray0CorErrData_34_0[35];
  4763. pseudo_bit_t LaFifoArray0CorErrCheckBit_10_0[11];
  4764. pseudo_bit_t LaFifoArray0CorErrAddr_10_0[11];
  4765. pseudo_bit_t _unused_0[7];
  4766. };
  4767. struct QIB_7322_LaFifoArray0CorErrLog_1 {
  4768. PSEUDO_BIT_STRUCT ( struct QIB_7322_LaFifoArray0CorErrLog_1_pb );
  4769. };
  4770. /* Default value: 0x0000000000000000 */
  4771. #define QIB_7322_RmFifoArrayCorErrLogA_1_offset 0x000029c0UL
  4772. struct QIB_7322_RmFifoArrayCorErrLogA_1_pb {
  4773. pseudo_bit_t RmFifoArrayCorErrData_63_0[64];
  4774. };
  4775. struct QIB_7322_RmFifoArrayCorErrLogA_1 {
  4776. PSEUDO_BIT_STRUCT ( struct QIB_7322_RmFifoArrayCorErrLogA_1_pb );
  4777. };
  4778. /* Default value: 0x0000000000000000 */
  4779. #define QIB_7322_RmFifoArrayCorErrLogB_1_offset 0x000029c8UL
  4780. struct QIB_7322_RmFifoArrayCorErrLogB_1_pb {
  4781. pseudo_bit_t RmFifoArrayCorErrData_127_64[64];
  4782. };
  4783. struct QIB_7322_RmFifoArrayCorErrLogB_1 {
  4784. PSEUDO_BIT_STRUCT ( struct QIB_7322_RmFifoArrayCorErrLogB_1_pb );
  4785. };
  4786. /* Default value: 0x0000000000000000 */
  4787. #define QIB_7322_RmFifoArrayCorErrLogC_1_offset 0x000029d0UL
  4788. struct QIB_7322_RmFifoArrayCorErrLogC_1_pb {
  4789. pseudo_bit_t RmFifoArrayCorErrCheckBit_27_0[28];
  4790. pseudo_bit_t RmFifoArrayCorErrAddr_13_0[14];
  4791. pseudo_bit_t _unused_0[18];
  4792. pseudo_bit_t RmFifoArrayCorErrDword_3_0[4];
  4793. };
  4794. struct QIB_7322_RmFifoArrayCorErrLogC_1 {
  4795. PSEUDO_BIT_STRUCT ( struct QIB_7322_RmFifoArrayCorErrLogC_1_pb );
  4796. };
  4797. /* Default value: 0x0000000000000000 */
  4798. #define QIB_7322_HighPriorityLimit_1_offset 0x00002bc0UL
  4799. struct QIB_7322_HighPriorityLimit_1_pb {
  4800. pseudo_bit_t Limit[8];
  4801. pseudo_bit_t _unused_0[56];
  4802. };
  4803. struct QIB_7322_HighPriorityLimit_1 {
  4804. PSEUDO_BIT_STRUCT ( struct QIB_7322_HighPriorityLimit_1_pb );
  4805. };
  4806. /* Default value: 0x0000000000000000 */
  4807. #define QIB_7322_LowPriority0_1_offset 0x00002c00UL
  4808. struct QIB_7322_LowPriority0_1_pb {
  4809. pseudo_bit_t Weight[8];
  4810. pseudo_bit_t _unused_0[8];
  4811. pseudo_bit_t VirtualLane[3];
  4812. pseudo_bit_t _unused_1[45];
  4813. };
  4814. struct QIB_7322_LowPriority0_1 {
  4815. PSEUDO_BIT_STRUCT ( struct QIB_7322_LowPriority0_1_pb );
  4816. };
  4817. /* Default value: 0x0000000000000000 */
  4818. #define QIB_7322_HighPriority0_1_offset 0x00002e00UL
  4819. struct QIB_7322_HighPriority0_1_pb {
  4820. pseudo_bit_t Weight[8];
  4821. pseudo_bit_t _unused_0[8];
  4822. pseudo_bit_t VirtualLane[3];
  4823. pseudo_bit_t _unused_1[45];
  4824. };
  4825. struct QIB_7322_HighPriority0_1 {
  4826. PSEUDO_BIT_STRUCT ( struct QIB_7322_HighPriority0_1_pb );
  4827. };
  4828. /* Default value: 0x0000000000000000 */
  4829. #define QIB_7322_SendBufAvail0_offset 0x00003000UL
  4830. struct QIB_7322_SendBufAvail0_pb {
  4831. pseudo_bit_t SendBuf_31_0[64];
  4832. };
  4833. struct QIB_7322_SendBufAvail0 {
  4834. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufAvail0_pb );
  4835. };
  4836. /* Default value: 0x0000000000000000 */
  4837. #define QIB_7322_MsixTable_offset 0x00008000UL
  4838. /* Default value: 0x0000000000000000 */
  4839. #define QIB_7322_MsixPba_offset 0x00009000UL
  4840. /* Default value: 0x0000000000000000 */
  4841. #define QIB_7322_LAMemory_offset 0x0000a000UL
  4842. /* Default value: 0x0000000000000000 */
  4843. #define QIB_7322_LBIntCnt_offset 0x00011000UL
  4844. /* Default value: 0x0000000000000000 */
  4845. #define QIB_7322_LBFlowStallCnt_offset 0x00011008UL
  4846. /* Default value: 0x0000000000000000 */
  4847. #define QIB_7322_RxTIDFullErrCnt_offset 0x000110d0UL
  4848. /* Default value: 0x0000000000000000 */
  4849. #define QIB_7322_RxTIDValidErrCnt_offset 0x000110d8UL
  4850. /* Default value: 0x0000000000000000 */
  4851. #define QIB_7322_RxP0HdrEgrOvflCnt_offset 0x000110e8UL
  4852. /* Default value: 0x0000000000000000 */
  4853. #define QIB_7322_PcieRetryBufDiagQwordCnt_offset 0x000111a0UL
  4854. /* Default value: 0x0000000000000000 */
  4855. #define QIB_7322_RxTidFlowDropCnt_offset 0x000111e0UL
  4856. /* Default value: 0x0000000000000000 */
  4857. #define QIB_7322_LBIntCnt_0_offset 0x00012000UL
  4858. /* Default value: 0x0000000000000000 */
  4859. #define QIB_7322_TxCreditUpToDateTimeOut_0_offset 0x00012008UL
  4860. /* Default value: 0x0000000000000000 */
  4861. #define QIB_7322_TxSDmaDescCnt_0_offset 0x00012010UL
  4862. /* Default value: 0x0000000000000000 */
  4863. #define QIB_7322_TxUnsupVLErrCnt_0_offset 0x00012018UL
  4864. /* Default value: 0x0000000000000000 */
  4865. #define QIB_7322_TxDataPktCnt_0_offset 0x00012020UL
  4866. /* Default value: 0x0000000000000000 */
  4867. #define QIB_7322_TxFlowPktCnt_0_offset 0x00012028UL
  4868. /* Default value: 0x0000000000000000 */
  4869. #define QIB_7322_TxDwordCnt_0_offset 0x00012030UL
  4870. /* Default value: 0x0000000000000000 */
  4871. #define QIB_7322_TxLenErrCnt_0_offset 0x00012038UL
  4872. /* Default value: 0x0000000000000000 */
  4873. #define QIB_7322_TxMaxMinLenErrCnt_0_offset 0x00012040UL
  4874. /* Default value: 0x0000000000000000 */
  4875. #define QIB_7322_TxUnderrunCnt_0_offset 0x00012048UL
  4876. /* Default value: 0x0000000000000000 */
  4877. #define QIB_7322_TxFlowStallCnt_0_offset 0x00012050UL
  4878. /* Default value: 0x0000000000000000 */
  4879. #define QIB_7322_TxDroppedPktCnt_0_offset 0x00012058UL
  4880. /* Default value: 0x0000000000000000 */
  4881. #define QIB_7322_RxDroppedPktCnt_0_offset 0x00012060UL
  4882. /* Default value: 0x0000000000000000 */
  4883. #define QIB_7322_RxDataPktCnt_0_offset 0x00012068UL
  4884. /* Default value: 0x0000000000000000 */
  4885. #define QIB_7322_RxFlowPktCnt_0_offset 0x00012070UL
  4886. /* Default value: 0x0000000000000000 */
  4887. #define QIB_7322_RxDwordCnt_0_offset 0x00012078UL
  4888. /* Default value: 0x0000000000000000 */
  4889. #define QIB_7322_RxLenErrCnt_0_offset 0x00012080UL
  4890. /* Default value: 0x0000000000000000 */
  4891. #define QIB_7322_RxMaxMinLenErrCnt_0_offset 0x00012088UL
  4892. /* Default value: 0x0000000000000000 */
  4893. #define QIB_7322_RxICRCErrCnt_0_offset 0x00012090UL
  4894. /* Default value: 0x0000000000000000 */
  4895. #define QIB_7322_RxVCRCErrCnt_0_offset 0x00012098UL
  4896. /* Default value: 0x0000000000000000 */
  4897. #define QIB_7322_RxFlowCtrlViolCnt_0_offset 0x000120a0UL
  4898. /* Default value: 0x0000000000000000 */
  4899. #define QIB_7322_RxVersionErrCnt_0_offset 0x000120a8UL
  4900. /* Default value: 0x0000000000000000 */
  4901. #define QIB_7322_RxLinkMalformCnt_0_offset 0x000120b0UL
  4902. /* Default value: 0x0000000000000000 */
  4903. #define QIB_7322_RxEBPCnt_0_offset 0x000120b8UL
  4904. /* Default value: 0x0000000000000000 */
  4905. #define QIB_7322_RxLPCRCErrCnt_0_offset 0x000120c0UL
  4906. /* Default value: 0x0000000000000000 */
  4907. #define QIB_7322_RxBufOvflCnt_0_offset 0x000120c8UL
  4908. /* Default value: 0x0000000000000000 */
  4909. #define QIB_7322_RxLenTruncateCnt_0_offset 0x000120d0UL
  4910. /* Default value: 0x0000000000000000 */
  4911. #define QIB_7322_RxPKeyMismatchCnt_0_offset 0x000120e0UL
  4912. /* Default value: 0x0000000000000000 */
  4913. #define QIB_7322_IBLinkDownedCnt_0_offset 0x00012180UL
  4914. /* Default value: 0x0000000000000000 */
  4915. #define QIB_7322_IBSymbolErrCnt_0_offset 0x00012188UL
  4916. /* Default value: 0x0000000000000000 */
  4917. #define QIB_7322_IBStatusChangeCnt_0_offset 0x00012190UL
  4918. /* Default value: 0x0000000000000000 */
  4919. #define QIB_7322_IBLinkErrRecoveryCnt_0_offset 0x00012198UL
  4920. /* Default value: 0x0000000000000000 */
  4921. #define QIB_7322_ExcessBufferOvflCnt_0_offset 0x000121a8UL
  4922. /* Default value: 0x0000000000000000 */
  4923. #define QIB_7322_LocalLinkIntegrityErrCnt_0_offset 0x000121b0UL
  4924. /* Default value: 0x0000000000000000 */
  4925. #define QIB_7322_RxVlErrCnt_0_offset 0x000121b8UL
  4926. /* Default value: 0x0000000000000000 */
  4927. #define QIB_7322_RxDlidFltrCnt_0_offset 0x000121c0UL
  4928. /* Default value: 0x0000000000000000 */
  4929. #define QIB_7322_RxVL15DroppedPktCnt_0_offset 0x000121c8UL
  4930. /* Default value: 0x0000000000000000 */
  4931. #define QIB_7322_RxOtherLocalPhyErrCnt_0_offset 0x000121d0UL
  4932. /* Default value: 0x0000000000000000 */
  4933. #define QIB_7322_RxQPInvalidContextCnt_0_offset 0x000121d8UL
  4934. /* Default value: 0x0000000000000000 */
  4935. #define QIB_7322_TxHeadersErrCnt_0_offset 0x000121f8UL
  4936. /* Default value: 0x0000000000000000 */
  4937. #define QIB_7322_PSRcvDataCount_0_offset 0x00012218UL
  4938. /* Default value: 0x0000000000000000 */
  4939. #define QIB_7322_PSRcvPktsCount_0_offset 0x00012220UL
  4940. /* Default value: 0x0000000000000000 */
  4941. #define QIB_7322_PSXmitDataCount_0_offset 0x00012228UL
  4942. /* Default value: 0x0000000000000000 */
  4943. #define QIB_7322_PSXmitPktsCount_0_offset 0x00012230UL
  4944. /* Default value: 0x0000000000000000 */
  4945. #define QIB_7322_PSXmitWaitCount_0_offset 0x00012238UL
  4946. /* Default value: 0x0000000000000000 */
  4947. #define QIB_7322_LBIntCnt_1_offset 0x00013000UL
  4948. /* Default value: 0x0000000000000000 */
  4949. #define QIB_7322_TxCreditUpToDateTimeOut_1_offset 0x00013008UL
  4950. /* Default value: 0x0000000000000000 */
  4951. #define QIB_7322_TxSDmaDescCnt_1_offset 0x00013010UL
  4952. /* Default value: 0x0000000000000000 */
  4953. #define QIB_7322_TxUnsupVLErrCnt_1_offset 0x00013018UL
  4954. /* Default value: 0x0000000000000000 */
  4955. #define QIB_7322_TxDataPktCnt_1_offset 0x00013020UL
  4956. /* Default value: 0x0000000000000000 */
  4957. #define QIB_7322_TxFlowPktCnt_1_offset 0x00013028UL
  4958. /* Default value: 0x0000000000000000 */
  4959. #define QIB_7322_TxDwordCnt_1_offset 0x00013030UL
  4960. /* Default value: 0x0000000000000000 */
  4961. #define QIB_7322_TxLenErrCnt_1_offset 0x00013038UL
  4962. /* Default value: 0x0000000000000000 */
  4963. #define QIB_7322_TxMaxMinLenErrCnt_1_offset 0x00013040UL
  4964. /* Default value: 0x0000000000000000 */
  4965. #define QIB_7322_TxUnderrunCnt_1_offset 0x00013048UL
  4966. /* Default value: 0x0000000000000000 */
  4967. #define QIB_7322_TxFlowStallCnt_1_offset 0x00013050UL
  4968. /* Default value: 0x0000000000000000 */
  4969. #define QIB_7322_TxDroppedPktCnt_1_offset 0x00013058UL
  4970. /* Default value: 0x0000000000000000 */
  4971. #define QIB_7322_RxDroppedPktCnt_1_offset 0x00013060UL
  4972. /* Default value: 0x0000000000000000 */
  4973. #define QIB_7322_RxDataPktCnt_1_offset 0x00013068UL
  4974. /* Default value: 0x0000000000000000 */
  4975. #define QIB_7322_RxFlowPktCnt_1_offset 0x00013070UL
  4976. /* Default value: 0x0000000000000000 */
  4977. #define QIB_7322_RxDwordCnt_1_offset 0x00013078UL
  4978. /* Default value: 0x0000000000000000 */
  4979. #define QIB_7322_RxLenErrCnt_1_offset 0x00013080UL
  4980. /* Default value: 0x0000000000000000 */
  4981. #define QIB_7322_RxMaxMinLenErrCnt_1_offset 0x00013088UL
  4982. /* Default value: 0x0000000000000000 */
  4983. #define QIB_7322_RxICRCErrCnt_1_offset 0x00013090UL
  4984. /* Default value: 0x0000000000000000 */
  4985. #define QIB_7322_RxVCRCErrCnt_1_offset 0x00013098UL
  4986. /* Default value: 0x0000000000000000 */
  4987. #define QIB_7322_RxFlowCtrlViolCnt_1_offset 0x000130a0UL
  4988. /* Default value: 0x0000000000000000 */
  4989. #define QIB_7322_RxVersionErrCnt_1_offset 0x000130a8UL
  4990. /* Default value: 0x0000000000000000 */
  4991. #define QIB_7322_RxLinkMalformCnt_1_offset 0x000130b0UL
  4992. /* Default value: 0x0000000000000000 */
  4993. #define QIB_7322_RxEBPCnt_1_offset 0x000130b8UL
  4994. /* Default value: 0x0000000000000000 */
  4995. #define QIB_7322_RxLPCRCErrCnt_1_offset 0x000130c0UL
  4996. /* Default value: 0x0000000000000000 */
  4997. #define QIB_7322_RxBufOvflCnt_1_offset 0x000130c8UL
  4998. /* Default value: 0x0000000000000000 */
  4999. #define QIB_7322_RxLenTruncateCnt_1_offset 0x000130d0UL
  5000. /* Default value: 0x0000000000000000 */
  5001. #define QIB_7322_RxPKeyMismatchCnt_1_offset 0x000130e0UL
  5002. /* Default value: 0x0000000000000000 */
  5003. #define QIB_7322_IBLinkDownedCnt_1_offset 0x00013180UL
  5004. /* Default value: 0x0000000000000000 */
  5005. #define QIB_7322_IBSymbolErrCnt_1_offset 0x00013188UL
  5006. /* Default value: 0x0000000000000000 */
  5007. #define QIB_7322_IBStatusChangeCnt_1_offset 0x00013190UL
  5008. /* Default value: 0x0000000000000000 */
  5009. #define QIB_7322_IBLinkErrRecoveryCnt_1_offset 0x00013198UL
  5010. /* Default value: 0x0000000000000000 */
  5011. #define QIB_7322_ExcessBufferOvflCnt_1_offset 0x000131a8UL
  5012. /* Default value: 0x0000000000000000 */
  5013. #define QIB_7322_LocalLinkIntegrityErrCnt_1_offset 0x000131b0UL
  5014. /* Default value: 0x0000000000000000 */
  5015. #define QIB_7322_RxVlErrCnt_1_offset 0x000131b8UL
  5016. /* Default value: 0x0000000000000000 */
  5017. #define QIB_7322_RxDlidFltrCnt_1_offset 0x000131c0UL
  5018. /* Default value: 0x0000000000000000 */
  5019. #define QIB_7322_RxVL15DroppedPktCnt_1_offset 0x000131c8UL
  5020. /* Default value: 0x0000000000000000 */
  5021. #define QIB_7322_RxOtherLocalPhyErrCnt_1_offset 0x000131d0UL
  5022. /* Default value: 0x0000000000000000 */
  5023. #define QIB_7322_RxQPInvalidContextCnt_1_offset 0x000131d8UL
  5024. /* Default value: 0x0000000000000000 */
  5025. #define QIB_7322_TxHeadersErrCnt_1_offset 0x000131f8UL
  5026. /* Default value: 0x0000000000000000 */
  5027. #define QIB_7322_PSRcvDataCount_1_offset 0x00013218UL
  5028. /* Default value: 0x0000000000000000 */
  5029. #define QIB_7322_PSRcvPktsCount_1_offset 0x00013220UL
  5030. /* Default value: 0x0000000000000000 */
  5031. #define QIB_7322_PSXmitDataCount_1_offset 0x00013228UL
  5032. /* Default value: 0x0000000000000000 */
  5033. #define QIB_7322_PSXmitPktsCount_1_offset 0x00013230UL
  5034. /* Default value: 0x0000000000000000 */
  5035. #define QIB_7322_PSXmitWaitCount_1_offset 0x00013238UL
  5036. /* Default value: 0x0000000000000000 */
  5037. #define QIB_7322_RcvEgrArray_offset 0x00014000UL
  5038. struct QIB_7322_RcvEgrArray_pb {
  5039. pseudo_bit_t RT_Addr[37];
  5040. pseudo_bit_t RT_BufSize[3];
  5041. pseudo_bit_t _unused_0[24];
  5042. };
  5043. struct QIB_7322_RcvEgrArray {
  5044. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvEgrArray_pb );
  5045. };
  5046. /* Default value: 0x0000000000000000 */
  5047. #define QIB_7322_RcvTIDArray0_offset 0x00050000UL
  5048. struct QIB_7322_RcvTIDArray0_pb {
  5049. pseudo_bit_t RT_Addr[37];
  5050. pseudo_bit_t RT_BufSize[3];
  5051. pseudo_bit_t _unused_0[24];
  5052. };
  5053. struct QIB_7322_RcvTIDArray0 {
  5054. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDArray0_pb );
  5055. };
  5056. /* Default value: 0x0000000000000000 */
  5057. #define QIB_7322_SendPbcCache_offset 0x00070000UL
  5058. /* Default value: 0x0000000000000000 */
  5059. #define QIB_7322_LaunchFIFO_v0p0_offset 0x00072000UL
  5060. /* Default value: 0x0000000000000000 */
  5061. #define QIB_7322_LaunchElement_v15p0_offset 0x00076000UL
  5062. /* Default value: 0x0000000000000000 */
  5063. #define QIB_7322_PreLaunchFIFO_0_offset 0x00076100UL
  5064. /* Default value: 0x0000000000000000 */
  5065. #define QIB_7322_ScoreBoard_0_offset 0x00076200UL
  5066. /* Default value: 0x0000000000000000 */
  5067. #define QIB_7322_DescriptorFIFO_0_offset 0x00076300UL
  5068. /* Default value: 0x0000000000000000 */
  5069. #define QIB_7322_LaunchFIFO_v0p1_offset 0x00078000UL
  5070. /* Default value: 0x0000000000000000 */
  5071. #define QIB_7322_LaunchElement_v15p1_offset 0x0007c000UL
  5072. /* Default value: 0x0000000000000000 */
  5073. #define QIB_7322_PreLaunchFIFO_1_offset 0x0007c100UL
  5074. /* Default value: 0x0000000000000000 */
  5075. #define QIB_7322_ScoreBoard_1_offset 0x0007c200UL
  5076. /* Default value: 0x0000000000000000 */
  5077. #define QIB_7322_DescriptorFIFO_1_offset 0x0007c300UL
  5078. /* Default value: 0x0000000000000000 */
  5079. #define QIB_7322_RcvBufA_0_offset 0x00080000UL
  5080. /* Default value: 0x0000000000000000 */
  5081. #define QIB_7322_RcvBufB_0_offset 0x00088000UL
  5082. /* Default value: 0x0000000000000000 */
  5083. #define QIB_7322_RcvFlags_0_offset 0x0008a000UL
  5084. /* Default value: 0x0000000000000000 */
  5085. #define QIB_7322_RcvLookupiqBuf_0_offset 0x0008c000UL
  5086. /* Default value: 0x0000000000000000 */
  5087. #define QIB_7322_RcvDMADatBuf_0_offset 0x0008e000UL
  5088. /* Default value: 0x0000000000000000 */
  5089. #define QIB_7322_RcvDMAHdrBuf_0_offset 0x0008e800UL
  5090. /* Default value: 0x0000000000000000 */
  5091. #define QIB_7322_RcvBufA_1_offset 0x00090000UL
  5092. /* Default value: 0x0000000000000000 */
  5093. #define QIB_7322_RcvBufB_1_offset 0x00098000UL
  5094. /* Default value: 0x0000000000000000 */
  5095. #define QIB_7322_RcvFlags_1_offset 0x0009a000UL
  5096. /* Default value: 0x0000000000000000 */
  5097. #define QIB_7322_RcvLookupiqBuf_1_offset 0x0009c000UL
  5098. /* Default value: 0x0000000000000000 */
  5099. #define QIB_7322_RcvDMADatBuf_1_offset 0x0009e000UL
  5100. /* Default value: 0x0000000000000000 */
  5101. #define QIB_7322_RcvDMAHdrBuf_1_offset 0x0009e800UL
  5102. /* Default value: 0x0000000000000000 */
  5103. #define QIB_7322_PCIERcvBuf_offset 0x000a0000UL
  5104. /* Default value: 0x0000000000000000 */
  5105. #define QIB_7322_PCIERetryBuf_offset 0x000a4000UL
  5106. /* Default value: 0x0000000000000000 */
  5107. #define QIB_7322_PCIERcvBufRdToWrAddr_offset 0x000a8000UL
  5108. /* Default value: 0x0000000000000000 */
  5109. #define QIB_7322_PCIERcvHdrRdToWrAddr_offset 0x000b0000UL
  5110. /* Default value: 0x0000000000000000 */
  5111. #define QIB_7322_PCIECplBuf_offset 0x000b8000UL
  5112. /* Default value: 0x0000000000000000 */
  5113. #define QIB_7322_PCIECplHdr_offset 0x000bc000UL
  5114. /* Default value: 0x0000000000000000 */
  5115. #define QIB_7322_PCIERcvHdr_offset 0x000bc200UL
  5116. /* Default value: 0x0000000000000000 */
  5117. #define QIB_7322_IBSD_DDS_MAP_TABLE_0_offset 0x000d0000UL
  5118. /* Default value: 0x0000000000000000 */
  5119. #define QIB_7322_SendBufMA_0_offset 0x00100000UL
  5120. /* Default value: 0x0000000000000000 */
  5121. #define QIB_7322_SendBufEA_0_offset 0x00100800UL
  5122. /* Default value: 0x0000000000000000 */
  5123. #define QIB_7322_SendBufMA_1_offset 0x00101000UL
  5124. /* Default value: 0x0000000000000000 */
  5125. #define QIB_7322_SendBufEA_1_offset 0x00101800UL
  5126. /* Default value: 0x0000000000000000 */
  5127. #define QIB_7322_SendBufMA_2_offset 0x00102000UL
  5128. /* Default value: 0x0000000000000000 */
  5129. #define QIB_7322_SendBufEA_2_offset 0x00102800UL
  5130. /* Default value: 0x0000000000000000 */
  5131. #define QIB_7322_SendBufMA_3_offset 0x00103000UL
  5132. /* Default value: 0x0000000000000000 */
  5133. #define QIB_7322_SendBufEA_3_offset 0x00103800UL
  5134. /* Default value: 0x0000000000000000 */
  5135. #define QIB_7322_SendBufMA_4_offset 0x00104000UL
  5136. /* Default value: 0x0000000000000000 */
  5137. #define QIB_7322_SendBufEA_4_offset 0x00104800UL
  5138. /* Default value: 0x0000000000000000 */
  5139. #define QIB_7322_SendBufMA_5_offset 0x00105000UL
  5140. /* Default value: 0x0000000000000000 */
  5141. #define QIB_7322_SendBufEA_5_offset 0x00105800UL
  5142. /* Default value: 0x0000000000000000 */
  5143. #define QIB_7322_SendBufMA_6_offset 0x00106000UL
  5144. /* Default value: 0x0000000000000000 */
  5145. #define QIB_7322_SendBufEA_6_offset 0x00106800UL
  5146. /* Default value: 0x0000000000000000 */
  5147. #define QIB_7322_SendBufMA_7_offset 0x00107000UL
  5148. /* Default value: 0x0000000000000000 */
  5149. #define QIB_7322_SendBufEA_7_offset 0x00107800UL
  5150. /* Default value: 0x0000000000000000 */
  5151. #define QIB_7322_SendBufMA_8_offset 0x00108000UL
  5152. /* Default value: 0x0000000000000000 */
  5153. #define QIB_7322_SendBufEA_8_offset 0x00108800UL
  5154. /* Default value: 0x0000000000000000 */
  5155. #define QIB_7322_SendBufMA_9_offset 0x00109000UL
  5156. /* Default value: 0x0000000000000000 */
  5157. #define QIB_7322_SendBufEA_9_offset 0x00109800UL
  5158. /* Default value: 0x0000000000000000 */
  5159. #define QIB_7322_SendBufMA_10_offset 0x0010a000UL
  5160. /* Default value: 0x0000000000000000 */
  5161. #define QIB_7322_SendBufEA_10_offset 0x0010a800UL
  5162. /* Default value: 0x0000000000000000 */
  5163. #define QIB_7322_SendBufMA_11_offset 0x0010b000UL
  5164. /* Default value: 0x0000000000000000 */
  5165. #define QIB_7322_SendBufEA_11_offset 0x0010b800UL
  5166. /* Default value: 0x0000000000000000 */
  5167. #define QIB_7322_SendBufMA_12_offset 0x0010c000UL
  5168. /* Default value: 0x0000000000000000 */
  5169. #define QIB_7322_SendBufEA_12_offset 0x0010c800UL
  5170. /* Default value: 0x0000000000000000 */
  5171. #define QIB_7322_SendBufMA_13_offset 0x0010d000UL
  5172. /* Default value: 0x0000000000000000 */
  5173. #define QIB_7322_SendBufEA_13_offset 0x0010d800UL
  5174. /* Default value: 0x0000000000000000 */
  5175. #define QIB_7322_SendBufMA_14_offset 0x0010e000UL
  5176. /* Default value: 0x0000000000000000 */
  5177. #define QIB_7322_SendBufEA_14_offset 0x0010e800UL
  5178. /* Default value: 0x0000000000000000 */
  5179. #define QIB_7322_SendBufMA_15_offset 0x0010f000UL
  5180. /* Default value: 0x0000000000000000 */
  5181. #define QIB_7322_SendBufEA_15_offset 0x0010f800UL
  5182. /* Default value: 0x0000000000000000 */
  5183. #define QIB_7322_SendBufMA_16_offset 0x00110000UL
  5184. /* Default value: 0x0000000000000000 */
  5185. #define QIB_7322_SendBufEA_16_offset 0x00110800UL
  5186. /* Default value: 0x0000000000000000 */
  5187. #define QIB_7322_SendBufMA_17_offset 0x00111000UL
  5188. /* Default value: 0x0000000000000000 */
  5189. #define QIB_7322_SendBufEA_17_offset 0x00111800UL
  5190. /* Default value: 0x0000000000000000 */
  5191. #define QIB_7322_SendBufMA_18_offset 0x00112000UL
  5192. /* Default value: 0x0000000000000000 */
  5193. #define QIB_7322_SendBufEA_18_offset 0x00112800UL
  5194. /* Default value: 0x0000000000000000 */
  5195. #define QIB_7322_SendBufMA_19_offset 0x00113000UL
  5196. /* Default value: 0x0000000000000000 */
  5197. #define QIB_7322_SendBufEA_19_offset 0x00113800UL
  5198. /* Default value: 0x0000000000000000 */
  5199. #define QIB_7322_SendBufMA_20_offset 0x00114000UL
  5200. /* Default value: 0x0000000000000000 */
  5201. #define QIB_7322_SendBufEA_20_offset 0x00114800UL
  5202. /* Default value: 0x0000000000000000 */
  5203. #define QIB_7322_SendBufMA_21_offset 0x00115000UL
  5204. /* Default value: 0x0000000000000000 */
  5205. #define QIB_7322_SendBufEA_21_offset 0x00115800UL
  5206. /* Default value: 0x0000000000000000 */
  5207. #define QIB_7322_SendBufMA_22_offset 0x00116000UL
  5208. /* Default value: 0x0000000000000000 */
  5209. #define QIB_7322_SendBufEA_22_offset 0x00116800UL
  5210. /* Default value: 0x0000000000000000 */
  5211. #define QIB_7322_SendBufMA_23_offset 0x00117000UL
  5212. /* Default value: 0x0000000000000000 */
  5213. #define QIB_7322_SendBufEA_23_offset 0x00117800UL
  5214. /* Default value: 0x0000000000000000 */
  5215. #define QIB_7322_SendBufMA_24_offset 0x00118000UL
  5216. /* Default value: 0x0000000000000000 */
  5217. #define QIB_7322_SendBufEA_24_offset 0x00118800UL
  5218. /* Default value: 0x0000000000000000 */
  5219. #define QIB_7322_SendBufMA_25_offset 0x00119000UL
  5220. /* Default value: 0x0000000000000000 */
  5221. #define QIB_7322_SendBufEA_25_offset 0x00119800UL
  5222. /* Default value: 0x0000000000000000 */
  5223. #define QIB_7322_SendBufMA_26_offset 0x0011a000UL
  5224. /* Default value: 0x0000000000000000 */
  5225. #define QIB_7322_SendBufEA_26_offset 0x0011a800UL
  5226. /* Default value: 0x0000000000000000 */
  5227. #define QIB_7322_SendBufMA_27_offset 0x0011b000UL
  5228. /* Default value: 0x0000000000000000 */
  5229. #define QIB_7322_SendBufEA_27_offset 0x0011b800UL
  5230. /* Default value: 0x0000000000000000 */
  5231. #define QIB_7322_SendBufMA_28_offset 0x0011c000UL
  5232. /* Default value: 0x0000000000000000 */
  5233. #define QIB_7322_SendBufEA_28_offset 0x0011c800UL
  5234. /* Default value: 0x0000000000000000 */
  5235. #define QIB_7322_SendBufMA_29_offset 0x0011d000UL
  5236. /* Default value: 0x0000000000000000 */
  5237. #define QIB_7322_SendBufEA_29_offset 0x0011d800UL
  5238. /* Default value: 0x0000000000000000 */
  5239. #define QIB_7322_SendBufMA_30_offset 0x0011e000UL
  5240. /* Default value: 0x0000000000000000 */
  5241. #define QIB_7322_SendBufEA_30_offset 0x0011e800UL
  5242. /* Default value: 0x0000000000000000 */
  5243. #define QIB_7322_SendBufMA_31_offset 0x0011f000UL
  5244. /* Default value: 0x0000000000000000 */
  5245. #define QIB_7322_SendBufEA_31_offset 0x0011f800UL
  5246. /* Default value: 0x0000000000000000 */
  5247. #define QIB_7322_SendBufMA_32_offset 0x00120000UL
  5248. /* Default value: 0x0000000000000000 */
  5249. #define QIB_7322_SendBufEA_32_offset 0x00120800UL
  5250. /* Default value: 0x0000000000000000 */
  5251. #define QIB_7322_SendBufMA_33_offset 0x00121000UL
  5252. /* Default value: 0x0000000000000000 */
  5253. #define QIB_7322_SendBufEA_33_offset 0x00121800UL
  5254. /* Default value: 0x0000000000000000 */
  5255. #define QIB_7322_SendBufMA_34_offset 0x00122000UL
  5256. /* Default value: 0x0000000000000000 */
  5257. #define QIB_7322_SendBufEA_34_offset 0x00122800UL
  5258. /* Default value: 0x0000000000000000 */
  5259. #define QIB_7322_SendBufMA_35_offset 0x00123000UL
  5260. /* Default value: 0x0000000000000000 */
  5261. #define QIB_7322_SendBufEA_35_offset 0x00123800UL
  5262. /* Default value: 0x0000000000000000 */
  5263. #define QIB_7322_SendBufMA_36_offset 0x00124000UL
  5264. /* Default value: 0x0000000000000000 */
  5265. #define QIB_7322_SendBufEA_36_offset 0x00124800UL
  5266. /* Default value: 0x0000000000000000 */
  5267. #define QIB_7322_SendBufMA_37_offset 0x00125000UL
  5268. /* Default value: 0x0000000000000000 */
  5269. #define QIB_7322_SendBufEA_37_offset 0x00125800UL
  5270. /* Default value: 0x0000000000000000 */
  5271. #define QIB_7322_SendBufMA_38_offset 0x00126000UL
  5272. /* Default value: 0x0000000000000000 */
  5273. #define QIB_7322_SendBufEA_38_offset 0x00126800UL
  5274. /* Default value: 0x0000000000000000 */
  5275. #define QIB_7322_SendBufMA_39_offset 0x00127000UL
  5276. /* Default value: 0x0000000000000000 */
  5277. #define QIB_7322_SendBufEA_39_offset 0x00127800UL
  5278. /* Default value: 0x0000000000000000 */
  5279. #define QIB_7322_SendBufMA_40_offset 0x00128000UL
  5280. /* Default value: 0x0000000000000000 */
  5281. #define QIB_7322_SendBufEA_40_offset 0x00128800UL
  5282. /* Default value: 0x0000000000000000 */
  5283. #define QIB_7322_SendBufMA_41_offset 0x00129000UL
  5284. /* Default value: 0x0000000000000000 */
  5285. #define QIB_7322_SendBufEA_41_offset 0x00129800UL
  5286. /* Default value: 0x0000000000000000 */
  5287. #define QIB_7322_SendBufMA_42_offset 0x0012a000UL
  5288. /* Default value: 0x0000000000000000 */
  5289. #define QIB_7322_SendBufEA_42_offset 0x0012a800UL
  5290. /* Default value: 0x0000000000000000 */
  5291. #define QIB_7322_SendBufMA_43_offset 0x0012b000UL
  5292. /* Default value: 0x0000000000000000 */
  5293. #define QIB_7322_SendBufEA_43_offset 0x0012b800UL
  5294. /* Default value: 0x0000000000000000 */
  5295. #define QIB_7322_SendBufMA_44_offset 0x0012c000UL
  5296. /* Default value: 0x0000000000000000 */
  5297. #define QIB_7322_SendBufEA_44_offset 0x0012c800UL
  5298. /* Default value: 0x0000000000000000 */
  5299. #define QIB_7322_SendBufMA_45_offset 0x0012d000UL
  5300. /* Default value: 0x0000000000000000 */
  5301. #define QIB_7322_SendBufEA_45_offset 0x0012d800UL
  5302. /* Default value: 0x0000000000000000 */
  5303. #define QIB_7322_SendBufMA_46_offset 0x0012e000UL
  5304. /* Default value: 0x0000000000000000 */
  5305. #define QIB_7322_SendBufEA_46_offset 0x0012e800UL
  5306. /* Default value: 0x0000000000000000 */
  5307. #define QIB_7322_SendBufMA_47_offset 0x0012f000UL
  5308. /* Default value: 0x0000000000000000 */
  5309. #define QIB_7322_SendBufEA_47_offset 0x0012f800UL
  5310. /* Default value: 0x0000000000000000 */
  5311. #define QIB_7322_SendBufMA_48_offset 0x00130000UL
  5312. /* Default value: 0x0000000000000000 */
  5313. #define QIB_7322_SendBufEA_48_offset 0x00130800UL
  5314. /* Default value: 0x0000000000000000 */
  5315. #define QIB_7322_SendBufMA_49_offset 0x00131000UL
  5316. /* Default value: 0x0000000000000000 */
  5317. #define QIB_7322_SendBufEA_49_offset 0x00131800UL
  5318. /* Default value: 0x0000000000000000 */
  5319. #define QIB_7322_SendBufMA_50_offset 0x00132000UL
  5320. /* Default value: 0x0000000000000000 */
  5321. #define QIB_7322_SendBufEA_50_offset 0x00132800UL
  5322. /* Default value: 0x0000000000000000 */
  5323. #define QIB_7322_SendBufMA_51_offset 0x00133000UL
  5324. /* Default value: 0x0000000000000000 */
  5325. #define QIB_7322_SendBufEA_51_offset 0x00133800UL
  5326. /* Default value: 0x0000000000000000 */
  5327. #define QIB_7322_SendBufMA_52_offset 0x00134000UL
  5328. /* Default value: 0x0000000000000000 */
  5329. #define QIB_7322_SendBufEA_52_offset 0x00134800UL
  5330. /* Default value: 0x0000000000000000 */
  5331. #define QIB_7322_SendBufMA_53_offset 0x00135000UL
  5332. /* Default value: 0x0000000000000000 */
  5333. #define QIB_7322_SendBufEA_53_offset 0x00135800UL
  5334. /* Default value: 0x0000000000000000 */
  5335. #define QIB_7322_SendBufMA_54_offset 0x00136000UL
  5336. /* Default value: 0x0000000000000000 */
  5337. #define QIB_7322_SendBufEA_54_offset 0x00136800UL
  5338. /* Default value: 0x0000000000000000 */
  5339. #define QIB_7322_SendBufMA_55_offset 0x00137000UL
  5340. /* Default value: 0x0000000000000000 */
  5341. #define QIB_7322_SendBufEA_55_offset 0x00137800UL
  5342. /* Default value: 0x0000000000000000 */
  5343. #define QIB_7322_SendBufMA_56_offset 0x00138000UL
  5344. /* Default value: 0x0000000000000000 */
  5345. #define QIB_7322_SendBufEA_56_offset 0x00138800UL
  5346. /* Default value: 0x0000000000000000 */
  5347. #define QIB_7322_SendBufMA_57_offset 0x00139000UL
  5348. /* Default value: 0x0000000000000000 */
  5349. #define QIB_7322_SendBufEA_57_offset 0x00139800UL
  5350. /* Default value: 0x0000000000000000 */
  5351. #define QIB_7322_SendBufMA_58_offset 0x0013a000UL
  5352. /* Default value: 0x0000000000000000 */
  5353. #define QIB_7322_SendBufEA_58_offset 0x0013a800UL
  5354. /* Default value: 0x0000000000000000 */
  5355. #define QIB_7322_SendBufMA_59_offset 0x0013b000UL
  5356. /* Default value: 0x0000000000000000 */
  5357. #define QIB_7322_SendBufEA_59_offset 0x0013b800UL
  5358. /* Default value: 0x0000000000000000 */
  5359. #define QIB_7322_SendBufMA_60_offset 0x0013c000UL
  5360. /* Default value: 0x0000000000000000 */
  5361. #define QIB_7322_SendBufEA_60_offset 0x0013c800UL
  5362. /* Default value: 0x0000000000000000 */
  5363. #define QIB_7322_SendBufMA_61_offset 0x0013d000UL
  5364. /* Default value: 0x0000000000000000 */
  5365. #define QIB_7322_SendBufEA_61_offset 0x0013d800UL
  5366. /* Default value: 0x0000000000000000 */
  5367. #define QIB_7322_SendBufMA_62_offset 0x0013e000UL
  5368. /* Default value: 0x0000000000000000 */
  5369. #define QIB_7322_SendBufEA_62_offset 0x0013e800UL
  5370. /* Default value: 0x0000000000000000 */
  5371. #define QIB_7322_SendBufMA_63_offset 0x0013f000UL
  5372. /* Default value: 0x0000000000000000 */
  5373. #define QIB_7322_SendBufEA_63_offset 0x0013f800UL
  5374. /* Default value: 0x0000000000000000 */
  5375. #define QIB_7322_SendBufMA_64_offset 0x00140000UL
  5376. /* Default value: 0x0000000000000000 */
  5377. #define QIB_7322_SendBufEA_64_offset 0x00140800UL
  5378. /* Default value: 0x0000000000000000 */
  5379. #define QIB_7322_SendBufMA_65_offset 0x00141000UL
  5380. /* Default value: 0x0000000000000000 */
  5381. #define QIB_7322_SendBufEA_65_offset 0x00141800UL
  5382. /* Default value: 0x0000000000000000 */
  5383. #define QIB_7322_SendBufMA_66_offset 0x00142000UL
  5384. /* Default value: 0x0000000000000000 */
  5385. #define QIB_7322_SendBufEA_66_offset 0x00142800UL
  5386. /* Default value: 0x0000000000000000 */
  5387. #define QIB_7322_SendBufMA_67_offset 0x00143000UL
  5388. /* Default value: 0x0000000000000000 */
  5389. #define QIB_7322_SendBufEA_67_offset 0x00143800UL
  5390. /* Default value: 0x0000000000000000 */
  5391. #define QIB_7322_SendBufMA_68_offset 0x00144000UL
  5392. /* Default value: 0x0000000000000000 */
  5393. #define QIB_7322_SendBufEA_68_offset 0x00144800UL
  5394. /* Default value: 0x0000000000000000 */
  5395. #define QIB_7322_SendBufMA_69_offset 0x00145000UL
  5396. /* Default value: 0x0000000000000000 */
  5397. #define QIB_7322_SendBufEA_69_offset 0x00145800UL
  5398. /* Default value: 0x0000000000000000 */
  5399. #define QIB_7322_SendBufMA_70_offset 0x00146000UL
  5400. /* Default value: 0x0000000000000000 */
  5401. #define QIB_7322_SendBufEA_70_offset 0x00146800UL
  5402. /* Default value: 0x0000000000000000 */
  5403. #define QIB_7322_SendBufMA_71_offset 0x00147000UL
  5404. /* Default value: 0x0000000000000000 */
  5405. #define QIB_7322_SendBufEA_71_offset 0x00147800UL
  5406. /* Default value: 0x0000000000000000 */
  5407. #define QIB_7322_SendBufMA_72_offset 0x00148000UL
  5408. /* Default value: 0x0000000000000000 */
  5409. #define QIB_7322_SendBufEA_72_offset 0x00148800UL
  5410. /* Default value: 0x0000000000000000 */
  5411. #define QIB_7322_SendBufMA_73_offset 0x00149000UL
  5412. /* Default value: 0x0000000000000000 */
  5413. #define QIB_7322_SendBufEA_73_offset 0x00149800UL
  5414. /* Default value: 0x0000000000000000 */
  5415. #define QIB_7322_SendBufMA_74_offset 0x0014a000UL
  5416. /* Default value: 0x0000000000000000 */
  5417. #define QIB_7322_SendBufEA_74_offset 0x0014a800UL
  5418. /* Default value: 0x0000000000000000 */
  5419. #define QIB_7322_SendBufMA_75_offset 0x0014b000UL
  5420. /* Default value: 0x0000000000000000 */
  5421. #define QIB_7322_SendBufEA_75_offset 0x0014b800UL
  5422. /* Default value: 0x0000000000000000 */
  5423. #define QIB_7322_SendBufMA_76_offset 0x0014c000UL
  5424. /* Default value: 0x0000000000000000 */
  5425. #define QIB_7322_SendBufEA_76_offset 0x0014c800UL
  5426. /* Default value: 0x0000000000000000 */
  5427. #define QIB_7322_SendBufMA_77_offset 0x0014d000UL
  5428. /* Default value: 0x0000000000000000 */
  5429. #define QIB_7322_SendBufEA_77_offset 0x0014d800UL
  5430. /* Default value: 0x0000000000000000 */
  5431. #define QIB_7322_SendBufMA_78_offset 0x0014e000UL
  5432. /* Default value: 0x0000000000000000 */
  5433. #define QIB_7322_SendBufEA_78_offset 0x0014e800UL
  5434. /* Default value: 0x0000000000000000 */
  5435. #define QIB_7322_SendBufMA_79_offset 0x0014f000UL
  5436. /* Default value: 0x0000000000000000 */
  5437. #define QIB_7322_SendBufEA_79_offset 0x0014f800UL
  5438. /* Default value: 0x0000000000000000 */
  5439. #define QIB_7322_SendBufMA_80_offset 0x00150000UL
  5440. /* Default value: 0x0000000000000000 */
  5441. #define QIB_7322_SendBufEA_80_offset 0x00150800UL
  5442. /* Default value: 0x0000000000000000 */
  5443. #define QIB_7322_SendBufMA_81_offset 0x00151000UL
  5444. /* Default value: 0x0000000000000000 */
  5445. #define QIB_7322_SendBufEA_81_offset 0x00151800UL
  5446. /* Default value: 0x0000000000000000 */
  5447. #define QIB_7322_SendBufMA_82_offset 0x00152000UL
  5448. /* Default value: 0x0000000000000000 */
  5449. #define QIB_7322_SendBufEA_82_offset 0x00152800UL
  5450. /* Default value: 0x0000000000000000 */
  5451. #define QIB_7322_SendBufMA_83_offset 0x00153000UL
  5452. /* Default value: 0x0000000000000000 */
  5453. #define QIB_7322_SendBufEA_83_offset 0x00153800UL
  5454. /* Default value: 0x0000000000000000 */
  5455. #define QIB_7322_SendBufMA_84_offset 0x00154000UL
  5456. /* Default value: 0x0000000000000000 */
  5457. #define QIB_7322_SendBufEA_84_offset 0x00154800UL
  5458. /* Default value: 0x0000000000000000 */
  5459. #define QIB_7322_SendBufMA_85_offset 0x00155000UL
  5460. /* Default value: 0x0000000000000000 */
  5461. #define QIB_7322_SendBufEA_85_offset 0x00155800UL
  5462. /* Default value: 0x0000000000000000 */
  5463. #define QIB_7322_SendBufMA_86_offset 0x00156000UL
  5464. /* Default value: 0x0000000000000000 */
  5465. #define QIB_7322_SendBufEA_86_offset 0x00156800UL
  5466. /* Default value: 0x0000000000000000 */
  5467. #define QIB_7322_SendBufMA_87_offset 0x00157000UL
  5468. /* Default value: 0x0000000000000000 */
  5469. #define QIB_7322_SendBufEA_87_offset 0x00157800UL
  5470. /* Default value: 0x0000000000000000 */
  5471. #define QIB_7322_SendBufMA_88_offset 0x00158000UL
  5472. /* Default value: 0x0000000000000000 */
  5473. #define QIB_7322_SendBufEA_88_offset 0x00158800UL
  5474. /* Default value: 0x0000000000000000 */
  5475. #define QIB_7322_SendBufMA_89_offset 0x00159000UL
  5476. /* Default value: 0x0000000000000000 */
  5477. #define QIB_7322_SendBufEA_89_offset 0x00159800UL
  5478. /* Default value: 0x0000000000000000 */
  5479. #define QIB_7322_SendBufMA_90_offset 0x0015a000UL
  5480. /* Default value: 0x0000000000000000 */
  5481. #define QIB_7322_SendBufEA_90_offset 0x0015a800UL
  5482. /* Default value: 0x0000000000000000 */
  5483. #define QIB_7322_SendBufMA_91_offset 0x0015b000UL
  5484. /* Default value: 0x0000000000000000 */
  5485. #define QIB_7322_SendBufEA_91_offset 0x0015b800UL
  5486. /* Default value: 0x0000000000000000 */
  5487. #define QIB_7322_SendBufMA_92_offset 0x0015c000UL
  5488. /* Default value: 0x0000000000000000 */
  5489. #define QIB_7322_SendBufEA_92_offset 0x0015c800UL
  5490. /* Default value: 0x0000000000000000 */
  5491. #define QIB_7322_SendBufMA_93_offset 0x0015d000UL
  5492. /* Default value: 0x0000000000000000 */
  5493. #define QIB_7322_SendBufEA_93_offset 0x0015d800UL
  5494. /* Default value: 0x0000000000000000 */
  5495. #define QIB_7322_SendBufMA_94_offset 0x0015e000UL
  5496. /* Default value: 0x0000000000000000 */
  5497. #define QIB_7322_SendBufEA_94_offset 0x0015e800UL
  5498. /* Default value: 0x0000000000000000 */
  5499. #define QIB_7322_SendBufMA_95_offset 0x0015f000UL
  5500. /* Default value: 0x0000000000000000 */
  5501. #define QIB_7322_SendBufEA_95_offset 0x0015f800UL
  5502. /* Default value: 0x0000000000000000 */
  5503. #define QIB_7322_SendBufMA_96_offset 0x00160000UL
  5504. /* Default value: 0x0000000000000000 */
  5505. #define QIB_7322_SendBufEA_96_offset 0x00160800UL
  5506. /* Default value: 0x0000000000000000 */
  5507. #define QIB_7322_SendBufMA_97_offset 0x00161000UL
  5508. /* Default value: 0x0000000000000000 */
  5509. #define QIB_7322_SendBufEA_97_offset 0x00161800UL
  5510. /* Default value: 0x0000000000000000 */
  5511. #define QIB_7322_SendBufMA_98_offset 0x00162000UL
  5512. /* Default value: 0x0000000000000000 */
  5513. #define QIB_7322_SendBufEA_98_offset 0x00162800UL
  5514. /* Default value: 0x0000000000000000 */
  5515. #define QIB_7322_SendBufMA_99_offset 0x00163000UL
  5516. /* Default value: 0x0000000000000000 */
  5517. #define QIB_7322_SendBufEA_99_offset 0x00163800UL
  5518. /* Default value: 0x0000000000000000 */
  5519. #define QIB_7322_SendBufMA_100_offset 0x00164000UL
  5520. /* Default value: 0x0000000000000000 */
  5521. #define QIB_7322_SendBufEA_100_offset 0x00164800UL
  5522. /* Default value: 0x0000000000000000 */
  5523. #define QIB_7322_SendBufMA_101_offset 0x00165000UL
  5524. /* Default value: 0x0000000000000000 */
  5525. #define QIB_7322_SendBufEA_101_offset 0x00165800UL
  5526. /* Default value: 0x0000000000000000 */
  5527. #define QIB_7322_SendBufMA_102_offset 0x00166000UL
  5528. /* Default value: 0x0000000000000000 */
  5529. #define QIB_7322_SendBufEA_102_offset 0x00166800UL
  5530. /* Default value: 0x0000000000000000 */
  5531. #define QIB_7322_SendBufMA_103_offset 0x00167000UL
  5532. /* Default value: 0x0000000000000000 */
  5533. #define QIB_7322_SendBufEA_103_offset 0x00167800UL
  5534. /* Default value: 0x0000000000000000 */
  5535. #define QIB_7322_SendBufMA_104_offset 0x00168000UL
  5536. /* Default value: 0x0000000000000000 */
  5537. #define QIB_7322_SendBufEA_104_offset 0x00168800UL
  5538. /* Default value: 0x0000000000000000 */
  5539. #define QIB_7322_SendBufMA_105_offset 0x00169000UL
  5540. /* Default value: 0x0000000000000000 */
  5541. #define QIB_7322_SendBufEA_105_offset 0x00169800UL
  5542. /* Default value: 0x0000000000000000 */
  5543. #define QIB_7322_SendBufMA_106_offset 0x0016a000UL
  5544. /* Default value: 0x0000000000000000 */
  5545. #define QIB_7322_SendBufEA_106_offset 0x0016a800UL
  5546. /* Default value: 0x0000000000000000 */
  5547. #define QIB_7322_SendBufMA_107_offset 0x0016b000UL
  5548. /* Default value: 0x0000000000000000 */
  5549. #define QIB_7322_SendBufEA_107_offset 0x0016b800UL
  5550. /* Default value: 0x0000000000000000 */
  5551. #define QIB_7322_SendBufMA_108_offset 0x0016c000UL
  5552. /* Default value: 0x0000000000000000 */
  5553. #define QIB_7322_SendBufEA_108_offset 0x0016c800UL
  5554. /* Default value: 0x0000000000000000 */
  5555. #define QIB_7322_SendBufMA_109_offset 0x0016d000UL
  5556. /* Default value: 0x0000000000000000 */
  5557. #define QIB_7322_SendBufEA_109_offset 0x0016d800UL
  5558. /* Default value: 0x0000000000000000 */
  5559. #define QIB_7322_SendBufMA_110_offset 0x0016e000UL
  5560. /* Default value: 0x0000000000000000 */
  5561. #define QIB_7322_SendBufEA_110_offset 0x0016e800UL
  5562. /* Default value: 0x0000000000000000 */
  5563. #define QIB_7322_SendBufMA_111_offset 0x0016f000UL
  5564. /* Default value: 0x0000000000000000 */
  5565. #define QIB_7322_SendBufEA_111_offset 0x0016f800UL
  5566. /* Default value: 0x0000000000000000 */
  5567. #define QIB_7322_SendBufMA_112_offset 0x00170000UL
  5568. /* Default value: 0x0000000000000000 */
  5569. #define QIB_7322_SendBufEA_112_offset 0x00170800UL
  5570. /* Default value: 0x0000000000000000 */
  5571. #define QIB_7322_SendBufMA_113_offset 0x00171000UL
  5572. /* Default value: 0x0000000000000000 */
  5573. #define QIB_7322_SendBufEA_113_offset 0x00171800UL
  5574. /* Default value: 0x0000000000000000 */
  5575. #define QIB_7322_SendBufMA_114_offset 0x00172000UL
  5576. /* Default value: 0x0000000000000000 */
  5577. #define QIB_7322_SendBufEA_114_offset 0x00172800UL
  5578. /* Default value: 0x0000000000000000 */
  5579. #define QIB_7322_SendBufMA_115_offset 0x00173000UL
  5580. /* Default value: 0x0000000000000000 */
  5581. #define QIB_7322_SendBufEA_115_offset 0x00173800UL
  5582. /* Default value: 0x0000000000000000 */
  5583. #define QIB_7322_SendBufMA_116_offset 0x00174000UL
  5584. /* Default value: 0x0000000000000000 */
  5585. #define QIB_7322_SendBufEA_116_offset 0x00174800UL
  5586. /* Default value: 0x0000000000000000 */
  5587. #define QIB_7322_SendBufMA_117_offset 0x00175000UL
  5588. /* Default value: 0x0000000000000000 */
  5589. #define QIB_7322_SendBufEA_117_offset 0x00175800UL
  5590. /* Default value: 0x0000000000000000 */
  5591. #define QIB_7322_SendBufMA_118_offset 0x00176000UL
  5592. /* Default value: 0x0000000000000000 */
  5593. #define QIB_7322_SendBufEA_118_offset 0x00176800UL
  5594. /* Default value: 0x0000000000000000 */
  5595. #define QIB_7322_SendBufMA_119_offset 0x00177000UL
  5596. /* Default value: 0x0000000000000000 */
  5597. #define QIB_7322_SendBufEA_119_offset 0x00177800UL
  5598. /* Default value: 0x0000000000000000 */
  5599. #define QIB_7322_SendBufMA_120_offset 0x00178000UL
  5600. /* Default value: 0x0000000000000000 */
  5601. #define QIB_7322_SendBufEA_120_offset 0x00178800UL
  5602. /* Default value: 0x0000000000000000 */
  5603. #define QIB_7322_SendBufMA_121_offset 0x00179000UL
  5604. /* Default value: 0x0000000000000000 */
  5605. #define QIB_7322_SendBufEA_121_offset 0x00179800UL
  5606. /* Default value: 0x0000000000000000 */
  5607. #define QIB_7322_SendBufMA_122_offset 0x0017a000UL
  5608. /* Default value: 0x0000000000000000 */
  5609. #define QIB_7322_SendBufEA_122_offset 0x0017a800UL
  5610. /* Default value: 0x0000000000000000 */
  5611. #define QIB_7322_SendBufMA_123_offset 0x0017b000UL
  5612. /* Default value: 0x0000000000000000 */
  5613. #define QIB_7322_SendBufEA_123_offset 0x0017b800UL
  5614. /* Default value: 0x0000000000000000 */
  5615. #define QIB_7322_SendBufMA_124_offset 0x0017c000UL
  5616. /* Default value: 0x0000000000000000 */
  5617. #define QIB_7322_SendBufEA_124_offset 0x0017c800UL
  5618. /* Default value: 0x0000000000000000 */
  5619. #define QIB_7322_SendBufMA_125_offset 0x0017d000UL
  5620. /* Default value: 0x0000000000000000 */
  5621. #define QIB_7322_SendBufEA_125_offset 0x0017d800UL
  5622. /* Default value: 0x0000000000000000 */
  5623. #define QIB_7322_SendBufMA_126_offset 0x0017e000UL
  5624. /* Default value: 0x0000000000000000 */
  5625. #define QIB_7322_SendBufEA_126_offset 0x0017e800UL
  5626. /* Default value: 0x0000000000000000 */
  5627. #define QIB_7322_SendBufMA_127_offset 0x0017f000UL
  5628. /* Default value: 0x0000000000000000 */
  5629. #define QIB_7322_SendBufEA_127_offset 0x0017f800UL
  5630. /* Default value: 0x0000000000000000 */
  5631. #define QIB_7322_SendBufMA_128_offset 0x00180000UL
  5632. /* Default value: 0x0000000000000000 */
  5633. #define QIB_7322_SendBufEA_128_offset 0x00181000UL
  5634. /* Default value: 0x0000000000000000 */
  5635. #define QIB_7322_SendBufMA_129_offset 0x00182000UL
  5636. /* Default value: 0x0000000000000000 */
  5637. #define QIB_7322_SendBufEA_129_offset 0x00183000UL
  5638. /* Default value: 0x0000000000000000 */
  5639. #define QIB_7322_SendBufMA_130_offset 0x00184000UL
  5640. /* Default value: 0x0000000000000000 */
  5641. #define QIB_7322_SendBufEA_130_offset 0x00185000UL
  5642. /* Default value: 0x0000000000000000 */
  5643. #define QIB_7322_SendBufMA_131_offset 0x00186000UL
  5644. /* Default value: 0x0000000000000000 */
  5645. #define QIB_7322_SendBufEA_131_offset 0x00187000UL
  5646. /* Default value: 0x0000000000000000 */
  5647. #define QIB_7322_SendBufMA_132_offset 0x00188000UL
  5648. /* Default value: 0x0000000000000000 */
  5649. #define QIB_7322_SendBufEA_132_offset 0x00189000UL
  5650. /* Default value: 0x0000000000000000 */
  5651. #define QIB_7322_SendBufMA_133_offset 0x0018a000UL
  5652. /* Default value: 0x0000000000000000 */
  5653. #define QIB_7322_SendBufEA_133_offset 0x0018b000UL
  5654. /* Default value: 0x0000000000000000 */
  5655. #define QIB_7322_SendBufMA_134_offset 0x0018c000UL
  5656. /* Default value: 0x0000000000000000 */
  5657. #define QIB_7322_SendBufEA_134_offset 0x0018d000UL
  5658. /* Default value: 0x0000000000000000 */
  5659. #define QIB_7322_SendBufMA_135_offset 0x0018e000UL
  5660. /* Default value: 0x0000000000000000 */
  5661. #define QIB_7322_SendBufEA_135_offset 0x0018f000UL
  5662. /* Default value: 0x0000000000000000 */
  5663. #define QIB_7322_SendBufMA_136_offset 0x00190000UL
  5664. /* Default value: 0x0000000000000000 */
  5665. #define QIB_7322_SendBufEA_136_offset 0x00191000UL
  5666. /* Default value: 0x0000000000000000 */
  5667. #define QIB_7322_SendBufMA_137_offset 0x00192000UL
  5668. /* Default value: 0x0000000000000000 */
  5669. #define QIB_7322_SendBufEA_137_offset 0x00193000UL
  5670. /* Default value: 0x0000000000000000 */
  5671. #define QIB_7322_SendBufMA_138_offset 0x00194000UL
  5672. /* Default value: 0x0000000000000000 */
  5673. #define QIB_7322_SendBufEA_138_offset 0x00195000UL
  5674. /* Default value: 0x0000000000000000 */
  5675. #define QIB_7322_SendBufMA_139_offset 0x00196000UL
  5676. /* Default value: 0x0000000000000000 */
  5677. #define QIB_7322_SendBufEA_139_offset 0x00197000UL
  5678. /* Default value: 0x0000000000000000 */
  5679. #define QIB_7322_SendBufMA_140_offset 0x00198000UL
  5680. /* Default value: 0x0000000000000000 */
  5681. #define QIB_7322_SendBufEA_140_offset 0x00199000UL
  5682. /* Default value: 0x0000000000000000 */
  5683. #define QIB_7322_SendBufMA_141_offset 0x0019a000UL
  5684. /* Default value: 0x0000000000000000 */
  5685. #define QIB_7322_SendBufEA_141_offset 0x0019b000UL
  5686. /* Default value: 0x0000000000000000 */
  5687. #define QIB_7322_SendBufMA_142_offset 0x0019c000UL
  5688. /* Default value: 0x0000000000000000 */
  5689. #define QIB_7322_SendBufEA_142_offset 0x0019d000UL
  5690. /* Default value: 0x0000000000000000 */
  5691. #define QIB_7322_SendBufMA_143_offset 0x0019e000UL
  5692. /* Default value: 0x0000000000000000 */
  5693. #define QIB_7322_SendBufEA_143_offset 0x0019f000UL
  5694. /* Default value: 0x0000000000000000 */
  5695. #define QIB_7322_SendBufMA_144_offset 0x001a0000UL
  5696. /* Default value: 0x0000000000000000 */
  5697. #define QIB_7322_SendBufEA_144_offset 0x001a1000UL
  5698. /* Default value: 0x0000000000000000 */
  5699. #define QIB_7322_SendBufMA_145_offset 0x001a2000UL
  5700. /* Default value: 0x0000000000000000 */
  5701. #define QIB_7322_SendBufEA_145_offset 0x001a3000UL
  5702. /* Default value: 0x0000000000000000 */
  5703. #define QIB_7322_SendBufMA_146_offset 0x001a4000UL
  5704. /* Default value: 0x0000000000000000 */
  5705. #define QIB_7322_SendBufEA_146_offset 0x001a5000UL
  5706. /* Default value: 0x0000000000000000 */
  5707. #define QIB_7322_SendBufMA_147_offset 0x001a6000UL
  5708. /* Default value: 0x0000000000000000 */
  5709. #define QIB_7322_SendBufEA_147_offset 0x001a7000UL
  5710. /* Default value: 0x0000000000000000 */
  5711. #define QIB_7322_SendBufMA_148_offset 0x001a8000UL
  5712. /* Default value: 0x0000000000000000 */
  5713. #define QIB_7322_SendBufEA_148_offset 0x001a9000UL
  5714. /* Default value: 0x0000000000000000 */
  5715. #define QIB_7322_SendBufMA_149_offset 0x001aa000UL
  5716. /* Default value: 0x0000000000000000 */
  5717. #define QIB_7322_SendBufEA_149_offset 0x001ab000UL
  5718. /* Default value: 0x0000000000000000 */
  5719. #define QIB_7322_SendBufMA_150_offset 0x001ac000UL
  5720. /* Default value: 0x0000000000000000 */
  5721. #define QIB_7322_SendBufEA_150_offset 0x001ad000UL
  5722. /* Default value: 0x0000000000000000 */
  5723. #define QIB_7322_SendBufMA_151_offset 0x001ae000UL
  5724. /* Default value: 0x0000000000000000 */
  5725. #define QIB_7322_SendBufEA_151_offset 0x001af000UL
  5726. /* Default value: 0x0000000000000000 */
  5727. #define QIB_7322_SendBufMA_152_offset 0x001b0000UL
  5728. /* Default value: 0x0000000000000000 */
  5729. #define QIB_7322_SendBufEA_152_offset 0x001b1000UL
  5730. /* Default value: 0x0000000000000000 */
  5731. #define QIB_7322_SendBufMA_153_offset 0x001b2000UL
  5732. /* Default value: 0x0000000000000000 */
  5733. #define QIB_7322_SendBufEA_153_offset 0x001b3000UL
  5734. /* Default value: 0x0000000000000000 */
  5735. #define QIB_7322_SendBufMA_154_offset 0x001b4000UL
  5736. /* Default value: 0x0000000000000000 */
  5737. #define QIB_7322_SendBufEA_154_offset 0x001b5000UL
  5738. /* Default value: 0x0000000000000000 */
  5739. #define QIB_7322_SendBufMA_155_offset 0x001b6000UL
  5740. /* Default value: 0x0000000000000000 */
  5741. #define QIB_7322_SendBufEA_155_offset 0x001b7000UL
  5742. /* Default value: 0x0000000000000000 */
  5743. #define QIB_7322_SendBufMA_156_offset 0x001b8000UL
  5744. /* Default value: 0x0000000000000000 */
  5745. #define QIB_7322_SendBufEA_156_offset 0x001b9000UL
  5746. /* Default value: 0x0000000000000000 */
  5747. #define QIB_7322_SendBufMA_157_offset 0x001ba000UL
  5748. /* Default value: 0x0000000000000000 */
  5749. #define QIB_7322_SendBufEA_157_offset 0x001bb000UL
  5750. /* Default value: 0x0000000000000000 */
  5751. #define QIB_7322_SendBufMA_158_offset 0x001bc000UL
  5752. /* Default value: 0x0000000000000000 */
  5753. #define QIB_7322_SendBufEA_158_offset 0x001bd000UL
  5754. /* Default value: 0x0000000000000000 */
  5755. #define QIB_7322_SendBufMA_159_offset 0x001be000UL
  5756. /* Default value: 0x0000000000000000 */
  5757. #define QIB_7322_SendBufEA_159_offset 0x001bf000UL
  5758. /* Default value: 0x0000000000000000 */
  5759. #define QIB_7322_SendBufVL15_0_offset 0x001c0000UL
  5760. /* Default value: 0x0000000000000000 */
  5761. #define QIB_7322_RcvHdrTail0_offset 0x00200000UL
  5762. /* Default value: 0x0000000000000000 */
  5763. #define QIB_7322_RcvHdrHead0_offset 0x00200008UL
  5764. struct QIB_7322_RcvHdrHead0_pb {
  5765. pseudo_bit_t RcvHeadPointer[32];
  5766. pseudo_bit_t counter[16];
  5767. pseudo_bit_t _unused_0[16];
  5768. };
  5769. struct QIB_7322_RcvHdrHead0 {
  5770. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead0_pb );
  5771. };
  5772. /* Default value: 0x0000000000000000 */
  5773. #define QIB_7322_RcvEgrIndexTail0_offset 0x00200010UL
  5774. /* Default value: 0x0000000000000000 */
  5775. #define QIB_7322_RcvEgrIndexHead0_offset 0x00200018UL
  5776. /* Default value: 0x0000000000000000 */
  5777. #define QIB_7322_RcvTIDFlowTable0_offset 0x00201000UL
  5778. struct QIB_7322_RcvTIDFlowTable0_pb {
  5779. pseudo_bit_t SeqNum[11];
  5780. pseudo_bit_t GenVal[8];
  5781. pseudo_bit_t FlowValid[1];
  5782. pseudo_bit_t HdrSuppEnabled[1];
  5783. pseudo_bit_t KeepAfterSeqErr[1];
  5784. pseudo_bit_t KeepOnGenErr[1];
  5785. pseudo_bit_t _unused_0[4];
  5786. pseudo_bit_t SeqMismatch[1];
  5787. pseudo_bit_t GenMismatch[1];
  5788. pseudo_bit_t _unused_1[35];
  5789. };
  5790. struct QIB_7322_RcvTIDFlowTable0 {
  5791. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable0_pb );
  5792. };
  5793. /* Default value: 0x0000000000000000 */
  5794. #define QIB_7322_RcvHdrTail1_offset 0x00210000UL
  5795. /* Default value: 0x0000000000000000 */
  5796. #define QIB_7322_RcvHdrHead1_offset 0x00210008UL
  5797. struct QIB_7322_RcvHdrHead1_pb {
  5798. pseudo_bit_t RcvHeadPointer[32];
  5799. pseudo_bit_t counter[16];
  5800. pseudo_bit_t _unused_0[16];
  5801. };
  5802. struct QIB_7322_RcvHdrHead1 {
  5803. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead1_pb );
  5804. };
  5805. /* Default value: 0x0000000000000000 */
  5806. #define QIB_7322_RcvEgrIndexTail1_offset 0x00210010UL
  5807. /* Default value: 0x0000000000000000 */
  5808. #define QIB_7322_RcvEgrIndexHead1_offset 0x00210018UL
  5809. /* Default value: 0x0000000000000000 */
  5810. #define QIB_7322_RcvTIDFlowTable1_offset 0x00211000UL
  5811. struct QIB_7322_RcvTIDFlowTable1_pb {
  5812. pseudo_bit_t SeqNum[11];
  5813. pseudo_bit_t GenVal[8];
  5814. pseudo_bit_t FlowValid[1];
  5815. pseudo_bit_t HdrSuppEnabled[1];
  5816. pseudo_bit_t KeepAfterSeqErr[1];
  5817. pseudo_bit_t KeepOnGenErr[1];
  5818. pseudo_bit_t _unused_0[4];
  5819. pseudo_bit_t SeqMismatch[1];
  5820. pseudo_bit_t GenMismatch[1];
  5821. pseudo_bit_t _unused_1[35];
  5822. };
  5823. struct QIB_7322_RcvTIDFlowTable1 {
  5824. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable1_pb );
  5825. };
  5826. /* Default value: 0x0000000000000000 */
  5827. #define QIB_7322_RcvHdrTail2_offset 0x00220000UL
  5828. /* Default value: 0x0000000000000000 */
  5829. #define QIB_7322_RcvHdrHead2_offset 0x00220008UL
  5830. struct QIB_7322_RcvHdrHead2_pb {
  5831. pseudo_bit_t RcvHeadPointer[32];
  5832. pseudo_bit_t counter[16];
  5833. pseudo_bit_t _unused_0[16];
  5834. };
  5835. struct QIB_7322_RcvHdrHead2 {
  5836. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead2_pb );
  5837. };
  5838. /* Default value: 0x0000000000000000 */
  5839. #define QIB_7322_RcvEgrIndexTail2_offset 0x00220010UL
  5840. /* Default value: 0x0000000000000000 */
  5841. #define QIB_7322_RcvEgrIndexHead2_offset 0x00220018UL
  5842. /* Default value: 0x0000000000000000 */
  5843. #define QIB_7322_RcvTIDFlowTable2_offset 0x00221000UL
  5844. struct QIB_7322_RcvTIDFlowTable2_pb {
  5845. pseudo_bit_t SeqNum[11];
  5846. pseudo_bit_t GenVal[8];
  5847. pseudo_bit_t FlowValid[1];
  5848. pseudo_bit_t HdrSuppEnabled[1];
  5849. pseudo_bit_t KeepAfterSeqErr[1];
  5850. pseudo_bit_t KeepOnGenErr[1];
  5851. pseudo_bit_t _unused_0[4];
  5852. pseudo_bit_t SeqMismatch[1];
  5853. pseudo_bit_t GenMismatch[1];
  5854. pseudo_bit_t _unused_1[35];
  5855. };
  5856. struct QIB_7322_RcvTIDFlowTable2 {
  5857. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable2_pb );
  5858. };
  5859. /* Default value: 0x0000000000000000 */
  5860. #define QIB_7322_RcvHdrTail3_offset 0x00230000UL
  5861. /* Default value: 0x0000000000000000 */
  5862. #define QIB_7322_RcvHdrHead3_offset 0x00230008UL
  5863. struct QIB_7322_RcvHdrHead3_pb {
  5864. pseudo_bit_t RcvHeadPointer[32];
  5865. pseudo_bit_t counter[16];
  5866. pseudo_bit_t _unused_0[16];
  5867. };
  5868. struct QIB_7322_RcvHdrHead3 {
  5869. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead3_pb );
  5870. };
  5871. /* Default value: 0x0000000000000000 */
  5872. #define QIB_7322_RcvEgrIndexTail3_offset 0x00230010UL
  5873. /* Default value: 0x0000000000000000 */
  5874. #define QIB_7322_RcvEgrIndexHead3_offset 0x00230018UL
  5875. /* Default value: 0x0000000000000000 */
  5876. #define QIB_7322_RcvTIDFlowTable3_offset 0x00231000UL
  5877. struct QIB_7322_RcvTIDFlowTable3_pb {
  5878. pseudo_bit_t SeqNum[11];
  5879. pseudo_bit_t GenVal[8];
  5880. pseudo_bit_t FlowValid[1];
  5881. pseudo_bit_t HdrSuppEnabled[1];
  5882. pseudo_bit_t KeepAfterSeqErr[1];
  5883. pseudo_bit_t KeepOnGenErr[1];
  5884. pseudo_bit_t _unused_0[4];
  5885. pseudo_bit_t SeqMismatch[1];
  5886. pseudo_bit_t GenMismatch[1];
  5887. pseudo_bit_t _unused_1[35];
  5888. };
  5889. struct QIB_7322_RcvTIDFlowTable3 {
  5890. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable3_pb );
  5891. };
  5892. /* Default value: 0x0000000000000000 */
  5893. #define QIB_7322_RcvHdrTail4_offset 0x00240000UL
  5894. /* Default value: 0x0000000000000000 */
  5895. #define QIB_7322_RcvHdrHead4_offset 0x00240008UL
  5896. struct QIB_7322_RcvHdrHead4_pb {
  5897. pseudo_bit_t RcvHeadPointer[32];
  5898. pseudo_bit_t counter[16];
  5899. pseudo_bit_t _unused_0[16];
  5900. };
  5901. struct QIB_7322_RcvHdrHead4 {
  5902. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead4_pb );
  5903. };
  5904. /* Default value: 0x0000000000000000 */
  5905. #define QIB_7322_RcvEgrIndexTail4_offset 0x00240010UL
  5906. /* Default value: 0x0000000000000000 */
  5907. #define QIB_7322_RcvEgrIndexHead4_offset 0x00240018UL
  5908. /* Default value: 0x0000000000000000 */
  5909. #define QIB_7322_RcvTIDFlowTable4_offset 0x00241000UL
  5910. struct QIB_7322_RcvTIDFlowTable4_pb {
  5911. pseudo_bit_t SeqNum[11];
  5912. pseudo_bit_t GenVal[8];
  5913. pseudo_bit_t FlowValid[1];
  5914. pseudo_bit_t HdrSuppEnabled[1];
  5915. pseudo_bit_t KeepAfterSeqErr[1];
  5916. pseudo_bit_t KeepOnGenErr[1];
  5917. pseudo_bit_t _unused_0[4];
  5918. pseudo_bit_t SeqMismatch[1];
  5919. pseudo_bit_t GenMismatch[1];
  5920. pseudo_bit_t _unused_1[35];
  5921. };
  5922. struct QIB_7322_RcvTIDFlowTable4 {
  5923. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable4_pb );
  5924. };
  5925. /* Default value: 0x0000000000000000 */
  5926. #define QIB_7322_RcvHdrTail5_offset 0x00250000UL
  5927. /* Default value: 0x0000000000000000 */
  5928. #define QIB_7322_RcvHdrHead5_offset 0x00250008UL
  5929. struct QIB_7322_RcvHdrHead5_pb {
  5930. pseudo_bit_t RcvHeadPointer[32];
  5931. pseudo_bit_t counter[16];
  5932. pseudo_bit_t _unused_0[16];
  5933. };
  5934. struct QIB_7322_RcvHdrHead5 {
  5935. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead5_pb );
  5936. };
  5937. /* Default value: 0x0000000000000000 */
  5938. #define QIB_7322_RcvEgrIndexTail5_offset 0x00250010UL
  5939. /* Default value: 0x0000000000000000 */
  5940. #define QIB_7322_RcvEgrIndexHead5_offset 0x00250018UL
  5941. /* Default value: 0x0000000000000000 */
  5942. #define QIB_7322_RcvTIDFlowTable5_offset 0x00251000UL
  5943. struct QIB_7322_RcvTIDFlowTable5_pb {
  5944. pseudo_bit_t SeqNum[11];
  5945. pseudo_bit_t GenVal[8];
  5946. pseudo_bit_t FlowValid[1];
  5947. pseudo_bit_t HdrSuppEnabled[1];
  5948. pseudo_bit_t KeepAfterSeqErr[1];
  5949. pseudo_bit_t KeepOnGenErr[1];
  5950. pseudo_bit_t _unused_0[4];
  5951. pseudo_bit_t SeqMismatch[1];
  5952. pseudo_bit_t GenMismatch[1];
  5953. pseudo_bit_t _unused_1[35];
  5954. };
  5955. struct QIB_7322_RcvTIDFlowTable5 {
  5956. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable5_pb );
  5957. };
  5958. /* Default value: 0x0000000000000000 */
  5959. #define QIB_7322_RcvHdrTail6_offset 0x00260000UL
  5960. /* Default value: 0x0000000000000000 */
  5961. #define QIB_7322_RcvHdrHead6_offset 0x00260008UL
  5962. struct QIB_7322_RcvHdrHead6_pb {
  5963. pseudo_bit_t RcvHeadPointer[32];
  5964. pseudo_bit_t counter[16];
  5965. pseudo_bit_t _unused_0[16];
  5966. };
  5967. struct QIB_7322_RcvHdrHead6 {
  5968. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead6_pb );
  5969. };
  5970. /* Default value: 0x0000000000000000 */
  5971. #define QIB_7322_RcvEgrIndexTail6_offset 0x00260010UL
  5972. /* Default value: 0x0000000000000000 */
  5973. #define QIB_7322_RcvEgrIndexHead6_offset 0x00260018UL
  5974. /* Default value: 0x0000000000000000 */
  5975. #define QIB_7322_RcvTIDFlowTable6_offset 0x00261000UL
  5976. struct QIB_7322_RcvTIDFlowTable6_pb {
  5977. pseudo_bit_t SeqNum[11];
  5978. pseudo_bit_t GenVal[8];
  5979. pseudo_bit_t FlowValid[1];
  5980. pseudo_bit_t HdrSuppEnabled[1];
  5981. pseudo_bit_t KeepAfterSeqErr[1];
  5982. pseudo_bit_t KeepOnGenErr[1];
  5983. pseudo_bit_t _unused_0[4];
  5984. pseudo_bit_t SeqMismatch[1];
  5985. pseudo_bit_t GenMismatch[1];
  5986. pseudo_bit_t _unused_1[35];
  5987. };
  5988. struct QIB_7322_RcvTIDFlowTable6 {
  5989. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable6_pb );
  5990. };
  5991. /* Default value: 0x0000000000000000 */
  5992. #define QIB_7322_RcvHdrTail7_offset 0x00270000UL
  5993. /* Default value: 0x0000000000000000 */
  5994. #define QIB_7322_RcvHdrHead7_offset 0x00270008UL
  5995. struct QIB_7322_RcvHdrHead7_pb {
  5996. pseudo_bit_t RcvHeadPointer[32];
  5997. pseudo_bit_t counter[16];
  5998. pseudo_bit_t _unused_0[16];
  5999. };
  6000. struct QIB_7322_RcvHdrHead7 {
  6001. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead7_pb );
  6002. };
  6003. /* Default value: 0x0000000000000000 */
  6004. #define QIB_7322_RcvEgrIndexTail7_offset 0x00270010UL
  6005. /* Default value: 0x0000000000000000 */
  6006. #define QIB_7322_RcvEgrIndexHead7_offset 0x00270018UL
  6007. /* Default value: 0x0000000000000000 */
  6008. #define QIB_7322_RcvTIDFlowTable7_offset 0x00271000UL
  6009. struct QIB_7322_RcvTIDFlowTable7_pb {
  6010. pseudo_bit_t SeqNum[11];
  6011. pseudo_bit_t GenVal[8];
  6012. pseudo_bit_t FlowValid[1];
  6013. pseudo_bit_t HdrSuppEnabled[1];
  6014. pseudo_bit_t KeepAfterSeqErr[1];
  6015. pseudo_bit_t KeepOnGenErr[1];
  6016. pseudo_bit_t _unused_0[4];
  6017. pseudo_bit_t SeqMismatch[1];
  6018. pseudo_bit_t GenMismatch[1];
  6019. pseudo_bit_t _unused_1[35];
  6020. };
  6021. struct QIB_7322_RcvTIDFlowTable7 {
  6022. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable7_pb );
  6023. };
  6024. /* Default value: 0x0000000000000000 */
  6025. #define QIB_7322_RcvHdrTail8_offset 0x00280000UL
  6026. /* Default value: 0x0000000000000000 */
  6027. #define QIB_7322_RcvHdrHead8_offset 0x00280008UL
  6028. struct QIB_7322_RcvHdrHead8_pb {
  6029. pseudo_bit_t RcvHeadPointer[32];
  6030. pseudo_bit_t counter[16];
  6031. pseudo_bit_t _unused_0[16];
  6032. };
  6033. struct QIB_7322_RcvHdrHead8 {
  6034. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead8_pb );
  6035. };
  6036. /* Default value: 0x0000000000000000 */
  6037. #define QIB_7322_RcvEgrIndexTail8_offset 0x00280010UL
  6038. /* Default value: 0x0000000000000000 */
  6039. #define QIB_7322_RcvEgrIndexHead8_offset 0x00280018UL
  6040. /* Default value: 0x0000000000000000 */
  6041. #define QIB_7322_RcvTIDFlowTable8_offset 0x00281000UL
  6042. struct QIB_7322_RcvTIDFlowTable8_pb {
  6043. pseudo_bit_t SeqNum[11];
  6044. pseudo_bit_t GenVal[8];
  6045. pseudo_bit_t FlowValid[1];
  6046. pseudo_bit_t HdrSuppEnabled[1];
  6047. pseudo_bit_t KeepAfterSeqErr[1];
  6048. pseudo_bit_t KeepOnGenErr[1];
  6049. pseudo_bit_t _unused_0[4];
  6050. pseudo_bit_t SeqMismatch[1];
  6051. pseudo_bit_t GenMismatch[1];
  6052. pseudo_bit_t _unused_1[35];
  6053. };
  6054. struct QIB_7322_RcvTIDFlowTable8 {
  6055. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable8_pb );
  6056. };
  6057. /* Default value: 0x0000000000000000 */
  6058. #define QIB_7322_RcvHdrTail9_offset 0x00290000UL
  6059. /* Default value: 0x0000000000000000 */
  6060. #define QIB_7322_RcvHdrHead9_offset 0x00290008UL
  6061. struct QIB_7322_RcvHdrHead9_pb {
  6062. pseudo_bit_t RcvHeadPointer[32];
  6063. pseudo_bit_t counter[16];
  6064. pseudo_bit_t _unused_0[16];
  6065. };
  6066. struct QIB_7322_RcvHdrHead9 {
  6067. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead9_pb );
  6068. };
  6069. /* Default value: 0x0000000000000000 */
  6070. #define QIB_7322_RcvEgrIndexTail9_offset 0x00290010UL
  6071. /* Default value: 0x0000000000000000 */
  6072. #define QIB_7322_RcvEgrIndexHead9_offset 0x00290018UL
  6073. /* Default value: 0x0000000000000000 */
  6074. #define QIB_7322_RcvTIDFlowTable9_offset 0x00291000UL
  6075. struct QIB_7322_RcvTIDFlowTable9_pb {
  6076. pseudo_bit_t SeqNum[11];
  6077. pseudo_bit_t GenVal[8];
  6078. pseudo_bit_t FlowValid[1];
  6079. pseudo_bit_t HdrSuppEnabled[1];
  6080. pseudo_bit_t KeepAfterSeqErr[1];
  6081. pseudo_bit_t KeepOnGenErr[1];
  6082. pseudo_bit_t _unused_0[4];
  6083. pseudo_bit_t SeqMismatch[1];
  6084. pseudo_bit_t GenMismatch[1];
  6085. pseudo_bit_t _unused_1[35];
  6086. };
  6087. struct QIB_7322_RcvTIDFlowTable9 {
  6088. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable9_pb );
  6089. };
  6090. /* Default value: 0x0000000000000000 */
  6091. #define QIB_7322_RcvHdrTail10_offset 0x002a0000UL
  6092. /* Default value: 0x0000000000000000 */
  6093. #define QIB_7322_RcvHdrHead10_offset 0x002a0008UL
  6094. struct QIB_7322_RcvHdrHead10_pb {
  6095. pseudo_bit_t RcvHeadPointer[32];
  6096. pseudo_bit_t counter[16];
  6097. pseudo_bit_t _unused_0[16];
  6098. };
  6099. struct QIB_7322_RcvHdrHead10 {
  6100. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead10_pb );
  6101. };
  6102. /* Default value: 0x0000000000000000 */
  6103. #define QIB_7322_RcvEgrIndexTail10_offset 0x002a0010UL
  6104. /* Default value: 0x0000000000000000 */
  6105. #define QIB_7322_RcvEgrIndexHead10_offset 0x002a0018UL
  6106. /* Default value: 0x0000000000000000 */
  6107. #define QIB_7322_RcvTIDFlowTable10_offset 0x002a1000UL
  6108. struct QIB_7322_RcvTIDFlowTable10_pb {
  6109. pseudo_bit_t SeqNum[11];
  6110. pseudo_bit_t GenVal[8];
  6111. pseudo_bit_t FlowValid[1];
  6112. pseudo_bit_t HdrSuppEnabled[1];
  6113. pseudo_bit_t KeepAfterSeqErr[1];
  6114. pseudo_bit_t KeepOnGenErr[1];
  6115. pseudo_bit_t _unused_0[4];
  6116. pseudo_bit_t SeqMismatch[1];
  6117. pseudo_bit_t GenMismatch[1];
  6118. pseudo_bit_t _unused_1[35];
  6119. };
  6120. struct QIB_7322_RcvTIDFlowTable10 {
  6121. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable10_pb );
  6122. };
  6123. /* Default value: 0x0000000000000000 */
  6124. #define QIB_7322_RcvHdrTail11_offset 0x002b0000UL
  6125. /* Default value: 0x0000000000000000 */
  6126. #define QIB_7322_RcvHdrHead11_offset 0x002b0008UL
  6127. struct QIB_7322_RcvHdrHead11_pb {
  6128. pseudo_bit_t RcvHeadPointer[32];
  6129. pseudo_bit_t counter[16];
  6130. pseudo_bit_t _unused_0[16];
  6131. };
  6132. struct QIB_7322_RcvHdrHead11 {
  6133. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead11_pb );
  6134. };
  6135. /* Default value: 0x0000000000000000 */
  6136. #define QIB_7322_RcvEgrIndexTail11_offset 0x002b0010UL
  6137. /* Default value: 0x0000000000000000 */
  6138. #define QIB_7322_RcvEgrIndexHead11_offset 0x002b0018UL
  6139. /* Default value: 0x0000000000000000 */
  6140. #define QIB_7322_RcvTIDFlowTable11_offset 0x002b1000UL
  6141. struct QIB_7322_RcvTIDFlowTable11_pb {
  6142. pseudo_bit_t SeqNum[11];
  6143. pseudo_bit_t GenVal[8];
  6144. pseudo_bit_t FlowValid[1];
  6145. pseudo_bit_t HdrSuppEnabled[1];
  6146. pseudo_bit_t KeepAfterSeqErr[1];
  6147. pseudo_bit_t KeepOnGenErr[1];
  6148. pseudo_bit_t _unused_0[4];
  6149. pseudo_bit_t SeqMismatch[1];
  6150. pseudo_bit_t GenMismatch[1];
  6151. pseudo_bit_t _unused_1[35];
  6152. };
  6153. struct QIB_7322_RcvTIDFlowTable11 {
  6154. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable11_pb );
  6155. };
  6156. /* Default value: 0x0000000000000000 */
  6157. #define QIB_7322_RcvHdrTail12_offset 0x002c0000UL
  6158. /* Default value: 0x0000000000000000 */
  6159. #define QIB_7322_RcvHdrHead12_offset 0x002c0008UL
  6160. struct QIB_7322_RcvHdrHead12_pb {
  6161. pseudo_bit_t RcvHeadPointer[32];
  6162. pseudo_bit_t counter[16];
  6163. pseudo_bit_t _unused_0[16];
  6164. };
  6165. struct QIB_7322_RcvHdrHead12 {
  6166. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead12_pb );
  6167. };
  6168. /* Default value: 0x0000000000000000 */
  6169. #define QIB_7322_RcvEgrIndexTail12_offset 0x002c0010UL
  6170. /* Default value: 0x0000000000000000 */
  6171. #define QIB_7322_RcvEgrIndexHead12_offset 0x002c0018UL
  6172. /* Default value: 0x0000000000000000 */
  6173. #define QIB_7322_RcvTIDFlowTable12_offset 0x002c1000UL
  6174. struct QIB_7322_RcvTIDFlowTable12_pb {
  6175. pseudo_bit_t SeqNum[11];
  6176. pseudo_bit_t GenVal[8];
  6177. pseudo_bit_t FlowValid[1];
  6178. pseudo_bit_t HdrSuppEnabled[1];
  6179. pseudo_bit_t KeepAfterSeqErr[1];
  6180. pseudo_bit_t KeepOnGenErr[1];
  6181. pseudo_bit_t _unused_0[4];
  6182. pseudo_bit_t SeqMismatch[1];
  6183. pseudo_bit_t GenMismatch[1];
  6184. pseudo_bit_t _unused_1[35];
  6185. };
  6186. struct QIB_7322_RcvTIDFlowTable12 {
  6187. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable12_pb );
  6188. };
  6189. /* Default value: 0x0000000000000000 */
  6190. #define QIB_7322_RcvHdrTail13_offset 0x002d0000UL
  6191. /* Default value: 0x0000000000000000 */
  6192. #define QIB_7322_RcvHdrHead13_offset 0x002d0008UL
  6193. struct QIB_7322_RcvHdrHead13_pb {
  6194. pseudo_bit_t RcvHeadPointer[32];
  6195. pseudo_bit_t counter[16];
  6196. pseudo_bit_t _unused_0[16];
  6197. };
  6198. struct QIB_7322_RcvHdrHead13 {
  6199. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead13_pb );
  6200. };
  6201. /* Default value: 0x0000000000000000 */
  6202. #define QIB_7322_RcvEgrIndexTail13_offset 0x002d0010UL
  6203. /* Default value: 0x0000000000000000 */
  6204. #define QIB_7322_RcvEgrIndexHead13_offset 0x002d0018UL
  6205. /* Default value: 0x0000000000000000 */
  6206. #define QIB_7322_RcvTIDFlowTable13_offset 0x002d1000UL
  6207. struct QIB_7322_RcvTIDFlowTable13_pb {
  6208. pseudo_bit_t SeqNum[11];
  6209. pseudo_bit_t GenVal[8];
  6210. pseudo_bit_t FlowValid[1];
  6211. pseudo_bit_t HdrSuppEnabled[1];
  6212. pseudo_bit_t KeepAfterSeqErr[1];
  6213. pseudo_bit_t KeepOnGenErr[1];
  6214. pseudo_bit_t _unused_0[4];
  6215. pseudo_bit_t SeqMismatch[1];
  6216. pseudo_bit_t GenMismatch[1];
  6217. pseudo_bit_t _unused_1[35];
  6218. };
  6219. struct QIB_7322_RcvTIDFlowTable13 {
  6220. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable13_pb );
  6221. };
  6222. /* Default value: 0x0000000000000000 */
  6223. #define QIB_7322_RcvHdrTail14_offset 0x002e0000UL
  6224. /* Default value: 0x0000000000000000 */
  6225. #define QIB_7322_RcvHdrHead14_offset 0x002e0008UL
  6226. struct QIB_7322_RcvHdrHead14_pb {
  6227. pseudo_bit_t RcvHeadPointer[32];
  6228. pseudo_bit_t counter[16];
  6229. pseudo_bit_t _unused_0[16];
  6230. };
  6231. struct QIB_7322_RcvHdrHead14 {
  6232. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead14_pb );
  6233. };
  6234. /* Default value: 0x0000000000000000 */
  6235. #define QIB_7322_RcvEgrIndexTail14_offset 0x002e0010UL
  6236. /* Default value: 0x0000000000000000 */
  6237. #define QIB_7322_RcvEgrIndexHead14_offset 0x002e0018UL
  6238. /* Default value: 0x0000000000000000 */
  6239. #define QIB_7322_RcvTIDFlowTable14_offset 0x002e1000UL
  6240. struct QIB_7322_RcvTIDFlowTable14_pb {
  6241. pseudo_bit_t SeqNum[11];
  6242. pseudo_bit_t GenVal[8];
  6243. pseudo_bit_t FlowValid[1];
  6244. pseudo_bit_t HdrSuppEnabled[1];
  6245. pseudo_bit_t KeepAfterSeqErr[1];
  6246. pseudo_bit_t KeepOnGenErr[1];
  6247. pseudo_bit_t _unused_0[4];
  6248. pseudo_bit_t SeqMismatch[1];
  6249. pseudo_bit_t GenMismatch[1];
  6250. pseudo_bit_t _unused_1[35];
  6251. };
  6252. struct QIB_7322_RcvTIDFlowTable14 {
  6253. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable14_pb );
  6254. };
  6255. /* Default value: 0x0000000000000000 */
  6256. #define QIB_7322_RcvHdrTail15_offset 0x002f0000UL
  6257. /* Default value: 0x0000000000000000 */
  6258. #define QIB_7322_RcvHdrHead15_offset 0x002f0008UL
  6259. struct QIB_7322_RcvHdrHead15_pb {
  6260. pseudo_bit_t RcvHeadPointer[32];
  6261. pseudo_bit_t counter[16];
  6262. pseudo_bit_t _unused_0[16];
  6263. };
  6264. struct QIB_7322_RcvHdrHead15 {
  6265. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead15_pb );
  6266. };
  6267. /* Default value: 0x0000000000000000 */
  6268. #define QIB_7322_RcvEgrIndexTail15_offset 0x002f0010UL
  6269. /* Default value: 0x0000000000000000 */
  6270. #define QIB_7322_RcvEgrIndexHead15_offset 0x002f0018UL
  6271. /* Default value: 0x0000000000000000 */
  6272. #define QIB_7322_RcvTIDFlowTable15_offset 0x002f1000UL
  6273. struct QIB_7322_RcvTIDFlowTable15_pb {
  6274. pseudo_bit_t SeqNum[11];
  6275. pseudo_bit_t GenVal[8];
  6276. pseudo_bit_t FlowValid[1];
  6277. pseudo_bit_t HdrSuppEnabled[1];
  6278. pseudo_bit_t KeepAfterSeqErr[1];
  6279. pseudo_bit_t KeepOnGenErr[1];
  6280. pseudo_bit_t _unused_0[4];
  6281. pseudo_bit_t SeqMismatch[1];
  6282. pseudo_bit_t GenMismatch[1];
  6283. pseudo_bit_t _unused_1[35];
  6284. };
  6285. struct QIB_7322_RcvTIDFlowTable15 {
  6286. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable15_pb );
  6287. };
  6288. /* Default value: 0x0000000000000000 */
  6289. #define QIB_7322_RcvHdrTail16_offset 0x00300000UL
  6290. /* Default value: 0x0000000000000000 */
  6291. #define QIB_7322_RcvHdrHead16_offset 0x00300008UL
  6292. struct QIB_7322_RcvHdrHead16_pb {
  6293. pseudo_bit_t RcvHeadPointer[32];
  6294. pseudo_bit_t counter[16];
  6295. pseudo_bit_t _unused_0[16];
  6296. };
  6297. struct QIB_7322_RcvHdrHead16 {
  6298. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead16_pb );
  6299. };
  6300. /* Default value: 0x0000000000000000 */
  6301. #define QIB_7322_RcvEgrIndexTail16_offset 0x00300010UL
  6302. /* Default value: 0x0000000000000000 */
  6303. #define QIB_7322_RcvEgrIndexHead16_offset 0x00300018UL
  6304. /* Default value: 0x0000000000000000 */
  6305. #define QIB_7322_RcvTIDFlowTable16_offset 0x00301000UL
  6306. struct QIB_7322_RcvTIDFlowTable16_pb {
  6307. pseudo_bit_t SeqNum[11];
  6308. pseudo_bit_t GenVal[8];
  6309. pseudo_bit_t FlowValid[1];
  6310. pseudo_bit_t HdrSuppEnabled[1];
  6311. pseudo_bit_t KeepAfterSeqErr[1];
  6312. pseudo_bit_t KeepOnGenErr[1];
  6313. pseudo_bit_t _unused_0[4];
  6314. pseudo_bit_t SeqMismatch[1];
  6315. pseudo_bit_t GenMismatch[1];
  6316. pseudo_bit_t _unused_1[35];
  6317. };
  6318. struct QIB_7322_RcvTIDFlowTable16 {
  6319. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable16_pb );
  6320. };
  6321. /* Default value: 0x0000000000000000 */
  6322. #define QIB_7322_RcvHdrTail17_offset 0x00310000UL
  6323. /* Default value: 0x0000000000000000 */
  6324. #define QIB_7322_RcvHdrHead17_offset 0x00310008UL
  6325. struct QIB_7322_RcvHdrHead17_pb {
  6326. pseudo_bit_t RcvHeadPointer[32];
  6327. pseudo_bit_t counter[16];
  6328. pseudo_bit_t _unused_0[16];
  6329. };
  6330. struct QIB_7322_RcvHdrHead17 {
  6331. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrHead17_pb );
  6332. };
  6333. /* Default value: 0x0000000000000000 */
  6334. #define QIB_7322_RcvEgrIndexTail17_offset 0x00310010UL
  6335. /* Default value: 0x0000000000000000 */
  6336. #define QIB_7322_RcvEgrIndexHead17_offset 0x00310018UL
  6337. /* Default value: 0x0000000000000000 */
  6338. #define QIB_7322_RcvTIDFlowTable17_offset 0x00311000UL
  6339. struct QIB_7322_RcvTIDFlowTable17_pb {
  6340. pseudo_bit_t SeqNum[11];
  6341. pseudo_bit_t GenVal[8];
  6342. pseudo_bit_t FlowValid[1];
  6343. pseudo_bit_t HdrSuppEnabled[1];
  6344. pseudo_bit_t KeepAfterSeqErr[1];
  6345. pseudo_bit_t KeepOnGenErr[1];
  6346. pseudo_bit_t _unused_0[4];
  6347. pseudo_bit_t SeqMismatch[1];
  6348. pseudo_bit_t GenMismatch[1];
  6349. pseudo_bit_t _unused_1[35];
  6350. };
  6351. struct QIB_7322_RcvTIDFlowTable17 {
  6352. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvTIDFlowTable17_pb );
  6353. };
  6354. /* Default value: 0x0000000000000000 */