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natsemi.h 9.7KB

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  1. #ifndef _NATSEMI_H
  2. #define _NATSEMI_H
  3. /** @file
  4. *
  5. * National Semiconductor "MacPhyter" network card driver
  6. *
  7. */
  8. FILE_LICENCE ( GPL2_OR_LATER );
  9. #include <stdint.h>
  10. #include <ipxe/spi.h>
  11. #include <ipxe/spi_bit.h>
  12. /** BAR size */
  13. #define NATSEMI_BAR_SIZE 0x100
  14. /** A 32-bit packet descriptor */
  15. struct natsemi_descriptor_32 {
  16. /** Link to next descriptor */
  17. uint32_t link;
  18. /** Command / status */
  19. uint32_t cmdsts;
  20. /** Buffer pointer */
  21. uint32_t bufptr;
  22. } __attribute__ (( packed ));
  23. /** A 64-bit packet descriptor */
  24. struct natsemi_descriptor_64 {
  25. /** Link to next descriptor */
  26. uint64_t link;
  27. /** Buffer pointer */
  28. uint64_t bufptr;
  29. /** Command / status */
  30. uint32_t cmdsts;
  31. /** Extended status */
  32. uint32_t extsts;
  33. } __attribute__ (( packed ));
  34. /** A packet descriptor
  35. *
  36. * The 32-bit and 64-bit variants are overlaid such that "cmdsts" can
  37. * be accessed as a common field, and the overall size is a power of
  38. * two (to allow the descriptor ring length to be used as an
  39. * alignment).
  40. */
  41. union natsemi_descriptor {
  42. /** Common fields */
  43. struct {
  44. /** Reserved */
  45. uint8_t reserved_a[16];
  46. /** Command / status */
  47. uint32_t cmdsts;
  48. /** Reserved */
  49. uint8_t reserved_b[12];
  50. } __attribute__ (( packed )) common;
  51. /** 64-bit descriptor */
  52. struct natsemi_descriptor_64 d64;
  53. /** 32-bit descriptor */
  54. struct {
  55. /** Reserved */
  56. uint8_t reserved[12];
  57. /** Descriptor */
  58. struct natsemi_descriptor_32 d32;
  59. } __attribute__ (( packed )) d32pad;
  60. };
  61. /** Descriptor buffer size mask */
  62. #define NATSEMI_DESC_SIZE_MASK 0xfff
  63. /** Packet descriptor flags */
  64. enum natsemi_descriptor_flags {
  65. /** Descriptor is owned by NIC */
  66. NATSEMI_DESC_OWN = 0x80000000UL,
  67. /** Request descriptor interrupt */
  68. NATSEMI_DESC_INTR = 0x20000000UL,
  69. /** Packet OK */
  70. NATSEMI_DESC_OK = 0x08000000UL,
  71. };
  72. /** Command Register */
  73. #define NATSEMI_CR 0x0000
  74. #define NATSEMI_CR_RST 0x00000100UL /**< Reset */
  75. #define NATSEMI_CR_RXR 0x00000020UL /**< Receiver reset */
  76. #define NATSEMI_CR_TXR 0x00000010UL /**< Transmit reset */
  77. #define NATSEMI_CR_RXE 0x00000004UL /**< Receiver enable */
  78. #define NATSEMI_CR_TXE 0x00000001UL /**< Transmit enable */
  79. /** Maximum time to wait for a reset, in milliseconds */
  80. #define NATSEMI_RESET_MAX_WAIT_MS 100
  81. /** Configuration and Media Status Register */
  82. #define NATSEMI_CFG 0x0004
  83. #define NATSEMI_CFG_LNKSTS 0x80000000UL /**< Link status */
  84. #define NATSEMI_CFG_SPDSTS1 0x40000000UL /**< Speed status bit 1 */
  85. #define NATSEMI_CFG_MODE_1000 0x00400000UL /**< 1000 Mb/s mode control */
  86. #define NATSEMI_CFG_PCI64_DET 0x00002000UL /**< PCI 64-bit bus detected */
  87. #define NATSEMI_CFG_DATA64_EN 0x00001000UL /**< 64-bit data enable */
  88. #define NATSEMI_CFG_M64ADDR 0x00000800UL /**< 64-bit address enable */
  89. #define NATSEMI_CFG_EXTSTS_EN 0x00000100UL /**< Extended status enable */
  90. /** EEPROM Access Register */
  91. #define NATSEMI_MEAR 0x0008
  92. #define NATSEMI_MEAR_EESEL 0x00000008UL /**< EEPROM chip select */
  93. #define NATSEMI_MEAR_EECLK 0x00000004UL /**< EEPROM serial clock */
  94. #define NATSEMI_MEAR_EEDO 0x00000002UL /**< EEPROM data out */
  95. #define NATSEMI_MEAR_EEDI 0x00000001UL /**< EEPROM data in */
  96. /** Size of EEPROM (in bytes) */
  97. #define NATSEMI_EEPROM_SIZE 32
  98. /** Word offset of MAC address within sane EEPROM layout */
  99. #define NATSEMI_EEPROM_MAC_SANE 0x0a
  100. /** Word offset of MAC address within insane EEPROM layout */
  101. #define NATSEMI_EEPROM_MAC_INSANE 0x06
  102. /** PCI Test Control Register */
  103. #define NATSEMI_PTSCR 0x000c
  104. #define NATSEMI_PTSCR_EELOAD_EN 0x00000004UL /**< Enable EEPROM load */
  105. /** Maximum time to wait for a configuration reload, in milliseconds */
  106. #define NATSEMI_EELOAD_MAX_WAIT_MS 100
  107. /** Interrupt Status Register */
  108. #define NATSEMI_ISR 0x0010
  109. #define NATSEMI_IRQ_TXDESC 0x00000080UL /**< TX descriptor */
  110. #define NATSEMI_IRQ_RXDESC 0x00000002UL /**< RX descriptor */
  111. /** Interrupt Mask Register */
  112. #define NATSEMI_IMR 0x0014
  113. /** Interrupt Enable Register */
  114. #define NATSEMI_IER 0x0018
  115. #define NATSEMI_IER_IE 0x00000001UL /**< Interrupt enable */
  116. /** Transmit Descriptor Pointer */
  117. #define NATSEMI_TXDP 0x0020
  118. /** Transmit Descriptor Pointer High Dword (64-bit) */
  119. #define NATSEMI_TXDP_HI_64 0x0024
  120. /** Number of transmit descriptors */
  121. #define NATSEMI_NUM_TX_DESC 4
  122. /** Transmit configuration register (32-bit) */
  123. #define NATSEMI_TXCFG_32 0x24
  124. /** Transmit configuration register (64-bit) */
  125. #define NATSEMI_TXCFG_64 0x28
  126. #define NATSEMI_TXCFG_CSI 0x80000000UL /**< Carrier sense ignore */
  127. #define NATSEMI_TXCFG_HBI 0x40000000UL /**< Heartbeat ignore */
  128. #define NATSEMI_TXCFG_ATP 0x10000000UL /**< Automatic padding */
  129. #define NATSEMI_TXCFG_ECRETRY 0x00800000UL /**< Excess collision retry */
  130. #define NATSEMI_TXCFG_MXDMA(x) ( (x) << 20 ) /**< Max DMA burst size */
  131. #define NATSEMI_TXCFG_FLTH(x) ( (x) << 8 ) /**< Fill threshold */
  132. #define NATSEMI_TXCFG_DRTH(x) ( (x) << 0 ) /**< Drain threshold */
  133. /** Max DMA burst size (encoded value)
  134. *
  135. * This represents 256-byte bursts on 83815 controllers and 512-byte
  136. * bursts on 83820 controllers.
  137. */
  138. #define NATSEMI_TXCFG_MXDMA_DEFAULT NATSEMI_TXCFG_MXDMA ( 0x7 )
  139. /** Fill threshold (in units of 32 bytes)
  140. *
  141. * Must be at least as large as the max DMA burst size, so use a value
  142. * of 512 bytes.
  143. */
  144. #define NATSEMI_TXCFG_FLTH_DEFAULT NATSEMI_TXCFG_FLTH ( 512 / 32 )
  145. /** Drain threshold (in units of 32 bytes)
  146. *
  147. * Start transmission once we receive a conservative 1024 bytes, to
  148. * avoid FIFO underrun errors. (83815 does not allow us to specify a
  149. * value of 0 for "wait until whole packet is present".)
  150. *
  151. * Fill threshold plus drain threshold must be less than the transmit
  152. * FIFO size, which is 2kB on 83815 and 8kB on 83820.
  153. */
  154. #define NATSEMI_TXCFG_DRTH_DEFAULT NATSEMI_TXCFG_DRTH ( 1024 / 32 )
  155. /** Receive Descriptor Pointer */
  156. #define NATSEMI_RXDP 0x0030
  157. /** Receive Descriptor Pointer High Dword (64-bit) */
  158. #define NATSEMI_RXDP_HI_64 0x0034
  159. /** Number of receive descriptors */
  160. #define NATSEMI_NUM_RX_DESC 4
  161. /** Receive buffer length */
  162. #define NATSEMI_RX_MAX_LEN ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ )
  163. /** Receive configuration register (32-bit) */
  164. #define NATSEMI_RXCFG_32 0x34
  165. /** Receive configuration register (64-bit) */
  166. #define NATSEMI_RXCFG_64 0x38
  167. #define NATSEMI_RXCFG_ARP 0x40000000UL /**< Accept runt packets */
  168. #define NATSEMI_RXCFG_ATX 0x10000000UL /**< Accept transmit packets */
  169. #define NATSEMI_RXCFG_ALP 0x08000000UL /**< Accept long packets */
  170. #define NATSEMI_RXCFG_MXDMA(x) ( (x) << 20 ) /**< Max DMA burst size */
  171. #define NATSEMI_RXCFG_DRTH(x) ( (x) << 1 ) /**< Drain threshold */
  172. /** Max DMA burst size (encoded value)
  173. *
  174. * This represents 256-byte bursts on 83815 controllers and 512-byte
  175. * bursts on 83820 controllers.
  176. */
  177. #define NATSEMI_RXCFG_MXDMA_DEFAULT NATSEMI_RXCFG_MXDMA ( 0x7 )
  178. /** Drain threshold (in units of 8 bytes)
  179. *
  180. * Start draining after 64 bytes.
  181. *
  182. * Must be large enough to allow packet's accept/reject status to be
  183. * determined before draining begins.
  184. */
  185. #define NATSEMI_RXCFG_DRTH_DEFAULT NATSEMI_RXCFG_DRTH ( 64 / 8 )
  186. /** Receive Filter/Match Control Register */
  187. #define NATSEMI_RFCR 0x0048
  188. #define NATSEMI_RFCR_RFEN 0x80000000UL /**< RX filter enable */
  189. #define NATSEMI_RFCR_AAB 0x40000000UL /**< Accept all broadcast */
  190. #define NATSEMI_RFCR_AAM 0x20000000UL /**< Accept all multicast */
  191. #define NATSEMI_RFCR_AAU 0x10000000UL /**< Accept all unicast */
  192. #define NATSEMI_RFCR_RFADDR( addr ) ( (addr) << 0 ) /**< Extended address */
  193. #define NATSEMI_RFCR_RFADDR_MASK NATSEMI_RFCR_RFADDR ( 0x3ff )
  194. /** Perfect match filter address base */
  195. #define NATSEMI_RFADDR_PMATCH_BASE 0x000
  196. /** Receive Filter/Match Data Register */
  197. #define NATSEMI_RFDR 0x004c
  198. #define NATSEMI_RFDR_BMASK 0x00030000UL /**< Byte mask */
  199. #define NATSEMI_RFDR_DATA( value ) ( (value) & 0xffff ) /**< Filter data */
  200. /** National Semiconductor network card flags */
  201. enum natsemi_nic_flags {
  202. /** EEPROM is little-endian */
  203. NATSEMI_EEPROM_LITTLE_ENDIAN = 0x0001,
  204. /** EEPROM layout is insane */
  205. NATSEMI_EEPROM_INSANE = 0x0002,
  206. /** Card supports 64-bit operation */
  207. NATSEMI_64BIT = 0x0004,
  208. /** Card supports 1000Mbps link */
  209. NATSEMI_1000 = 0x0008,
  210. };
  211. /** A National Semiconductor descriptor ring */
  212. struct natsemi_ring {
  213. /** Descriptors */
  214. union natsemi_descriptor *desc;
  215. /** Producer index */
  216. unsigned int prod;
  217. /** Consumer index */
  218. unsigned int cons;
  219. /** Number of descriptors */
  220. unsigned int count;
  221. /** Descriptor start address register */
  222. unsigned int reg;
  223. };
  224. /**
  225. * Initialise descriptor ring
  226. *
  227. * @v ring Descriptor ring
  228. * @v count Number of descriptors
  229. * @v reg Descriptor start address register
  230. */
  231. static inline __attribute__ (( always_inline)) void
  232. natsemi_init_ring ( struct natsemi_ring *ring, unsigned int count,
  233. unsigned int reg ) {
  234. ring->count = count;
  235. ring->reg = reg;
  236. }
  237. /** A National Semiconductor network card */
  238. struct natsemi_nic {
  239. /** Flags */
  240. unsigned int flags;
  241. /** Registers */
  242. void *regs;
  243. /** SPI bit-bashing interface */
  244. struct spi_bit_basher spibit;
  245. /** EEPROM */
  246. struct spi_device eeprom;
  247. /** Transmit descriptor ring */
  248. struct natsemi_ring tx;
  249. /** Receive descriptor ring */
  250. struct natsemi_ring rx;
  251. /** Receive I/O buffers */
  252. struct io_buffer *rx_iobuf[NATSEMI_NUM_RX_DESC];
  253. /** Link status (cache) */
  254. uint32_t cfg;
  255. };
  256. /**
  257. * Check if card can access physical address
  258. *
  259. * @v natsemi National Semiconductor device
  260. * @v address Physical address
  261. * @v address_ok Card can access physical address
  262. */
  263. static inline __attribute__ (( always_inline )) int
  264. natsemi_address_ok ( struct natsemi_nic *natsemi, physaddr_t address ) {
  265. /* In a 32-bit build, all addresses can be accessed */
  266. if ( sizeof ( physaddr_t ) <= sizeof ( uint32_t ) )
  267. return 1;
  268. /* A 64-bit card can access all addresses */
  269. if ( natsemi->flags & NATSEMI_64BIT )
  270. return 1;
  271. /* A 32-bit card can access all addresses below 4GB */
  272. if ( ( address & ~0xffffffffULL ) == 0 )
  273. return 1;
  274. return 0;
  275. }
  276. #endif /* _NATSEMI_H */