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ipxe/src/arch/armnommu/include/hardware.h

hardware.h 7.3KB
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  1. /*

  2.  *  Copyright (C) 2004 Tobias Lorenz

  3.  *

  4.  * This program is free software; you can redistribute it and/or modify

  5.  * it under the terms of the GNU General Public License version 2 as

  6.  * published by the Free Software Foundation.

  7.  */

  8. 

  9. /*

  10.  * Architecture: ARM9TDMI

  11.  * Processor   : P2001

  12.  */

  13. 

  14. #ifndef ARCH_HARDWARE_H

  15. #define ARCH_HARDWARE_H

  16. 

  17. #ifndef __ASSEMBLY__

  18. 

  19. /* DMA descriptor */

  20. typedef struct {

  21. 	unsigned int stat;			/* status: own, start, end, offset, status */

  22. 	unsigned int cntl;			/* control: loop, int, type, channel, length */

  23. 	char	*buf;				/* buffer */

  24. 	void	*next;				/* nextdsc */

  25. } DMA_DSC;

  26. 

  27. 

  28. /* The address definitions are from asic_bf.h */

  29. typedef struct {					// 0x00100000U

  30. 	volatile unsigned int reserved1[0x3];

  31. 	volatile unsigned int ArmDmaPri;		// 0x0000000CU

  32. 	volatile unsigned int SDRAM_Ctrl;		// 0x00000010U

  33. 	volatile unsigned int ExtMem_Ctrl;		// 0x00000014U

  34. 	volatile unsigned int WaitState_Ext;		// 0x00000018U

  35. 	volatile unsigned int WaitState_Asic;		// 0x0000001CU

  36. 	volatile unsigned int TOP;			// 0x00000020U

  37. 	volatile unsigned int reserved2[0x3];

  38. 	volatile unsigned int Adr1_EQ_30Bit;		// 0x00000030U

  39. 	volatile unsigned int Adr2_EQ_30Bit;		// 0x00000034U

  40. 	volatile unsigned int Adr3_EQ_30Bit;		// 0x00000038U

  41. 	volatile unsigned int Dat3_EQ_32Bit;		// 0x0000003CU

  42. 	volatile unsigned int Adr4_HE_20Bit;		// 0x00000040U

  43. 	volatile unsigned int Adr4_LT_20Bit;		// 0x00000044U

  44. 	volatile unsigned int Adr5_HE_20Bit;		// 0x00000048U

  45. 	volatile unsigned int Adr5_LT_20Bit;		// 0x0000004CU

  46. 	volatile unsigned int Adr_Control;		// 0x00000050U

  47. 	volatile unsigned int ABORT_IA_32Bit;		// 0x00000054U

  48. } *P2001_SYS_regs_ptr;

  49. #define P2001_SYS ((volatile P2001_SYS_regs_ptr) 0x00100000)

  50. 

  51. typedef struct {					// 0x00110000U

  52. 	volatile unsigned int Timer1;			// 0x00000000U

  53. 	volatile unsigned int Timer2;			// 0x00000004U

  54. 	volatile unsigned int TIMER_PRELOAD;		// 0x00000008U

  55. 	volatile unsigned int Timer12_PreDiv;		// 0x0000000CU

  56. 	volatile unsigned int TIMER_INT;		// 0x00000010U

  57. 	volatile unsigned int Freerun_Timer;		// 0x00000014U

  58. 	volatile unsigned int WatchDog_Timer;		// 0x00000018U

  59. 	volatile unsigned int PWM_CNT;			// 0x00000020U

  60. 	volatile unsigned int PWM_CNT2;			// 0x00000024U

  61. 	volatile unsigned int PLL_12000_config;		// 0x00000030U

  62. 	volatile unsigned int PLL_12288_config;		// 0x00000034U

  63. 	volatile unsigned int DIV_12288_config;		// 0x00000038U

  64. 	volatile unsigned int MOD_CNT_768;		// 0x0000003CU

  65. 	volatile unsigned int FSC_IRQ_STATUS;		// 0x00000040U

  66. 	volatile unsigned int FSC_CONFIG;		// 0x00000044U

  67. 	volatile unsigned int FSC_CONSTRUCT;		// 0x00000048U

  68. 	volatile unsigned int FSC_base_clk_reg;		// 0x0000004CU

  69. 	volatile unsigned int SYSCLK_SHAPE;		// 0x00000050U

  70. 	volatile unsigned int SDRAMCLK_SHAPE;		// 0x00000054U

  71. 	volatile unsigned int RING_OSZI;		// 0x00000058U

  72. } *P2001_TIMER_regs_ptr;

  73. #define P2001_TIMER ((volatile P2001_TIMER_regs_ptr) 0x00110000)

  74. 

  75. typedef struct {					// 0x00120000U

  76. 	volatile unsigned int reserved1[0x5];

  77. 	volatile unsigned int GPIO_Config;		// 0x00000014U

  78. 	volatile unsigned int GPIO_INT;			// 0x00000018U

  79. 	volatile unsigned int GPIO_Out;			// 0x0000001CU

  80. 	volatile unsigned int GPIO_IN;			// 0x00000020U

  81. 	volatile unsigned int GPIO_En;			// 0x00000024U

  82. 	volatile unsigned int PIN_MUX;			// 0x00000028U

  83. 	volatile unsigned int NRES_OUT;			// 0x0000002CU

  84. 	volatile unsigned int GPIO2_Out;		// 0x00000030U

  85. 	volatile unsigned int GPIO2_IN;			// 0x00000034U

  86. 	volatile unsigned int GPIO2_En;			// 0x00000038U

  87. 	volatile unsigned int GPIO_INT_SEL;		// 0x0000003CU

  88. 	volatile unsigned int GPI3_IN;			// 0x00000040U

  89. 	volatile unsigned int GPO4_OUT;			// 0x00000044U

  90. } *P2001_GPIO_regs_ptr;

  91. #define P2001_GPIO ((volatile P2001_GPIO_regs_ptr) 0x00120000)

  92. 

  93. typedef struct {					// 0x00130000U

  94. 	volatile unsigned int Main_NFIQ_Int_Ctrl;	// 0x00000000U

  95. 	volatile unsigned int Main_NIRQ_Int_Ctrl;	// 0x00000004U

  96. 	volatile unsigned int Status_NFIQ;		// 0x00000008U

  97. 	volatile unsigned int Status_NIRQ;		// 0x0000000CU

  98. } *P2001_INT_CTRL_regs_ptr;

  99. #define P2001_INT_CTRL ((volatile P2001_INT_CTRL_regs_ptr) 0x00130000)

  100. 

  101. typedef union {						// 0x00140000U

  102. 	struct {	// write

  103. 		volatile unsigned int TX1;		// 0x00000000U

  104. 		volatile unsigned int TX2;		// 0x00000004U

  105. 		volatile unsigned int TX3;		// 0x00000008U

  106. 		volatile unsigned int TX4;		// 0x0000000CU

  107. 		volatile unsigned int Baudrate;		// 0x00000010U

  108. 		volatile unsigned int reserved1[0x3];

  109. 		volatile unsigned int Config;		// 0x00000020U

  110. 		volatile unsigned int Clear;		// 0x00000024U

  111. 		volatile unsigned int Echo_EN;		// 0x00000028U

  112. 		volatile unsigned int IRQ_Status;	// 0x0000002CU

  113. 	} w;		// write

  114. 	

  115. 	struct {	// read

  116. 		volatile unsigned int RX1;		// 0x00000000U

  117. 		volatile unsigned int RX2;		// 0x00000004U

  118. 		volatile unsigned int RX3;		// 0x00000008U

  119. 		volatile unsigned int RX4;		// 0x0000000CU

  120. 		volatile unsigned int reserved1[0x4];

  121. 		volatile unsigned int PRE_STATUS;	// 0x00000020U

  122. 		volatile unsigned int STATUS;		// 0x00000024U

  123. 		volatile unsigned int reserved2[0x1];

  124. 		volatile unsigned int IRQ_Status;	// 0x0000002CU

  125. 	} r;		// read

  126. } *P2001_UART_regs_ptr;

  127. #define P2001_UART ((volatile P2001_UART_regs_ptr) 0x00140000)

  128. 

  129. typedef struct {				// 0x0018_000U _=0,1,2,3

  130. 	volatile DMA_DSC *    RMAC_DMA_DESC;	// 0x00000000U

  131. 	volatile unsigned int RMAC_DMA_CNTL;	// 0x00000004U

  132. 	volatile unsigned int RMAC_DMA_STAT;	// 0x00000008U

  133. 	volatile unsigned int RMAC_DMA_EN;	// 0x0000000CU

  134. 	volatile unsigned int RMAC_CNTL;	// 0x00000010U

  135. 	volatile unsigned int RMAC_TLEN;	// 0x00000014U

  136. 	volatile unsigned int RMAC_PHYU;	// 0x00000018U

  137. 	volatile unsigned int RMAC_PHYL;	// 0x0000001CU

  138. 	volatile unsigned int RMAC_PFM0;	// 0x00000020U

  139. 	volatile unsigned int RMAC_PFM1;	// 0x00000024U

  140. 	volatile unsigned int RMAC_PFM2;	// 0x00000028U

  141. 	volatile unsigned int RMAC_PFM3;	// 0x0000002CU

  142. 	volatile unsigned int RMAC_PFM4;	// 0x00000030U

  143. 	volatile unsigned int RMAC_PFM5;	// 0x00000034U

  144. 	volatile unsigned int RMAC_PFM6;	// 0x00000038U

  145. 	volatile unsigned int RMAC_PFM7;	// 0x0000003CU

  146. 	volatile unsigned int RMAC_MIB0;	// 0x00000040U

  147. 	volatile unsigned int RMAC_MIB1;	// 0x00000044U

  148. 	volatile unsigned int RMAC_MIB2;	// 0x00000048U

  149. 	volatile unsigned int RMAC_MIB3;	// 0x0000004CU

  150. 	volatile unsigned int RMAC_MIB4;	// 0x00000050U

  151. 	volatile unsigned int RMAC_MIB5;	// 0x00000054U

  152. 	volatile unsigned int reserved1[0x1e8];

  153. 	volatile unsigned int RMAC_DMA_DATA;	// 0x000007F8U

  154. 	volatile unsigned int RMAC_DMA_ADR;	// 0x000007FCU

  155. 	volatile DMA_DSC *    TMAC_DMA_DESC;	// 0x00000800U

  156. 	volatile unsigned int TMAC_DMA_CNTL;	// 0x00000804U

  157. 	volatile unsigned int TMAC_DMA_STAT;	// 0x00000808U

  158. 	volatile unsigned int TMAC_DMA_EN;	// 0x0000080CU

  159. 	volatile unsigned int TMAC_CNTL;	// 0x00000810U

  160. 	volatile unsigned int TMAC_MIB6;	// 0x00000814U

  161. 	volatile unsigned int TMAC_MIB7;	// 0x00000818U

  162. 	volatile unsigned int reserved2[0x1];

  163. 	volatile unsigned int MU_CNTL;		// 0x00000820U

  164. 	volatile unsigned int MU_DATA;		// 0x00000824U

  165. 	volatile unsigned int MU_DIV;		// 0x00000828U

  166. 	volatile unsigned int CONF_RMII;	// 0x0000082CU

  167. 	volatile unsigned int reserved3[0x1f2];

  168. 	volatile unsigned int TMAC_DMA_DATA;	// 0x00000FF8U

  169. 	volatile unsigned int TMAC_DMA_ADR;	// 0x00000FFCU

  170. } *P2001_ETH_regs_ptr;

  171. #define P2001_EU0 ((volatile P2001_ETH_regs_ptr) 0x00180000)

  172. #define P2001_EU1 ((volatile P2001_ETH_regs_ptr) 0x00181000)

  173. #define P2001_EU2 ((volatile P2001_ETH_regs_ptr) 0x00182000)

  174. #define P2001_EU3 ((volatile P2001_ETH_regs_ptr) 0x00183000)

  175. #define P2001_MU  P2001_EU0

  176. 

  177. #endif

  178. 

  179. #endif  /* ARCH_HARDWARE_H */