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xhci.c 87KB

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  1. /*
  2. * Copyright (C) 2014 Michael Brown <mbrown@fensystems.co.uk>.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation; either version 2 of the
  7. * License, or (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but
  10. * WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  12. * General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  17. * 02110-1301, USA.
  18. *
  19. * You can also choose to distribute this program under the terms of
  20. * the Unmodified Binary Distribution Licence (as given in the file
  21. * COPYING.UBDL), provided that you have satisfied its requirements.
  22. */
  23. FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
  24. #include <stdlib.h>
  25. #include <stdio.h>
  26. #include <unistd.h>
  27. #include <string.h>
  28. #include <strings.h>
  29. #include <errno.h>
  30. #include <byteswap.h>
  31. #include <ipxe/malloc.h>
  32. #include <ipxe/umalloc.h>
  33. #include <ipxe/pci.h>
  34. #include <ipxe/usb.h>
  35. #include <ipxe/init.h>
  36. #include <ipxe/profile.h>
  37. #include "xhci.h"
  38. /** @file
  39. *
  40. * USB eXtensible Host Controller Interface (xHCI) driver
  41. *
  42. */
  43. /** Message transfer profiler */
  44. static struct profiler xhci_message_profiler __profiler =
  45. { .name = "xhci.message" };
  46. /** Stream transfer profiler */
  47. static struct profiler xhci_stream_profiler __profiler =
  48. { .name = "xhci.stream" };
  49. /** Event ring profiler */
  50. static struct profiler xhci_event_profiler __profiler =
  51. { .name = "xhci.event" };
  52. /** Transfer event profiler */
  53. static struct profiler xhci_transfer_profiler __profiler =
  54. { .name = "xhci.transfer" };
  55. /* Disambiguate the various error causes */
  56. #define EIO_DATA \
  57. __einfo_error ( EINFO_EIO_DATA )
  58. #define EINFO_EIO_DATA \
  59. __einfo_uniqify ( EINFO_EIO, ( 2 - 0 ), \
  60. "Data buffer error" )
  61. #define EIO_BABBLE \
  62. __einfo_error ( EINFO_EIO_BABBLE )
  63. #define EINFO_EIO_BABBLE \
  64. __einfo_uniqify ( EINFO_EIO, ( 3 - 0 ), \
  65. "Babble detected" )
  66. #define EIO_USB \
  67. __einfo_error ( EINFO_EIO_USB )
  68. #define EINFO_EIO_USB \
  69. __einfo_uniqify ( EINFO_EIO, ( 4 - 0 ), \
  70. "USB transaction error" )
  71. #define EIO_TRB \
  72. __einfo_error ( EINFO_EIO_TRB )
  73. #define EINFO_EIO_TRB \
  74. __einfo_uniqify ( EINFO_EIO, ( 5 - 0 ), \
  75. "TRB error" )
  76. #define EIO_STALL \
  77. __einfo_error ( EINFO_EIO_STALL )
  78. #define EINFO_EIO_STALL \
  79. __einfo_uniqify ( EINFO_EIO, ( 6 - 0 ), \
  80. "Stall error" )
  81. #define EIO_RESOURCE \
  82. __einfo_error ( EINFO_EIO_RESOURCE )
  83. #define EINFO_EIO_RESOURCE \
  84. __einfo_uniqify ( EINFO_EIO, ( 7 - 0 ), \
  85. "Resource error" )
  86. #define EIO_BANDWIDTH \
  87. __einfo_error ( EINFO_EIO_BANDWIDTH )
  88. #define EINFO_EIO_BANDWIDTH \
  89. __einfo_uniqify ( EINFO_EIO, ( 8 - 0 ), \
  90. "Bandwidth error" )
  91. #define EIO_NO_SLOTS \
  92. __einfo_error ( EINFO_EIO_NO_SLOTS )
  93. #define EINFO_EIO_NO_SLOTS \
  94. __einfo_uniqify ( EINFO_EIO, ( 9 - 0 ), \
  95. "No slots available" )
  96. #define EIO_STREAM_TYPE \
  97. __einfo_error ( EINFO_EIO_STREAM_TYPE )
  98. #define EINFO_EIO_STREAM_TYPE \
  99. __einfo_uniqify ( EINFO_EIO, ( 10 - 0 ), \
  100. "Invalid stream type" )
  101. #define EIO_SLOT \
  102. __einfo_error ( EINFO_EIO_SLOT )
  103. #define EINFO_EIO_SLOT \
  104. __einfo_uniqify ( EINFO_EIO, ( 11 - 0 ), \
  105. "Slot not enabled" )
  106. #define EIO_ENDPOINT \
  107. __einfo_error ( EINFO_EIO_ENDPOINT )
  108. #define EINFO_EIO_ENDPOINT \
  109. __einfo_uniqify ( EINFO_EIO, ( 12 - 0 ), \
  110. "Endpoint not enabled" )
  111. #define EIO_SHORT \
  112. __einfo_error ( EINFO_EIO_SHORT )
  113. #define EINFO_EIO_SHORT \
  114. __einfo_uniqify ( EINFO_EIO, ( 13 - 0 ), \
  115. "Short packet" )
  116. #define EIO_UNDERRUN \
  117. __einfo_error ( EINFO_EIO_UNDERRUN )
  118. #define EINFO_EIO_UNDERRUN \
  119. __einfo_uniqify ( EINFO_EIO, ( 14 - 0 ), \
  120. "Ring underrun" )
  121. #define EIO_OVERRUN \
  122. __einfo_error ( EINFO_EIO_OVERRUN )
  123. #define EINFO_EIO_OVERRUN \
  124. __einfo_uniqify ( EINFO_EIO, ( 15 - 0 ), \
  125. "Ring overrun" )
  126. #define EIO_VF_RING_FULL \
  127. __einfo_error ( EINFO_EIO_VF_RING_FULL )
  128. #define EINFO_EIO_VF_RING_FULL \
  129. __einfo_uniqify ( EINFO_EIO, ( 16 - 0 ), \
  130. "Virtual function event ring full" )
  131. #define EIO_PARAMETER \
  132. __einfo_error ( EINFO_EIO_PARAMETER )
  133. #define EINFO_EIO_PARAMETER \
  134. __einfo_uniqify ( EINFO_EIO, ( 17 - 0 ), \
  135. "Parameter error" )
  136. #define EIO_BANDWIDTH_OVERRUN \
  137. __einfo_error ( EINFO_EIO_BANDWIDTH_OVERRUN )
  138. #define EINFO_EIO_BANDWIDTH_OVERRUN \
  139. __einfo_uniqify ( EINFO_EIO, ( 18 - 0 ), \
  140. "Bandwidth overrun" )
  141. #define EIO_CONTEXT \
  142. __einfo_error ( EINFO_EIO_CONTEXT )
  143. #define EINFO_EIO_CONTEXT \
  144. __einfo_uniqify ( EINFO_EIO, ( 19 - 0 ), \
  145. "Context state error" )
  146. #define EIO_NO_PING \
  147. __einfo_error ( EINFO_EIO_NO_PING )
  148. #define EINFO_EIO_NO_PING \
  149. __einfo_uniqify ( EINFO_EIO, ( 20 - 0 ), \
  150. "No ping response" )
  151. #define EIO_RING_FULL \
  152. __einfo_error ( EINFO_EIO_RING_FULL )
  153. #define EINFO_EIO_RING_FULL \
  154. __einfo_uniqify ( EINFO_EIO, ( 21 - 0 ), \
  155. "Event ring full" )
  156. #define EIO_INCOMPATIBLE \
  157. __einfo_error ( EINFO_EIO_INCOMPATIBLE )
  158. #define EINFO_EIO_INCOMPATIBLE \
  159. __einfo_uniqify ( EINFO_EIO, ( 22 - 0 ), \
  160. "Incompatible device" )
  161. #define EIO_MISSED \
  162. __einfo_error ( EINFO_EIO_MISSED )
  163. #define EINFO_EIO_MISSED \
  164. __einfo_uniqify ( EINFO_EIO, ( 23 - 0 ), \
  165. "Missed service error" )
  166. #define EIO_CMD_STOPPED \
  167. __einfo_error ( EINFO_EIO_CMD_STOPPED )
  168. #define EINFO_EIO_CMD_STOPPED \
  169. __einfo_uniqify ( EINFO_EIO, ( 24 - 0 ), \
  170. "Command ring stopped" )
  171. #define EIO_CMD_ABORTED \
  172. __einfo_error ( EINFO_EIO_CMD_ABORTED )
  173. #define EINFO_EIO_CMD_ABORTED \
  174. __einfo_uniqify ( EINFO_EIO, ( 25 - 0 ), \
  175. "Command aborted" )
  176. #define EIO_STOP \
  177. __einfo_error ( EINFO_EIO_STOP )
  178. #define EINFO_EIO_STOP \
  179. __einfo_uniqify ( EINFO_EIO, ( 26 - 0 ), \
  180. "Stopped" )
  181. #define EIO_STOP_LEN \
  182. __einfo_error ( EINFO_EIO_STOP_LEN )
  183. #define EINFO_EIO_STOP_LEN \
  184. __einfo_uniqify ( EINFO_EIO, ( 27 - 0 ), \
  185. "Stopped - length invalid" )
  186. #define EIO_STOP_SHORT \
  187. __einfo_error ( EINFO_EIO_STOP_SHORT )
  188. #define EINFO_EIO_STOP_SHORT \
  189. __einfo_uniqify ( EINFO_EIO, ( 28 - 0 ), \
  190. "Stopped - short packet" )
  191. #define EIO_LATENCY \
  192. __einfo_error ( EINFO_EIO_LATENCY )
  193. #define EINFO_EIO_LATENCY \
  194. __einfo_uniqify ( EINFO_EIO, ( 29 - 0 ), \
  195. "Maximum exit latency too large" )
  196. #define EIO_ISOCH \
  197. __einfo_error ( EINFO_EIO_ISOCH )
  198. #define EINFO_EIO_ISOCH \
  199. __einfo_uniqify ( EINFO_EIO, ( 31 - 0 ), \
  200. "Isochronous buffer overrun" )
  201. #define EPROTO_LOST \
  202. __einfo_error ( EINFO_EPROTO_LOST )
  203. #define EINFO_EPROTO_LOST \
  204. __einfo_uniqify ( EINFO_EPROTO, ( 32 - 32 ), \
  205. "Event lost" )
  206. #define EPROTO_UNDEFINED \
  207. __einfo_error ( EINFO_EPROTO_UNDEFINED )
  208. #define EINFO_EPROTO_UNDEFINED \
  209. __einfo_uniqify ( EINFO_EPROTO, ( 33 - 32 ), \
  210. "Undefined error" )
  211. #define EPROTO_STREAM_ID \
  212. __einfo_error ( EINFO_EPROTO_STREAM_ID )
  213. #define EINFO_EPROTO_STREAM_ID \
  214. __einfo_uniqify ( EINFO_EPROTO, ( 34 - 32 ), \
  215. "Invalid stream ID" )
  216. #define EPROTO_SECONDARY \
  217. __einfo_error ( EINFO_EPROTO_SECONDARY )
  218. #define EINFO_EPROTO_SECONDARY \
  219. __einfo_uniqify ( EINFO_EPROTO, ( 35 - 32 ), \
  220. "Secondary bandwidth error" )
  221. #define EPROTO_SPLIT \
  222. __einfo_error ( EINFO_EPROTO_SPLIT )
  223. #define EINFO_EPROTO_SPLIT \
  224. __einfo_uniqify ( EINFO_EPROTO, ( 36 - 32 ), \
  225. "Split transaction error" )
  226. #define ECODE(code) \
  227. ( ( (code) < 32 ) ? \
  228. EUNIQ ( EINFO_EIO, ( (code) & 31 ), EIO_DATA, EIO_BABBLE, \
  229. EIO_USB, EIO_TRB, EIO_STALL, EIO_RESOURCE, \
  230. EIO_BANDWIDTH, EIO_NO_SLOTS, EIO_STREAM_TYPE, \
  231. EIO_SLOT, EIO_ENDPOINT, EIO_SHORT, EIO_UNDERRUN, \
  232. EIO_OVERRUN, EIO_VF_RING_FULL, EIO_PARAMETER, \
  233. EIO_BANDWIDTH_OVERRUN, EIO_CONTEXT, EIO_NO_PING, \
  234. EIO_RING_FULL, EIO_INCOMPATIBLE, EIO_MISSED, \
  235. EIO_CMD_STOPPED, EIO_CMD_ABORTED, EIO_STOP, \
  236. EIO_STOP_LEN, EIO_STOP_SHORT, EIO_LATENCY, \
  237. EIO_ISOCH ) : \
  238. ( (code) < 64 ) ? \
  239. EUNIQ ( EINFO_EPROTO, ( (code) & 31 ), EPROTO_LOST, \
  240. EPROTO_UNDEFINED, EPROTO_STREAM_ID, \
  241. EPROTO_SECONDARY, EPROTO_SPLIT ) : \
  242. EFAULT )
  243. /******************************************************************************
  244. *
  245. * Register access
  246. *
  247. ******************************************************************************
  248. */
  249. /**
  250. * Initialise device
  251. *
  252. * @v xhci xHCI device
  253. * @v regs MMIO registers
  254. */
  255. static void xhci_init ( struct xhci_device *xhci, void *regs ) {
  256. uint32_t hcsparams1;
  257. uint32_t hcsparams2;
  258. uint32_t hccparams1;
  259. uint32_t pagesize;
  260. size_t caplength;
  261. size_t rtsoff;
  262. size_t dboff;
  263. /* Locate capability, operational, runtime, and doorbell registers */
  264. xhci->cap = regs;
  265. caplength = readb ( xhci->cap + XHCI_CAP_CAPLENGTH );
  266. rtsoff = readl ( xhci->cap + XHCI_CAP_RTSOFF );
  267. dboff = readl ( xhci->cap + XHCI_CAP_DBOFF );
  268. xhci->op = ( xhci->cap + caplength );
  269. xhci->run = ( xhci->cap + rtsoff );
  270. xhci->db = ( xhci->cap + dboff );
  271. DBGC2 ( xhci, "XHCI %s cap %08lx op %08lx run %08lx db %08lx\n",
  272. xhci->name, virt_to_phys ( xhci->cap ),
  273. virt_to_phys ( xhci->op ), virt_to_phys ( xhci->run ),
  274. virt_to_phys ( xhci->db ) );
  275. /* Read structural parameters 1 */
  276. hcsparams1 = readl ( xhci->cap + XHCI_CAP_HCSPARAMS1 );
  277. xhci->slots = XHCI_HCSPARAMS1_SLOTS ( hcsparams1 );
  278. xhci->intrs = XHCI_HCSPARAMS1_INTRS ( hcsparams1 );
  279. xhci->ports = XHCI_HCSPARAMS1_PORTS ( hcsparams1 );
  280. DBGC ( xhci, "XHCI %s has %d slots %d intrs %d ports\n",
  281. xhci->name, xhci->slots, xhci->intrs, xhci->ports );
  282. /* Read structural parameters 2 */
  283. hcsparams2 = readl ( xhci->cap + XHCI_CAP_HCSPARAMS2 );
  284. xhci->scratchpads = XHCI_HCSPARAMS2_SCRATCHPADS ( hcsparams2 );
  285. DBGC2 ( xhci, "XHCI %s needs %d scratchpads\n",
  286. xhci->name, xhci->scratchpads );
  287. /* Read capability parameters 1 */
  288. hccparams1 = readl ( xhci->cap + XHCI_CAP_HCCPARAMS1 );
  289. xhci->addr64 = XHCI_HCCPARAMS1_ADDR64 ( hccparams1 );
  290. xhci->csz_shift = XHCI_HCCPARAMS1_CSZ_SHIFT ( hccparams1 );
  291. xhci->xecp = XHCI_HCCPARAMS1_XECP ( hccparams1 );
  292. /* Read page size */
  293. pagesize = readl ( xhci->op + XHCI_OP_PAGESIZE );
  294. xhci->pagesize = XHCI_PAGESIZE ( pagesize );
  295. assert ( xhci->pagesize != 0 );
  296. assert ( ( ( xhci->pagesize ) & ( xhci->pagesize - 1 ) ) == 0 );
  297. DBGC2 ( xhci, "XHCI %s page size %zd bytes\n",
  298. xhci->name, xhci->pagesize );
  299. }
  300. /**
  301. * Find extended capability
  302. *
  303. * @v xhci xHCI device
  304. * @v id Capability ID
  305. * @v offset Offset to previous extended capability instance, or zero
  306. * @ret offset Offset to extended capability, or zero if not found
  307. */
  308. static unsigned int xhci_extended_capability ( struct xhci_device *xhci,
  309. unsigned int id,
  310. unsigned int offset ) {
  311. uint32_t xecp;
  312. unsigned int next;
  313. /* Locate the extended capability */
  314. while ( 1 ) {
  315. /* Locate first or next capability as applicable */
  316. if ( offset ) {
  317. xecp = readl ( xhci->cap + offset );
  318. next = XHCI_XECP_NEXT ( xecp );
  319. } else {
  320. next = xhci->xecp;
  321. }
  322. if ( ! next )
  323. return 0;
  324. offset += next;
  325. /* Check if this is the requested capability */
  326. xecp = readl ( xhci->cap + offset );
  327. if ( XHCI_XECP_ID ( xecp ) == id )
  328. return offset;
  329. }
  330. }
  331. /**
  332. * Write potentially 64-bit register
  333. *
  334. * @v xhci xHCI device
  335. * @v value Value
  336. * @v reg Register address
  337. * @ret rc Return status code
  338. */
  339. static inline __attribute__ (( always_inline )) int
  340. xhci_writeq ( struct xhci_device *xhci, physaddr_t value, void *reg ) {
  341. /* If this is a 32-bit build, then this can never fail
  342. * (allowing the compiler to optimise out the error path).
  343. */
  344. if ( sizeof ( value ) <= sizeof ( uint32_t ) ) {
  345. writel ( value, reg );
  346. writel ( 0, ( reg + sizeof ( uint32_t ) ) );
  347. return 0;
  348. }
  349. /* If the device does not support 64-bit addresses and this
  350. * address is outside the 32-bit address space, then fail.
  351. */
  352. if ( ( value & ~0xffffffffULL ) && ! xhci->addr64 ) {
  353. DBGC ( xhci, "XHCI %s cannot access address %lx\n",
  354. xhci->name, value );
  355. return -ENOTSUP;
  356. }
  357. /* If this is a 64-bit build, then writeq() is available */
  358. writeq ( value, reg );
  359. return 0;
  360. }
  361. /**
  362. * Calculate buffer alignment
  363. *
  364. * @v len Length
  365. * @ret align Buffer alignment
  366. *
  367. * Determine alignment required for a buffer which must be aligned to
  368. * at least XHCI_MIN_ALIGN and which must not cross a page boundary.
  369. */
  370. static inline size_t xhci_align ( size_t len ) {
  371. size_t align;
  372. /* Align to own length (rounded up to a power of two) */
  373. align = ( 1 << fls ( len - 1 ) );
  374. /* Round up to XHCI_MIN_ALIGN if needed */
  375. if ( align < XHCI_MIN_ALIGN )
  376. align = XHCI_MIN_ALIGN;
  377. return align;
  378. }
  379. /**
  380. * Calculate device context offset
  381. *
  382. * @v xhci xHCI device
  383. * @v ctx Context index
  384. */
  385. static inline size_t xhci_device_context_offset ( struct xhci_device *xhci,
  386. unsigned int ctx ) {
  387. return ( XHCI_DCI ( ctx ) << xhci->csz_shift );
  388. }
  389. /**
  390. * Calculate input context offset
  391. *
  392. * @v xhci xHCI device
  393. * @v ctx Context index
  394. */
  395. static inline size_t xhci_input_context_offset ( struct xhci_device *xhci,
  396. unsigned int ctx ) {
  397. return ( XHCI_ICI ( ctx ) << xhci->csz_shift );
  398. }
  399. /******************************************************************************
  400. *
  401. * Diagnostics
  402. *
  403. ******************************************************************************
  404. */
  405. /**
  406. * Dump host controller registers
  407. *
  408. * @v xhci xHCI device
  409. */
  410. static inline void xhci_dump ( struct xhci_device *xhci ) {
  411. uint32_t usbcmd;
  412. uint32_t usbsts;
  413. uint32_t pagesize;
  414. uint32_t dnctrl;
  415. uint32_t config;
  416. /* Do nothing unless debugging is enabled */
  417. if ( ! DBG_LOG )
  418. return;
  419. /* Dump USBCMD */
  420. usbcmd = readl ( xhci->op + XHCI_OP_USBCMD );
  421. DBGC ( xhci, "XHCI %s USBCMD %08x%s%s\n", xhci->name, usbcmd,
  422. ( ( usbcmd & XHCI_USBCMD_RUN ) ? " run" : "" ),
  423. ( ( usbcmd & XHCI_USBCMD_HCRST ) ? " hcrst" : "" ) );
  424. /* Dump USBSTS */
  425. usbsts = readl ( xhci->op + XHCI_OP_USBSTS );
  426. DBGC ( xhci, "XHCI %s USBSTS %08x%s\n", xhci->name, usbsts,
  427. ( ( usbsts & XHCI_USBSTS_HCH ) ? " hch" : "" ) );
  428. /* Dump PAGESIZE */
  429. pagesize = readl ( xhci->op + XHCI_OP_PAGESIZE );
  430. DBGC ( xhci, "XHCI %s PAGESIZE %08x\n", xhci->name, pagesize );
  431. /* Dump DNCTRL */
  432. dnctrl = readl ( xhci->op + XHCI_OP_DNCTRL );
  433. DBGC ( xhci, "XHCI %s DNCTRL %08x\n", xhci->name, dnctrl );
  434. /* Dump CONFIG */
  435. config = readl ( xhci->op + XHCI_OP_CONFIG );
  436. DBGC ( xhci, "XHCI %s CONFIG %08x\n", xhci->name, config );
  437. }
  438. /**
  439. * Dump port registers
  440. *
  441. * @v xhci xHCI device
  442. * @v port Port number
  443. */
  444. static inline void xhci_dump_port ( struct xhci_device *xhci,
  445. unsigned int port ) {
  446. uint32_t portsc;
  447. uint32_t portpmsc;
  448. uint32_t portli;
  449. uint32_t porthlpmc;
  450. /* Do nothing unless debugging is enabled */
  451. if ( ! DBG_LOG )
  452. return;
  453. /* Dump PORTSC */
  454. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port ) );
  455. DBGC ( xhci, "XHCI %s-%d PORTSC %08x%s%s%s%s psiv=%d\n",
  456. xhci->name, port, portsc,
  457. ( ( portsc & XHCI_PORTSC_CCS ) ? " ccs" : "" ),
  458. ( ( portsc & XHCI_PORTSC_PED ) ? " ped" : "" ),
  459. ( ( portsc & XHCI_PORTSC_PR ) ? " pr" : "" ),
  460. ( ( portsc & XHCI_PORTSC_PP ) ? " pp" : "" ),
  461. XHCI_PORTSC_PSIV ( portsc ) );
  462. /* Dump PORTPMSC */
  463. portpmsc = readl ( xhci->op + XHCI_OP_PORTPMSC ( port ) );
  464. DBGC ( xhci, "XHCI %s-%d PORTPMSC %08x\n", xhci->name, port, portpmsc );
  465. /* Dump PORTLI */
  466. portli = readl ( xhci->op + XHCI_OP_PORTLI ( port ) );
  467. DBGC ( xhci, "XHCI %s-%d PORTLI %08x\n", xhci->name, port, portli );
  468. /* Dump PORTHLPMC */
  469. porthlpmc = readl ( xhci->op + XHCI_OP_PORTHLPMC ( port ) );
  470. DBGC ( xhci, "XHCI %s-%d PORTHLPMC %08x\n",
  471. xhci->name, port, porthlpmc );
  472. }
  473. /******************************************************************************
  474. *
  475. * USB legacy support
  476. *
  477. ******************************************************************************
  478. */
  479. /** Prevent the release of ownership back to BIOS */
  480. static int xhci_legacy_prevent_release;
  481. /**
  482. * Initialise USB legacy support
  483. *
  484. * @v xhci xHCI device
  485. */
  486. static void xhci_legacy_init ( struct xhci_device *xhci ) {
  487. unsigned int legacy;
  488. uint8_t bios;
  489. /* Locate USB legacy support capability (if present) */
  490. legacy = xhci_extended_capability ( xhci, XHCI_XECP_ID_LEGACY, 0 );
  491. if ( ! legacy ) {
  492. /* Not an error; capability may not be present */
  493. DBGC ( xhci, "XHCI %s has no USB legacy support capability\n",
  494. xhci->name );
  495. return;
  496. }
  497. /* Check if legacy USB support is enabled */
  498. bios = readb ( xhci->cap + legacy + XHCI_USBLEGSUP_BIOS );
  499. if ( ! ( bios & XHCI_USBLEGSUP_BIOS_OWNED ) ) {
  500. /* Not an error; already owned by OS */
  501. DBGC ( xhci, "XHCI %s USB legacy support already disabled\n",
  502. xhci->name );
  503. return;
  504. }
  505. /* Record presence of USB legacy support capability */
  506. xhci->legacy = legacy;
  507. }
  508. /**
  509. * Claim ownership from BIOS
  510. *
  511. * @v xhci xHCI device
  512. */
  513. static void xhci_legacy_claim ( struct xhci_device *xhci ) {
  514. uint32_t ctlsts;
  515. uint8_t bios;
  516. unsigned int i;
  517. /* Do nothing unless legacy support capability is present */
  518. if ( ! xhci->legacy )
  519. return;
  520. /* Claim ownership */
  521. writeb ( XHCI_USBLEGSUP_OS_OWNED,
  522. xhci->cap + xhci->legacy + XHCI_USBLEGSUP_OS );
  523. /* Wait for BIOS to release ownership */
  524. for ( i = 0 ; i < XHCI_USBLEGSUP_MAX_WAIT_MS ; i++ ) {
  525. /* Check if BIOS has released ownership */
  526. bios = readb ( xhci->cap + xhci->legacy + XHCI_USBLEGSUP_BIOS );
  527. if ( ! ( bios & XHCI_USBLEGSUP_BIOS_OWNED ) ) {
  528. DBGC ( xhci, "XHCI %s claimed ownership from BIOS\n",
  529. xhci->name );
  530. ctlsts = readl ( xhci->cap + xhci->legacy +
  531. XHCI_USBLEGSUP_CTLSTS );
  532. if ( ctlsts ) {
  533. DBGC ( xhci, "XHCI %s warning: BIOS retained "
  534. "SMIs: %08x\n", xhci->name, ctlsts );
  535. }
  536. return;
  537. }
  538. /* Delay */
  539. mdelay ( 1 );
  540. }
  541. /* BIOS did not release ownership. Claim it forcibly by
  542. * disabling all SMIs.
  543. */
  544. DBGC ( xhci, "XHCI %s could not claim ownership from BIOS: forcibly "
  545. "disabling SMIs\n", xhci->name );
  546. writel ( 0, xhci->cap + xhci->legacy + XHCI_USBLEGSUP_CTLSTS );
  547. }
  548. /**
  549. * Release ownership back to BIOS
  550. *
  551. * @v xhci xHCI device
  552. */
  553. static void xhci_legacy_release ( struct xhci_device *xhci ) {
  554. /* Do nothing unless legacy support capability is present */
  555. if ( ! xhci->legacy )
  556. return;
  557. /* Do nothing if releasing ownership is prevented */
  558. if ( xhci_legacy_prevent_release ) {
  559. DBGC ( xhci, "XHCI %s not releasing ownership to BIOS\n",
  560. xhci->name );
  561. return;
  562. }
  563. /* Release ownership */
  564. writeb ( 0, xhci->cap + xhci->legacy + XHCI_USBLEGSUP_OS );
  565. DBGC ( xhci, "XHCI %s released ownership to BIOS\n", xhci->name );
  566. }
  567. /******************************************************************************
  568. *
  569. * Supported protocols
  570. *
  571. ******************************************************************************
  572. */
  573. /**
  574. * Transcribe port speed (for debugging)
  575. *
  576. * @v psi Protocol speed ID
  577. * @ret speed Transcribed speed
  578. */
  579. static inline const char * xhci_speed_name ( uint32_t psi ) {
  580. static const char *exponents[4] = { "", "k", "M", "G" };
  581. static char buf[ 10 /* "xxxxxXbps" + NUL */ ];
  582. unsigned int mantissa;
  583. unsigned int exponent;
  584. /* Extract mantissa and exponent */
  585. mantissa = XHCI_SUPPORTED_PSI_MANTISSA ( psi );
  586. exponent = XHCI_SUPPORTED_PSI_EXPONENT ( psi );
  587. /* Transcribe speed */
  588. snprintf ( buf, sizeof ( buf ), "%d%sbps",
  589. mantissa, exponents[exponent] );
  590. return buf;
  591. }
  592. /**
  593. * Find supported protocol extended capability for a port
  594. *
  595. * @v xhci xHCI device
  596. * @v port Port number
  597. * @ret supported Offset to extended capability, or zero if not found
  598. */
  599. static unsigned int xhci_supported_protocol ( struct xhci_device *xhci,
  600. unsigned int port ) {
  601. unsigned int supported = 0;
  602. unsigned int offset;
  603. unsigned int count;
  604. uint32_t ports;
  605. /* Iterate over all supported protocol structures */
  606. while ( ( supported = xhci_extended_capability ( xhci,
  607. XHCI_XECP_ID_SUPPORTED,
  608. supported ) ) ) {
  609. /* Determine port range */
  610. ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS );
  611. offset = XHCI_SUPPORTED_PORTS_OFFSET ( ports );
  612. count = XHCI_SUPPORTED_PORTS_COUNT ( ports );
  613. /* Check if port lies within this range */
  614. if ( ( port - offset ) < count )
  615. return supported;
  616. }
  617. DBGC ( xhci, "XHCI %s-%d has no supported protocol\n",
  618. xhci->name, port );
  619. return 0;
  620. }
  621. /**
  622. * Find port protocol
  623. *
  624. * @v xhci xHCI device
  625. * @v port Port number
  626. * @ret protocol USB protocol, or zero if not found
  627. */
  628. static unsigned int xhci_port_protocol ( struct xhci_device *xhci,
  629. unsigned int port ) {
  630. unsigned int supported = xhci_supported_protocol ( xhci, port );
  631. union {
  632. uint32_t raw;
  633. char text[5];
  634. } name;
  635. unsigned int protocol;
  636. unsigned int type;
  637. unsigned int psic;
  638. unsigned int psiv;
  639. unsigned int i;
  640. uint32_t revision;
  641. uint32_t ports;
  642. uint32_t slot;
  643. uint32_t psi;
  644. /* Fail if there is no supported protocol */
  645. if ( ! supported )
  646. return 0;
  647. /* Determine protocol version */
  648. revision = readl ( xhci->cap + supported + XHCI_SUPPORTED_REVISION );
  649. protocol = XHCI_SUPPORTED_REVISION_VER ( revision );
  650. /* Describe port protocol */
  651. if ( DBG_EXTRA ) {
  652. name.raw = cpu_to_le32 ( readl ( xhci->cap + supported +
  653. XHCI_SUPPORTED_NAME ) );
  654. name.text[4] = '\0';
  655. slot = readl ( xhci->cap + supported + XHCI_SUPPORTED_SLOT );
  656. type = XHCI_SUPPORTED_SLOT_TYPE ( slot );
  657. DBGC2 ( xhci, "XHCI %s-%d %sv%04x type %d",
  658. xhci->name, port, name.text, protocol, type );
  659. ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS );
  660. psic = XHCI_SUPPORTED_PORTS_PSIC ( ports );
  661. if ( psic ) {
  662. DBGC2 ( xhci, " speeds" );
  663. for ( i = 0 ; i < psic ; i++ ) {
  664. psi = readl ( xhci->cap + supported +
  665. XHCI_SUPPORTED_PSI ( i ) );
  666. psiv = XHCI_SUPPORTED_PSI_VALUE ( psi );
  667. DBGC2 ( xhci, " %d:%s", psiv,
  668. xhci_speed_name ( psi ) );
  669. }
  670. }
  671. if ( xhci->quirks & XHCI_BAD_PSIV )
  672. DBGC2 ( xhci, " (ignored)" );
  673. DBGC2 ( xhci, "\n" );
  674. }
  675. return protocol;
  676. }
  677. /**
  678. * Find port slot type
  679. *
  680. * @v xhci xHCI device
  681. * @v port Port number
  682. * @ret type Slot type, or negative error
  683. */
  684. static int xhci_port_slot_type ( struct xhci_device *xhci, unsigned int port ) {
  685. unsigned int supported = xhci_supported_protocol ( xhci, port );
  686. unsigned int type;
  687. uint32_t slot;
  688. /* Fail if there is no supported protocol */
  689. if ( ! supported )
  690. return -ENOTSUP;
  691. /* Get slot type */
  692. slot = readl ( xhci->cap + supported + XHCI_SUPPORTED_SLOT );
  693. type = XHCI_SUPPORTED_SLOT_TYPE ( slot );
  694. return type;
  695. }
  696. /**
  697. * Find port speed
  698. *
  699. * @v xhci xHCI device
  700. * @v port Port number
  701. * @v psiv Protocol speed ID value
  702. * @ret speed Port speed, or negative error
  703. */
  704. static int xhci_port_speed ( struct xhci_device *xhci, unsigned int port,
  705. unsigned int psiv ) {
  706. unsigned int supported = xhci_supported_protocol ( xhci, port );
  707. unsigned int psic;
  708. unsigned int mantissa;
  709. unsigned int exponent;
  710. unsigned int speed;
  711. unsigned int i;
  712. uint32_t ports;
  713. uint32_t psi;
  714. /* Fail if there is no supported protocol */
  715. if ( ! supported )
  716. return -ENOTSUP;
  717. /* Get protocol speed ID count */
  718. ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS );
  719. psic = XHCI_SUPPORTED_PORTS_PSIC ( ports );
  720. /* Use protocol speed ID table unless device is known to be faulty */
  721. if ( ! ( xhci->quirks & XHCI_BAD_PSIV ) ) {
  722. /* Iterate over PSI dwords looking for a match */
  723. for ( i = 0 ; i < psic ; i++ ) {
  724. psi = readl ( xhci->cap + supported +
  725. XHCI_SUPPORTED_PSI ( i ) );
  726. if ( psiv == XHCI_SUPPORTED_PSI_VALUE ( psi ) ) {
  727. mantissa = XHCI_SUPPORTED_PSI_MANTISSA ( psi );
  728. exponent = XHCI_SUPPORTED_PSI_EXPONENT ( psi );
  729. speed = USB_SPEED ( mantissa, exponent );
  730. return speed;
  731. }
  732. }
  733. /* Record device as faulty if no match is found */
  734. if ( psic != 0 ) {
  735. DBGC ( xhci, "XHCI %s-%d spurious PSI value %d: "
  736. "assuming PSI table is invalid\n",
  737. xhci->name, port, psiv );
  738. xhci->quirks |= XHCI_BAD_PSIV;
  739. }
  740. }
  741. /* Use the default mappings */
  742. switch ( psiv ) {
  743. case XHCI_SPEED_LOW : return USB_SPEED_LOW;
  744. case XHCI_SPEED_FULL : return USB_SPEED_FULL;
  745. case XHCI_SPEED_HIGH : return USB_SPEED_HIGH;
  746. case XHCI_SPEED_SUPER : return USB_SPEED_SUPER;
  747. default:
  748. DBGC ( xhci, "XHCI %s-%d unrecognised PSI value %d\n",
  749. xhci->name, port, psiv );
  750. return -ENOTSUP;
  751. }
  752. }
  753. /**
  754. * Find protocol speed ID value
  755. *
  756. * @v xhci xHCI device
  757. * @v port Port number
  758. * @v speed USB speed
  759. * @ret psiv Protocol speed ID value, or negative error
  760. */
  761. static int xhci_port_psiv ( struct xhci_device *xhci, unsigned int port,
  762. unsigned int speed ) {
  763. unsigned int supported = xhci_supported_protocol ( xhci, port );
  764. unsigned int psic;
  765. unsigned int mantissa;
  766. unsigned int exponent;
  767. unsigned int psiv;
  768. unsigned int i;
  769. uint32_t ports;
  770. uint32_t psi;
  771. /* Fail if there is no supported protocol */
  772. if ( ! supported )
  773. return -ENOTSUP;
  774. /* Get protocol speed ID count */
  775. ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS );
  776. psic = XHCI_SUPPORTED_PORTS_PSIC ( ports );
  777. /* Use the default mappings if applicable */
  778. if ( ( psic == 0 ) || ( xhci->quirks & XHCI_BAD_PSIV ) ) {
  779. switch ( speed ) {
  780. case USB_SPEED_LOW : return XHCI_SPEED_LOW;
  781. case USB_SPEED_FULL : return XHCI_SPEED_FULL;
  782. case USB_SPEED_HIGH : return XHCI_SPEED_HIGH;
  783. case USB_SPEED_SUPER : return XHCI_SPEED_SUPER;
  784. default:
  785. DBGC ( xhci, "XHCI %s-%d non-standard speed %d\n",
  786. xhci->name, port, speed );
  787. return -ENOTSUP;
  788. }
  789. }
  790. /* Iterate over PSI dwords looking for a match */
  791. for ( i = 0 ; i < psic ; i++ ) {
  792. psi = readl ( xhci->cap + supported + XHCI_SUPPORTED_PSI ( i ));
  793. mantissa = XHCI_SUPPORTED_PSI_MANTISSA ( psi );
  794. exponent = XHCI_SUPPORTED_PSI_EXPONENT ( psi );
  795. if ( speed == USB_SPEED ( mantissa, exponent ) ) {
  796. psiv = XHCI_SUPPORTED_PSI_VALUE ( psi );
  797. return psiv;
  798. }
  799. }
  800. DBGC ( xhci, "XHCI %s-%d unrepresentable speed %#x\n",
  801. xhci->name, port, speed );
  802. return -ENOENT;
  803. }
  804. /******************************************************************************
  805. *
  806. * Device context base address array
  807. *
  808. ******************************************************************************
  809. */
  810. /**
  811. * Allocate device context base address array
  812. *
  813. * @v xhci xHCI device
  814. * @ret rc Return status code
  815. */
  816. static int xhci_dcbaa_alloc ( struct xhci_device *xhci ) {
  817. size_t len;
  818. physaddr_t dcbaap;
  819. int rc;
  820. /* Allocate and initialise structure. Must be at least
  821. * 64-byte aligned and must not cross a page boundary, so
  822. * align on its own size (rounded up to a power of two and
  823. * with a minimum of 64 bytes).
  824. */
  825. len = ( ( xhci->slots + 1 ) * sizeof ( xhci->dcbaa[0] ) );
  826. xhci->dcbaa = malloc_dma ( len, xhci_align ( len ) );
  827. if ( ! xhci->dcbaa ) {
  828. DBGC ( xhci, "XHCI %s could not allocate DCBAA\n", xhci->name );
  829. rc = -ENOMEM;
  830. goto err_alloc;
  831. }
  832. memset ( xhci->dcbaa, 0, len );
  833. /* Program DCBAA pointer */
  834. dcbaap = virt_to_phys ( xhci->dcbaa );
  835. if ( ( rc = xhci_writeq ( xhci, dcbaap,
  836. xhci->op + XHCI_OP_DCBAAP ) ) != 0 )
  837. goto err_writeq;
  838. DBGC2 ( xhci, "XHCI %s DCBAA at [%08lx,%08lx)\n",
  839. xhci->name, dcbaap, ( dcbaap + len ) );
  840. return 0;
  841. err_writeq:
  842. free_dma ( xhci->dcbaa, len );
  843. err_alloc:
  844. return rc;
  845. }
  846. /**
  847. * Free device context base address array
  848. *
  849. * @v xhci xHCI device
  850. */
  851. static void xhci_dcbaa_free ( struct xhci_device *xhci ) {
  852. size_t len;
  853. unsigned int i;
  854. /* Sanity check */
  855. for ( i = 0 ; i <= xhci->slots ; i++ )
  856. assert ( xhci->dcbaa[i] == 0 );
  857. /* Clear DCBAA pointer */
  858. xhci_writeq ( xhci, 0, xhci->op + XHCI_OP_DCBAAP );
  859. /* Free DCBAA */
  860. len = ( ( xhci->slots + 1 ) * sizeof ( xhci->dcbaa[0] ) );
  861. free_dma ( xhci->dcbaa, len );
  862. }
  863. /******************************************************************************
  864. *
  865. * Scratchpad buffers
  866. *
  867. ******************************************************************************
  868. */
  869. /**
  870. * Allocate scratchpad buffers
  871. *
  872. * @v xhci xHCI device
  873. * @ret rc Return status code
  874. */
  875. static int xhci_scratchpad_alloc ( struct xhci_device *xhci ) {
  876. size_t array_len;
  877. size_t len;
  878. physaddr_t phys;
  879. unsigned int i;
  880. int rc;
  881. /* Do nothing if no scratchpad buffers are used */
  882. if ( ! xhci->scratchpads )
  883. return 0;
  884. /* Allocate scratchpads */
  885. len = ( xhci->scratchpads * xhci->pagesize );
  886. xhci->scratchpad = umalloc ( len );
  887. if ( ! xhci->scratchpad ) {
  888. DBGC ( xhci, "XHCI %s could not allocate scratchpad buffers\n",
  889. xhci->name );
  890. rc = -ENOMEM;
  891. goto err_alloc;
  892. }
  893. memset_user ( xhci->scratchpad, 0, 0, len );
  894. /* Allocate scratchpad array */
  895. array_len = ( xhci->scratchpads * sizeof ( xhci->scratchpad_array[0] ));
  896. xhci->scratchpad_array =
  897. malloc_dma ( array_len, xhci_align ( array_len ) );
  898. if ( ! xhci->scratchpad_array ) {
  899. DBGC ( xhci, "XHCI %s could not allocate scratchpad buffer "
  900. "array\n", xhci->name );
  901. rc = -ENOMEM;
  902. goto err_alloc_array;
  903. }
  904. /* Populate scratchpad array */
  905. for ( i = 0 ; i < xhci->scratchpads ; i++ ) {
  906. phys = user_to_phys ( xhci->scratchpad, ( i * xhci->pagesize ));
  907. xhci->scratchpad_array[i] = phys;
  908. }
  909. /* Set scratchpad array pointer */
  910. assert ( xhci->dcbaa != NULL );
  911. xhci->dcbaa[0] = cpu_to_le64 ( virt_to_phys ( xhci->scratchpad_array ));
  912. DBGC2 ( xhci, "XHCI %s scratchpad [%08lx,%08lx) array [%08lx,%08lx)\n",
  913. xhci->name, user_to_phys ( xhci->scratchpad, 0 ),
  914. user_to_phys ( xhci->scratchpad, len ),
  915. virt_to_phys ( xhci->scratchpad_array ),
  916. ( virt_to_phys ( xhci->scratchpad_array ) + array_len ) );
  917. return 0;
  918. free_dma ( xhci->scratchpad_array, array_len );
  919. err_alloc_array:
  920. ufree ( xhci->scratchpad );
  921. err_alloc:
  922. return rc;
  923. }
  924. /**
  925. * Free scratchpad buffers
  926. *
  927. * @v xhci xHCI device
  928. */
  929. static void xhci_scratchpad_free ( struct xhci_device *xhci ) {
  930. size_t array_len;
  931. /* Do nothing if no scratchpad buffers are used */
  932. if ( ! xhci->scratchpads )
  933. return;
  934. /* Clear scratchpad array pointer */
  935. assert ( xhci->dcbaa != NULL );
  936. xhci->dcbaa[0] = 0;
  937. /* Free scratchpad array */
  938. array_len = ( xhci->scratchpads * sizeof ( xhci->scratchpad_array[0] ));
  939. free_dma ( xhci->scratchpad_array, array_len );
  940. /* Free scratchpads */
  941. ufree ( xhci->scratchpad );
  942. }
  943. /******************************************************************************
  944. *
  945. * Run / stop / reset
  946. *
  947. ******************************************************************************
  948. */
  949. /**
  950. * Start xHCI device
  951. *
  952. * @v xhci xHCI device
  953. */
  954. static void xhci_run ( struct xhci_device *xhci ) {
  955. uint32_t config;
  956. uint32_t usbcmd;
  957. /* Configure number of device slots */
  958. config = readl ( xhci->op + XHCI_OP_CONFIG );
  959. config &= ~XHCI_CONFIG_MAX_SLOTS_EN_MASK;
  960. config |= XHCI_CONFIG_MAX_SLOTS_EN ( xhci->slots );
  961. writel ( config, xhci->op + XHCI_OP_CONFIG );
  962. /* Set run/stop bit */
  963. usbcmd = readl ( xhci->op + XHCI_OP_USBCMD );
  964. usbcmd |= XHCI_USBCMD_RUN;
  965. writel ( usbcmd, xhci->op + XHCI_OP_USBCMD );
  966. }
  967. /**
  968. * Stop xHCI device
  969. *
  970. * @v xhci xHCI device
  971. * @ret rc Return status code
  972. */
  973. static int xhci_stop ( struct xhci_device *xhci ) {
  974. uint32_t usbcmd;
  975. uint32_t usbsts;
  976. unsigned int i;
  977. /* Clear run/stop bit */
  978. usbcmd = readl ( xhci->op + XHCI_OP_USBCMD );
  979. usbcmd &= ~XHCI_USBCMD_RUN;
  980. writel ( usbcmd, xhci->op + XHCI_OP_USBCMD );
  981. /* Wait for device to stop */
  982. for ( i = 0 ; i < XHCI_STOP_MAX_WAIT_MS ; i++ ) {
  983. /* Check if device is stopped */
  984. usbsts = readl ( xhci->op + XHCI_OP_USBSTS );
  985. if ( usbsts & XHCI_USBSTS_HCH )
  986. return 0;
  987. /* Delay */
  988. mdelay ( 1 );
  989. }
  990. DBGC ( xhci, "XHCI %s timed out waiting for stop\n", xhci->name );
  991. return -ETIMEDOUT;
  992. }
  993. /**
  994. * Reset xHCI device
  995. *
  996. * @v xhci xHCI device
  997. * @ret rc Return status code
  998. */
  999. static int xhci_reset ( struct xhci_device *xhci ) {
  1000. uint32_t usbcmd;
  1001. unsigned int i;
  1002. int rc;
  1003. /* The xHCI specification states that resetting a running
  1004. * device may result in undefined behaviour, so try stopping
  1005. * it first.
  1006. */
  1007. if ( ( rc = xhci_stop ( xhci ) ) != 0 ) {
  1008. /* Ignore errors and attempt to reset the device anyway */
  1009. }
  1010. /* Reset device */
  1011. writel ( XHCI_USBCMD_HCRST, xhci->op + XHCI_OP_USBCMD );
  1012. /* Wait for reset to complete */
  1013. for ( i = 0 ; i < XHCI_RESET_MAX_WAIT_MS ; i++ ) {
  1014. /* Check if reset is complete */
  1015. usbcmd = readl ( xhci->op + XHCI_OP_USBCMD );
  1016. if ( ! ( usbcmd & XHCI_USBCMD_HCRST ) )
  1017. return 0;
  1018. /* Delay */
  1019. mdelay ( 1 );
  1020. }
  1021. DBGC ( xhci, "XHCI %s timed out waiting for reset\n", xhci->name );
  1022. return -ETIMEDOUT;
  1023. }
  1024. /******************************************************************************
  1025. *
  1026. * Transfer request blocks
  1027. *
  1028. ******************************************************************************
  1029. */
  1030. /**
  1031. * Allocate transfer request block ring
  1032. *
  1033. * @v xhci xHCI device
  1034. * @v ring TRB ring
  1035. * @v shift Ring size (log2)
  1036. * @v slot Device slot
  1037. * @v target Doorbell target
  1038. * @v stream Doorbell stream ID
  1039. * @ret rc Return status code
  1040. */
  1041. static int xhci_ring_alloc ( struct xhci_device *xhci,
  1042. struct xhci_trb_ring *ring,
  1043. unsigned int shift, unsigned int slot,
  1044. unsigned int target, unsigned int stream ) {
  1045. struct xhci_trb_link *link;
  1046. unsigned int count;
  1047. int rc;
  1048. /* Sanity check */
  1049. assert ( shift > 0 );
  1050. /* Initialise structure */
  1051. memset ( ring, 0, sizeof ( *ring ) );
  1052. ring->shift = shift;
  1053. count = ( 1U << shift );
  1054. ring->mask = ( count - 1 );
  1055. ring->len = ( ( count + 1 /* Link TRB */ ) * sizeof ( ring->trb[0] ) );
  1056. ring->db = ( xhci->db + ( slot * sizeof ( ring->dbval ) ) );
  1057. ring->dbval = XHCI_DBVAL ( target, stream );
  1058. /* Allocate I/O buffers */
  1059. ring->iobuf = zalloc ( count * sizeof ( ring->iobuf[0] ) );
  1060. if ( ! ring->iobuf ) {
  1061. rc = -ENOMEM;
  1062. goto err_alloc_iobuf;
  1063. }
  1064. /* Allocate TRBs */
  1065. ring->trb = malloc_dma ( ring->len, xhci_align ( ring->len ) );
  1066. if ( ! ring->trb ) {
  1067. rc = -ENOMEM;
  1068. goto err_alloc_trb;
  1069. }
  1070. memset ( ring->trb, 0, ring->len );
  1071. /* Initialise Link TRB */
  1072. link = &ring->trb[count].link;
  1073. link->next = cpu_to_le64 ( virt_to_phys ( ring->trb ) );
  1074. link->flags = XHCI_TRB_TC;
  1075. link->type = XHCI_TRB_LINK;
  1076. ring->link = link;
  1077. return 0;
  1078. free_dma ( ring->trb, ring->len );
  1079. err_alloc_trb:
  1080. free ( ring->iobuf );
  1081. err_alloc_iobuf:
  1082. return rc;
  1083. }
  1084. /**
  1085. * Reset transfer request block ring
  1086. *
  1087. * @v ring TRB ring
  1088. */
  1089. static void xhci_ring_reset ( struct xhci_trb_ring *ring ) {
  1090. unsigned int count = ( 1U << ring->shift );
  1091. /* Reset producer and consumer counters */
  1092. ring->prod = 0;
  1093. ring->cons = 0;
  1094. /* Reset TRBs (except Link TRB) */
  1095. memset ( ring->trb, 0, ( count * sizeof ( ring->trb[0] ) ) );
  1096. }
  1097. /**
  1098. * Free transfer request block ring
  1099. *
  1100. * @v ring TRB ring
  1101. */
  1102. static void xhci_ring_free ( struct xhci_trb_ring *ring ) {
  1103. unsigned int count = ( 1U << ring->shift );
  1104. unsigned int i;
  1105. /* Sanity checks */
  1106. assert ( ring->cons == ring->prod );
  1107. for ( i = 0 ; i < count ; i++ )
  1108. assert ( ring->iobuf[i] == NULL );
  1109. /* Free TRBs */
  1110. free_dma ( ring->trb, ring->len );
  1111. /* Free I/O buffers */
  1112. free ( ring->iobuf );
  1113. }
  1114. /**
  1115. * Enqueue a transfer request block
  1116. *
  1117. * @v ring TRB ring
  1118. * @v iobuf I/O buffer (if any)
  1119. * @v trb Transfer request block (with empty Cycle flag)
  1120. * @ret rc Return status code
  1121. *
  1122. * This operation does not implicitly ring the doorbell register.
  1123. */
  1124. static int xhci_enqueue ( struct xhci_trb_ring *ring, struct io_buffer *iobuf,
  1125. const union xhci_trb *trb ) {
  1126. union xhci_trb *dest;
  1127. unsigned int prod;
  1128. unsigned int mask;
  1129. unsigned int index;
  1130. unsigned int cycle;
  1131. /* Sanity check */
  1132. assert ( ! ( trb->common.flags & XHCI_TRB_C ) );
  1133. /* Fail if ring is full */
  1134. if ( ! xhci_ring_remaining ( ring ) )
  1135. return -ENOBUFS;
  1136. /* Update producer counter (and link TRB, if applicable) */
  1137. prod = ring->prod++;
  1138. mask = ring->mask;
  1139. cycle = ( ( ~( prod >> ring->shift ) ) & XHCI_TRB_C );
  1140. index = ( prod & mask );
  1141. if ( index == 0 )
  1142. ring->link->flags = ( XHCI_TRB_TC | ( cycle ^ XHCI_TRB_C ) );
  1143. /* Record I/O buffer */
  1144. ring->iobuf[index] = iobuf;
  1145. /* Enqueue TRB */
  1146. dest = &ring->trb[index];
  1147. dest->template.parameter = trb->template.parameter;
  1148. dest->template.status = trb->template.status;
  1149. wmb();
  1150. dest->template.control = ( trb->template.control |
  1151. cpu_to_le32 ( cycle ) );
  1152. return 0;
  1153. }
  1154. /**
  1155. * Dequeue a transfer request block
  1156. *
  1157. * @v ring TRB ring
  1158. * @ret iobuf I/O buffer
  1159. */
  1160. static struct io_buffer * xhci_dequeue ( struct xhci_trb_ring *ring ) {
  1161. struct io_buffer *iobuf;
  1162. unsigned int cons;
  1163. unsigned int mask;
  1164. unsigned int index;
  1165. /* Sanity check */
  1166. assert ( xhci_ring_fill ( ring ) != 0 );
  1167. /* Update consumer counter */
  1168. cons = ring->cons++;
  1169. mask = ring->mask;
  1170. index = ( cons & mask );
  1171. /* Retrieve I/O buffer */
  1172. iobuf = ring->iobuf[index];
  1173. ring->iobuf[index] = NULL;
  1174. return iobuf;
  1175. }
  1176. /**
  1177. * Enqueue multiple transfer request blocks
  1178. *
  1179. * @v ring TRB ring
  1180. * @v iobuf I/O buffer
  1181. * @v trbs Transfer request blocks (with empty Cycle flag)
  1182. * @v count Number of transfer request blocks
  1183. * @ret rc Return status code
  1184. *
  1185. * This operation does not implicitly ring the doorbell register.
  1186. */
  1187. static int xhci_enqueue_multi ( struct xhci_trb_ring *ring,
  1188. struct io_buffer *iobuf,
  1189. const union xhci_trb *trbs,
  1190. unsigned int count ) {
  1191. const union xhci_trb *trb = trbs;
  1192. int rc;
  1193. /* Sanity check */
  1194. assert ( iobuf != NULL );
  1195. /* Fail if ring does not have sufficient space */
  1196. if ( xhci_ring_remaining ( ring ) < count )
  1197. return -ENOBUFS;
  1198. /* Enqueue each TRB, recording the I/O buffer with the final TRB */
  1199. while ( count-- ) {
  1200. rc = xhci_enqueue ( ring, ( count ? NULL : iobuf ), trb++ );
  1201. assert ( rc == 0 ); /* Should never be able to fail */
  1202. }
  1203. return 0;
  1204. }
  1205. /**
  1206. * Dequeue multiple transfer request blocks
  1207. *
  1208. * @v ring TRB ring
  1209. * @ret iobuf I/O buffer
  1210. */
  1211. static struct io_buffer * xhci_dequeue_multi ( struct xhci_trb_ring *ring ) {
  1212. struct io_buffer *iobuf;
  1213. /* Dequeue TRBs until we reach the final TRB for an I/O buffer */
  1214. do {
  1215. iobuf = xhci_dequeue ( ring );
  1216. } while ( iobuf == NULL );
  1217. return iobuf;
  1218. }
  1219. /**
  1220. * Ring doorbell register
  1221. *
  1222. * @v ring TRB ring
  1223. */
  1224. static inline __attribute__ (( always_inline )) void
  1225. xhci_doorbell ( struct xhci_trb_ring *ring ) {
  1226. wmb();
  1227. writel ( ring->dbval, ring->db );
  1228. }
  1229. /******************************************************************************
  1230. *
  1231. * Command and event rings
  1232. *
  1233. ******************************************************************************
  1234. */
  1235. /**
  1236. * Allocate command ring
  1237. *
  1238. * @v xhci xHCI device
  1239. * @ret rc Return status code
  1240. */
  1241. static int xhci_command_alloc ( struct xhci_device *xhci ) {
  1242. physaddr_t crp;
  1243. int rc;
  1244. /* Allocate TRB ring */
  1245. if ( ( rc = xhci_ring_alloc ( xhci, &xhci->command, XHCI_CMD_TRBS_LOG2,
  1246. 0, 0, 0 ) ) != 0 )
  1247. goto err_ring_alloc;
  1248. /* Program command ring control register */
  1249. crp = virt_to_phys ( xhci->command.trb );
  1250. if ( ( rc = xhci_writeq ( xhci, ( crp | XHCI_CRCR_RCS ),
  1251. xhci->op + XHCI_OP_CRCR ) ) != 0 )
  1252. goto err_writeq;
  1253. DBGC2 ( xhci, "XHCI %s CRCR at [%08lx,%08lx)\n",
  1254. xhci->name, crp, ( crp + xhci->command.len ) );
  1255. return 0;
  1256. err_writeq:
  1257. xhci_ring_free ( &xhci->command );
  1258. err_ring_alloc:
  1259. return rc;
  1260. }
  1261. /**
  1262. * Free command ring
  1263. *
  1264. * @v xhci xHCI device
  1265. */
  1266. static void xhci_command_free ( struct xhci_device *xhci ) {
  1267. /* Sanity check */
  1268. assert ( ( readl ( xhci->op + XHCI_OP_CRCR ) & XHCI_CRCR_CRR ) == 0 );
  1269. /* Clear command ring control register */
  1270. xhci_writeq ( xhci, 0, xhci->op + XHCI_OP_CRCR );
  1271. /* Free TRB ring */
  1272. xhci_ring_free ( &xhci->command );
  1273. }
  1274. /**
  1275. * Allocate event ring
  1276. *
  1277. * @v xhci xHCI device
  1278. * @ret rc Return status code
  1279. */
  1280. static int xhci_event_alloc ( struct xhci_device *xhci ) {
  1281. struct xhci_event_ring *event = &xhci->event;
  1282. unsigned int count;
  1283. size_t len;
  1284. int rc;
  1285. /* Allocate event ring */
  1286. count = ( 1 << XHCI_EVENT_TRBS_LOG2 );
  1287. len = ( count * sizeof ( event->trb[0] ) );
  1288. event->trb = malloc_dma ( len, xhci_align ( len ) );
  1289. if ( ! event->trb ) {
  1290. rc = -ENOMEM;
  1291. goto err_alloc_trb;
  1292. }
  1293. memset ( event->trb, 0, len );
  1294. /* Allocate event ring segment table */
  1295. event->segment = malloc_dma ( sizeof ( event->segment[0] ),
  1296. xhci_align ( sizeof (event->segment[0])));
  1297. if ( ! event->segment ) {
  1298. rc = -ENOMEM;
  1299. goto err_alloc_segment;
  1300. }
  1301. memset ( event->segment, 0, sizeof ( event->segment[0] ) );
  1302. event->segment[0].base = cpu_to_le64 ( virt_to_phys ( event->trb ) );
  1303. event->segment[0].count = cpu_to_le32 ( count );
  1304. /* Program event ring registers */
  1305. writel ( 1, xhci->run + XHCI_RUN_ERSTSZ ( 0 ) );
  1306. if ( ( rc = xhci_writeq ( xhci, virt_to_phys ( event->trb ),
  1307. xhci->run + XHCI_RUN_ERDP ( 0 ) ) ) != 0 )
  1308. goto err_writeq_erdp;
  1309. if ( ( rc = xhci_writeq ( xhci, virt_to_phys ( event->segment ),
  1310. xhci->run + XHCI_RUN_ERSTBA ( 0 ) ) ) != 0 )
  1311. goto err_writeq_erstba;
  1312. DBGC2 ( xhci, "XHCI %s event ring [%08lx,%08lx) table [%08lx,%08lx)\n",
  1313. xhci->name, virt_to_phys ( event->trb ),
  1314. ( virt_to_phys ( event->trb ) + len ),
  1315. virt_to_phys ( event->segment ),
  1316. ( virt_to_phys ( event->segment ) +
  1317. sizeof (event->segment[0] ) ) );
  1318. return 0;
  1319. xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERSTBA ( 0 ) );
  1320. err_writeq_erstba:
  1321. xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERDP ( 0 ) );
  1322. err_writeq_erdp:
  1323. free_dma ( event->trb, len );
  1324. err_alloc_segment:
  1325. free_dma ( event->segment, sizeof ( event->segment[0] ) );
  1326. err_alloc_trb:
  1327. return rc;
  1328. }
  1329. /**
  1330. * Free event ring
  1331. *
  1332. * @v xhci xHCI device
  1333. */
  1334. static void xhci_event_free ( struct xhci_device *xhci ) {
  1335. struct xhci_event_ring *event = &xhci->event;
  1336. unsigned int count;
  1337. size_t len;
  1338. /* Clear event ring registers */
  1339. writel ( 0, xhci->run + XHCI_RUN_ERSTSZ ( 0 ) );
  1340. xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERSTBA ( 0 ) );
  1341. xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERDP ( 0 ) );
  1342. /* Free event ring segment table */
  1343. free_dma ( event->segment, sizeof ( event->segment[0] ) );
  1344. /* Free event ring */
  1345. count = ( 1 << XHCI_EVENT_TRBS_LOG2 );
  1346. len = ( count * sizeof ( event->trb[0] ) );
  1347. free_dma ( event->trb, len );
  1348. }
  1349. /**
  1350. * Handle transfer event
  1351. *
  1352. * @v xhci xHCI device
  1353. * @v trb Transfer event TRB
  1354. */
  1355. static void xhci_transfer ( struct xhci_device *xhci,
  1356. struct xhci_trb_transfer *trb ) {
  1357. struct xhci_slot *slot;
  1358. struct xhci_endpoint *endpoint;
  1359. struct io_buffer *iobuf;
  1360. int rc;
  1361. /* Profile transfer events */
  1362. profile_start ( &xhci_transfer_profiler );
  1363. /* Identify slot */
  1364. if ( ( trb->slot > xhci->slots ) ||
  1365. ( ( slot = xhci->slot[trb->slot] ) == NULL ) ) {
  1366. DBGC ( xhci, "XHCI %s transfer event invalid slot %d:\n",
  1367. xhci->name, trb->slot );
  1368. DBGC_HDA ( xhci, 0, trb, sizeof ( *trb ) );
  1369. return;
  1370. }
  1371. /* Identify endpoint */
  1372. if ( ( trb->endpoint >= XHCI_CTX_END ) ||
  1373. ( ( endpoint = slot->endpoint[trb->endpoint] ) == NULL ) ) {
  1374. DBGC ( xhci, "XHCI %s slot %d transfer event invalid epid "
  1375. "%d:\n", xhci->name, slot->id, trb->endpoint );
  1376. DBGC_HDA ( xhci, 0, trb, sizeof ( *trb ) );
  1377. return;
  1378. }
  1379. /* Dequeue TRB(s) */
  1380. iobuf = xhci_dequeue_multi ( &endpoint->ring );
  1381. assert ( iobuf != NULL );
  1382. /* Check for errors */
  1383. if ( ! ( ( trb->code == XHCI_CMPLT_SUCCESS ) ||
  1384. ( trb->code == XHCI_CMPLT_SHORT ) ) ) {
  1385. /* Construct error */
  1386. rc = -ECODE ( trb->code );
  1387. DBGC ( xhci, "XHCI %s slot %d ctx %d failed (code %d): %s\n",
  1388. xhci->name, slot->id, endpoint->ctx, trb->code,
  1389. strerror ( rc ) );
  1390. DBGC_HDA ( xhci, 0, trb, sizeof ( *trb ) );
  1391. /* Sanity check */
  1392. assert ( ( endpoint->context->state & XHCI_ENDPOINT_STATE_MASK )
  1393. != XHCI_ENDPOINT_RUNNING );
  1394. /* Report failure to USB core */
  1395. usb_complete_err ( endpoint->ep, iobuf, rc );
  1396. return;
  1397. }
  1398. /* Record actual transfer size */
  1399. iob_unput ( iobuf, le16_to_cpu ( trb->residual ) );
  1400. /* Sanity check (for successful completions only) */
  1401. assert ( xhci_ring_consumed ( &endpoint->ring ) ==
  1402. le64_to_cpu ( trb->transfer ) );
  1403. /* Report completion to USB core */
  1404. usb_complete ( endpoint->ep, iobuf );
  1405. profile_stop ( &xhci_transfer_profiler );
  1406. }
  1407. /**
  1408. * Handle command completion event
  1409. *
  1410. * @v xhci xHCI device
  1411. * @v trb Command completion event
  1412. */
  1413. static void xhci_complete ( struct xhci_device *xhci,
  1414. struct xhci_trb_complete *trb ) {
  1415. int rc;
  1416. /* Ignore "command ring stopped" notifications */
  1417. if ( trb->code == XHCI_CMPLT_CMD_STOPPED ) {
  1418. DBGC2 ( xhci, "XHCI %s command ring stopped\n", xhci->name );
  1419. return;
  1420. }
  1421. /* Ignore unexpected completions */
  1422. if ( ! xhci->pending ) {
  1423. rc = -ECODE ( trb->code );
  1424. DBGC ( xhci, "XHCI %s unexpected completion (code %d): %s\n",
  1425. xhci->name, trb->code, strerror ( rc ) );
  1426. DBGC_HDA ( xhci, 0, trb, sizeof ( *trb ) );
  1427. return;
  1428. }
  1429. /* Dequeue command TRB */
  1430. xhci_dequeue ( &xhci->command );
  1431. /* Sanity check */
  1432. assert ( xhci_ring_consumed ( &xhci->command ) ==
  1433. le64_to_cpu ( trb->command ) );
  1434. /* Record completion */
  1435. memcpy ( xhci->pending, trb, sizeof ( *xhci->pending ) );
  1436. xhci->pending = NULL;
  1437. }
  1438. /**
  1439. * Handle port status event
  1440. *
  1441. * @v xhci xHCI device
  1442. * @v trb Port status event
  1443. */
  1444. static void xhci_port_status ( struct xhci_device *xhci,
  1445. struct xhci_trb_port_status *trb ) {
  1446. struct usb_port *port = usb_port ( xhci->bus->hub, trb->port );
  1447. uint32_t portsc;
  1448. /* Sanity check */
  1449. assert ( ( trb->port > 0 ) && ( trb->port <= xhci->ports ) );
  1450. /* Record disconnections and clear changes */
  1451. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( trb->port ) );
  1452. port->disconnected |= ( portsc & XHCI_PORTSC_CSC );
  1453. portsc &= ( XHCI_PORTSC_PRESERVE | XHCI_PORTSC_CHANGE );
  1454. writel ( portsc, xhci->op + XHCI_OP_PORTSC ( trb->port ) );
  1455. /* Report port status change */
  1456. usb_port_changed ( port );
  1457. }
  1458. /**
  1459. * Handle host controller event
  1460. *
  1461. * @v xhci xHCI device
  1462. * @v trb Host controller event
  1463. */
  1464. static void xhci_host_controller ( struct xhci_device *xhci,
  1465. struct xhci_trb_host_controller *trb ) {
  1466. int rc;
  1467. /* Construct error */
  1468. rc = -ECODE ( trb->code );
  1469. DBGC ( xhci, "XHCI %s host controller event (code %d): %s\n",
  1470. xhci->name, trb->code, strerror ( rc ) );
  1471. }
  1472. /**
  1473. * Poll event ring
  1474. *
  1475. * @v xhci xHCI device
  1476. */
  1477. static void xhci_event_poll ( struct xhci_device *xhci ) {
  1478. struct xhci_event_ring *event = &xhci->event;
  1479. union xhci_trb *trb;
  1480. unsigned int shift = XHCI_EVENT_TRBS_LOG2;
  1481. unsigned int count = ( 1 << shift );
  1482. unsigned int mask = ( count - 1 );
  1483. unsigned int consumed;
  1484. unsigned int type;
  1485. /* Poll for events */
  1486. profile_start ( &xhci_event_profiler );
  1487. for ( consumed = 0 ; ; consumed++ ) {
  1488. /* Stop if we reach an empty TRB */
  1489. rmb();
  1490. trb = &event->trb[ event->cons & mask ];
  1491. if ( ! ( ( trb->common.flags ^
  1492. ( event->cons >> shift ) ) & XHCI_TRB_C ) )
  1493. break;
  1494. /* Consume this TRB */
  1495. event->cons++;
  1496. /* Handle TRB */
  1497. type = ( trb->common.type & XHCI_TRB_TYPE_MASK );
  1498. switch ( type ) {
  1499. case XHCI_TRB_TRANSFER :
  1500. xhci_transfer ( xhci, &trb->transfer );
  1501. break;
  1502. case XHCI_TRB_COMPLETE :
  1503. xhci_complete ( xhci, &trb->complete );
  1504. break;
  1505. case XHCI_TRB_PORT_STATUS:
  1506. xhci_port_status ( xhci, &trb->port );
  1507. break;
  1508. case XHCI_TRB_HOST_CONTROLLER:
  1509. xhci_host_controller ( xhci, &trb->host );
  1510. break;
  1511. default:
  1512. DBGC ( xhci, "XHCI %s unrecognised event %#x\n:",
  1513. xhci->name, ( event->cons - 1 ) );
  1514. DBGC_HDA ( xhci, virt_to_phys ( trb ),
  1515. trb, sizeof ( *trb ) );
  1516. break;
  1517. }
  1518. }
  1519. /* Update dequeue pointer if applicable */
  1520. if ( consumed ) {
  1521. xhci_writeq ( xhci, virt_to_phys ( trb ),
  1522. xhci->run + XHCI_RUN_ERDP ( 0 ) );
  1523. profile_stop ( &xhci_event_profiler );
  1524. }
  1525. }
  1526. /**
  1527. * Abort command
  1528. *
  1529. * @v xhci xHCI device
  1530. */
  1531. static void xhci_abort ( struct xhci_device *xhci ) {
  1532. physaddr_t crp;
  1533. /* Abort the command */
  1534. DBGC2 ( xhci, "XHCI %s aborting command\n", xhci->name );
  1535. xhci_writeq ( xhci, XHCI_CRCR_CA, xhci->op + XHCI_OP_CRCR );
  1536. /* Allow time for command to abort */
  1537. mdelay ( XHCI_COMMAND_ABORT_DELAY_MS );
  1538. /* Sanity check */
  1539. assert ( ( readl ( xhci->op + XHCI_OP_CRCR ) & XHCI_CRCR_CRR ) == 0 );
  1540. /* Consume (and ignore) any final command status */
  1541. xhci_event_poll ( xhci );
  1542. /* Reset the command ring control register */
  1543. xhci_ring_reset ( &xhci->command );
  1544. crp = virt_to_phys ( xhci->command.trb );
  1545. xhci_writeq ( xhci, ( crp | XHCI_CRCR_RCS ), xhci->op + XHCI_OP_CRCR );
  1546. }
  1547. /**
  1548. * Issue command and wait for completion
  1549. *
  1550. * @v xhci xHCI device
  1551. * @v trb Transfer request block (with empty Cycle flag)
  1552. * @ret rc Return status code
  1553. *
  1554. * On a successful completion, the TRB will be overwritten with the
  1555. * completion.
  1556. */
  1557. static int xhci_command ( struct xhci_device *xhci, union xhci_trb *trb ) {
  1558. struct xhci_trb_complete *complete = &trb->complete;
  1559. unsigned int i;
  1560. int rc;
  1561. /* Record the pending command */
  1562. xhci->pending = trb;
  1563. /* Enqueue the command */
  1564. if ( ( rc = xhci_enqueue ( &xhci->command, NULL, trb ) ) != 0 )
  1565. goto err_enqueue;
  1566. /* Ring the command doorbell */
  1567. xhci_doorbell ( &xhci->command );
  1568. /* Wait for the command to complete */
  1569. for ( i = 0 ; i < XHCI_COMMAND_MAX_WAIT_MS ; i++ ) {
  1570. /* Poll event ring */
  1571. xhci_event_poll ( xhci );
  1572. /* Check for completion */
  1573. if ( ! xhci->pending ) {
  1574. if ( complete->code != XHCI_CMPLT_SUCCESS ) {
  1575. rc = -ECODE ( complete->code );
  1576. DBGC ( xhci, "XHCI %s command failed (code "
  1577. "%d): %s\n", xhci->name, complete->code,
  1578. strerror ( rc ) );
  1579. DBGC_HDA ( xhci, 0, trb, sizeof ( *trb ) );
  1580. return rc;
  1581. }
  1582. return 0;
  1583. }
  1584. /* Delay */
  1585. mdelay ( 1 );
  1586. }
  1587. /* Timeout */
  1588. DBGC ( xhci, "XHCI %s timed out waiting for completion\n", xhci->name );
  1589. rc = -ETIMEDOUT;
  1590. /* Abort command */
  1591. xhci_abort ( xhci );
  1592. err_enqueue:
  1593. xhci->pending = NULL;
  1594. return rc;
  1595. }
  1596. /**
  1597. * Issue NOP and wait for completion
  1598. *
  1599. * @v xhci xHCI device
  1600. * @ret rc Return status code
  1601. */
  1602. static inline int xhci_nop ( struct xhci_device *xhci ) {
  1603. union xhci_trb trb;
  1604. struct xhci_trb_common *nop = &trb.common;
  1605. int rc;
  1606. /* Construct command */
  1607. memset ( nop, 0, sizeof ( *nop ) );
  1608. nop->flags = XHCI_TRB_IOC;
  1609. nop->type = XHCI_TRB_NOP_CMD;
  1610. /* Issue command and wait for completion */
  1611. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 )
  1612. return rc;
  1613. return 0;
  1614. }
  1615. /**
  1616. * Enable slot
  1617. *
  1618. * @v xhci xHCI device
  1619. * @v type Slot type
  1620. * @ret slot Device slot ID, or negative error
  1621. */
  1622. static inline int xhci_enable_slot ( struct xhci_device *xhci,
  1623. unsigned int type ) {
  1624. union xhci_trb trb;
  1625. struct xhci_trb_enable_slot *enable = &trb.enable;
  1626. struct xhci_trb_complete *enabled = &trb.complete;
  1627. unsigned int slot;
  1628. int rc;
  1629. /* Construct command */
  1630. memset ( enable, 0, sizeof ( *enable ) );
  1631. enable->slot = type;
  1632. enable->type = XHCI_TRB_ENABLE_SLOT;
  1633. /* Issue command and wait for completion */
  1634. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 ) {
  1635. DBGC ( xhci, "XHCI %s could not enable new slot: %s\n",
  1636. xhci->name, strerror ( rc ) );
  1637. return rc;
  1638. }
  1639. /* Extract slot number */
  1640. slot = enabled->slot;
  1641. DBGC2 ( xhci, "XHCI %s slot %d enabled\n", xhci->name, slot );
  1642. return slot;
  1643. }
  1644. /**
  1645. * Disable slot
  1646. *
  1647. * @v xhci xHCI device
  1648. * @v slot Device slot
  1649. * @ret rc Return status code
  1650. */
  1651. static inline int xhci_disable_slot ( struct xhci_device *xhci,
  1652. unsigned int slot ) {
  1653. union xhci_trb trb;
  1654. struct xhci_trb_disable_slot *disable = &trb.disable;
  1655. int rc;
  1656. /* Construct command */
  1657. memset ( disable, 0, sizeof ( *disable ) );
  1658. disable->type = XHCI_TRB_DISABLE_SLOT;
  1659. disable->slot = slot;
  1660. /* Issue command and wait for completion */
  1661. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 ) {
  1662. DBGC ( xhci, "XHCI %s could not disable slot %d: %s\n",
  1663. xhci->name, slot, strerror ( rc ) );
  1664. return rc;
  1665. }
  1666. DBGC2 ( xhci, "XHCI %s slot %d disabled\n", xhci->name, slot );
  1667. return 0;
  1668. }
  1669. /**
  1670. * Issue context-based command and wait for completion
  1671. *
  1672. * @v xhci xHCI device
  1673. * @v slot Device slot
  1674. * @v endpoint Endpoint
  1675. * @v type TRB type
  1676. * @v populate Input context populater
  1677. * @ret rc Return status code
  1678. */
  1679. static int xhci_context ( struct xhci_device *xhci, struct xhci_slot *slot,
  1680. struct xhci_endpoint *endpoint, unsigned int type,
  1681. void ( * populate ) ( struct xhci_device *xhci,
  1682. struct xhci_slot *slot,
  1683. struct xhci_endpoint *endpoint,
  1684. void *input ) ) {
  1685. union xhci_trb trb;
  1686. struct xhci_trb_context *context = &trb.context;
  1687. size_t len;
  1688. void *input;
  1689. int rc;
  1690. /* Allocate an input context */
  1691. len = xhci_input_context_offset ( xhci, XHCI_CTX_END );
  1692. input = malloc_dma ( len, xhci_align ( len ) );
  1693. if ( ! input ) {
  1694. rc = -ENOMEM;
  1695. goto err_alloc;
  1696. }
  1697. memset ( input, 0, len );
  1698. /* Populate input context */
  1699. populate ( xhci, slot, endpoint, input );
  1700. /* Construct command */
  1701. memset ( context, 0, sizeof ( *context ) );
  1702. context->type = type;
  1703. context->input = cpu_to_le64 ( virt_to_phys ( input ) );
  1704. context->slot = slot->id;
  1705. /* Issue command and wait for completion */
  1706. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 )
  1707. goto err_command;
  1708. err_command:
  1709. free_dma ( input, len );
  1710. err_alloc:
  1711. return rc;
  1712. }
  1713. /**
  1714. * Populate address device input context
  1715. *
  1716. * @v xhci xHCI device
  1717. * @v slot Device slot
  1718. * @v endpoint Endpoint
  1719. * @v input Input context
  1720. */
  1721. static void xhci_address_device_input ( struct xhci_device *xhci,
  1722. struct xhci_slot *slot,
  1723. struct xhci_endpoint *endpoint,
  1724. void *input ) {
  1725. struct xhci_control_context *control_ctx;
  1726. struct xhci_slot_context *slot_ctx;
  1727. struct xhci_endpoint_context *ep_ctx;
  1728. /* Sanity checks */
  1729. assert ( endpoint->ctx == XHCI_CTX_EP0 );
  1730. /* Populate control context */
  1731. control_ctx = input;
  1732. control_ctx->add = cpu_to_le32 ( ( 1 << XHCI_CTX_SLOT ) |
  1733. ( 1 << XHCI_CTX_EP0 ) );
  1734. /* Populate slot context */
  1735. slot_ctx = ( input + xhci_input_context_offset ( xhci, XHCI_CTX_SLOT ));
  1736. slot_ctx->info = cpu_to_le32 ( XHCI_SLOT_INFO ( 1, 0, slot->psiv,
  1737. slot->route ) );
  1738. slot_ctx->port = slot->port;
  1739. slot_ctx->tt_id = slot->tt_id;
  1740. slot_ctx->tt_port = slot->tt_port;
  1741. /* Populate control endpoint context */
  1742. ep_ctx = ( input + xhci_input_context_offset ( xhci, XHCI_CTX_EP0 ) );
  1743. ep_ctx->type = XHCI_EP_TYPE_CONTROL;
  1744. ep_ctx->burst = endpoint->ep->burst;
  1745. ep_ctx->mtu = cpu_to_le16 ( endpoint->ep->mtu );
  1746. ep_ctx->dequeue = cpu_to_le64 ( virt_to_phys ( endpoint->ring.trb ) |
  1747. XHCI_EP_DCS );
  1748. ep_ctx->trb_len = cpu_to_le16 ( XHCI_EP0_TRB_LEN );
  1749. }
  1750. /**
  1751. * Address device
  1752. *
  1753. * @v xhci xHCI device
  1754. * @v slot Device slot
  1755. * @ret rc Return status code
  1756. */
  1757. static inline int xhci_address_device ( struct xhci_device *xhci,
  1758. struct xhci_slot *slot ) {
  1759. struct usb_device *usb = slot->usb;
  1760. struct xhci_slot_context *slot_ctx;
  1761. int rc;
  1762. /* Assign device address */
  1763. if ( ( rc = xhci_context ( xhci, slot, slot->endpoint[XHCI_CTX_EP0],
  1764. XHCI_TRB_ADDRESS_DEVICE,
  1765. xhci_address_device_input ) ) != 0 )
  1766. return rc;
  1767. /* Get assigned address */
  1768. slot_ctx = ( slot->context +
  1769. xhci_device_context_offset ( xhci, XHCI_CTX_SLOT ) );
  1770. usb->address = slot_ctx->address;
  1771. DBGC2 ( xhci, "XHCI %s assigned address %d to %s\n",
  1772. xhci->name, usb->address, usb->name );
  1773. return 0;
  1774. }
  1775. /**
  1776. * Populate configure endpoint input context
  1777. *
  1778. * @v xhci xHCI device
  1779. * @v slot Device slot
  1780. * @v endpoint Endpoint
  1781. * @v input Input context
  1782. */
  1783. static void xhci_configure_endpoint_input ( struct xhci_device *xhci,
  1784. struct xhci_slot *slot,
  1785. struct xhci_endpoint *endpoint,
  1786. void *input ) {
  1787. struct xhci_control_context *control_ctx;
  1788. struct xhci_slot_context *slot_ctx;
  1789. struct xhci_endpoint_context *ep_ctx;
  1790. /* Populate control context */
  1791. control_ctx = input;
  1792. control_ctx->add = cpu_to_le32 ( ( 1 << XHCI_CTX_SLOT ) |
  1793. ( 1 << endpoint->ctx ) );
  1794. /* Populate slot context */
  1795. slot_ctx = ( input + xhci_input_context_offset ( xhci, XHCI_CTX_SLOT ));
  1796. slot_ctx->info = cpu_to_le32 ( XHCI_SLOT_INFO ( ( XHCI_CTX_END - 1 ),
  1797. ( slot->ports ? 1 : 0 ),
  1798. slot->psiv, 0 ) );
  1799. slot_ctx->ports = slot->ports;
  1800. /* Populate endpoint context */
  1801. ep_ctx = ( input + xhci_input_context_offset ( xhci, endpoint->ctx ) );
  1802. ep_ctx->interval = endpoint->interval;
  1803. ep_ctx->type = endpoint->type;
  1804. ep_ctx->burst = endpoint->ep->burst;
  1805. ep_ctx->mtu = cpu_to_le16 ( endpoint->ep->mtu );
  1806. ep_ctx->dequeue = cpu_to_le64 ( virt_to_phys ( endpoint->ring.trb ) |
  1807. XHCI_EP_DCS );
  1808. ep_ctx->trb_len = cpu_to_le16 ( endpoint->ep->mtu ); /* best guess */
  1809. }
  1810. /**
  1811. * Configure endpoint
  1812. *
  1813. * @v xhci xHCI device
  1814. * @v slot Device slot
  1815. * @v endpoint Endpoint
  1816. * @ret rc Return status code
  1817. */
  1818. static inline int xhci_configure_endpoint ( struct xhci_device *xhci,
  1819. struct xhci_slot *slot,
  1820. struct xhci_endpoint *endpoint ) {
  1821. int rc;
  1822. /* Configure endpoint */
  1823. if ( ( rc = xhci_context ( xhci, slot, endpoint,
  1824. XHCI_TRB_CONFIGURE_ENDPOINT,
  1825. xhci_configure_endpoint_input ) ) != 0 )
  1826. return rc;
  1827. DBGC2 ( xhci, "XHCI %s slot %d ctx %d configured\n",
  1828. xhci->name, slot->id, endpoint->ctx );
  1829. return 0;
  1830. }
  1831. /**
  1832. * Populate deconfigure endpoint input context
  1833. *
  1834. * @v xhci xHCI device
  1835. * @v slot Device slot
  1836. * @v endpoint Endpoint
  1837. * @v input Input context
  1838. */
  1839. static void
  1840. xhci_deconfigure_endpoint_input ( struct xhci_device *xhci __unused,
  1841. struct xhci_slot *slot __unused,
  1842. struct xhci_endpoint *endpoint,
  1843. void *input ) {
  1844. struct xhci_control_context *control_ctx;
  1845. struct xhci_slot_context *slot_ctx;
  1846. /* Populate control context */
  1847. control_ctx = input;
  1848. control_ctx->add = cpu_to_le32 ( 1 << XHCI_CTX_SLOT );
  1849. control_ctx->drop = cpu_to_le32 ( 1 << endpoint->ctx );
  1850. /* Populate slot context */
  1851. slot_ctx = ( input + xhci_input_context_offset ( xhci, XHCI_CTX_SLOT ));
  1852. slot_ctx->info = cpu_to_le32 ( XHCI_SLOT_INFO ( ( XHCI_CTX_END - 1 ),
  1853. 0, 0, 0 ) );
  1854. }
  1855. /**
  1856. * Deconfigure endpoint
  1857. *
  1858. * @v xhci xHCI device
  1859. * @v slot Device slot
  1860. * @v endpoint Endpoint
  1861. * @ret rc Return status code
  1862. */
  1863. static inline int xhci_deconfigure_endpoint ( struct xhci_device *xhci,
  1864. struct xhci_slot *slot,
  1865. struct xhci_endpoint *endpoint ) {
  1866. int rc;
  1867. /* Deconfigure endpoint */
  1868. if ( ( rc = xhci_context ( xhci, slot, endpoint,
  1869. XHCI_TRB_CONFIGURE_ENDPOINT,
  1870. xhci_deconfigure_endpoint_input ) ) != 0 )
  1871. return rc;
  1872. DBGC2 ( xhci, "XHCI %s slot %d ctx %d deconfigured\n",
  1873. xhci->name, slot->id, endpoint->ctx );
  1874. return 0;
  1875. }
  1876. /**
  1877. * Populate evaluate context input context
  1878. *
  1879. * @v xhci xHCI device
  1880. * @v slot Device slot
  1881. * @v endpoint Endpoint
  1882. * @v input Input context
  1883. */
  1884. static void xhci_evaluate_context_input ( struct xhci_device *xhci,
  1885. struct xhci_slot *slot __unused,
  1886. struct xhci_endpoint *endpoint,
  1887. void *input ) {
  1888. struct xhci_control_context *control_ctx;
  1889. struct xhci_slot_context *slot_ctx;
  1890. struct xhci_endpoint_context *ep_ctx;
  1891. /* Populate control context */
  1892. control_ctx = input;
  1893. control_ctx->add = cpu_to_le32 ( ( 1 << XHCI_CTX_SLOT ) |
  1894. ( 1 << endpoint->ctx ) );
  1895. /* Populate slot context */
  1896. slot_ctx = ( input + xhci_input_context_offset ( xhci, XHCI_CTX_SLOT ));
  1897. slot_ctx->info = cpu_to_le32 ( XHCI_SLOT_INFO ( ( XHCI_CTX_END - 1 ),
  1898. 0, 0, 0 ) );
  1899. /* Populate endpoint context */
  1900. ep_ctx = ( input + xhci_input_context_offset ( xhci, endpoint->ctx ) );
  1901. ep_ctx->mtu = cpu_to_le16 ( endpoint->ep->mtu );
  1902. }
  1903. /**
  1904. * Evaluate context
  1905. *
  1906. * @v xhci xHCI device
  1907. * @v slot Device slot
  1908. * @v endpoint Endpoint
  1909. * @ret rc Return status code
  1910. */
  1911. static inline int xhci_evaluate_context ( struct xhci_device *xhci,
  1912. struct xhci_slot *slot,
  1913. struct xhci_endpoint *endpoint ) {
  1914. int rc;
  1915. /* Configure endpoint */
  1916. if ( ( rc = xhci_context ( xhci, slot, endpoint,
  1917. XHCI_TRB_EVALUATE_CONTEXT,
  1918. xhci_evaluate_context_input ) ) != 0 )
  1919. return rc;
  1920. DBGC2 ( xhci, "XHCI %s slot %d ctx %d (re-)evaluated\n",
  1921. xhci->name, slot->id, endpoint->ctx );
  1922. return 0;
  1923. }
  1924. /**
  1925. * Reset endpoint
  1926. *
  1927. * @v xhci xHCI device
  1928. * @v slot Device slot
  1929. * @v endpoint Endpoint
  1930. * @ret rc Return status code
  1931. */
  1932. static inline int xhci_reset_endpoint ( struct xhci_device *xhci,
  1933. struct xhci_slot *slot,
  1934. struct xhci_endpoint *endpoint ) {
  1935. union xhci_trb trb;
  1936. struct xhci_trb_reset_endpoint *reset = &trb.reset;
  1937. int rc;
  1938. /* Construct command */
  1939. memset ( reset, 0, sizeof ( *reset ) );
  1940. reset->slot = slot->id;
  1941. reset->endpoint = endpoint->ctx;
  1942. reset->type = XHCI_TRB_RESET_ENDPOINT;
  1943. /* Issue command and wait for completion */
  1944. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 ) {
  1945. DBGC ( xhci, "XHCI %s slot %d ctx %d could not reset endpoint "
  1946. "in state %d: %s\n", xhci->name, slot->id, endpoint->ctx,
  1947. endpoint->context->state, strerror ( rc ) );
  1948. return rc;
  1949. }
  1950. return 0;
  1951. }
  1952. /**
  1953. * Stop endpoint
  1954. *
  1955. * @v xhci xHCI device
  1956. * @v slot Device slot
  1957. * @v endpoint Endpoint
  1958. * @ret rc Return status code
  1959. */
  1960. static inline int xhci_stop_endpoint ( struct xhci_device *xhci,
  1961. struct xhci_slot *slot,
  1962. struct xhci_endpoint *endpoint ) {
  1963. union xhci_trb trb;
  1964. struct xhci_trb_stop_endpoint *stop = &trb.stop;
  1965. int rc;
  1966. /* Construct command */
  1967. memset ( stop, 0, sizeof ( *stop ) );
  1968. stop->slot = slot->id;
  1969. stop->endpoint = endpoint->ctx;
  1970. stop->type = XHCI_TRB_STOP_ENDPOINT;
  1971. /* Issue command and wait for completion */
  1972. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 ) {
  1973. DBGC ( xhci, "XHCI %s slot %d ctx %d could not stop endpoint "
  1974. "in state %d: %s\n", xhci->name, slot->id, endpoint->ctx,
  1975. endpoint->context->state, strerror ( rc ) );
  1976. return rc;
  1977. }
  1978. return 0;
  1979. }
  1980. /**
  1981. * Set transfer ring dequeue pointer
  1982. *
  1983. * @v xhci xHCI device
  1984. * @v slot Device slot
  1985. * @v endpoint Endpoint
  1986. * @ret rc Return status code
  1987. */
  1988. static inline int
  1989. xhci_set_tr_dequeue_pointer ( struct xhci_device *xhci,
  1990. struct xhci_slot *slot,
  1991. struct xhci_endpoint *endpoint ) {
  1992. union xhci_trb trb;
  1993. struct xhci_trb_set_tr_dequeue_pointer *dequeue = &trb.dequeue;
  1994. struct xhci_trb_ring *ring = &endpoint->ring;
  1995. unsigned int cons;
  1996. unsigned int mask;
  1997. unsigned int index;
  1998. unsigned int dcs;
  1999. int rc;
  2000. /* Construct command */
  2001. memset ( dequeue, 0, sizeof ( *dequeue ) );
  2002. cons = ring->cons;
  2003. mask = ring->mask;
  2004. dcs = ( ( ~( cons >> ring->shift ) ) & XHCI_EP_DCS );
  2005. index = ( cons & mask );
  2006. dequeue->dequeue =
  2007. cpu_to_le64 ( virt_to_phys ( &ring->trb[index] ) | dcs );
  2008. dequeue->slot = slot->id;
  2009. dequeue->endpoint = endpoint->ctx;
  2010. dequeue->type = XHCI_TRB_SET_TR_DEQUEUE_POINTER;
  2011. /* Issue command and wait for completion */
  2012. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 ) {
  2013. DBGC ( xhci, "XHCI %s slot %d ctx %d could not set TR dequeue "
  2014. "pointer in state %d: %s\n", xhci->name, slot->id,
  2015. endpoint->ctx, endpoint->context->state, strerror ( rc));
  2016. return rc;
  2017. }
  2018. return 0;
  2019. }
  2020. /******************************************************************************
  2021. *
  2022. * Endpoint operations
  2023. *
  2024. ******************************************************************************
  2025. */
  2026. /**
  2027. * Open endpoint
  2028. *
  2029. * @v ep USB endpoint
  2030. * @ret rc Return status code
  2031. */
  2032. static int xhci_endpoint_open ( struct usb_endpoint *ep ) {
  2033. struct usb_device *usb = ep->usb;
  2034. struct xhci_slot *slot = usb_get_hostdata ( usb );
  2035. struct xhci_device *xhci = slot->xhci;
  2036. struct xhci_endpoint *endpoint;
  2037. unsigned int ctx;
  2038. unsigned int type;
  2039. unsigned int interval;
  2040. int rc;
  2041. /* Calculate context index */
  2042. ctx = XHCI_CTX ( ep->address );
  2043. assert ( slot->endpoint[ctx] == NULL );
  2044. /* Calculate endpoint type */
  2045. type = XHCI_EP_TYPE ( ep->attributes & USB_ENDPOINT_ATTR_TYPE_MASK );
  2046. if ( type == XHCI_EP_TYPE ( USB_ENDPOINT_ATTR_CONTROL ) )
  2047. type = XHCI_EP_TYPE_CONTROL;
  2048. if ( ep->address & USB_DIR_IN )
  2049. type |= XHCI_EP_TYPE_IN;
  2050. /* Calculate interval */
  2051. if ( type & XHCI_EP_TYPE_PERIODIC ) {
  2052. interval = ( fls ( ep->interval ) - 1 );
  2053. } else {
  2054. interval = ep->interval;
  2055. }
  2056. /* Allocate and initialise structure */
  2057. endpoint = zalloc ( sizeof ( *endpoint ) );
  2058. if ( ! endpoint ) {
  2059. rc = -ENOMEM;
  2060. goto err_alloc;
  2061. }
  2062. usb_endpoint_set_hostdata ( ep, endpoint );
  2063. slot->endpoint[ctx] = endpoint;
  2064. endpoint->xhci = xhci;
  2065. endpoint->slot = slot;
  2066. endpoint->ep = ep;
  2067. endpoint->ctx = ctx;
  2068. endpoint->type = type;
  2069. endpoint->interval = interval;
  2070. endpoint->context = ( ( ( void * ) slot->context ) +
  2071. xhci_device_context_offset ( xhci, ctx ) );
  2072. /* Allocate transfer ring */
  2073. if ( ( rc = xhci_ring_alloc ( xhci, &endpoint->ring,
  2074. XHCI_TRANSFER_TRBS_LOG2,
  2075. slot->id, ctx, 0 ) ) != 0 )
  2076. goto err_ring_alloc;
  2077. /* Configure endpoint, if applicable */
  2078. if ( ( ctx != XHCI_CTX_EP0 ) &&
  2079. ( ( rc = xhci_configure_endpoint ( xhci, slot, endpoint ) ) != 0 ))
  2080. goto err_configure_endpoint;
  2081. DBGC2 ( xhci, "XHCI %s slot %d ctx %d ring [%08lx,%08lx)\n",
  2082. xhci->name, slot->id, ctx, virt_to_phys ( endpoint->ring.trb ),
  2083. ( virt_to_phys ( endpoint->ring.trb ) + endpoint->ring.len ) );
  2084. return 0;
  2085. xhci_deconfigure_endpoint ( xhci, slot, endpoint );
  2086. err_configure_endpoint:
  2087. xhci_ring_free ( &endpoint->ring );
  2088. err_ring_alloc:
  2089. slot->endpoint[ctx] = NULL;
  2090. free ( endpoint );
  2091. err_alloc:
  2092. return rc;
  2093. }
  2094. /**
  2095. * Close endpoint
  2096. *
  2097. * @v ep USB endpoint
  2098. */
  2099. static void xhci_endpoint_close ( struct usb_endpoint *ep ) {
  2100. struct xhci_endpoint *endpoint = usb_endpoint_get_hostdata ( ep );
  2101. struct xhci_slot *slot = endpoint->slot;
  2102. struct xhci_device *xhci = slot->xhci;
  2103. struct io_buffer *iobuf;
  2104. unsigned int ctx = endpoint->ctx;
  2105. /* Deconfigure endpoint, if applicable */
  2106. if ( ctx != XHCI_CTX_EP0 )
  2107. xhci_deconfigure_endpoint ( xhci, slot, endpoint );
  2108. /* Cancel any incomplete transfers */
  2109. while ( xhci_ring_fill ( &endpoint->ring ) ) {
  2110. iobuf = xhci_dequeue_multi ( &endpoint->ring );
  2111. usb_complete_err ( ep, iobuf, -ECANCELED );
  2112. }
  2113. /* Free endpoint */
  2114. xhci_ring_free ( &endpoint->ring );
  2115. slot->endpoint[ctx] = NULL;
  2116. free ( endpoint );
  2117. }
  2118. /**
  2119. * Reset endpoint
  2120. *
  2121. * @v ep USB endpoint
  2122. * @ret rc Return status code
  2123. */
  2124. static int xhci_endpoint_reset ( struct usb_endpoint *ep ) {
  2125. struct xhci_endpoint *endpoint = usb_endpoint_get_hostdata ( ep );
  2126. struct xhci_slot *slot = endpoint->slot;
  2127. struct xhci_device *xhci = slot->xhci;
  2128. int rc;
  2129. /* Reset endpoint context */
  2130. if ( ( rc = xhci_reset_endpoint ( xhci, slot, endpoint ) ) != 0 )
  2131. return rc;
  2132. /* Set transfer ring dequeue pointer */
  2133. if ( ( rc = xhci_set_tr_dequeue_pointer ( xhci, slot, endpoint ) ) != 0)
  2134. return rc;
  2135. /* Ring doorbell to resume processing */
  2136. xhci_doorbell ( &endpoint->ring );
  2137. DBGC ( xhci, "XHCI %s slot %d ctx %d reset\n",
  2138. xhci->name, slot->id, endpoint->ctx );
  2139. return 0;
  2140. }
  2141. /**
  2142. * Update MTU
  2143. *
  2144. * @v ep USB endpoint
  2145. * @ret rc Return status code
  2146. */
  2147. static int xhci_endpoint_mtu ( struct usb_endpoint *ep ) {
  2148. struct xhci_endpoint *endpoint = usb_endpoint_get_hostdata ( ep );
  2149. struct xhci_slot *slot = endpoint->slot;
  2150. struct xhci_device *xhci = slot->xhci;
  2151. int rc;
  2152. /* Evalulate context */
  2153. if ( ( rc = xhci_evaluate_context ( xhci, slot, endpoint ) ) != 0 )
  2154. return rc;
  2155. return 0;
  2156. }
  2157. /**
  2158. * Enqueue message transfer
  2159. *
  2160. * @v ep USB endpoint
  2161. * @v iobuf I/O buffer
  2162. * @ret rc Return status code
  2163. */
  2164. static int xhci_endpoint_message ( struct usb_endpoint *ep,
  2165. struct io_buffer *iobuf ) {
  2166. struct xhci_endpoint *endpoint = usb_endpoint_get_hostdata ( ep );
  2167. struct usb_setup_packet *packet;
  2168. unsigned int input;
  2169. size_t len;
  2170. union xhci_trb trbs[ 1 /* setup */ + 1 /* possible data */ +
  2171. 1 /* status */ ];
  2172. union xhci_trb *trb = trbs;
  2173. struct xhci_trb_setup *setup;
  2174. struct xhci_trb_data *data;
  2175. struct xhci_trb_status *status;
  2176. int rc;
  2177. /* Profile message transfers */
  2178. profile_start ( &xhci_message_profiler );
  2179. /* Construct setup stage TRB */
  2180. memset ( trbs, 0, sizeof ( trbs ) );
  2181. assert ( iob_len ( iobuf ) >= sizeof ( *packet ) );
  2182. packet = iobuf->data;
  2183. iob_pull ( iobuf, sizeof ( *packet ) );
  2184. setup = &(trb++)->setup;
  2185. memcpy ( &setup->packet, packet, sizeof ( setup->packet ) );
  2186. setup->len = cpu_to_le32 ( sizeof ( *packet ) );
  2187. setup->flags = XHCI_TRB_IDT;
  2188. setup->type = XHCI_TRB_SETUP;
  2189. len = iob_len ( iobuf );
  2190. input = ( packet->request & cpu_to_le16 ( USB_DIR_IN ) );
  2191. if ( len )
  2192. setup->direction = ( input ? XHCI_SETUP_IN : XHCI_SETUP_OUT );
  2193. /* Construct data stage TRB, if applicable */
  2194. if ( len ) {
  2195. data = &(trb++)->data;
  2196. data->data = cpu_to_le64 ( virt_to_phys ( iobuf->data ) );
  2197. data->len = cpu_to_le32 ( len );
  2198. data->type = XHCI_TRB_DATA;
  2199. data->direction = ( input ? XHCI_DATA_IN : XHCI_DATA_OUT );
  2200. }
  2201. /* Construct status stage TRB */
  2202. status = &(trb++)->status;
  2203. status->flags = XHCI_TRB_IOC;
  2204. status->type = XHCI_TRB_STATUS;
  2205. status->direction =
  2206. ( ( len && input ) ? XHCI_STATUS_OUT : XHCI_STATUS_IN );
  2207. /* Enqueue TRBs */
  2208. if ( ( rc = xhci_enqueue_multi ( &endpoint->ring, iobuf, trbs,
  2209. ( trb - trbs ) ) ) != 0 )
  2210. return rc;
  2211. /* Ring the doorbell */
  2212. xhci_doorbell ( &endpoint->ring );
  2213. profile_stop ( &xhci_message_profiler );
  2214. return 0;
  2215. }
  2216. /**
  2217. * Calculate number of TRBs
  2218. *
  2219. * @v len Length of data
  2220. * @v zlp Append a zero-length packet
  2221. * @ret count Number of transfer descriptors
  2222. */
  2223. static unsigned int xhci_endpoint_count ( size_t len, int zlp ) {
  2224. unsigned int count;
  2225. /* Split into 64kB TRBs */
  2226. count = ( ( len + XHCI_MTU - 1 ) / XHCI_MTU );
  2227. /* Append a zero-length TRB if applicable */
  2228. if ( zlp || ( count == 0 ) )
  2229. count++;
  2230. return count;
  2231. }
  2232. /**
  2233. * Enqueue stream transfer
  2234. *
  2235. * @v ep USB endpoint
  2236. * @v iobuf I/O buffer
  2237. * @v zlp Append a zero-length packet
  2238. * @ret rc Return status code
  2239. */
  2240. static int xhci_endpoint_stream ( struct usb_endpoint *ep,
  2241. struct io_buffer *iobuf, int zlp ) {
  2242. struct xhci_endpoint *endpoint = usb_endpoint_get_hostdata ( ep );
  2243. void *data = iobuf->data;
  2244. size_t len = iob_len ( iobuf );
  2245. unsigned int count = xhci_endpoint_count ( len, zlp );
  2246. union xhci_trb trbs[count];
  2247. union xhci_trb *trb = trbs;
  2248. struct xhci_trb_normal *normal;
  2249. unsigned int i;
  2250. size_t trb_len;
  2251. int rc;
  2252. /* Profile stream transfers */
  2253. profile_start ( &xhci_stream_profiler );
  2254. /* Construct normal TRBs */
  2255. memset ( &trbs, 0, sizeof ( trbs ) );
  2256. for ( i = 0 ; i < count ; i ++ ) {
  2257. /* Calculate TRB length */
  2258. trb_len = XHCI_MTU;
  2259. if ( trb_len > len )
  2260. trb_len = len;
  2261. /* Construct normal TRB */
  2262. normal = &trb->normal;
  2263. normal->data = cpu_to_le64 ( virt_to_phys ( data ) );
  2264. normal->len = cpu_to_le32 ( trb_len );
  2265. normal->type = XHCI_TRB_NORMAL;
  2266. normal->flags = XHCI_TRB_CH;
  2267. /* Move to next TRB */
  2268. data += trb_len;
  2269. len -= trb_len;
  2270. trb++;
  2271. }
  2272. /* Mark zero-length packet (if present) as a separate transfer */
  2273. if ( zlp && ( count > 1 ) )
  2274. trb[-2].normal.flags = 0;
  2275. /* Generate completion for final TRB */
  2276. trb[-1].normal.flags = XHCI_TRB_IOC;
  2277. /* Enqueue TRBs */
  2278. if ( ( rc = xhci_enqueue_multi ( &endpoint->ring, iobuf, trbs,
  2279. count ) ) != 0 )
  2280. return rc;
  2281. /* Ring the doorbell */
  2282. xhci_doorbell ( &endpoint->ring );
  2283. profile_stop ( &xhci_stream_profiler );
  2284. return 0;
  2285. }
  2286. /******************************************************************************
  2287. *
  2288. * Device operations
  2289. *
  2290. ******************************************************************************
  2291. */
  2292. /**
  2293. * Open device
  2294. *
  2295. * @v usb USB device
  2296. * @ret rc Return status code
  2297. */
  2298. static int xhci_device_open ( struct usb_device *usb ) {
  2299. struct xhci_device *xhci = usb_bus_get_hostdata ( usb->port->hub->bus );
  2300. struct usb_port *tt = usb_transaction_translator ( usb );
  2301. struct xhci_slot *slot;
  2302. struct xhci_slot *tt_slot;
  2303. size_t len;
  2304. int type;
  2305. int id;
  2306. int rc;
  2307. /* Determine applicable slot type */
  2308. type = xhci_port_slot_type ( xhci, usb->port->address );
  2309. if ( type < 0 ) {
  2310. rc = type;
  2311. DBGC ( xhci, "XHCI %s-%d has no slot type\n",
  2312. xhci->name, usb->port->address );
  2313. goto err_type;
  2314. }
  2315. /* Allocate a device slot number */
  2316. id = xhci_enable_slot ( xhci, type );
  2317. if ( id < 0 ) {
  2318. rc = id;
  2319. goto err_enable_slot;
  2320. }
  2321. assert ( ( id > 0 ) && ( ( unsigned int ) id <= xhci->slots ) );
  2322. assert ( xhci->slot[id] == NULL );
  2323. /* Allocate and initialise structure */
  2324. slot = zalloc ( sizeof ( *slot ) );
  2325. if ( ! slot ) {
  2326. rc = -ENOMEM;
  2327. goto err_alloc;
  2328. }
  2329. usb_set_hostdata ( usb, slot );
  2330. xhci->slot[id] = slot;
  2331. slot->xhci = xhci;
  2332. slot->usb = usb;
  2333. slot->id = id;
  2334. if ( tt ) {
  2335. tt_slot = usb_get_hostdata ( tt->hub->usb );
  2336. slot->tt_id = tt_slot->id;
  2337. slot->tt_port = tt->address;
  2338. }
  2339. /* Allocate a device context */
  2340. len = xhci_device_context_offset ( xhci, XHCI_CTX_END );
  2341. slot->context = malloc_dma ( len, xhci_align ( len ) );
  2342. if ( ! slot->context ) {
  2343. rc = -ENOMEM;
  2344. goto err_alloc_context;
  2345. }
  2346. memset ( slot->context, 0, len );
  2347. /* Set device context base address */
  2348. assert ( xhci->dcbaa[id] == 0 );
  2349. xhci->dcbaa[id] = cpu_to_le64 ( virt_to_phys ( slot->context ) );
  2350. DBGC2 ( xhci, "XHCI %s slot %d device context [%08lx,%08lx) for %s\n",
  2351. xhci->name, slot->id, virt_to_phys ( slot->context ),
  2352. ( virt_to_phys ( slot->context ) + len ), usb->name );
  2353. return 0;
  2354. xhci->dcbaa[id] = 0;
  2355. free_dma ( slot->context, len );
  2356. err_alloc_context:
  2357. xhci->slot[id] = NULL;
  2358. free ( slot );
  2359. err_alloc:
  2360. xhci_disable_slot ( xhci, id );
  2361. err_enable_slot:
  2362. err_type:
  2363. return rc;
  2364. }
  2365. /**
  2366. * Close device
  2367. *
  2368. * @v usb USB device
  2369. */
  2370. static void xhci_device_close ( struct usb_device *usb ) {
  2371. struct xhci_slot *slot = usb_get_hostdata ( usb );
  2372. struct xhci_device *xhci = slot->xhci;
  2373. size_t len = xhci_device_context_offset ( xhci, XHCI_CTX_END );
  2374. unsigned int id = slot->id;
  2375. int rc;
  2376. /* Disable slot */
  2377. if ( ( rc = xhci_disable_slot ( xhci, id ) ) != 0 ) {
  2378. /* Slot is still enabled. Leak the slot context,
  2379. * since the controller may still write to this
  2380. * memory, and leave the DCBAA entry intact.
  2381. *
  2382. * If the controller later reports that this same slot
  2383. * has been re-enabled, then some assertions will be
  2384. * triggered.
  2385. */
  2386. DBGC ( xhci, "XHCI %s slot %d leaking context memory\n",
  2387. xhci->name, slot->id );
  2388. slot->context = NULL;
  2389. }
  2390. /* Free slot */
  2391. if ( slot->context ) {
  2392. free_dma ( slot->context, len );
  2393. xhci->dcbaa[id] = 0;
  2394. }
  2395. xhci->slot[id] = NULL;
  2396. free ( slot );
  2397. }
  2398. /**
  2399. * Assign device address
  2400. *
  2401. * @v usb USB device
  2402. * @ret rc Return status code
  2403. */
  2404. static int xhci_device_address ( struct usb_device *usb ) {
  2405. struct xhci_slot *slot = usb_get_hostdata ( usb );
  2406. struct xhci_device *xhci = slot->xhci;
  2407. struct usb_port *root_port;
  2408. int psiv;
  2409. int rc;
  2410. /* Calculate route string */
  2411. slot->route = usb_route_string ( usb );
  2412. /* Calculate root hub port number */
  2413. root_port = usb_root_hub_port ( usb );
  2414. slot->port = root_port->address;
  2415. /* Calculate protocol speed ID */
  2416. psiv = xhci_port_psiv ( xhci, slot->port, usb->speed );
  2417. if ( psiv < 0 ) {
  2418. rc = psiv;
  2419. return rc;
  2420. }
  2421. slot->psiv = psiv;
  2422. /* Address device */
  2423. if ( ( rc = xhci_address_device ( xhci, slot ) ) != 0 )
  2424. return rc;
  2425. return 0;
  2426. }
  2427. /******************************************************************************
  2428. *
  2429. * Bus operations
  2430. *
  2431. ******************************************************************************
  2432. */
  2433. /**
  2434. * Open USB bus
  2435. *
  2436. * @v bus USB bus
  2437. * @ret rc Return status code
  2438. */
  2439. static int xhci_bus_open ( struct usb_bus *bus ) {
  2440. struct xhci_device *xhci = usb_bus_get_hostdata ( bus );
  2441. int rc;
  2442. /* Allocate device slot array */
  2443. xhci->slot = zalloc ( ( xhci->slots + 1 ) * sizeof ( xhci->slot[0] ) );
  2444. if ( ! xhci->slot ) {
  2445. rc = -ENOMEM;
  2446. goto err_slot_alloc;
  2447. }
  2448. /* Allocate device context base address array */
  2449. if ( ( rc = xhci_dcbaa_alloc ( xhci ) ) != 0 )
  2450. goto err_dcbaa_alloc;
  2451. /* Allocate scratchpad buffers */
  2452. if ( ( rc = xhci_scratchpad_alloc ( xhci ) ) != 0 )
  2453. goto err_scratchpad_alloc;
  2454. /* Allocate command ring */
  2455. if ( ( rc = xhci_command_alloc ( xhci ) ) != 0 )
  2456. goto err_command_alloc;
  2457. /* Allocate event ring */
  2458. if ( ( rc = xhci_event_alloc ( xhci ) ) != 0 )
  2459. goto err_event_alloc;
  2460. /* Start controller */
  2461. xhci_run ( xhci );
  2462. return 0;
  2463. xhci_stop ( xhci );
  2464. xhci_event_free ( xhci );
  2465. err_event_alloc:
  2466. xhci_command_free ( xhci );
  2467. err_command_alloc:
  2468. xhci_scratchpad_free ( xhci );
  2469. err_scratchpad_alloc:
  2470. xhci_dcbaa_free ( xhci );
  2471. err_dcbaa_alloc:
  2472. free ( xhci->slot );
  2473. err_slot_alloc:
  2474. return rc;
  2475. }
  2476. /**
  2477. * Close USB bus
  2478. *
  2479. * @v bus USB bus
  2480. */
  2481. static void xhci_bus_close ( struct usb_bus *bus ) {
  2482. struct xhci_device *xhci = usb_bus_get_hostdata ( bus );
  2483. unsigned int i;
  2484. /* Sanity checks */
  2485. assert ( xhci->slot != NULL );
  2486. for ( i = 0 ; i <= xhci->slots ; i++ )
  2487. assert ( xhci->slot[i] == NULL );
  2488. xhci_stop ( xhci );
  2489. xhci_event_free ( xhci );
  2490. xhci_command_free ( xhci );
  2491. xhci_scratchpad_free ( xhci );
  2492. xhci_dcbaa_free ( xhci );
  2493. free ( xhci->slot );
  2494. }
  2495. /**
  2496. * Poll USB bus
  2497. *
  2498. * @v bus USB bus
  2499. */
  2500. static void xhci_bus_poll ( struct usb_bus *bus ) {
  2501. struct xhci_device *xhci = usb_bus_get_hostdata ( bus );
  2502. /* Poll event ring */
  2503. xhci_event_poll ( xhci );
  2504. }
  2505. /******************************************************************************
  2506. *
  2507. * Hub operations
  2508. *
  2509. ******************************************************************************
  2510. */
  2511. /**
  2512. * Open hub
  2513. *
  2514. * @v hub USB hub
  2515. * @ret rc Return status code
  2516. */
  2517. static int xhci_hub_open ( struct usb_hub *hub ) {
  2518. struct xhci_slot *slot;
  2519. /* Do nothing if this is the root hub */
  2520. if ( ! hub->usb )
  2521. return 0;
  2522. /* Get device slot */
  2523. slot = usb_get_hostdata ( hub->usb );
  2524. /* Update device slot hub parameters. We don't inform the
  2525. * hardware of this information until the hub's interrupt
  2526. * endpoint is opened, since the only mechanism for so doing
  2527. * provided by the xHCI specification is a Configure Endpoint
  2528. * command, and we can't issue that command until we have a
  2529. * non-EP0 endpoint to configure.
  2530. */
  2531. slot->ports = hub->ports;
  2532. return 0;
  2533. }
  2534. /**
  2535. * Close hub
  2536. *
  2537. * @v hub USB hub
  2538. */
  2539. static void xhci_hub_close ( struct usb_hub *hub __unused ) {
  2540. /* Nothing to do */
  2541. }
  2542. /******************************************************************************
  2543. *
  2544. * Root hub operations
  2545. *
  2546. ******************************************************************************
  2547. */
  2548. /**
  2549. * Open root hub
  2550. *
  2551. * @v hub USB hub
  2552. * @ret rc Return status code
  2553. */
  2554. static int xhci_root_open ( struct usb_hub *hub ) {
  2555. struct usb_bus *bus = hub->bus;
  2556. struct xhci_device *xhci = usb_bus_get_hostdata ( bus );
  2557. struct usb_port *port;
  2558. uint32_t portsc;
  2559. unsigned int i;
  2560. /* Enable power to all ports */
  2561. for ( i = 1 ; i <= xhci->ports ; i++ ) {
  2562. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( i ) );
  2563. portsc &= XHCI_PORTSC_PRESERVE;
  2564. portsc |= XHCI_PORTSC_PP;
  2565. writel ( portsc, xhci->op + XHCI_OP_PORTSC ( i ) );
  2566. }
  2567. /* xHCI spec requires us to potentially wait 20ms after
  2568. * enabling power to a port.
  2569. */
  2570. mdelay ( XHCI_PORT_POWER_DELAY_MS );
  2571. /* USB3 ports may power up as Disabled */
  2572. for ( i = 1 ; i <= xhci->ports ; i++ ) {
  2573. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( i ) );
  2574. port = usb_port ( hub, i );
  2575. if ( ( port->protocol >= USB_PROTO_3_0 ) &&
  2576. ( ( portsc & XHCI_PORTSC_PLS_MASK ) ==
  2577. XHCI_PORTSC_PLS_DISABLED ) ) {
  2578. /* Force link state to RxDetect */
  2579. portsc &= XHCI_PORTSC_PRESERVE;
  2580. portsc |= ( XHCI_PORTSC_PLS_RXDETECT | XHCI_PORTSC_LWS);
  2581. writel ( portsc, xhci->op + XHCI_OP_PORTSC ( i ) );
  2582. }
  2583. }
  2584. /* Some xHCI cards seem to require an additional delay after
  2585. * setting the link state to RxDetect.
  2586. */
  2587. mdelay ( XHCI_LINK_STATE_DELAY_MS );
  2588. /* Record hub driver private data */
  2589. usb_hub_set_drvdata ( hub, xhci );
  2590. return 0;
  2591. }
  2592. /**
  2593. * Close root hub
  2594. *
  2595. * @v hub USB hub
  2596. */
  2597. static void xhci_root_close ( struct usb_hub *hub ) {
  2598. /* Clear hub driver private data */
  2599. usb_hub_set_drvdata ( hub, NULL );
  2600. }
  2601. /**
  2602. * Enable port
  2603. *
  2604. * @v hub USB hub
  2605. * @v port USB port
  2606. * @ret rc Return status code
  2607. */
  2608. static int xhci_root_enable ( struct usb_hub *hub, struct usb_port *port ) {
  2609. struct xhci_device *xhci = usb_hub_get_drvdata ( hub );
  2610. uint32_t portsc;
  2611. unsigned int i;
  2612. /* Reset port */
  2613. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2614. portsc &= XHCI_PORTSC_PRESERVE;
  2615. portsc |= XHCI_PORTSC_PR;
  2616. writel ( portsc, xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2617. /* Wait for port to become enabled */
  2618. for ( i = 0 ; i < XHCI_PORT_RESET_MAX_WAIT_MS ; i++ ) {
  2619. /* Check port status */
  2620. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2621. if ( portsc & XHCI_PORTSC_PED )
  2622. return 0;
  2623. /* Delay */
  2624. mdelay ( 1 );
  2625. }
  2626. DBGC ( xhci, "XHCI %s-%d timed out waiting for port to enable\n",
  2627. xhci->name, port->address );
  2628. return -ETIMEDOUT;
  2629. }
  2630. /**
  2631. * Disable port
  2632. *
  2633. * @v hub USB hub
  2634. * @v port USB port
  2635. * @ret rc Return status code
  2636. */
  2637. static int xhci_root_disable ( struct usb_hub *hub, struct usb_port *port ) {
  2638. struct xhci_device *xhci = usb_hub_get_drvdata ( hub );
  2639. uint32_t portsc;
  2640. /* Disable port */
  2641. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2642. portsc &= XHCI_PORTSC_PRESERVE;
  2643. portsc |= XHCI_PORTSC_PED;
  2644. writel ( portsc, xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2645. return 0;
  2646. }
  2647. /**
  2648. * Update root hub port speed
  2649. *
  2650. * @v hub USB hub
  2651. * @v port USB port
  2652. * @ret rc Return status code
  2653. */
  2654. static int xhci_root_speed ( struct usb_hub *hub, struct usb_port *port ) {
  2655. struct xhci_device *xhci = usb_hub_get_drvdata ( hub );
  2656. uint32_t portsc;
  2657. unsigned int psiv;
  2658. int ccs;
  2659. int ped;
  2660. int csc;
  2661. int speed;
  2662. int rc;
  2663. /* Read port status */
  2664. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2665. DBGC2 ( xhci, "XHCI %s-%d status is %08x\n",
  2666. xhci->name, port->address, portsc );
  2667. ccs = ( portsc & XHCI_PORTSC_CCS );
  2668. ped = ( portsc & XHCI_PORTSC_PED );
  2669. csc = ( portsc & XHCI_PORTSC_CSC );
  2670. psiv = XHCI_PORTSC_PSIV ( portsc );
  2671. /* Record disconnections and clear changes */
  2672. port->disconnected |= csc;
  2673. portsc &= ( XHCI_PORTSC_PRESERVE | XHCI_PORTSC_CHANGE );
  2674. writel ( portsc, xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2675. /* Port speed is not valid unless port is connected */
  2676. if ( ! ccs ) {
  2677. port->speed = USB_SPEED_NONE;
  2678. return 0;
  2679. }
  2680. /* For USB2 ports, the PSIV field is not valid until the port
  2681. * completes reset and becomes enabled.
  2682. */
  2683. if ( ( port->protocol < USB_PROTO_3_0 ) && ! ped ) {
  2684. port->speed = USB_SPEED_FULL;
  2685. return 0;
  2686. }
  2687. /* Get port speed and map to generic USB speed */
  2688. speed = xhci_port_speed ( xhci, port->address, psiv );
  2689. if ( speed < 0 ) {
  2690. rc = speed;
  2691. return rc;
  2692. }
  2693. port->speed = speed;
  2694. return 0;
  2695. }
  2696. /**
  2697. * Clear transaction translator buffer
  2698. *
  2699. * @v hub USB hub
  2700. * @v port USB port
  2701. * @v ep USB endpoint
  2702. * @ret rc Return status code
  2703. */
  2704. static int xhci_root_clear_tt ( struct usb_hub *hub, struct usb_port *port,
  2705. struct usb_endpoint *ep ) {
  2706. struct xhci_device *xhci = usb_hub_get_drvdata ( hub );
  2707. /* Should never be called; this is a root hub */
  2708. DBGC ( xhci, "XHCI %s-%d nonsensical CLEAR_TT for %s %s\n", xhci->name,
  2709. port->address, ep->usb->name, usb_endpoint_name ( ep ) );
  2710. return -ENOTSUP;
  2711. }
  2712. /******************************************************************************
  2713. *
  2714. * PCI interface
  2715. *
  2716. ******************************************************************************
  2717. */
  2718. /** USB host controller operations */
  2719. static struct usb_host_operations xhci_operations = {
  2720. .endpoint = {
  2721. .open = xhci_endpoint_open,
  2722. .close = xhci_endpoint_close,
  2723. .reset = xhci_endpoint_reset,
  2724. .mtu = xhci_endpoint_mtu,
  2725. .message = xhci_endpoint_message,
  2726. .stream = xhci_endpoint_stream,
  2727. },
  2728. .device = {
  2729. .open = xhci_device_open,
  2730. .close = xhci_device_close,
  2731. .address = xhci_device_address,
  2732. },
  2733. .bus = {
  2734. .open = xhci_bus_open,
  2735. .close = xhci_bus_close,
  2736. .poll = xhci_bus_poll,
  2737. },
  2738. .hub = {
  2739. .open = xhci_hub_open,
  2740. .close = xhci_hub_close,
  2741. },
  2742. .root = {
  2743. .open = xhci_root_open,
  2744. .close = xhci_root_close,
  2745. .enable = xhci_root_enable,
  2746. .disable = xhci_root_disable,
  2747. .speed = xhci_root_speed,
  2748. .clear_tt = xhci_root_clear_tt,
  2749. },
  2750. };
  2751. /**
  2752. * Fix Intel PCH-specific quirks
  2753. *
  2754. * @v xhci xHCI device
  2755. * @v pci PCI device
  2756. */
  2757. static void xhci_pch_fix ( struct xhci_device *xhci, struct pci_device *pci ) {
  2758. struct xhci_pch *pch = &xhci->pch;
  2759. uint32_t xusb2pr;
  2760. uint32_t xusb2prm;
  2761. uint32_t usb3pssen;
  2762. uint32_t usb3prm;
  2763. /* Enable SuperSpeed capability. Do this before rerouting
  2764. * USB2 ports, so that USB3 devices connect at SuperSpeed.
  2765. */
  2766. pci_read_config_dword ( pci, XHCI_PCH_USB3PSSEN, &usb3pssen );
  2767. pci_read_config_dword ( pci, XHCI_PCH_USB3PRM, &usb3prm );
  2768. if ( usb3prm & ~usb3pssen ) {
  2769. DBGC ( xhci, "XHCI %s enabling SuperSpeed on ports %08x\n",
  2770. xhci->name, ( usb3prm & ~usb3pssen ) );
  2771. }
  2772. pch->usb3pssen = usb3pssen;
  2773. usb3pssen |= usb3prm;
  2774. pci_write_config_dword ( pci, XHCI_PCH_USB3PSSEN, usb3pssen );
  2775. /* Route USB2 ports from EHCI to xHCI */
  2776. pci_read_config_dword ( pci, XHCI_PCH_XUSB2PR, &xusb2pr );
  2777. pci_read_config_dword ( pci, XHCI_PCH_XUSB2PRM, &xusb2prm );
  2778. if ( xusb2prm & ~xusb2pr ) {
  2779. DBGC ( xhci, "XHCI %s routing ports %08x from EHCI to xHCI\n",
  2780. xhci->name, ( xusb2prm & ~xusb2pr ) );
  2781. }
  2782. pch->xusb2pr = xusb2pr;
  2783. xusb2pr |= xusb2prm;
  2784. pci_write_config_dword ( pci, XHCI_PCH_XUSB2PR, xusb2pr );
  2785. }
  2786. /**
  2787. * Undo Intel PCH-specific quirk fixes
  2788. *
  2789. * @v xhci xHCI device
  2790. * @v pci PCI device
  2791. */
  2792. static void xhci_pch_undo ( struct xhci_device *xhci, struct pci_device *pci ) {
  2793. struct xhci_pch *pch = &xhci->pch;
  2794. /* Restore USB2 port routing to original state */
  2795. pci_write_config_dword ( pci, XHCI_PCH_XUSB2PR, pch->xusb2pr );
  2796. /* Restore SuperSpeed capability to original state */
  2797. pci_write_config_dword ( pci, XHCI_PCH_USB3PSSEN, pch->usb3pssen );
  2798. }
  2799. /**
  2800. * Probe PCI device
  2801. *
  2802. * @v pci PCI device
  2803. * @ret rc Return status code
  2804. */
  2805. static int xhci_probe ( struct pci_device *pci ) {
  2806. struct xhci_device *xhci;
  2807. struct usb_port *port;
  2808. unsigned long bar_start;
  2809. size_t bar_size;
  2810. unsigned int i;
  2811. int rc;
  2812. /* Allocate and initialise structure */
  2813. xhci = zalloc ( sizeof ( *xhci ) );
  2814. if ( ! xhci ) {
  2815. rc = -ENOMEM;
  2816. goto err_alloc;
  2817. }
  2818. xhci->name = pci->dev.name;
  2819. xhci->quirks = pci->id->driver_data;
  2820. /* Fix up PCI device */
  2821. adjust_pci_device ( pci );
  2822. /* Map registers */
  2823. bar_start = pci_bar_start ( pci, XHCI_BAR );
  2824. bar_size = pci_bar_size ( pci, XHCI_BAR );
  2825. xhci->regs = ioremap ( bar_start, bar_size );
  2826. if ( ! xhci->regs ) {
  2827. rc = -ENODEV;
  2828. goto err_ioremap;
  2829. }
  2830. /* Initialise xHCI device */
  2831. xhci_init ( xhci, xhci->regs );
  2832. /* Initialise USB legacy support and claim ownership */
  2833. xhci_legacy_init ( xhci );
  2834. xhci_legacy_claim ( xhci );
  2835. /* Fix Intel PCH-specific quirks, if applicable */
  2836. if ( xhci->quirks & XHCI_PCH )
  2837. xhci_pch_fix ( xhci, pci );
  2838. /* Reset device */
  2839. if ( ( rc = xhci_reset ( xhci ) ) != 0 )
  2840. goto err_reset;
  2841. /* Allocate USB bus */
  2842. xhci->bus = alloc_usb_bus ( &pci->dev, xhci->ports, XHCI_MTU,
  2843. &xhci_operations );
  2844. if ( ! xhci->bus ) {
  2845. rc = -ENOMEM;
  2846. goto err_alloc_bus;
  2847. }
  2848. usb_bus_set_hostdata ( xhci->bus, xhci );
  2849. usb_hub_set_drvdata ( xhci->bus->hub, xhci );
  2850. /* Set port protocols */
  2851. for ( i = 1 ; i <= xhci->ports ; i++ ) {
  2852. port = usb_port ( xhci->bus->hub, i );
  2853. port->protocol = xhci_port_protocol ( xhci, i );
  2854. }
  2855. /* Register USB bus */
  2856. if ( ( rc = register_usb_bus ( xhci->bus ) ) != 0 )
  2857. goto err_register;
  2858. pci_set_drvdata ( pci, xhci );
  2859. return 0;
  2860. unregister_usb_bus ( xhci->bus );
  2861. err_register:
  2862. free_usb_bus ( xhci->bus );
  2863. err_alloc_bus:
  2864. xhci_reset ( xhci );
  2865. err_reset:
  2866. if ( xhci->quirks & XHCI_PCH )
  2867. xhci_pch_undo ( xhci, pci );
  2868. xhci_legacy_release ( xhci );
  2869. iounmap ( xhci->regs );
  2870. err_ioremap:
  2871. free ( xhci );
  2872. err_alloc:
  2873. return rc;
  2874. }
  2875. /**
  2876. * Remove PCI device
  2877. *
  2878. * @v pci PCI device
  2879. */
  2880. static void xhci_remove ( struct pci_device *pci ) {
  2881. struct xhci_device *xhci = pci_get_drvdata ( pci );
  2882. struct usb_bus *bus = xhci->bus;
  2883. unregister_usb_bus ( bus );
  2884. free_usb_bus ( bus );
  2885. xhci_reset ( xhci );
  2886. if ( xhci->quirks & XHCI_PCH )
  2887. xhci_pch_undo ( xhci, pci );
  2888. xhci_legacy_release ( xhci );
  2889. iounmap ( xhci->regs );
  2890. free ( xhci );
  2891. }
  2892. /** XHCI PCI device IDs */
  2893. static struct pci_device_id xhci_ids[] = {
  2894. PCI_ROM ( 0x8086, 0x9d2f, "xhci-skylake", "xHCI (Skylake)", ( XHCI_PCH | XHCI_BAD_PSIV ) ),
  2895. PCI_ROM ( 0x8086, 0xffff, "xhci-pch", "xHCI (Intel PCH)", XHCI_PCH ),
  2896. PCI_ROM ( 0xffff, 0xffff, "xhci", "xHCI", 0 ),
  2897. };
  2898. /** XHCI PCI driver */
  2899. struct pci_driver xhci_driver __pci_driver = {
  2900. .ids = xhci_ids,
  2901. .id_count = ( sizeof ( xhci_ids ) / sizeof ( xhci_ids[0] ) ),
  2902. .class = PCI_CLASS_ID ( PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB,
  2903. PCI_CLASS_SERIAL_USB_XHCI ),
  2904. .probe = xhci_probe,
  2905. .remove = xhci_remove,
  2906. };
  2907. /**
  2908. * Prepare for exit
  2909. *
  2910. * @v booting System is shutting down for OS boot
  2911. */
  2912. static void xhci_shutdown ( int booting ) {
  2913. /* If we are shutting down to boot an OS, then prevent the
  2914. * release of ownership back to BIOS.
  2915. */
  2916. xhci_legacy_prevent_release = booting;
  2917. }
  2918. /** Startup/shutdown function */
  2919. struct startup_fn xhci_startup __startup_fn ( STARTUP_LATE ) = {
  2920. .name = "xhci",
  2921. .shutdown = xhci_shutdown,
  2922. };