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xhci.c 81KB

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  1. /*
  2. * Copyright (C) 2014 Michael Brown <mbrown@fensystems.co.uk>.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation; either version 2 of the
  7. * License, or (at your option) any later version.
  8. *
  9. * This program is distributed in the hope that it will be useful, but
  10. * WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  12. * General Public License for more details.
  13. *
  14. * You should have received a copy of the GNU General Public License
  15. * along with this program; if not, write to the Free Software
  16. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  17. * 02110-1301, USA.
  18. *
  19. * You can also choose to distribute this program under the terms of
  20. * the Unmodified Binary Distribution Licence (as given in the file
  21. * COPYING.UBDL), provided that you have satisfied its requirements.
  22. */
  23. FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
  24. #include <stdlib.h>
  25. #include <stdio.h>
  26. #include <unistd.h>
  27. #include <string.h>
  28. #include <strings.h>
  29. #include <errno.h>
  30. #include <byteswap.h>
  31. #include <ipxe/malloc.h>
  32. #include <ipxe/umalloc.h>
  33. #include <ipxe/pci.h>
  34. #include <ipxe/usb.h>
  35. #include <ipxe/profile.h>
  36. #include "xhci.h"
  37. /** @file
  38. *
  39. * USB eXtensible Host Controller Interface (xHCI) driver
  40. *
  41. */
  42. /** Message transfer profiler */
  43. static struct profiler xhci_message_profiler __profiler =
  44. { .name = "xhci.message" };
  45. /** Stream transfer profiler */
  46. static struct profiler xhci_stream_profiler __profiler =
  47. { .name = "xhci.stream" };
  48. /** Event ring profiler */
  49. static struct profiler xhci_event_profiler __profiler =
  50. { .name = "xhci.event" };
  51. /** Transfer event profiler */
  52. static struct profiler xhci_transfer_profiler __profiler =
  53. { .name = "xhci.transfer" };
  54. /* Disambiguate the various error causes */
  55. #define EIO_DATA \
  56. __einfo_error ( EINFO_EIO_DATA )
  57. #define EINFO_EIO_DATA \
  58. __einfo_uniqify ( EINFO_EIO, ( 2 - 0 ), \
  59. "Data buffer error" )
  60. #define EIO_BABBLE \
  61. __einfo_error ( EINFO_EIO_BABBLE )
  62. #define EINFO_EIO_BABBLE \
  63. __einfo_uniqify ( EINFO_EIO, ( 3 - 0 ), \
  64. "Babble detected" )
  65. #define EIO_USB \
  66. __einfo_error ( EINFO_EIO_USB )
  67. #define EINFO_EIO_USB \
  68. __einfo_uniqify ( EINFO_EIO, ( 4 - 0 ), \
  69. "USB transaction error" )
  70. #define EIO_TRB \
  71. __einfo_error ( EINFO_EIO_TRB )
  72. #define EINFO_EIO_TRB \
  73. __einfo_uniqify ( EINFO_EIO, ( 5 - 0 ), \
  74. "TRB error" )
  75. #define EIO_STALL \
  76. __einfo_error ( EINFO_EIO_STALL )
  77. #define EINFO_EIO_STALL \
  78. __einfo_uniqify ( EINFO_EIO, ( 6 - 0 ), \
  79. "Stall error" )
  80. #define EIO_RESOURCE \
  81. __einfo_error ( EINFO_EIO_RESOURCE )
  82. #define EINFO_EIO_RESOURCE \
  83. __einfo_uniqify ( EINFO_EIO, ( 7 - 0 ), \
  84. "Resource error" )
  85. #define EIO_BANDWIDTH \
  86. __einfo_error ( EINFO_EIO_BANDWIDTH )
  87. #define EINFO_EIO_BANDWIDTH \
  88. __einfo_uniqify ( EINFO_EIO, ( 8 - 0 ), \
  89. "Bandwidth error" )
  90. #define EIO_NO_SLOTS \
  91. __einfo_error ( EINFO_EIO_NO_SLOTS )
  92. #define EINFO_EIO_NO_SLOTS \
  93. __einfo_uniqify ( EINFO_EIO, ( 9 - 0 ), \
  94. "No slots available" )
  95. #define EIO_STREAM_TYPE \
  96. __einfo_error ( EINFO_EIO_STREAM_TYPE )
  97. #define EINFO_EIO_STREAM_TYPE \
  98. __einfo_uniqify ( EINFO_EIO, ( 10 - 0 ), \
  99. "Invalid stream type" )
  100. #define EIO_SLOT \
  101. __einfo_error ( EINFO_EIO_SLOT )
  102. #define EINFO_EIO_SLOT \
  103. __einfo_uniqify ( EINFO_EIO, ( 11 - 0 ), \
  104. "Slot not enabled" )
  105. #define EIO_ENDPOINT \
  106. __einfo_error ( EINFO_EIO_ENDPOINT )
  107. #define EINFO_EIO_ENDPOINT \
  108. __einfo_uniqify ( EINFO_EIO, ( 12 - 0 ), \
  109. "Endpoint not enabled" )
  110. #define EIO_SHORT \
  111. __einfo_error ( EINFO_EIO_SHORT )
  112. #define EINFO_EIO_SHORT \
  113. __einfo_uniqify ( EINFO_EIO, ( 13 - 0 ), \
  114. "Short packet" )
  115. #define EIO_UNDERRUN \
  116. __einfo_error ( EINFO_EIO_UNDERRUN )
  117. #define EINFO_EIO_UNDERRUN \
  118. __einfo_uniqify ( EINFO_EIO, ( 14 - 0 ), \
  119. "Ring underrun" )
  120. #define EIO_OVERRUN \
  121. __einfo_error ( EINFO_EIO_OVERRUN )
  122. #define EINFO_EIO_OVERRUN \
  123. __einfo_uniqify ( EINFO_EIO, ( 15 - 0 ), \
  124. "Ring overrun" )
  125. #define EIO_VF_RING_FULL \
  126. __einfo_error ( EINFO_EIO_VF_RING_FULL )
  127. #define EINFO_EIO_VF_RING_FULL \
  128. __einfo_uniqify ( EINFO_EIO, ( 16 - 0 ), \
  129. "Virtual function event ring full" )
  130. #define EIO_PARAMETER \
  131. __einfo_error ( EINFO_EIO_PARAMETER )
  132. #define EINFO_EIO_PARAMETER \
  133. __einfo_uniqify ( EINFO_EIO, ( 17 - 0 ), \
  134. "Parameter error" )
  135. #define EIO_BANDWIDTH_OVERRUN \
  136. __einfo_error ( EINFO_EIO_BANDWIDTH_OVERRUN )
  137. #define EINFO_EIO_BANDWIDTH_OVERRUN \
  138. __einfo_uniqify ( EINFO_EIO, ( 18 - 0 ), \
  139. "Bandwidth overrun" )
  140. #define EIO_CONTEXT \
  141. __einfo_error ( EINFO_EIO_CONTEXT )
  142. #define EINFO_EIO_CONTEXT \
  143. __einfo_uniqify ( EINFO_EIO, ( 19 - 0 ), \
  144. "Context state error" )
  145. #define EIO_NO_PING \
  146. __einfo_error ( EINFO_EIO_NO_PING )
  147. #define EINFO_EIO_NO_PING \
  148. __einfo_uniqify ( EINFO_EIO, ( 20 - 0 ), \
  149. "No ping response" )
  150. #define EIO_RING_FULL \
  151. __einfo_error ( EINFO_EIO_RING_FULL )
  152. #define EINFO_EIO_RING_FULL \
  153. __einfo_uniqify ( EINFO_EIO, ( 21 - 0 ), \
  154. "Event ring full" )
  155. #define EIO_INCOMPATIBLE \
  156. __einfo_error ( EINFO_EIO_INCOMPATIBLE )
  157. #define EINFO_EIO_INCOMPATIBLE \
  158. __einfo_uniqify ( EINFO_EIO, ( 22 - 0 ), \
  159. "Incompatible device" )
  160. #define EIO_MISSED \
  161. __einfo_error ( EINFO_EIO_MISSED )
  162. #define EINFO_EIO_MISSED \
  163. __einfo_uniqify ( EINFO_EIO, ( 23 - 0 ), \
  164. "Missed service error" )
  165. #define EIO_CMD_STOPPED \
  166. __einfo_error ( EINFO_EIO_CMD_STOPPED )
  167. #define EINFO_EIO_CMD_STOPPED \
  168. __einfo_uniqify ( EINFO_EIO, ( 24 - 0 ), \
  169. "Command ring stopped" )
  170. #define EIO_CMD_ABORTED \
  171. __einfo_error ( EINFO_EIO_CMD_ABORTED )
  172. #define EINFO_EIO_CMD_ABORTED \
  173. __einfo_uniqify ( EINFO_EIO, ( 25 - 0 ), \
  174. "Command aborted" )
  175. #define EIO_STOP \
  176. __einfo_error ( EINFO_EIO_STOP )
  177. #define EINFO_EIO_STOP \
  178. __einfo_uniqify ( EINFO_EIO, ( 26 - 0 ), \
  179. "Stopped" )
  180. #define EIO_STOP_LEN \
  181. __einfo_error ( EINFO_EIO_STOP_LEN )
  182. #define EINFO_EIO_STOP_LEN \
  183. __einfo_uniqify ( EINFO_EIO, ( 27 - 0 ), \
  184. "Stopped - length invalid" )
  185. #define EIO_STOP_SHORT \
  186. __einfo_error ( EINFO_EIO_STOP_SHORT )
  187. #define EINFO_EIO_STOP_SHORT \
  188. __einfo_uniqify ( EINFO_EIO, ( 28 - 0 ), \
  189. "Stopped - short packet" )
  190. #define EIO_LATENCY \
  191. __einfo_error ( EINFO_EIO_LATENCY )
  192. #define EINFO_EIO_LATENCY \
  193. __einfo_uniqify ( EINFO_EIO, ( 29 - 0 ), \
  194. "Maximum exit latency too large" )
  195. #define EIO_ISOCH \
  196. __einfo_error ( EINFO_EIO_ISOCH )
  197. #define EINFO_EIO_ISOCH \
  198. __einfo_uniqify ( EINFO_EIO, ( 31 - 0 ), \
  199. "Isochronous buffer overrun" )
  200. #define EPROTO_LOST \
  201. __einfo_error ( EINFO_EPROTO_LOST )
  202. #define EINFO_EPROTO_LOST \
  203. __einfo_uniqify ( EINFO_EPROTO, ( 32 - 32 ), \
  204. "Event lost" )
  205. #define EPROTO_UNDEFINED \
  206. __einfo_error ( EINFO_EPROTO_UNDEFINED )
  207. #define EINFO_EPROTO_UNDEFINED \
  208. __einfo_uniqify ( EINFO_EPROTO, ( 33 - 32 ), \
  209. "Undefined error" )
  210. #define EPROTO_STREAM_ID \
  211. __einfo_error ( EINFO_EPROTO_STREAM_ID )
  212. #define EINFO_EPROTO_STREAM_ID \
  213. __einfo_uniqify ( EINFO_EPROTO, ( 34 - 32 ), \
  214. "Invalid stream ID" )
  215. #define EPROTO_SECONDARY \
  216. __einfo_error ( EINFO_EPROTO_SECONDARY )
  217. #define EINFO_EPROTO_SECONDARY \
  218. __einfo_uniqify ( EINFO_EPROTO, ( 35 - 32 ), \
  219. "Secondary bandwidth error" )
  220. #define EPROTO_SPLIT \
  221. __einfo_error ( EINFO_EPROTO_SPLIT )
  222. #define EINFO_EPROTO_SPLIT \
  223. __einfo_uniqify ( EINFO_EPROTO, ( 36 - 32 ), \
  224. "Split transaction error" )
  225. #define ECODE(code) \
  226. ( ( (code) < 32 ) ? \
  227. EUNIQ ( EINFO_EIO, ( (code) & 31 ), EIO_DATA, EIO_BABBLE, \
  228. EIO_USB, EIO_TRB, EIO_STALL, EIO_RESOURCE, \
  229. EIO_BANDWIDTH, EIO_NO_SLOTS, EIO_STREAM_TYPE, \
  230. EIO_SLOT, EIO_ENDPOINT, EIO_SHORT, EIO_UNDERRUN, \
  231. EIO_OVERRUN, EIO_VF_RING_FULL, EIO_PARAMETER, \
  232. EIO_BANDWIDTH_OVERRUN, EIO_CONTEXT, EIO_NO_PING, \
  233. EIO_RING_FULL, EIO_INCOMPATIBLE, EIO_MISSED, \
  234. EIO_CMD_STOPPED, EIO_CMD_ABORTED, EIO_STOP, \
  235. EIO_STOP_LEN, EIO_STOP_SHORT, EIO_LATENCY, \
  236. EIO_ISOCH ) : \
  237. ( (code) < 64 ) ? \
  238. EUNIQ ( EINFO_EPROTO, ( (code) & 31 ), EPROTO_LOST, \
  239. EPROTO_UNDEFINED, EPROTO_STREAM_ID, \
  240. EPROTO_SECONDARY, EPROTO_SPLIT ) : \
  241. EFAULT )
  242. /******************************************************************************
  243. *
  244. * Register access
  245. *
  246. ******************************************************************************
  247. */
  248. /**
  249. * Initialise device
  250. *
  251. * @v xhci xHCI device
  252. * @v regs MMIO registers
  253. */
  254. static void xhci_init ( struct xhci_device *xhci, void *regs ) {
  255. uint32_t hcsparams1;
  256. uint32_t hcsparams2;
  257. uint32_t hccparams1;
  258. uint32_t pagesize;
  259. size_t caplength;
  260. size_t rtsoff;
  261. size_t dboff;
  262. /* Locate capability, operational, runtime, and doorbell registers */
  263. xhci->cap = regs;
  264. caplength = readb ( xhci->cap + XHCI_CAP_CAPLENGTH );
  265. rtsoff = readl ( xhci->cap + XHCI_CAP_RTSOFF );
  266. dboff = readl ( xhci->cap + XHCI_CAP_DBOFF );
  267. xhci->op = ( xhci->cap + caplength );
  268. xhci->run = ( xhci->cap + rtsoff );
  269. xhci->db = ( xhci->cap + dboff );
  270. DBGC2 ( xhci, "XHCI %p cap %08lx op %08lx run %08lx db %08lx\n",
  271. xhci, virt_to_phys ( xhci->cap ), virt_to_phys ( xhci->op ),
  272. virt_to_phys ( xhci->run ), virt_to_phys ( xhci->db ) );
  273. /* Read structural parameters 1 */
  274. hcsparams1 = readl ( xhci->cap + XHCI_CAP_HCSPARAMS1 );
  275. xhci->slots = XHCI_HCSPARAMS1_SLOTS ( hcsparams1 );
  276. xhci->intrs = XHCI_HCSPARAMS1_INTRS ( hcsparams1 );
  277. xhci->ports = XHCI_HCSPARAMS1_PORTS ( hcsparams1 );
  278. DBGC ( xhci, "XHCI %p has %d slots %d intrs %d ports\n",
  279. xhci, xhci->slots, xhci->intrs, xhci->ports );
  280. /* Read structural parameters 2 */
  281. hcsparams2 = readl ( xhci->cap + XHCI_CAP_HCSPARAMS2 );
  282. xhci->scratchpads = XHCI_HCSPARAMS2_SCRATCHPADS ( hcsparams2 );
  283. DBGC2 ( xhci, "XHCI %p needs %d scratchpads\n",
  284. xhci, xhci->scratchpads );
  285. /* Read capability parameters 1 */
  286. hccparams1 = readl ( xhci->cap + XHCI_CAP_HCCPARAMS1 );
  287. xhci->addr64 = XHCI_HCCPARAMS1_ADDR64 ( hccparams1 );
  288. xhci->csz_shift = XHCI_HCCPARAMS1_CSZ_SHIFT ( hccparams1 );
  289. xhci->xecp = XHCI_HCCPARAMS1_XECP ( hccparams1 );
  290. /* Read page size */
  291. pagesize = readl ( xhci->op + XHCI_OP_PAGESIZE );
  292. xhci->pagesize = XHCI_PAGESIZE ( pagesize );
  293. assert ( xhci->pagesize != 0 );
  294. assert ( ( ( xhci->pagesize ) & ( xhci->pagesize - 1 ) ) == 0 );
  295. DBGC2 ( xhci, "XHCI %p page size %zd bytes\n",
  296. xhci, xhci->pagesize );
  297. }
  298. /**
  299. * Find extended capability
  300. *
  301. * @v xhci xHCI device
  302. * @v id Capability ID
  303. * @v offset Offset to previous extended capability instance, or zero
  304. * @ret offset Offset to extended capability, or zero if not found
  305. */
  306. static unsigned int xhci_extended_capability ( struct xhci_device *xhci,
  307. unsigned int id,
  308. unsigned int offset ) {
  309. uint32_t xecp;
  310. unsigned int next;
  311. /* Locate the extended capability */
  312. while ( 1 ) {
  313. /* Locate first or next capability as applicable */
  314. if ( offset ) {
  315. xecp = readl ( xhci->cap + offset );
  316. next = XHCI_XECP_NEXT ( xecp );
  317. } else {
  318. next = xhci->xecp;
  319. }
  320. if ( ! next )
  321. return 0;
  322. offset += next;
  323. /* Check if this is the requested capability */
  324. xecp = readl ( xhci->cap + offset );
  325. if ( XHCI_XECP_ID ( xecp ) == id )
  326. return offset;
  327. }
  328. }
  329. /**
  330. * Write potentially 64-bit register
  331. *
  332. * @v xhci xHCI device
  333. * @v value Value
  334. * @v reg Register address
  335. * @ret rc Return status code
  336. */
  337. static inline __attribute__ (( always_inline )) int
  338. xhci_writeq ( struct xhci_device *xhci, physaddr_t value, void *reg ) {
  339. /* If this is a 32-bit build, then this can never fail
  340. * (allowing the compiler to optimise out the error path).
  341. */
  342. if ( sizeof ( value ) <= sizeof ( uint32_t ) ) {
  343. writel ( value, reg );
  344. writel ( 0, ( reg + sizeof ( uint32_t ) ) );
  345. return 0;
  346. }
  347. /* If the device does not support 64-bit addresses and this
  348. * address is outside the 32-bit address space, then fail.
  349. */
  350. if ( ( value & ~0xffffffffULL ) && ! xhci->addr64 ) {
  351. DBGC ( xhci, "XHCI %p cannot access address %lx\n",
  352. xhci, value );
  353. return -ENOTSUP;
  354. }
  355. /* If this is a 64-bit build, then writeq() is available */
  356. writeq ( value, reg );
  357. return 0;
  358. }
  359. /**
  360. * Calculate buffer alignment
  361. *
  362. * @v len Length
  363. * @ret align Buffer alignment
  364. *
  365. * Determine alignment required for a buffer which must be aligned to
  366. * at least XHCI_MIN_ALIGN and which must not cross a page boundary.
  367. */
  368. static inline size_t xhci_align ( size_t len ) {
  369. size_t align;
  370. /* Align to own length (rounded up to a power of two) */
  371. align = ( 1 << fls ( len - 1 ) );
  372. /* Round up to XHCI_MIN_ALIGN if needed */
  373. if ( align < XHCI_MIN_ALIGN )
  374. align = XHCI_MIN_ALIGN;
  375. return align;
  376. }
  377. /**
  378. * Calculate device context offset
  379. *
  380. * @v xhci xHCI device
  381. * @v ctx Context index
  382. */
  383. static inline size_t xhci_device_context_offset ( struct xhci_device *xhci,
  384. unsigned int ctx ) {
  385. return ( XHCI_DCI ( ctx ) << xhci->csz_shift );
  386. }
  387. /**
  388. * Calculate input context offset
  389. *
  390. * @v xhci xHCI device
  391. * @v ctx Context index
  392. */
  393. static inline size_t xhci_input_context_offset ( struct xhci_device *xhci,
  394. unsigned int ctx ) {
  395. return ( XHCI_ICI ( ctx ) << xhci->csz_shift );
  396. }
  397. /******************************************************************************
  398. *
  399. * Diagnostics
  400. *
  401. ******************************************************************************
  402. */
  403. /**
  404. * Dump host controller registers
  405. *
  406. * @v xhci xHCI device
  407. */
  408. static inline void xhci_dump ( struct xhci_device *xhci ) {
  409. uint32_t usbcmd;
  410. uint32_t usbsts;
  411. uint32_t pagesize;
  412. uint32_t dnctrl;
  413. uint32_t config;
  414. /* Do nothing unless debugging is enabled */
  415. if ( ! DBG_LOG )
  416. return;
  417. /* Dump USBCMD */
  418. usbcmd = readl ( xhci->op + XHCI_OP_USBCMD );
  419. DBGC ( xhci, "XHCI %p USBCMD %08x%s%s\n", xhci, usbcmd,
  420. ( ( usbcmd & XHCI_USBCMD_RUN ) ? " run" : "" ),
  421. ( ( usbcmd & XHCI_USBCMD_HCRST ) ? " hcrst" : "" ) );
  422. /* Dump USBSTS */
  423. usbsts = readl ( xhci->op + XHCI_OP_USBSTS );
  424. DBGC ( xhci, "XHCI %p USBSTS %08x%s\n", xhci, usbsts,
  425. ( ( usbsts & XHCI_USBSTS_HCH ) ? " hch" : "" ) );
  426. /* Dump PAGESIZE */
  427. pagesize = readl ( xhci->op + XHCI_OP_PAGESIZE );
  428. DBGC ( xhci, "XHCI %p PAGESIZE %08x\n", xhci, pagesize );
  429. /* Dump DNCTRL */
  430. dnctrl = readl ( xhci->op + XHCI_OP_DNCTRL );
  431. DBGC ( xhci, "XHCI %p DNCTRL %08x\n", xhci, dnctrl );
  432. /* Dump CONFIG */
  433. config = readl ( xhci->op + XHCI_OP_CONFIG );
  434. DBGC ( xhci, "XHCI %p CONFIG %08x\n", xhci, config );
  435. }
  436. /**
  437. * Dump port registers
  438. *
  439. * @v xhci xHCI device
  440. * @v port Port number
  441. */
  442. static inline void xhci_dump_port ( struct xhci_device *xhci,
  443. unsigned int port ) {
  444. uint32_t portsc;
  445. uint32_t portpmsc;
  446. uint32_t portli;
  447. uint32_t porthlpmc;
  448. /* Do nothing unless debugging is enabled */
  449. if ( ! DBG_LOG )
  450. return;
  451. /* Dump PORTSC */
  452. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port ) );
  453. DBGC ( xhci, "XHCI %p port %d PORTSC %08x%s%s%s%s psiv=%d\n",
  454. xhci, port, portsc,
  455. ( ( portsc & XHCI_PORTSC_CCS ) ? " ccs" : "" ),
  456. ( ( portsc & XHCI_PORTSC_PED ) ? " ped" : "" ),
  457. ( ( portsc & XHCI_PORTSC_PR ) ? " pr" : "" ),
  458. ( ( portsc & XHCI_PORTSC_PP ) ? " pp" : "" ),
  459. XHCI_PORTSC_PSIV ( portsc ) );
  460. /* Dump PORTPMSC */
  461. portpmsc = readl ( xhci->op + XHCI_OP_PORTPMSC ( port ) );
  462. DBGC ( xhci, "XHCI %p port %d PORTPMSC %08x\n", xhci, port, portpmsc );
  463. /* Dump PORTLI */
  464. portli = readl ( xhci->op + XHCI_OP_PORTLI ( port ) );
  465. DBGC ( xhci, "XHCI %p port %d PORTLI %08x\n", xhci, port, portli );
  466. /* Dump PORTHLPMC */
  467. porthlpmc = readl ( xhci->op + XHCI_OP_PORTHLPMC ( port ) );
  468. DBGC ( xhci, "XHCI %p port %d PORTHLPMC %08x\n",
  469. xhci, port, porthlpmc );
  470. }
  471. /******************************************************************************
  472. *
  473. * USB legacy support
  474. *
  475. ******************************************************************************
  476. */
  477. /**
  478. * Initialise USB legacy support
  479. *
  480. * @v xhci xHCI device
  481. */
  482. static void xhci_legacy_init ( struct xhci_device *xhci ) {
  483. unsigned int legacy;
  484. uint8_t bios;
  485. /* Locate USB legacy support capability (if present) */
  486. legacy = xhci_extended_capability ( xhci, XHCI_XECP_ID_LEGACY, 0 );
  487. if ( ! legacy ) {
  488. /* Not an error; capability may not be present */
  489. DBGC ( xhci, "XHCI %p has no USB legacy support capability\n",
  490. xhci );
  491. return;
  492. }
  493. /* Check if legacy USB support is enabled */
  494. bios = readb ( xhci->cap + legacy + XHCI_USBLEGSUP_BIOS );
  495. if ( ! ( bios & XHCI_USBLEGSUP_BIOS_OWNED ) ) {
  496. /* Not an error; already owned by OS */
  497. DBGC ( xhci, "XHCI %p USB legacy support already disabled\n",
  498. xhci );
  499. return;
  500. }
  501. /* Record presence of USB legacy support capability */
  502. xhci->legacy = legacy;
  503. }
  504. /**
  505. * Claim ownership from BIOS
  506. *
  507. * @v xhci xHCI device
  508. * @ret rc Return status code
  509. */
  510. static int xhci_legacy_claim ( struct xhci_device *xhci ) {
  511. uint32_t ctlsts;
  512. uint8_t bios;
  513. unsigned int i;
  514. /* Do nothing unless legacy support capability is present */
  515. if ( ! xhci->legacy )
  516. return 0;
  517. /* Claim ownership */
  518. writeb ( XHCI_USBLEGSUP_OS_OWNED,
  519. xhci->cap + xhci->legacy + XHCI_USBLEGSUP_OS );
  520. /* Wait for BIOS to release ownership */
  521. for ( i = 0 ; i < XHCI_USBLEGSUP_MAX_WAIT_MS ; i++ ) {
  522. /* Check if BIOS has released ownership */
  523. bios = readb ( xhci->cap + xhci->legacy + XHCI_USBLEGSUP_BIOS );
  524. if ( ! ( bios & XHCI_USBLEGSUP_BIOS_OWNED ) ) {
  525. DBGC ( xhci, "XHCI %p claimed ownership from BIOS\n",
  526. xhci );
  527. ctlsts = readl ( xhci->cap + xhci->legacy +
  528. XHCI_USBLEGSUP_CTLSTS );
  529. if ( ctlsts ) {
  530. DBGC ( xhci, "XHCI %p warning: BIOS retained "
  531. "SMIs: %08x\n", xhci, ctlsts );
  532. }
  533. return 0;
  534. }
  535. /* Delay */
  536. mdelay ( 1 );
  537. }
  538. DBGC ( xhci, "XHCI %p timed out waiting for BIOS to release "
  539. "ownership\n", xhci );
  540. return -ETIMEDOUT;
  541. }
  542. /**
  543. * Release ownership back to BIOS
  544. *
  545. * @v xhci xHCI device
  546. */
  547. static void xhci_legacy_release ( struct xhci_device *xhci ) {
  548. /* Do nothing unless legacy support capability is present */
  549. if ( ! xhci->legacy )
  550. return;
  551. /* Release ownership */
  552. writeb ( 0, xhci->cap + xhci->legacy + XHCI_USBLEGSUP_OS );
  553. DBGC ( xhci, "XHCI %p released ownership to BIOS\n", xhci );
  554. }
  555. /******************************************************************************
  556. *
  557. * Supported protocols
  558. *
  559. ******************************************************************************
  560. */
  561. /**
  562. * Transcribe port speed (for debugging)
  563. *
  564. * @v psi Protocol speed ID
  565. * @ret speed Transcribed speed
  566. */
  567. static inline const char * xhci_speed_name ( uint32_t psi ) {
  568. static const char *exponents[4] = { "", "k", "M", "G" };
  569. static char buf[ 10 /* "xxxxxXbps" + NUL */ ];
  570. unsigned int mantissa;
  571. unsigned int exponent;
  572. /* Extract mantissa and exponent */
  573. mantissa = XHCI_SUPPORTED_PSI_MANTISSA ( psi );
  574. exponent = XHCI_SUPPORTED_PSI_EXPONENT ( psi );
  575. /* Transcribe speed */
  576. snprintf ( buf, sizeof ( buf ), "%d%sbps",
  577. mantissa, exponents[exponent] );
  578. return buf;
  579. }
  580. /**
  581. * Find supported protocol extended capability for a port
  582. *
  583. * @v xhci xHCI device
  584. * @v port Port number
  585. * @ret supported Offset to extended capability, or zero if not found
  586. */
  587. static unsigned int xhci_supported_protocol ( struct xhci_device *xhci,
  588. unsigned int port ) {
  589. unsigned int supported = 0;
  590. unsigned int offset;
  591. unsigned int count;
  592. uint32_t ports;
  593. /* Iterate over all supported protocol structures */
  594. while ( ( supported = xhci_extended_capability ( xhci,
  595. XHCI_XECP_ID_SUPPORTED,
  596. supported ) ) ) {
  597. /* Determine port range */
  598. ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS );
  599. offset = XHCI_SUPPORTED_PORTS_OFFSET ( ports );
  600. count = XHCI_SUPPORTED_PORTS_COUNT ( ports );
  601. /* Check if port lies within this range */
  602. if ( ( port - offset ) < count )
  603. return supported;
  604. }
  605. DBGC ( xhci, "XHCI %p port %d has no supported protocol\n",
  606. xhci, port );
  607. return 0;
  608. }
  609. /**
  610. * Find port protocol
  611. *
  612. * @v xhci xHCI device
  613. * @v port Port number
  614. * @ret protocol USB protocol, or zero if not found
  615. */
  616. static unsigned int xhci_port_protocol ( struct xhci_device *xhci,
  617. unsigned int port ) {
  618. unsigned int supported = xhci_supported_protocol ( xhci, port );
  619. union {
  620. uint32_t raw;
  621. char text[5];
  622. } name;
  623. unsigned int protocol;
  624. unsigned int type;
  625. unsigned int psic;
  626. unsigned int psiv;
  627. unsigned int i;
  628. uint32_t revision;
  629. uint32_t ports;
  630. uint32_t slot;
  631. uint32_t psi;
  632. /* Fail if there is no supported protocol */
  633. if ( ! supported )
  634. return 0;
  635. /* Determine protocol version */
  636. revision = readl ( xhci->cap + supported + XHCI_SUPPORTED_REVISION );
  637. protocol = XHCI_SUPPORTED_REVISION_VER ( revision );
  638. /* Describe port protocol */
  639. if ( DBG_EXTRA ) {
  640. name.raw = cpu_to_le32 ( readl ( xhci->cap + supported +
  641. XHCI_SUPPORTED_NAME ) );
  642. name.text[4] = '\0';
  643. slot = readl ( xhci->cap + supported + XHCI_SUPPORTED_SLOT );
  644. type = XHCI_SUPPORTED_SLOT_TYPE ( slot );
  645. DBGC2 ( xhci, "XHCI %p port %d %sv%04x type %d",
  646. xhci, port, name.text, protocol, type );
  647. ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS );
  648. psic = XHCI_SUPPORTED_PORTS_PSIC ( ports );
  649. if ( psic ) {
  650. DBGC2 ( xhci, " speeds" );
  651. for ( i = 0 ; i < psic ; i++ ) {
  652. psi = readl ( xhci->cap + supported +
  653. XHCI_SUPPORTED_PSI ( i ) );
  654. psiv = XHCI_SUPPORTED_PSI_VALUE ( psi );
  655. DBGC2 ( xhci, " %d:%s", psiv,
  656. xhci_speed_name ( psi ) );
  657. }
  658. }
  659. DBGC2 ( xhci, "\n" );
  660. }
  661. return protocol;
  662. }
  663. /**
  664. * Find port slot type
  665. *
  666. * @v xhci xHCI device
  667. * @v port Port number
  668. * @ret type Slot type, or negative error
  669. */
  670. static int xhci_port_slot_type ( struct xhci_device *xhci, unsigned int port ) {
  671. unsigned int supported = xhci_supported_protocol ( xhci, port );
  672. unsigned int type;
  673. uint32_t slot;
  674. /* Fail if there is no supported protocol */
  675. if ( ! supported )
  676. return -ENOTSUP;
  677. /* Get slot type */
  678. slot = readl ( xhci->cap + supported + XHCI_SUPPORTED_SLOT );
  679. type = XHCI_SUPPORTED_SLOT_TYPE ( slot );
  680. return type;
  681. }
  682. /**
  683. * Find port speed
  684. *
  685. * @v xhci xHCI device
  686. * @v port Port number
  687. * @v psiv Protocol speed ID value
  688. * @ret speed Port speed, or negative error
  689. */
  690. static int xhci_port_speed ( struct xhci_device *xhci, unsigned int port,
  691. unsigned int psiv ) {
  692. unsigned int supported = xhci_supported_protocol ( xhci, port );
  693. unsigned int psic;
  694. unsigned int mantissa;
  695. unsigned int exponent;
  696. unsigned int speed;
  697. unsigned int i;
  698. uint32_t ports;
  699. uint32_t psi;
  700. /* Fail if there is no supported protocol */
  701. if ( ! supported )
  702. return -ENOTSUP;
  703. /* Get protocol speed ID count */
  704. ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS );
  705. psic = XHCI_SUPPORTED_PORTS_PSIC ( ports );
  706. /* Use the default mappings if applicable */
  707. if ( ! psic ) {
  708. switch ( psiv ) {
  709. case XHCI_SPEED_LOW : return USB_SPEED_LOW;
  710. case XHCI_SPEED_FULL : return USB_SPEED_FULL;
  711. case XHCI_SPEED_HIGH : return USB_SPEED_HIGH;
  712. case XHCI_SPEED_SUPER : return USB_SPEED_SUPER;
  713. default:
  714. DBGC ( xhci, "XHCI %p port %d non-standard PSI value "
  715. "%d\n", xhci, port, psiv );
  716. return -ENOTSUP;
  717. }
  718. }
  719. /* Iterate over PSI dwords looking for a match */
  720. for ( i = 0 ; i < psic ; i++ ) {
  721. psi = readl ( xhci->cap + supported + XHCI_SUPPORTED_PSI ( i ));
  722. if ( psiv == XHCI_SUPPORTED_PSI_VALUE ( psi ) ) {
  723. mantissa = XHCI_SUPPORTED_PSI_MANTISSA ( psi );
  724. exponent = XHCI_SUPPORTED_PSI_EXPONENT ( psi );
  725. speed = USB_SPEED ( mantissa, exponent );
  726. return speed;
  727. }
  728. }
  729. DBGC ( xhci, "XHCI %p port %d spurious PSI value %d\n",
  730. xhci, port, psiv );
  731. return -ENOENT;
  732. }
  733. /**
  734. * Find protocol speed ID value
  735. *
  736. * @v xhci xHCI device
  737. * @v port Port number
  738. * @v speed USB speed
  739. * @ret psiv Protocol speed ID value, or negative error
  740. */
  741. static int xhci_port_psiv ( struct xhci_device *xhci, unsigned int port,
  742. unsigned int speed ) {
  743. unsigned int supported = xhci_supported_protocol ( xhci, port );
  744. unsigned int psic;
  745. unsigned int mantissa;
  746. unsigned int exponent;
  747. unsigned int psiv;
  748. unsigned int i;
  749. uint32_t ports;
  750. uint32_t psi;
  751. /* Fail if there is no supported protocol */
  752. if ( ! supported )
  753. return -ENOTSUP;
  754. /* Get protocol speed ID count */
  755. ports = readl ( xhci->cap + supported + XHCI_SUPPORTED_PORTS );
  756. psic = XHCI_SUPPORTED_PORTS_PSIC ( ports );
  757. /* Use the default mappings if applicable */
  758. if ( ! psic ) {
  759. switch ( speed ) {
  760. case USB_SPEED_LOW : return XHCI_SPEED_LOW;
  761. case USB_SPEED_FULL : return XHCI_SPEED_FULL;
  762. case USB_SPEED_HIGH : return XHCI_SPEED_HIGH;
  763. case USB_SPEED_SUPER : return XHCI_SPEED_SUPER;
  764. default:
  765. DBGC ( xhci, "XHCI %p port %d non-standad speed %d\n",
  766. xhci, port, speed );
  767. return -ENOTSUP;
  768. }
  769. }
  770. /* Iterate over PSI dwords looking for a match */
  771. for ( i = 0 ; i < psic ; i++ ) {
  772. psi = readl ( xhci->cap + supported + XHCI_SUPPORTED_PSI ( i ));
  773. mantissa = XHCI_SUPPORTED_PSI_MANTISSA ( psi );
  774. exponent = XHCI_SUPPORTED_PSI_EXPONENT ( psi );
  775. if ( speed == USB_SPEED ( mantissa, exponent ) ) {
  776. psiv = XHCI_SUPPORTED_PSI_VALUE ( psi );
  777. return psiv;
  778. }
  779. }
  780. DBGC ( xhci, "XHCI %p port %d unrepresentable speed %#x\n",
  781. xhci, port, speed );
  782. return -ENOENT;
  783. }
  784. /******************************************************************************
  785. *
  786. * Device context base address array
  787. *
  788. ******************************************************************************
  789. */
  790. /**
  791. * Allocate device context base address array
  792. *
  793. * @v xhci xHCI device
  794. * @ret rc Return status code
  795. */
  796. static int xhci_dcbaa_alloc ( struct xhci_device *xhci ) {
  797. size_t len;
  798. physaddr_t dcbaap;
  799. int rc;
  800. /* Allocate and initialise structure. Must be at least
  801. * 64-byte aligned and must not cross a page boundary, so
  802. * align on its own size (rounded up to a power of two and
  803. * with a minimum of 64 bytes).
  804. */
  805. len = ( ( xhci->slots + 1 ) * sizeof ( xhci->dcbaa[0] ) );
  806. xhci->dcbaa = malloc_dma ( len, xhci_align ( len ) );
  807. if ( ! xhci->dcbaa ) {
  808. DBGC ( xhci, "XHCI %p could not allocate DCBAA\n", xhci );
  809. rc = -ENOMEM;
  810. goto err_alloc;
  811. }
  812. memset ( xhci->dcbaa, 0, len );
  813. /* Program DCBAA pointer */
  814. dcbaap = virt_to_phys ( xhci->dcbaa );
  815. if ( ( rc = xhci_writeq ( xhci, dcbaap,
  816. xhci->op + XHCI_OP_DCBAAP ) ) != 0 )
  817. goto err_writeq;
  818. DBGC2 ( xhci, "XHCI %p DCBAA at [%08lx,%08lx)\n",
  819. xhci, dcbaap, ( dcbaap + len ) );
  820. return 0;
  821. err_writeq:
  822. free_dma ( xhci->dcbaa, len );
  823. err_alloc:
  824. return rc;
  825. }
  826. /**
  827. * Free device context base address array
  828. *
  829. * @v xhci xHCI device
  830. */
  831. static void xhci_dcbaa_free ( struct xhci_device *xhci ) {
  832. size_t len;
  833. unsigned int i;
  834. /* Sanity check */
  835. for ( i = 0 ; i <= xhci->slots ; i++ )
  836. assert ( xhci->dcbaa[i] == 0 );
  837. /* Clear DCBAA pointer */
  838. xhci_writeq ( xhci, 0, xhci->op + XHCI_OP_DCBAAP );
  839. /* Free DCBAA */
  840. len = ( ( xhci->slots + 1 ) * sizeof ( xhci->dcbaa[0] ) );
  841. free_dma ( xhci->dcbaa, len );
  842. }
  843. /******************************************************************************
  844. *
  845. * Scratchpad buffers
  846. *
  847. ******************************************************************************
  848. */
  849. /**
  850. * Allocate scratchpad buffers
  851. *
  852. * @v xhci xHCI device
  853. * @ret rc Return status code
  854. */
  855. static int xhci_scratchpad_alloc ( struct xhci_device *xhci ) {
  856. size_t array_len;
  857. size_t len;
  858. physaddr_t phys;
  859. unsigned int i;
  860. int rc;
  861. /* Do nothing if no scratchpad buffers are used */
  862. if ( ! xhci->scratchpads )
  863. return 0;
  864. /* Allocate scratchpads */
  865. len = ( xhci->scratchpads * xhci->pagesize );
  866. xhci->scratchpad = umalloc ( len );
  867. if ( ! xhci->scratchpad ) {
  868. DBGC ( xhci, "XHCI %p could not allocate scratchpad buffers\n",
  869. xhci );
  870. rc = -ENOMEM;
  871. goto err_alloc;
  872. }
  873. memset_user ( xhci->scratchpad, 0, 0, len );
  874. /* Allocate scratchpad array */
  875. array_len = ( xhci->scratchpads * sizeof ( xhci->scratchpad_array[0] ));
  876. xhci->scratchpad_array =
  877. malloc_dma ( array_len, xhci_align ( array_len ) );
  878. if ( ! xhci->scratchpad_array ) {
  879. DBGC ( xhci, "XHCI %p could not allocate scratchpad buffer "
  880. "array\n", xhci );
  881. rc = -ENOMEM;
  882. goto err_alloc_array;
  883. }
  884. /* Populate scratchpad array */
  885. for ( i = 0 ; i < xhci->scratchpads ; i++ ) {
  886. phys = user_to_phys ( xhci->scratchpad, ( i * xhci->pagesize ));
  887. xhci->scratchpad_array[i] = phys;
  888. }
  889. /* Set scratchpad array pointer */
  890. assert ( xhci->dcbaa != NULL );
  891. xhci->dcbaa[0] = cpu_to_le64 ( virt_to_phys ( xhci->scratchpad_array ));
  892. DBGC2 ( xhci, "XHCI %p scratchpad [%08lx,%08lx) array [%08lx,%08lx)\n",
  893. xhci, user_to_phys ( xhci->scratchpad, 0 ),
  894. user_to_phys ( xhci->scratchpad, len ),
  895. virt_to_phys ( xhci->scratchpad_array ),
  896. ( virt_to_phys ( xhci->scratchpad_array ) + array_len ) );
  897. return 0;
  898. free_dma ( xhci->scratchpad_array, array_len );
  899. err_alloc_array:
  900. ufree ( xhci->scratchpad );
  901. err_alloc:
  902. return rc;
  903. }
  904. /**
  905. * Free scratchpad buffers
  906. *
  907. * @v xhci xHCI device
  908. */
  909. static void xhci_scratchpad_free ( struct xhci_device *xhci ) {
  910. size_t array_len;
  911. /* Do nothing if no scratchpad buffers are used */
  912. if ( ! xhci->scratchpads )
  913. return;
  914. /* Clear scratchpad array pointer */
  915. assert ( xhci->dcbaa != NULL );
  916. xhci->dcbaa[0] = 0;
  917. /* Free scratchpad array */
  918. array_len = ( xhci->scratchpads * sizeof ( xhci->scratchpad_array[0] ));
  919. free_dma ( xhci->scratchpad_array, array_len );
  920. /* Free scratchpads */
  921. ufree ( xhci->scratchpad );
  922. }
  923. /******************************************************************************
  924. *
  925. * Run / stop / reset
  926. *
  927. ******************************************************************************
  928. */
  929. /**
  930. * Start xHCI device
  931. *
  932. * @v xhci xHCI device
  933. */
  934. static void xhci_run ( struct xhci_device *xhci ) {
  935. uint32_t config;
  936. uint32_t usbcmd;
  937. /* Configure number of device slots */
  938. config = readl ( xhci->op + XHCI_OP_CONFIG );
  939. config &= ~XHCI_CONFIG_MAX_SLOTS_EN_MASK;
  940. config |= XHCI_CONFIG_MAX_SLOTS_EN ( xhci->slots );
  941. writel ( config, xhci->op + XHCI_OP_CONFIG );
  942. /* Set run/stop bit */
  943. usbcmd = readl ( xhci->op + XHCI_OP_USBCMD );
  944. usbcmd |= XHCI_USBCMD_RUN;
  945. writel ( usbcmd, xhci->op + XHCI_OP_USBCMD );
  946. }
  947. /**
  948. * Stop xHCI device
  949. *
  950. * @v xhci xHCI device
  951. * @ret rc Return status code
  952. */
  953. static int xhci_stop ( struct xhci_device *xhci ) {
  954. uint32_t usbcmd;
  955. uint32_t usbsts;
  956. unsigned int i;
  957. /* Clear run/stop bit */
  958. usbcmd = readl ( xhci->op + XHCI_OP_USBCMD );
  959. usbcmd &= ~XHCI_USBCMD_RUN;
  960. writel ( usbcmd, xhci->op + XHCI_OP_USBCMD );
  961. /* Wait for device to stop */
  962. for ( i = 0 ; i < XHCI_STOP_MAX_WAIT_MS ; i++ ) {
  963. /* Check if device is stopped */
  964. usbsts = readl ( xhci->op + XHCI_OP_USBSTS );
  965. if ( usbsts & XHCI_USBSTS_HCH )
  966. return 0;
  967. /* Delay */
  968. mdelay ( 1 );
  969. }
  970. DBGC ( xhci, "XHCI %p timed out waiting for stop\n", xhci );
  971. return -ETIMEDOUT;
  972. }
  973. /**
  974. * Reset xHCI device
  975. *
  976. * @v xhci xHCI device
  977. * @ret rc Return status code
  978. */
  979. static int xhci_reset ( struct xhci_device *xhci ) {
  980. uint32_t usbcmd;
  981. unsigned int i;
  982. int rc;
  983. /* The xHCI specification states that resetting a running
  984. * device may result in undefined behaviour, so try stopping
  985. * it first.
  986. */
  987. if ( ( rc = xhci_stop ( xhci ) ) != 0 ) {
  988. /* Ignore errors and attempt to reset the device anyway */
  989. }
  990. /* Reset device */
  991. writel ( XHCI_USBCMD_HCRST, xhci->op + XHCI_OP_USBCMD );
  992. /* Wait for reset to complete */
  993. for ( i = 0 ; i < XHCI_RESET_MAX_WAIT_MS ; i++ ) {
  994. /* Check if reset is complete */
  995. usbcmd = readl ( xhci->op + XHCI_OP_USBCMD );
  996. if ( ! ( usbcmd & XHCI_USBCMD_HCRST ) )
  997. return 0;
  998. /* Delay */
  999. mdelay ( 1 );
  1000. }
  1001. DBGC ( xhci, "XHCI %p timed out waiting for reset\n", xhci );
  1002. return -ETIMEDOUT;
  1003. }
  1004. /******************************************************************************
  1005. *
  1006. * Transfer request blocks
  1007. *
  1008. ******************************************************************************
  1009. */
  1010. /**
  1011. * Allocate transfer request block ring
  1012. *
  1013. * @v xhci xHCI device
  1014. * @v ring TRB ring
  1015. * @v shift Ring size (log2)
  1016. * @v slot Device slot
  1017. * @v target Doorbell target
  1018. * @v stream Doorbell stream ID
  1019. * @ret rc Return status code
  1020. */
  1021. static int xhci_ring_alloc ( struct xhci_device *xhci,
  1022. struct xhci_trb_ring *ring,
  1023. unsigned int shift, unsigned int slot,
  1024. unsigned int target, unsigned int stream ) {
  1025. struct xhci_trb_link *link;
  1026. unsigned int count;
  1027. int rc;
  1028. /* Sanity check */
  1029. assert ( shift > 0 );
  1030. /* Initialise structure */
  1031. memset ( ring, 0, sizeof ( *ring ) );
  1032. ring->shift = shift;
  1033. count = ( 1U << shift );
  1034. ring->mask = ( count - 1 );
  1035. ring->len = ( ( count + 1 /* Link TRB */ ) * sizeof ( ring->trb[0] ) );
  1036. ring->db = ( xhci->db + ( slot * sizeof ( ring->dbval ) ) );
  1037. ring->dbval = XHCI_DBVAL ( target, stream );
  1038. /* Allocate I/O buffers */
  1039. ring->iobuf = zalloc ( count * sizeof ( ring->iobuf[0] ) );
  1040. if ( ! ring->iobuf ) {
  1041. rc = -ENOMEM;
  1042. goto err_alloc_iobuf;
  1043. }
  1044. /* Allocate TRBs */
  1045. ring->trb = malloc_dma ( ring->len, xhci_align ( ring->len ) );
  1046. if ( ! ring->trb ) {
  1047. rc = -ENOMEM;
  1048. goto err_alloc_trb;
  1049. }
  1050. memset ( ring->trb, 0, ring->len );
  1051. /* Initialise Link TRB */
  1052. link = &ring->trb[count].link;
  1053. link->next = cpu_to_le64 ( virt_to_phys ( ring->trb ) );
  1054. link->flags = XHCI_TRB_TC;
  1055. link->type = XHCI_TRB_LINK;
  1056. ring->link = link;
  1057. return 0;
  1058. free_dma ( ring->trb, ring->len );
  1059. err_alloc_trb:
  1060. free ( ring->iobuf );
  1061. err_alloc_iobuf:
  1062. return rc;
  1063. }
  1064. /**
  1065. * Reset transfer request block ring
  1066. *
  1067. * @v ring TRB ring
  1068. */
  1069. static void xhci_ring_reset ( struct xhci_trb_ring *ring ) {
  1070. unsigned int count = ( 1U << ring->shift );
  1071. /* Reset producer and consumer counters */
  1072. ring->prod = 0;
  1073. ring->cons = 0;
  1074. /* Reset TRBs (except Link TRB) */
  1075. memset ( ring->trb, 0, ( count * sizeof ( ring->trb[0] ) ) );
  1076. }
  1077. /**
  1078. * Free transfer request block ring
  1079. *
  1080. * @v ring TRB ring
  1081. */
  1082. static void xhci_ring_free ( struct xhci_trb_ring *ring ) {
  1083. unsigned int count = ( 1U << ring->shift );
  1084. unsigned int i;
  1085. /* Sanity checks */
  1086. assert ( ring->cons == ring->prod );
  1087. for ( i = 0 ; i < count ; i++ )
  1088. assert ( ring->iobuf[i] == NULL );
  1089. /* Free TRBs */
  1090. free_dma ( ring->trb, ring->len );
  1091. /* Free I/O buffers */
  1092. free ( ring->iobuf );
  1093. }
  1094. /**
  1095. * Enqueue a transfer request block
  1096. *
  1097. * @v ring TRB ring
  1098. * @v iobuf I/O buffer (if any)
  1099. * @v trb Transfer request block (with empty Cycle flag)
  1100. * @ret rc Return status code
  1101. *
  1102. * This operation does not implicitly ring the doorbell register.
  1103. */
  1104. static int xhci_enqueue ( struct xhci_trb_ring *ring, struct io_buffer *iobuf,
  1105. const union xhci_trb *trb ) {
  1106. union xhci_trb *dest;
  1107. unsigned int prod;
  1108. unsigned int mask;
  1109. unsigned int index;
  1110. unsigned int cycle;
  1111. /* Sanity check */
  1112. assert ( ! ( trb->common.flags & XHCI_TRB_C ) );
  1113. /* Fail if ring is full */
  1114. if ( ! xhci_ring_remaining ( ring ) )
  1115. return -ENOBUFS;
  1116. /* Update producer counter (and link TRB, if applicable) */
  1117. prod = ring->prod++;
  1118. mask = ring->mask;
  1119. cycle = ( ( ~( prod >> ring->shift ) ) & XHCI_TRB_C );
  1120. index = ( prod & mask );
  1121. if ( index == 0 )
  1122. ring->link->flags = ( XHCI_TRB_TC | ( cycle ^ XHCI_TRB_C ) );
  1123. /* Record I/O buffer */
  1124. ring->iobuf[index] = iobuf;
  1125. /* Enqueue TRB */
  1126. dest = &ring->trb[index];
  1127. dest->template.parameter = trb->template.parameter;
  1128. dest->template.status = trb->template.status;
  1129. wmb();
  1130. dest->template.control = ( trb->template.control |
  1131. cpu_to_le32 ( cycle ) );
  1132. return 0;
  1133. }
  1134. /**
  1135. * Dequeue a transfer request block
  1136. *
  1137. * @v ring TRB ring
  1138. * @ret iobuf I/O buffer
  1139. */
  1140. static struct io_buffer * xhci_dequeue ( struct xhci_trb_ring *ring ) {
  1141. struct io_buffer *iobuf;
  1142. unsigned int cons;
  1143. unsigned int mask;
  1144. unsigned int index;
  1145. /* Sanity check */
  1146. assert ( xhci_ring_fill ( ring ) != 0 );
  1147. /* Update consumer counter */
  1148. cons = ring->cons++;
  1149. mask = ring->mask;
  1150. index = ( cons & mask );
  1151. /* Retrieve I/O buffer */
  1152. iobuf = ring->iobuf[index];
  1153. ring->iobuf[index] = NULL;
  1154. return iobuf;
  1155. }
  1156. /**
  1157. * Enqueue multiple transfer request blocks
  1158. *
  1159. * @v ring TRB ring
  1160. * @v iobuf I/O buffer
  1161. * @v trbs Transfer request blocks (with empty Cycle flag)
  1162. * @v count Number of transfer request blocks
  1163. * @ret rc Return status code
  1164. *
  1165. * This operation does not implicitly ring the doorbell register.
  1166. */
  1167. static int xhci_enqueue_multi ( struct xhci_trb_ring *ring,
  1168. struct io_buffer *iobuf,
  1169. const union xhci_trb *trbs,
  1170. unsigned int count ) {
  1171. const union xhci_trb *trb = trbs;
  1172. int rc;
  1173. /* Sanity check */
  1174. assert ( iobuf != NULL );
  1175. /* Fail if ring does not have sufficient space */
  1176. if ( xhci_ring_remaining ( ring ) < count )
  1177. return -ENOBUFS;
  1178. /* Enqueue each TRB, recording the I/O buffer with the final TRB */
  1179. while ( count-- ) {
  1180. rc = xhci_enqueue ( ring, ( count ? NULL : iobuf ), trb++ );
  1181. assert ( rc == 0 ); /* Should never be able to fail */
  1182. }
  1183. return 0;
  1184. }
  1185. /**
  1186. * Dequeue multiple transfer request blocks
  1187. *
  1188. * @v ring TRB ring
  1189. * @ret iobuf I/O buffer
  1190. */
  1191. static struct io_buffer * xhci_dequeue_multi ( struct xhci_trb_ring *ring ) {
  1192. struct io_buffer *iobuf;
  1193. /* Dequeue TRBs until we reach the final TRB for an I/O buffer */
  1194. do {
  1195. iobuf = xhci_dequeue ( ring );
  1196. } while ( iobuf == NULL );
  1197. return iobuf;
  1198. }
  1199. /**
  1200. * Ring doorbell register
  1201. *
  1202. * @v ring TRB ring
  1203. */
  1204. static inline __attribute__ (( always_inline )) void
  1205. xhci_doorbell ( struct xhci_trb_ring *ring ) {
  1206. wmb();
  1207. writel ( ring->dbval, ring->db );
  1208. }
  1209. /******************************************************************************
  1210. *
  1211. * Command and event rings
  1212. *
  1213. ******************************************************************************
  1214. */
  1215. /**
  1216. * Allocate command ring
  1217. *
  1218. * @v xhci xHCI device
  1219. * @ret rc Return status code
  1220. */
  1221. static int xhci_command_alloc ( struct xhci_device *xhci ) {
  1222. physaddr_t crp;
  1223. int rc;
  1224. /* Allocate TRB ring */
  1225. if ( ( rc = xhci_ring_alloc ( xhci, &xhci->command, XHCI_CMD_TRBS_LOG2,
  1226. 0, 0, 0 ) ) != 0 )
  1227. goto err_ring_alloc;
  1228. /* Program command ring control register */
  1229. crp = virt_to_phys ( xhci->command.trb );
  1230. if ( ( rc = xhci_writeq ( xhci, ( crp | XHCI_CRCR_RCS ),
  1231. xhci->op + XHCI_OP_CRCR ) ) != 0 )
  1232. goto err_writeq;
  1233. DBGC2 ( xhci, "XHCI %p CRCR at [%08lx,%08lx)\n",
  1234. xhci, crp, ( crp + xhci->command.len ) );
  1235. return 0;
  1236. err_writeq:
  1237. xhci_ring_free ( &xhci->command );
  1238. err_ring_alloc:
  1239. return rc;
  1240. }
  1241. /**
  1242. * Free command ring
  1243. *
  1244. * @v xhci xHCI device
  1245. */
  1246. static void xhci_command_free ( struct xhci_device *xhci ) {
  1247. /* Sanity check */
  1248. assert ( ( readl ( xhci->op + XHCI_OP_CRCR ) & XHCI_CRCR_CRR ) == 0 );
  1249. /* Clear command ring control register */
  1250. xhci_writeq ( xhci, 0, xhci->op + XHCI_OP_CRCR );
  1251. /* Free TRB ring */
  1252. xhci_ring_free ( &xhci->command );
  1253. }
  1254. /**
  1255. * Allocate event ring
  1256. *
  1257. * @v xhci xHCI device
  1258. * @ret rc Return status code
  1259. */
  1260. static int xhci_event_alloc ( struct xhci_device *xhci ) {
  1261. struct xhci_event_ring *event = &xhci->event;
  1262. unsigned int count;
  1263. size_t len;
  1264. int rc;
  1265. /* Allocate event ring */
  1266. count = ( 1 << XHCI_EVENT_TRBS_LOG2 );
  1267. len = ( count * sizeof ( event->trb[0] ) );
  1268. event->trb = malloc_dma ( len, xhci_align ( len ) );
  1269. if ( ! event->trb ) {
  1270. rc = -ENOMEM;
  1271. goto err_alloc_trb;
  1272. }
  1273. memset ( event->trb, 0, len );
  1274. /* Allocate event ring segment table */
  1275. event->segment = malloc_dma ( sizeof ( event->segment[0] ),
  1276. xhci_align ( sizeof (event->segment[0])));
  1277. if ( ! event->segment ) {
  1278. rc = -ENOMEM;
  1279. goto err_alloc_segment;
  1280. }
  1281. memset ( event->segment, 0, sizeof ( event->segment[0] ) );
  1282. event->segment[0].base = cpu_to_le64 ( virt_to_phys ( event->trb ) );
  1283. event->segment[0].count = cpu_to_le32 ( count );
  1284. /* Program event ring registers */
  1285. writel ( 1, xhci->run + XHCI_RUN_ERSTSZ ( 0 ) );
  1286. if ( ( rc = xhci_writeq ( xhci, virt_to_phys ( event->trb ),
  1287. xhci->run + XHCI_RUN_ERDP ( 0 ) ) ) != 0 )
  1288. goto err_writeq_erdp;
  1289. if ( ( rc = xhci_writeq ( xhci, virt_to_phys ( event->segment ),
  1290. xhci->run + XHCI_RUN_ERSTBA ( 0 ) ) ) != 0 )
  1291. goto err_writeq_erstba;
  1292. DBGC2 ( xhci, "XHCI %p event ring [%08lx,%08lx) table [%08lx,%08lx)\n",
  1293. xhci, virt_to_phys ( event->trb ),
  1294. ( virt_to_phys ( event->trb ) + len ),
  1295. virt_to_phys ( event->segment ),
  1296. ( virt_to_phys ( event->segment ) +
  1297. sizeof (event->segment[0] ) ) );
  1298. return 0;
  1299. xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERSTBA ( 0 ) );
  1300. err_writeq_erstba:
  1301. xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERDP ( 0 ) );
  1302. err_writeq_erdp:
  1303. free_dma ( event->trb, len );
  1304. err_alloc_segment:
  1305. free_dma ( event->segment, sizeof ( event->segment[0] ) );
  1306. err_alloc_trb:
  1307. return rc;
  1308. }
  1309. /**
  1310. * Free event ring
  1311. *
  1312. * @v xhci xHCI device
  1313. */
  1314. static void xhci_event_free ( struct xhci_device *xhci ) {
  1315. struct xhci_event_ring *event = &xhci->event;
  1316. unsigned int count;
  1317. size_t len;
  1318. /* Clear event ring registers */
  1319. writel ( 0, xhci->run + XHCI_RUN_ERSTSZ ( 0 ) );
  1320. xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERSTBA ( 0 ) );
  1321. xhci_writeq ( xhci, 0, xhci->run + XHCI_RUN_ERDP ( 0 ) );
  1322. /* Free event ring segment table */
  1323. free_dma ( event->segment, sizeof ( event->segment[0] ) );
  1324. /* Free event ring */
  1325. count = ( 1 << XHCI_EVENT_TRBS_LOG2 );
  1326. len = ( count * sizeof ( event->trb[0] ) );
  1327. free_dma ( event->trb, len );
  1328. }
  1329. /**
  1330. * Handle transfer event
  1331. *
  1332. * @v xhci xHCI device
  1333. * @v transfer Transfer event TRB
  1334. */
  1335. static void xhci_transfer ( struct xhci_device *xhci,
  1336. struct xhci_trb_transfer *transfer ) {
  1337. struct xhci_slot *slot;
  1338. struct xhci_endpoint *endpoint;
  1339. struct io_buffer *iobuf;
  1340. int rc;
  1341. /* Profile transfer events */
  1342. profile_start ( &xhci_transfer_profiler );
  1343. /* Identify slot */
  1344. if ( ( transfer->slot > xhci->slots ) ||
  1345. ( ( slot = xhci->slot[transfer->slot] ) == NULL ) ) {
  1346. DBGC ( xhci, "XHCI %p transfer event invalid slot %d:\n",
  1347. xhci, transfer->slot );
  1348. DBGC_HDA ( xhci, 0, transfer, sizeof ( *transfer ) );
  1349. return;
  1350. }
  1351. /* Identify endpoint */
  1352. if ( ( transfer->endpoint > XHCI_CTX_END ) ||
  1353. ( ( endpoint = slot->endpoint[transfer->endpoint] ) == NULL ) ) {
  1354. DBGC ( xhci, "XHCI %p slot %d transfer event invalid epid "
  1355. "%d:\n", xhci, slot->id, transfer->endpoint );
  1356. DBGC_HDA ( xhci, 0, transfer, sizeof ( *transfer ) );
  1357. return;
  1358. }
  1359. /* Dequeue TRB(s) */
  1360. iobuf = xhci_dequeue_multi ( &endpoint->ring );
  1361. assert ( iobuf != NULL );
  1362. /* Check for errors */
  1363. if ( ! ( ( transfer->code == XHCI_CMPLT_SUCCESS ) ||
  1364. ( transfer->code == XHCI_CMPLT_SHORT ) ) ) {
  1365. /* Construct error */
  1366. rc = -ECODE ( transfer->code );
  1367. DBGC ( xhci, "XHCI %p slot %d ctx %d failed (code %d): %s\n",
  1368. xhci, slot->id, endpoint->ctx, transfer->code,
  1369. strerror ( rc ) );
  1370. DBGC_HDA ( xhci, 0, transfer, sizeof ( *transfer ) );
  1371. /* Sanity check */
  1372. assert ( ( endpoint->context->state & XHCI_ENDPOINT_STATE_MASK )
  1373. != XHCI_ENDPOINT_RUNNING );
  1374. /* Report failure to USB core */
  1375. usb_complete_err ( endpoint->ep, iobuf, rc );
  1376. return;
  1377. }
  1378. /* Record actual transfer size */
  1379. iob_unput ( iobuf, le16_to_cpu ( transfer->residual ) );
  1380. /* Sanity check (for successful completions only) */
  1381. assert ( xhci_ring_consumed ( &endpoint->ring ) ==
  1382. le64_to_cpu ( transfer->transfer ) );
  1383. /* Report completion to USB core */
  1384. usb_complete ( endpoint->ep, iobuf );
  1385. profile_stop ( &xhci_transfer_profiler );
  1386. }
  1387. /**
  1388. * Handle command completion event
  1389. *
  1390. * @v xhci xHCI device
  1391. * @v complete Command completion event
  1392. */
  1393. static void xhci_complete ( struct xhci_device *xhci,
  1394. struct xhci_trb_complete *complete ) {
  1395. int rc;
  1396. /* Ignore "command ring stopped" notifications */
  1397. if ( complete->code == XHCI_CMPLT_CMD_STOPPED ) {
  1398. DBGC2 ( xhci, "XHCI %p command ring stopped\n", xhci );
  1399. return;
  1400. }
  1401. /* Ignore unexpected completions */
  1402. if ( ! xhci->pending ) {
  1403. rc = -ECODE ( complete->code );
  1404. DBGC ( xhci, "XHCI %p unexpected completion (code %d): %s\n",
  1405. xhci, complete->code, strerror ( rc ) );
  1406. DBGC_HDA ( xhci, 0, complete, sizeof ( *complete ) );
  1407. return;
  1408. }
  1409. /* Dequeue command TRB */
  1410. xhci_dequeue ( &xhci->command );
  1411. /* Sanity check */
  1412. assert ( xhci_ring_consumed ( &xhci->command ) ==
  1413. le64_to_cpu ( complete->command ) );
  1414. /* Record completion */
  1415. memcpy ( xhci->pending, complete, sizeof ( *xhci->pending ) );
  1416. xhci->pending = NULL;
  1417. }
  1418. /**
  1419. * Handle port status event
  1420. *
  1421. * @v xhci xHCI device
  1422. * @v port Port status event
  1423. */
  1424. static void xhci_port_status ( struct xhci_device *xhci,
  1425. struct xhci_trb_port_status *port ) {
  1426. uint32_t portsc;
  1427. /* Sanity check */
  1428. assert ( ( port->port > 0 ) && ( port->port <= xhci->ports ) );
  1429. /* Clear port status change bits */
  1430. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port->port ) );
  1431. portsc &= ( XHCI_PORTSC_PRESERVE | XHCI_PORTSC_CHANGE );
  1432. writel ( portsc, xhci->op + XHCI_OP_PORTSC ( port->port ) );
  1433. /* Report port status change */
  1434. usb_port_changed ( usb_port ( xhci->bus->hub, port->port ) );
  1435. }
  1436. /**
  1437. * Handle host controller event
  1438. *
  1439. * @v xhci xHCI device
  1440. * @v host Host controller event
  1441. */
  1442. static void xhci_host_controller ( struct xhci_device *xhci,
  1443. struct xhci_trb_host_controller *host ) {
  1444. int rc;
  1445. /* Construct error */
  1446. rc = -ECODE ( host->code );
  1447. DBGC ( xhci, "XHCI %p host controller event (code %d): %s\n",
  1448. xhci, host->code, strerror ( rc ) );
  1449. }
  1450. /**
  1451. * Poll event ring
  1452. *
  1453. * @v xhci xHCI device
  1454. */
  1455. static void xhci_event_poll ( struct xhci_device *xhci ) {
  1456. struct xhci_event_ring *event = &xhci->event;
  1457. union xhci_trb *trb;
  1458. unsigned int shift = XHCI_EVENT_TRBS_LOG2;
  1459. unsigned int count = ( 1 << shift );
  1460. unsigned int mask = ( count - 1 );
  1461. unsigned int consumed;
  1462. unsigned int type;
  1463. /* Poll for events */
  1464. profile_start ( &xhci_event_profiler );
  1465. for ( consumed = 0 ; ; consumed++ ) {
  1466. /* Stop if we reach an empty TRB */
  1467. rmb();
  1468. trb = &event->trb[ event->cons & mask ];
  1469. if ( ! ( ( trb->common.flags ^
  1470. ( event->cons >> shift ) ) & XHCI_TRB_C ) )
  1471. break;
  1472. /* Handle TRB */
  1473. type = ( trb->common.type & XHCI_TRB_TYPE_MASK );
  1474. switch ( type ) {
  1475. case XHCI_TRB_TRANSFER :
  1476. xhci_transfer ( xhci, &trb->transfer );
  1477. break;
  1478. case XHCI_TRB_COMPLETE :
  1479. xhci_complete ( xhci, &trb->complete );
  1480. break;
  1481. case XHCI_TRB_PORT_STATUS:
  1482. xhci_port_status ( xhci, &trb->port );
  1483. break;
  1484. case XHCI_TRB_HOST_CONTROLLER:
  1485. xhci_host_controller ( xhci, &trb->host );
  1486. break;
  1487. default:
  1488. DBGC ( xhci, "XHCI %p unrecognised event %#x\n:",
  1489. xhci, event->cons );
  1490. DBGC_HDA ( xhci, virt_to_phys ( trb ),
  1491. trb, sizeof ( *trb ) );
  1492. break;
  1493. }
  1494. /* Consume this TRB */
  1495. event->cons++;
  1496. }
  1497. /* Update dequeue pointer if applicable */
  1498. if ( consumed ) {
  1499. xhci_writeq ( xhci, virt_to_phys ( trb ),
  1500. xhci->run + XHCI_RUN_ERDP ( 0 ) );
  1501. profile_stop ( &xhci_event_profiler );
  1502. }
  1503. }
  1504. /**
  1505. * Abort command
  1506. *
  1507. * @v xhci xHCI device
  1508. */
  1509. static void xhci_abort ( struct xhci_device *xhci ) {
  1510. physaddr_t crp;
  1511. /* Abort the command */
  1512. DBGC2 ( xhci, "XHCI %p aborting command\n", xhci );
  1513. xhci_writeq ( xhci, XHCI_CRCR_CA, xhci->op + XHCI_OP_CRCR );
  1514. /* Allow time for command to abort */
  1515. mdelay ( XHCI_COMMAND_ABORT_DELAY_MS );
  1516. /* Sanity check */
  1517. assert ( ( readl ( xhci->op + XHCI_OP_CRCR ) & XHCI_CRCR_CRR ) == 0 );
  1518. /* Consume (and ignore) any final command status */
  1519. xhci_event_poll ( xhci );
  1520. /* Reset the command ring control register */
  1521. xhci_ring_reset ( &xhci->command );
  1522. crp = virt_to_phys ( xhci->command.trb );
  1523. xhci_writeq ( xhci, ( crp | XHCI_CRCR_RCS ), xhci->op + XHCI_OP_CRCR );
  1524. }
  1525. /**
  1526. * Issue command and wait for completion
  1527. *
  1528. * @v xhci xHCI device
  1529. * @v trb Transfer request block (with empty Cycle flag)
  1530. * @ret rc Return status code
  1531. *
  1532. * On a successful completion, the TRB will be overwritten with the
  1533. * completion.
  1534. */
  1535. static int xhci_command ( struct xhci_device *xhci, union xhci_trb *trb ) {
  1536. struct xhci_trb_complete *complete = &trb->complete;
  1537. unsigned int i;
  1538. int rc;
  1539. /* Record the pending command */
  1540. xhci->pending = trb;
  1541. /* Enqueue the command */
  1542. if ( ( rc = xhci_enqueue ( &xhci->command, NULL, trb ) ) != 0 )
  1543. goto err_enqueue;
  1544. /* Ring the command doorbell */
  1545. xhci_doorbell ( &xhci->command );
  1546. /* Wait for the command to complete */
  1547. for ( i = 0 ; i < XHCI_COMMAND_MAX_WAIT_MS ; i++ ) {
  1548. /* Poll event ring */
  1549. xhci_event_poll ( xhci );
  1550. /* Check for completion */
  1551. if ( ! xhci->pending ) {
  1552. if ( complete->code != XHCI_CMPLT_SUCCESS ) {
  1553. rc = -ECODE ( complete->code );
  1554. DBGC ( xhci, "XHCI %p command failed (code "
  1555. "%d): %s\n", xhci, complete->code,
  1556. strerror ( rc ) );
  1557. DBGC_HDA ( xhci, 0, trb, sizeof ( *trb ) );
  1558. return rc;
  1559. }
  1560. return 0;
  1561. }
  1562. /* Delay */
  1563. mdelay ( 1 );
  1564. }
  1565. /* Timeout */
  1566. DBGC ( xhci, "XHCI %p timed out waiting for completion\n", xhci );
  1567. rc = -ETIMEDOUT;
  1568. /* Abort command */
  1569. xhci_abort ( xhci );
  1570. err_enqueue:
  1571. xhci->pending = NULL;
  1572. return rc;
  1573. }
  1574. /**
  1575. * Issue NOP and wait for completion
  1576. *
  1577. * @v xhci xHCI device
  1578. * @ret rc Return status code
  1579. */
  1580. static inline int xhci_nop ( struct xhci_device *xhci ) {
  1581. union xhci_trb trb;
  1582. struct xhci_trb_common *nop = &trb.common;
  1583. int rc;
  1584. /* Construct command */
  1585. memset ( nop, 0, sizeof ( *nop ) );
  1586. nop->flags = XHCI_TRB_IOC;
  1587. nop->type = XHCI_TRB_NOP_CMD;
  1588. /* Issue command and wait for completion */
  1589. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 )
  1590. return rc;
  1591. return 0;
  1592. }
  1593. /**
  1594. * Enable slot
  1595. *
  1596. * @v xhci xHCI device
  1597. * @v type Slot type
  1598. * @ret slot Device slot ID, or negative error
  1599. */
  1600. static inline int xhci_enable_slot ( struct xhci_device *xhci,
  1601. unsigned int type ) {
  1602. union xhci_trb trb;
  1603. struct xhci_trb_enable_slot *enable = &trb.enable;
  1604. struct xhci_trb_complete *enabled = &trb.complete;
  1605. unsigned int slot;
  1606. int rc;
  1607. /* Construct command */
  1608. memset ( enable, 0, sizeof ( *enable ) );
  1609. enable->slot = type;
  1610. enable->type = XHCI_TRB_ENABLE_SLOT;
  1611. /* Issue command and wait for completion */
  1612. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 ) {
  1613. DBGC ( xhci, "XHCI %p could not enable new slot: %s\n",
  1614. xhci, strerror ( rc ) );
  1615. return rc;
  1616. }
  1617. /* Extract slot number */
  1618. slot = enabled->slot;
  1619. DBGC2 ( xhci, "XHCI %p slot %d enabled\n", xhci, slot );
  1620. return slot;
  1621. }
  1622. /**
  1623. * Disable slot
  1624. *
  1625. * @v xhci xHCI device
  1626. * @v slot Device slot
  1627. * @ret rc Return status code
  1628. */
  1629. static inline int xhci_disable_slot ( struct xhci_device *xhci,
  1630. unsigned int slot ) {
  1631. union xhci_trb trb;
  1632. struct xhci_trb_disable_slot *disable = &trb.disable;
  1633. int rc;
  1634. /* Construct command */
  1635. memset ( disable, 0, sizeof ( *disable ) );
  1636. disable->type = XHCI_TRB_DISABLE_SLOT;
  1637. disable->slot = slot;
  1638. /* Issue command and wait for completion */
  1639. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 ) {
  1640. DBGC ( xhci, "XHCI %p could not disable slot %d: %s\n",
  1641. xhci, slot, strerror ( rc ) );
  1642. return rc;
  1643. }
  1644. DBGC2 ( xhci, "XHCI %p slot %d disabled\n", xhci, slot );
  1645. return 0;
  1646. }
  1647. /**
  1648. * Issue context-based command and wait for completion
  1649. *
  1650. * @v xhci xHCI device
  1651. * @v slot Device slot
  1652. * @v endpoint Endpoint
  1653. * @v type TRB type
  1654. * @v populate Input context populater
  1655. * @ret rc Return status code
  1656. */
  1657. static int xhci_context ( struct xhci_device *xhci, struct xhci_slot *slot,
  1658. struct xhci_endpoint *endpoint, unsigned int type,
  1659. void ( * populate ) ( struct xhci_device *xhci,
  1660. struct xhci_slot *slot,
  1661. struct xhci_endpoint *endpoint,
  1662. void *input ) ) {
  1663. union xhci_trb trb;
  1664. struct xhci_trb_context *context = &trb.context;
  1665. size_t len;
  1666. void *input;
  1667. int rc;
  1668. /* Allocate an input context */
  1669. len = xhci_input_context_offset ( xhci, XHCI_CTX_END );
  1670. input = malloc_dma ( len, xhci_align ( len ) );
  1671. if ( ! input ) {
  1672. rc = -ENOMEM;
  1673. goto err_alloc;
  1674. }
  1675. memset ( input, 0, len );
  1676. /* Populate input context */
  1677. populate ( xhci, slot, endpoint, input );
  1678. /* Construct command */
  1679. memset ( context, 0, sizeof ( *context ) );
  1680. context->type = type;
  1681. context->input = cpu_to_le64 ( virt_to_phys ( input ) );
  1682. context->slot = slot->id;
  1683. /* Issue command and wait for completion */
  1684. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 )
  1685. goto err_command;
  1686. err_command:
  1687. free_dma ( input, len );
  1688. err_alloc:
  1689. return rc;
  1690. }
  1691. /**
  1692. * Populate address device input context
  1693. *
  1694. * @v xhci xHCI device
  1695. * @v slot Device slot
  1696. * @v endpoint Endpoint
  1697. * @v input Input context
  1698. */
  1699. static void xhci_address_device_input ( struct xhci_device *xhci,
  1700. struct xhci_slot *slot,
  1701. struct xhci_endpoint *endpoint,
  1702. void *input ) {
  1703. struct xhci_control_context *control_ctx;
  1704. struct xhci_slot_context *slot_ctx;
  1705. struct xhci_endpoint_context *ep_ctx;
  1706. /* Sanity checks */
  1707. assert ( endpoint->ctx == XHCI_CTX_EP0 );
  1708. /* Populate control context */
  1709. control_ctx = input;
  1710. control_ctx->add = cpu_to_le32 ( ( 1 << XHCI_CTX_SLOT ) |
  1711. ( 1 << XHCI_CTX_EP0 ) );
  1712. /* Populate slot context */
  1713. slot_ctx = ( input + xhci_input_context_offset ( xhci, XHCI_CTX_SLOT ));
  1714. slot_ctx->info = cpu_to_le32 ( XHCI_SLOT_INFO ( 1, 0, slot->psiv,
  1715. slot->route ) );
  1716. slot_ctx->port = slot->port;
  1717. /* Populate control endpoint context */
  1718. ep_ctx = ( input + xhci_input_context_offset ( xhci, XHCI_CTX_EP0 ) );
  1719. ep_ctx->type = XHCI_EP_TYPE_CONTROL;
  1720. ep_ctx->burst = endpoint->ep->burst;
  1721. ep_ctx->mtu = cpu_to_le16 ( endpoint->ep->mtu );
  1722. ep_ctx->dequeue = cpu_to_le64 ( virt_to_phys ( endpoint->ring.trb ) |
  1723. XHCI_EP_DCS );
  1724. ep_ctx->trb_len = cpu_to_le16 ( XHCI_EP0_TRB_LEN );
  1725. }
  1726. /**
  1727. * Address device
  1728. *
  1729. * @v xhci xHCI device
  1730. * @v slot Device slot
  1731. * @ret rc Return status code
  1732. */
  1733. static inline int xhci_address_device ( struct xhci_device *xhci,
  1734. struct xhci_slot *slot ) {
  1735. struct usb_device *usb = slot->usb;
  1736. struct xhci_slot_context *slot_ctx;
  1737. int rc;
  1738. /* Assign device address */
  1739. if ( ( rc = xhci_context ( xhci, slot, slot->endpoint[XHCI_CTX_EP0],
  1740. XHCI_TRB_ADDRESS_DEVICE,
  1741. xhci_address_device_input ) ) != 0 )
  1742. return rc;
  1743. /* Get assigned address */
  1744. slot_ctx = ( slot->context +
  1745. xhci_device_context_offset ( xhci, XHCI_CTX_SLOT ) );
  1746. usb->address = slot_ctx->address;
  1747. DBGC2 ( xhci, "XHCI %p assigned address %d to %s\n",
  1748. xhci, usb->address, usb->name );
  1749. return 0;
  1750. }
  1751. /**
  1752. * Populate configure endpoint input context
  1753. *
  1754. * @v xhci xHCI device
  1755. * @v slot Device slot
  1756. * @v endpoint Endpoint
  1757. * @v input Input context
  1758. */
  1759. static void xhci_configure_endpoint_input ( struct xhci_device *xhci,
  1760. struct xhci_slot *slot __unused,
  1761. struct xhci_endpoint *endpoint,
  1762. void *input ) {
  1763. struct xhci_control_context *control_ctx;
  1764. struct xhci_slot_context *slot_ctx;
  1765. struct xhci_endpoint_context *ep_ctx;
  1766. /* Populate control context */
  1767. control_ctx = input;
  1768. control_ctx->add = cpu_to_le32 ( ( 1 << XHCI_CTX_SLOT ) |
  1769. ( 1 << endpoint->ctx ) );
  1770. /* Populate slot context */
  1771. slot_ctx = ( input + xhci_input_context_offset ( xhci, XHCI_CTX_SLOT ));
  1772. slot_ctx->info = cpu_to_le32 ( XHCI_SLOT_INFO ( ( XHCI_CTX_END - 1 ),
  1773. 0, 0, 0 ) );
  1774. /* Populate endpoint context */
  1775. ep_ctx = ( input + xhci_input_context_offset ( xhci, endpoint->ctx ) );
  1776. ep_ctx->interval = endpoint->interval;
  1777. ep_ctx->type = endpoint->type;
  1778. ep_ctx->burst = endpoint->ep->burst;
  1779. ep_ctx->mtu = cpu_to_le16 ( endpoint->ep->mtu );
  1780. ep_ctx->dequeue = cpu_to_le64 ( virt_to_phys ( endpoint->ring.trb ) |
  1781. XHCI_EP_DCS );
  1782. ep_ctx->trb_len = cpu_to_le16 ( endpoint->ep->mtu ); /* best guess */
  1783. }
  1784. /**
  1785. * Configure endpoint
  1786. *
  1787. * @v xhci xHCI device
  1788. * @v slot Device slot
  1789. * @v endpoint Endpoint
  1790. * @ret rc Return status code
  1791. */
  1792. static inline int xhci_configure_endpoint ( struct xhci_device *xhci,
  1793. struct xhci_slot *slot,
  1794. struct xhci_endpoint *endpoint ) {
  1795. int rc;
  1796. /* Configure endpoint */
  1797. if ( ( rc = xhci_context ( xhci, slot, endpoint,
  1798. XHCI_TRB_CONFIGURE_ENDPOINT,
  1799. xhci_configure_endpoint_input ) ) != 0 )
  1800. return rc;
  1801. DBGC2 ( xhci, "XHCI %p slot %d ctx %d configured\n",
  1802. xhci, slot->id, endpoint->ctx );
  1803. return 0;
  1804. }
  1805. /**
  1806. * Populate deconfigure endpoint input context
  1807. *
  1808. * @v xhci xHCI device
  1809. * @v slot Device slot
  1810. * @v endpoint Endpoint
  1811. * @v input Input context
  1812. */
  1813. static void
  1814. xhci_deconfigure_endpoint_input ( struct xhci_device *xhci __unused,
  1815. struct xhci_slot *slot __unused,
  1816. struct xhci_endpoint *endpoint,
  1817. void *input ) {
  1818. struct xhci_control_context *control_ctx;
  1819. struct xhci_slot_context *slot_ctx;
  1820. /* Populate control context */
  1821. control_ctx = input;
  1822. control_ctx->add = cpu_to_le32 ( 1 << XHCI_CTX_SLOT );
  1823. control_ctx->drop = cpu_to_le32 ( 1 << endpoint->ctx );
  1824. /* Populate slot context */
  1825. slot_ctx = ( input + xhci_input_context_offset ( xhci, XHCI_CTX_SLOT ));
  1826. slot_ctx->info = cpu_to_le32 ( XHCI_SLOT_INFO ( ( XHCI_CTX_END - 1 ),
  1827. 0, 0, 0 ) );
  1828. }
  1829. /**
  1830. * Deconfigure endpoint
  1831. *
  1832. * @v xhci xHCI device
  1833. * @v slot Device slot
  1834. * @v endpoint Endpoint
  1835. * @ret rc Return status code
  1836. */
  1837. static inline int xhci_deconfigure_endpoint ( struct xhci_device *xhci,
  1838. struct xhci_slot *slot,
  1839. struct xhci_endpoint *endpoint ) {
  1840. int rc;
  1841. /* Deconfigure endpoint */
  1842. if ( ( rc = xhci_context ( xhci, slot, endpoint,
  1843. XHCI_TRB_CONFIGURE_ENDPOINT,
  1844. xhci_deconfigure_endpoint_input ) ) != 0 )
  1845. return rc;
  1846. DBGC2 ( xhci, "XHCI %p slot %d ctx %d deconfigured\n",
  1847. xhci, slot->id, endpoint->ctx );
  1848. return 0;
  1849. }
  1850. /**
  1851. * Populate evaluate context input context
  1852. *
  1853. * @v xhci xHCI device
  1854. * @v slot Device slot
  1855. * @v endpoint Endpoint
  1856. * @v input Input context
  1857. */
  1858. static void xhci_evaluate_context_input ( struct xhci_device *xhci,
  1859. struct xhci_slot *slot __unused,
  1860. struct xhci_endpoint *endpoint,
  1861. void *input ) {
  1862. struct xhci_control_context *control_ctx;
  1863. struct xhci_slot_context *slot_ctx;
  1864. struct xhci_endpoint_context *ep_ctx;
  1865. /* Populate control context */
  1866. control_ctx = input;
  1867. control_ctx->add = cpu_to_le32 ( ( 1 << XHCI_CTX_SLOT ) |
  1868. ( 1 << endpoint->ctx ) );
  1869. /* Populate slot context */
  1870. slot_ctx = ( input + xhci_input_context_offset ( xhci, XHCI_CTX_SLOT ));
  1871. slot_ctx->info = cpu_to_le32 ( XHCI_SLOT_INFO ( ( XHCI_CTX_END - 1 ),
  1872. 0, 0, 0 ) );
  1873. /* Populate endpoint context */
  1874. ep_ctx = ( input + xhci_input_context_offset ( xhci, endpoint->ctx ) );
  1875. ep_ctx->mtu = cpu_to_le16 ( endpoint->ep->mtu );
  1876. }
  1877. /**
  1878. * Evaluate context
  1879. *
  1880. * @v xhci xHCI device
  1881. * @v slot Device slot
  1882. * @v endpoint Endpoint
  1883. * @ret rc Return status code
  1884. */
  1885. static inline int xhci_evaluate_context ( struct xhci_device *xhci,
  1886. struct xhci_slot *slot,
  1887. struct xhci_endpoint *endpoint ) {
  1888. int rc;
  1889. /* Configure endpoint */
  1890. if ( ( rc = xhci_context ( xhci, slot, endpoint,
  1891. XHCI_TRB_EVALUATE_CONTEXT,
  1892. xhci_evaluate_context_input ) ) != 0 )
  1893. return rc;
  1894. DBGC2 ( xhci, "XHCI %p slot %d ctx %d (re-)evaluated\n",
  1895. xhci, slot->id, endpoint->ctx );
  1896. return 0;
  1897. }
  1898. /**
  1899. * Reset endpoint
  1900. *
  1901. * @v xhci xHCI device
  1902. * @v slot Device slot
  1903. * @v endpoint Endpoint
  1904. * @ret rc Return status code
  1905. */
  1906. static inline int xhci_reset_endpoint ( struct xhci_device *xhci,
  1907. struct xhci_slot *slot,
  1908. struct xhci_endpoint *endpoint ) {
  1909. union xhci_trb trb;
  1910. struct xhci_trb_reset_endpoint *reset = &trb.reset;
  1911. int rc;
  1912. /* Construct command */
  1913. memset ( reset, 0, sizeof ( *reset ) );
  1914. reset->slot = slot->id;
  1915. reset->endpoint = endpoint->ctx;
  1916. reset->type = XHCI_TRB_RESET_ENDPOINT;
  1917. /* Issue command and wait for completion */
  1918. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 ) {
  1919. DBGC ( xhci, "XHCI %p slot %d ctx %d could not reset endpoint "
  1920. "in state %d: %s\n", xhci, slot->id, endpoint->ctx,
  1921. endpoint->context->state, strerror ( rc ) );
  1922. return rc;
  1923. }
  1924. return 0;
  1925. }
  1926. /**
  1927. * Stop endpoint
  1928. *
  1929. * @v xhci xHCI device
  1930. * @v slot Device slot
  1931. * @v endpoint Endpoint
  1932. * @ret rc Return status code
  1933. */
  1934. static inline int xhci_stop_endpoint ( struct xhci_device *xhci,
  1935. struct xhci_slot *slot,
  1936. struct xhci_endpoint *endpoint ) {
  1937. union xhci_trb trb;
  1938. struct xhci_trb_stop_endpoint *stop = &trb.stop;
  1939. int rc;
  1940. /* Construct command */
  1941. memset ( stop, 0, sizeof ( *stop ) );
  1942. stop->slot = slot->id;
  1943. stop->endpoint = endpoint->ctx;
  1944. stop->type = XHCI_TRB_STOP_ENDPOINT;
  1945. /* Issue command and wait for completion */
  1946. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 ) {
  1947. DBGC ( xhci, "XHCI %p slot %d ctx %d could not stop endpoint "
  1948. "in state %d: %s\n", xhci, slot->id, endpoint->ctx,
  1949. endpoint->context->state, strerror ( rc ) );
  1950. return rc;
  1951. }
  1952. return 0;
  1953. }
  1954. /**
  1955. * Set transfer ring dequeue pointer
  1956. *
  1957. * @v xhci xHCI device
  1958. * @v slot Device slot
  1959. * @v endpoint Endpoint
  1960. * @ret rc Return status code
  1961. */
  1962. static inline int
  1963. xhci_set_tr_dequeue_pointer ( struct xhci_device *xhci,
  1964. struct xhci_slot *slot,
  1965. struct xhci_endpoint *endpoint ) {
  1966. union xhci_trb trb;
  1967. struct xhci_trb_set_tr_dequeue_pointer *dequeue = &trb.dequeue;
  1968. struct xhci_trb_ring *ring = &endpoint->ring;
  1969. unsigned int cons;
  1970. unsigned int mask;
  1971. unsigned int index;
  1972. unsigned int dcs;
  1973. int rc;
  1974. /* Construct command */
  1975. memset ( dequeue, 0, sizeof ( *dequeue ) );
  1976. cons = ring->cons;
  1977. mask = ring->mask;
  1978. dcs = ( ( ~( cons >> ring->shift ) ) & XHCI_EP_DCS );
  1979. index = ( cons & mask );
  1980. dequeue->dequeue =
  1981. cpu_to_le64 ( virt_to_phys ( &ring->trb[index] ) | dcs );
  1982. dequeue->slot = slot->id;
  1983. dequeue->endpoint = endpoint->ctx;
  1984. dequeue->type = XHCI_TRB_SET_TR_DEQUEUE_POINTER;
  1985. /* Issue command and wait for completion */
  1986. if ( ( rc = xhci_command ( xhci, &trb ) ) != 0 ) {
  1987. DBGC ( xhci, "XHCI %p slot %d ctx %d could not set TR dequeue "
  1988. "pointer in state %d: %s\n", xhci, slot->id,
  1989. endpoint->ctx, endpoint->context->state, strerror ( rc));
  1990. return rc;
  1991. }
  1992. return 0;
  1993. }
  1994. /******************************************************************************
  1995. *
  1996. * Endpoint operations
  1997. *
  1998. ******************************************************************************
  1999. */
  2000. /**
  2001. * Open endpoint
  2002. *
  2003. * @v ep USB endpoint
  2004. * @ret rc Return status code
  2005. */
  2006. static int xhci_endpoint_open ( struct usb_endpoint *ep ) {
  2007. struct usb_device *usb = ep->usb;
  2008. struct xhci_slot *slot = usb_get_hostdata ( usb );
  2009. struct xhci_device *xhci = slot->xhci;
  2010. struct xhci_endpoint *endpoint;
  2011. unsigned int ctx;
  2012. unsigned int type;
  2013. unsigned int interval;
  2014. int rc;
  2015. /* Calculate context index */
  2016. ctx = XHCI_CTX ( ep->address );
  2017. assert ( slot->endpoint[ctx] == NULL );
  2018. /* Calculate endpoint type */
  2019. type = XHCI_EP_TYPE ( ep->attributes & USB_ENDPOINT_ATTR_TYPE_MASK );
  2020. if ( type == XHCI_EP_TYPE ( USB_ENDPOINT_ATTR_CONTROL ) )
  2021. type = XHCI_EP_TYPE_CONTROL;
  2022. if ( ep->address & USB_DIR_IN )
  2023. type |= XHCI_EP_TYPE_IN;
  2024. /* Calculate interval */
  2025. if ( type & XHCI_EP_TYPE_PERIODIC ) {
  2026. interval = ( fls ( ep->interval ) - 1 );
  2027. } else {
  2028. interval = ep->interval;
  2029. }
  2030. /* Allocate and initialise structure */
  2031. endpoint = zalloc ( sizeof ( *endpoint ) );
  2032. if ( ! endpoint ) {
  2033. rc = -ENOMEM;
  2034. goto err_alloc;
  2035. }
  2036. usb_endpoint_set_hostdata ( ep, endpoint );
  2037. slot->endpoint[ctx] = endpoint;
  2038. endpoint->xhci = xhci;
  2039. endpoint->slot = slot;
  2040. endpoint->ep = ep;
  2041. endpoint->ctx = ctx;
  2042. endpoint->type = type;
  2043. endpoint->interval = interval;
  2044. endpoint->context = ( ( ( void * ) slot->context ) +
  2045. xhci_device_context_offset ( xhci, ctx ) );
  2046. /* Allocate transfer ring */
  2047. if ( ( rc = xhci_ring_alloc ( xhci, &endpoint->ring,
  2048. XHCI_TRANSFER_TRBS_LOG2,
  2049. slot->id, ctx, 0 ) ) != 0 )
  2050. goto err_ring_alloc;
  2051. /* Configure endpoint, if applicable */
  2052. if ( ( ctx != XHCI_CTX_EP0 ) &&
  2053. ( ( rc = xhci_configure_endpoint ( xhci, slot, endpoint ) ) != 0 ))
  2054. goto err_configure_endpoint;
  2055. DBGC2 ( xhci, "XHCI %p slot %d ctx %d ring [%08lx,%08lx)\n",
  2056. xhci, slot->id, ctx, virt_to_phys ( endpoint->ring.trb ),
  2057. ( virt_to_phys ( endpoint->ring.trb ) + endpoint->ring.len ) );
  2058. return 0;
  2059. xhci_deconfigure_endpoint ( xhci, slot, endpoint );
  2060. err_configure_endpoint:
  2061. xhci_ring_free ( &endpoint->ring );
  2062. err_ring_alloc:
  2063. slot->endpoint[ctx] = NULL;
  2064. free ( endpoint );
  2065. err_alloc:
  2066. return rc;
  2067. }
  2068. /**
  2069. * Close endpoint
  2070. *
  2071. * @v ep USB endpoint
  2072. */
  2073. static void xhci_endpoint_close ( struct usb_endpoint *ep ) {
  2074. struct xhci_endpoint *endpoint = usb_endpoint_get_hostdata ( ep );
  2075. struct xhci_slot *slot = endpoint->slot;
  2076. struct xhci_device *xhci = slot->xhci;
  2077. struct io_buffer *iobuf;
  2078. unsigned int ctx = endpoint->ctx;
  2079. /* Deconfigure endpoint, if applicable */
  2080. if ( ctx != XHCI_CTX_EP0 )
  2081. xhci_deconfigure_endpoint ( xhci, slot, endpoint );
  2082. /* Cancel any incomplete transfers */
  2083. while ( xhci_ring_fill ( &endpoint->ring ) ) {
  2084. iobuf = xhci_dequeue_multi ( &endpoint->ring );
  2085. usb_complete_err ( ep, iobuf, -ECANCELED );
  2086. }
  2087. /* Free endpoint */
  2088. xhci_ring_free ( &endpoint->ring );
  2089. slot->endpoint[ctx] = NULL;
  2090. free ( endpoint );
  2091. }
  2092. /**
  2093. * Reset endpoint
  2094. *
  2095. * @v ep USB endpoint
  2096. * @ret rc Return status code
  2097. */
  2098. static int xhci_endpoint_reset ( struct usb_endpoint *ep ) {
  2099. struct xhci_endpoint *endpoint = usb_endpoint_get_hostdata ( ep );
  2100. struct xhci_slot *slot = endpoint->slot;
  2101. struct xhci_device *xhci = slot->xhci;
  2102. int rc;
  2103. /* Reset endpoint context */
  2104. if ( ( rc = xhci_reset_endpoint ( xhci, slot, endpoint ) ) != 0 )
  2105. return rc;
  2106. /* Set transfer ring dequeue pointer */
  2107. if ( ( rc = xhci_set_tr_dequeue_pointer ( xhci, slot, endpoint ) ) != 0)
  2108. return rc;
  2109. DBGC ( xhci, "XHCI %p slot %d ctx %d reset\n",
  2110. xhci, slot->id, endpoint->ctx );
  2111. return 0;
  2112. }
  2113. /**
  2114. * Update MTU
  2115. *
  2116. * @v ep USB endpoint
  2117. * @ret rc Return status code
  2118. */
  2119. static int xhci_endpoint_mtu ( struct usb_endpoint *ep ) {
  2120. struct xhci_endpoint *endpoint = usb_endpoint_get_hostdata ( ep );
  2121. struct xhci_slot *slot = endpoint->slot;
  2122. struct xhci_device *xhci = slot->xhci;
  2123. int rc;
  2124. /* Evalulate context */
  2125. if ( ( rc = xhci_evaluate_context ( xhci, slot, endpoint ) ) != 0 )
  2126. return rc;
  2127. return 0;
  2128. }
  2129. /**
  2130. * Enqueue message transfer
  2131. *
  2132. * @v ep USB endpoint
  2133. * @v packet Setup packet
  2134. * @v iobuf I/O buffer
  2135. * @ret rc Return status code
  2136. */
  2137. static int xhci_endpoint_message ( struct usb_endpoint *ep,
  2138. struct usb_setup_packet *packet,
  2139. struct io_buffer *iobuf ) {
  2140. struct xhci_endpoint *endpoint = usb_endpoint_get_hostdata ( ep );
  2141. unsigned int input = ( le16_to_cpu ( packet->request ) & USB_DIR_IN );
  2142. size_t len = iob_len ( iobuf );
  2143. union xhci_trb trbs[ 1 /* setup */ + 1 /* possible data */ +
  2144. 1 /* status */ ];
  2145. union xhci_trb *trb = trbs;
  2146. struct xhci_trb_setup *setup;
  2147. struct xhci_trb_data *data;
  2148. struct xhci_trb_status *status;
  2149. int rc;
  2150. /* Profile message transfers */
  2151. profile_start ( &xhci_message_profiler );
  2152. /* Construct setup stage TRB */
  2153. memset ( trbs, 0, sizeof ( trbs ) );
  2154. setup = &(trb++)->setup;
  2155. memcpy ( &setup->packet, packet, sizeof ( setup->packet ) );
  2156. setup->len = cpu_to_le32 ( sizeof ( *packet ) );
  2157. setup->flags = XHCI_TRB_IDT;
  2158. setup->type = XHCI_TRB_SETUP;
  2159. if ( len )
  2160. setup->direction = ( input ? XHCI_SETUP_IN : XHCI_SETUP_OUT );
  2161. /* Construct data stage TRB, if applicable */
  2162. if ( len ) {
  2163. data = &(trb++)->data;
  2164. data->data = cpu_to_le64 ( virt_to_phys ( iobuf->data ) );
  2165. data->len = cpu_to_le32 ( len );
  2166. data->type = XHCI_TRB_DATA;
  2167. data->direction = ( input ? XHCI_DATA_IN : XHCI_DATA_OUT );
  2168. }
  2169. /* Construct status stage TRB */
  2170. status = &(trb++)->status;
  2171. status->flags = XHCI_TRB_IOC;
  2172. status->type = XHCI_TRB_STATUS;
  2173. status->direction =
  2174. ( ( len && input ) ? XHCI_STATUS_OUT : XHCI_STATUS_IN );
  2175. /* Enqueue TRBs */
  2176. if ( ( rc = xhci_enqueue_multi ( &endpoint->ring, iobuf, trbs,
  2177. ( trb - trbs ) ) ) != 0 )
  2178. return rc;
  2179. /* Ring the doorbell */
  2180. xhci_doorbell ( &endpoint->ring );
  2181. profile_stop ( &xhci_message_profiler );
  2182. return 0;
  2183. }
  2184. /**
  2185. * Enqueue stream transfer
  2186. *
  2187. * @v ep USB endpoint
  2188. * @v iobuf I/O buffer
  2189. * @v terminate Terminate using a short packet
  2190. * @ret rc Return status code
  2191. */
  2192. static int xhci_endpoint_stream ( struct usb_endpoint *ep,
  2193. struct io_buffer *iobuf, int terminate ) {
  2194. struct xhci_endpoint *endpoint = usb_endpoint_get_hostdata ( ep );
  2195. union xhci_trb trbs[ 1 /* Normal */ + 1 /* Possible zero-length */ ];
  2196. union xhci_trb *trb = trbs;
  2197. struct xhci_trb_normal *normal;
  2198. size_t len = iob_len ( iobuf );
  2199. int rc;
  2200. /* Profile stream transfers */
  2201. profile_start ( &xhci_stream_profiler );
  2202. /* Construct normal TRBs */
  2203. memset ( &trbs, 0, sizeof ( trbs ) );
  2204. normal = &(trb++)->normal;
  2205. normal->data = cpu_to_le64 ( virt_to_phys ( iobuf->data ) );
  2206. normal->len = cpu_to_le32 ( len );
  2207. normal->type = XHCI_TRB_NORMAL;
  2208. if ( terminate && ( ( len & ( ep->mtu - 1 ) ) == 0 ) ) {
  2209. normal->flags = XHCI_TRB_CH;
  2210. normal = &(trb++)->normal;
  2211. normal->type = XHCI_TRB_NORMAL;
  2212. }
  2213. normal->flags = XHCI_TRB_IOC;
  2214. /* Enqueue TRBs */
  2215. if ( ( rc = xhci_enqueue_multi ( &endpoint->ring, iobuf, trbs,
  2216. ( trb - trbs ) ) ) != 0 )
  2217. return rc;
  2218. /* Ring the doorbell */
  2219. xhci_doorbell ( &endpoint->ring );
  2220. profile_stop ( &xhci_stream_profiler );
  2221. return 0;
  2222. }
  2223. /******************************************************************************
  2224. *
  2225. * Device operations
  2226. *
  2227. ******************************************************************************
  2228. */
  2229. /**
  2230. * Open device
  2231. *
  2232. * @v usb USB device
  2233. * @ret rc Return status code
  2234. */
  2235. static int xhci_device_open ( struct usb_device *usb ) {
  2236. struct xhci_device *xhci = usb_bus_get_hostdata ( usb->port->hub->bus );
  2237. struct xhci_slot *slot;
  2238. size_t len;
  2239. int type;
  2240. int id;
  2241. int rc;
  2242. /* Determine applicable slot type */
  2243. type = xhci_port_slot_type ( xhci, usb->port->address );
  2244. if ( type < 0 ) {
  2245. rc = type;
  2246. DBGC ( xhci, "XHCI %p port %d has no slot type\n",
  2247. xhci, usb->port->address );
  2248. goto err_type;
  2249. }
  2250. /* Allocate a device slot number */
  2251. id = xhci_enable_slot ( xhci, type );
  2252. if ( id < 0 ) {
  2253. rc = id;
  2254. goto err_enable_slot;
  2255. }
  2256. assert ( xhci->slot[id] == NULL );
  2257. /* Allocate and initialise structure */
  2258. slot = zalloc ( sizeof ( *slot ) );
  2259. if ( ! slot ) {
  2260. rc = -ENOMEM;
  2261. goto err_alloc;
  2262. }
  2263. usb_set_hostdata ( usb, slot );
  2264. xhci->slot[id] = slot;
  2265. slot->xhci = xhci;
  2266. slot->usb = usb;
  2267. slot->id = id;
  2268. /* Allocate a device context */
  2269. len = xhci_device_context_offset ( xhci, XHCI_CTX_END );
  2270. slot->context = malloc_dma ( len, xhci_align ( len ) );
  2271. if ( ! slot->context ) {
  2272. rc = -ENOMEM;
  2273. goto err_alloc_context;
  2274. }
  2275. memset ( slot->context, 0, len );
  2276. /* Set device context base address */
  2277. assert ( xhci->dcbaa[id] == 0 );
  2278. xhci->dcbaa[id] = cpu_to_le64 ( virt_to_phys ( slot->context ) );
  2279. DBGC2 ( xhci, "XHCI %p slot %d device context [%08lx,%08lx) for %s\n",
  2280. xhci, slot->id, virt_to_phys ( slot->context ),
  2281. ( virt_to_phys ( slot->context ) + len ), usb->name );
  2282. return 0;
  2283. xhci->dcbaa[id] = 0;
  2284. free_dma ( slot->context, len );
  2285. err_alloc_context:
  2286. xhci->slot[id] = NULL;
  2287. free ( slot );
  2288. err_alloc:
  2289. xhci_disable_slot ( xhci, id );
  2290. err_enable_slot:
  2291. err_type:
  2292. return rc;
  2293. }
  2294. /**
  2295. * Close device
  2296. *
  2297. * @v usb USB device
  2298. */
  2299. static void xhci_device_close ( struct usb_device *usb ) {
  2300. struct xhci_slot *slot = usb_get_hostdata ( usb );
  2301. struct xhci_device *xhci = slot->xhci;
  2302. size_t len = xhci_device_context_offset ( xhci, XHCI_CTX_END );
  2303. unsigned int id = slot->id;
  2304. int rc;
  2305. /* Disable slot */
  2306. if ( ( rc = xhci_disable_slot ( xhci, id ) ) != 0 ) {
  2307. /* Slot is still enabled. Leak the slot context,
  2308. * since the controller may still write to this
  2309. * memory, and leave the DCBAA entry intact.
  2310. *
  2311. * If the controller later reports that this same slot
  2312. * has been re-enabled, then some assertions will be
  2313. * triggered.
  2314. */
  2315. DBGC ( xhci, "XHCI %p slot %d leaking context memory\n",
  2316. xhci, slot->id );
  2317. slot->context = NULL;
  2318. }
  2319. /* Free slot */
  2320. if ( slot->context ) {
  2321. free_dma ( slot->context, len );
  2322. xhci->dcbaa[id] = 0;
  2323. }
  2324. xhci->slot[id] = NULL;
  2325. free ( slot );
  2326. }
  2327. /**
  2328. * Assign device address
  2329. *
  2330. * @v usb USB device
  2331. * @ret rc Return status code
  2332. */
  2333. static int xhci_device_address ( struct usb_device *usb ) {
  2334. struct xhci_slot *slot = usb_get_hostdata ( usb );
  2335. struct xhci_device *xhci = slot->xhci;
  2336. struct usb_port *port = usb->port;
  2337. struct usb_port *root_port;
  2338. int psiv;
  2339. int rc;
  2340. /* Calculate route string */
  2341. slot->route = usb_route_string ( usb );
  2342. /* Calculate root hub port number */
  2343. root_port = usb_root_hub_port ( usb );
  2344. slot->port = root_port->address;
  2345. /* Calculate protocol speed ID */
  2346. psiv = xhci_port_psiv ( xhci, slot->port, port->speed );
  2347. if ( psiv < 0 ) {
  2348. rc = psiv;
  2349. return rc;
  2350. }
  2351. slot->psiv = psiv;
  2352. /* Address device */
  2353. if ( ( rc = xhci_address_device ( xhci, slot ) ) != 0 )
  2354. return rc;
  2355. return 0;
  2356. }
  2357. /******************************************************************************
  2358. *
  2359. * Bus operations
  2360. *
  2361. ******************************************************************************
  2362. */
  2363. /**
  2364. * Open USB bus
  2365. *
  2366. * @v bus USB bus
  2367. * @ret rc Return status code
  2368. */
  2369. static int xhci_bus_open ( struct usb_bus *bus ) {
  2370. struct xhci_device *xhci = usb_bus_get_hostdata ( bus );
  2371. int rc;
  2372. /* Allocate device slot array */
  2373. xhci->slot = zalloc ( xhci->slots * sizeof ( xhci->slot[0] ) );
  2374. if ( ! xhci->slot ) {
  2375. rc = -ENOMEM;
  2376. goto err_slot_alloc;
  2377. }
  2378. /* Allocate device context base address array */
  2379. if ( ( rc = xhci_dcbaa_alloc ( xhci ) ) != 0 )
  2380. goto err_dcbaa_alloc;
  2381. /* Allocate scratchpad buffers */
  2382. if ( ( rc = xhci_scratchpad_alloc ( xhci ) ) != 0 )
  2383. goto err_scratchpad_alloc;
  2384. /* Allocate command ring */
  2385. if ( ( rc = xhci_command_alloc ( xhci ) ) != 0 )
  2386. goto err_command_alloc;
  2387. /* Allocate event ring */
  2388. if ( ( rc = xhci_event_alloc ( xhci ) ) != 0 )
  2389. goto err_event_alloc;
  2390. /* Start controller */
  2391. xhci_run ( xhci );
  2392. return 0;
  2393. xhci_stop ( xhci );
  2394. xhci_event_free ( xhci );
  2395. err_event_alloc:
  2396. xhci_command_free ( xhci );
  2397. err_command_alloc:
  2398. xhci_scratchpad_free ( xhci );
  2399. err_scratchpad_alloc:
  2400. xhci_dcbaa_free ( xhci );
  2401. err_dcbaa_alloc:
  2402. free ( xhci->slot );
  2403. err_slot_alloc:
  2404. return rc;
  2405. }
  2406. /**
  2407. * Close USB bus
  2408. *
  2409. * @v bus USB bus
  2410. */
  2411. static void xhci_bus_close ( struct usb_bus *bus ) {
  2412. struct xhci_device *xhci = usb_bus_get_hostdata ( bus );
  2413. unsigned int i;
  2414. /* Sanity checks */
  2415. assert ( xhci->slot != NULL );
  2416. for ( i = 0 ; i < xhci->slots ; i++ )
  2417. assert ( xhci->slot[i] == NULL );
  2418. xhci_stop ( xhci );
  2419. xhci_event_free ( xhci );
  2420. xhci_command_free ( xhci );
  2421. xhci_scratchpad_free ( xhci );
  2422. xhci_dcbaa_free ( xhci );
  2423. free ( xhci->slot );
  2424. }
  2425. /**
  2426. * Poll USB bus
  2427. *
  2428. * @v bus USB bus
  2429. */
  2430. static void xhci_bus_poll ( struct usb_bus *bus ) {
  2431. struct xhci_device *xhci = usb_bus_get_hostdata ( bus );
  2432. /* Poll event ring */
  2433. xhci_event_poll ( xhci );
  2434. }
  2435. /******************************************************************************
  2436. *
  2437. * Root hub operations
  2438. *
  2439. ******************************************************************************
  2440. */
  2441. /**
  2442. * Open root hub
  2443. *
  2444. * @v hub USB hub
  2445. * @ret rc Return status code
  2446. */
  2447. static int xhci_hub_open ( struct usb_hub *hub ) {
  2448. struct usb_bus *bus = hub->bus;
  2449. struct xhci_device *xhci = usb_bus_get_hostdata ( bus );
  2450. struct usb_port *port;
  2451. uint32_t portsc;
  2452. unsigned int i;
  2453. /* Enable power to all ports */
  2454. for ( i = 1 ; i <= xhci->ports ; i++ ) {
  2455. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( i ) );
  2456. portsc &= XHCI_PORTSC_PRESERVE;
  2457. portsc |= XHCI_PORTSC_PP;
  2458. writel ( portsc, xhci->op + XHCI_OP_PORTSC ( i ) );
  2459. }
  2460. /* xHCI spec requires us to potentially wait 20ms after
  2461. * enabling power to a port.
  2462. */
  2463. mdelay ( XHCI_PORT_POWER_DELAY_MS );
  2464. /* USB3 ports may power up as Disabled */
  2465. for ( i = 1 ; i <= xhci->ports ; i++ ) {
  2466. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( i ) );
  2467. port = usb_port ( hub, i );
  2468. if ( ( port->protocol >= USB_PROTO_3_0 ) &&
  2469. ( ( portsc & XHCI_PORTSC_PLS_MASK ) ==
  2470. XHCI_PORTSC_PLS_DISABLED ) ) {
  2471. /* Force link state to RxDetect */
  2472. portsc &= XHCI_PORTSC_PRESERVE;
  2473. portsc |= ( XHCI_PORTSC_PLS_RXDETECT | XHCI_PORTSC_LWS);
  2474. writel ( portsc, xhci->op + XHCI_OP_PORTSC ( i ) );
  2475. }
  2476. }
  2477. /* Some xHCI cards seem to require an additional delay after
  2478. * setting the link state to RxDetect.
  2479. */
  2480. mdelay ( XHCI_LINK_STATE_DELAY_MS );
  2481. /* Record hub driver private data */
  2482. usb_hub_set_drvdata ( hub, xhci );
  2483. return 0;
  2484. }
  2485. /**
  2486. * Close root hub
  2487. *
  2488. * @v hub USB hub
  2489. */
  2490. static void xhci_hub_close ( struct usb_hub *hub ) {
  2491. /* Clear hub driver private data */
  2492. usb_hub_set_drvdata ( hub, NULL );
  2493. }
  2494. /**
  2495. * Enable port
  2496. *
  2497. * @v hub USB hub
  2498. * @v port USB port
  2499. * @ret rc Return status code
  2500. */
  2501. static int xhci_hub_enable ( struct usb_hub *hub, struct usb_port *port ) {
  2502. struct xhci_device *xhci = usb_hub_get_drvdata ( hub );
  2503. uint32_t portsc;
  2504. unsigned int i;
  2505. /* Reset port if applicable */
  2506. if ( port->protocol < USB_PROTO_3_0 ) {
  2507. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2508. portsc &= XHCI_PORTSC_PRESERVE;
  2509. portsc |= XHCI_PORTSC_PR;
  2510. writel ( portsc, xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2511. }
  2512. /* Wait for port to become enabled */
  2513. for ( i = 0 ; i < XHCI_PORT_RESET_MAX_WAIT_MS ; i++ ) {
  2514. /* Check port status */
  2515. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2516. if ( portsc & XHCI_PORTSC_PED )
  2517. return 0;
  2518. /* Delay */
  2519. mdelay ( 1 );
  2520. }
  2521. DBGC ( xhci, "XHCI %p timed out waiting for port %d to enable\n",
  2522. xhci, port->address );
  2523. return -ETIMEDOUT;
  2524. }
  2525. /**
  2526. * Disable port
  2527. *
  2528. * @v hub USB hub
  2529. * @v port USB port
  2530. * @ret rc Return status code
  2531. */
  2532. static int xhci_hub_disable ( struct usb_hub *hub, struct usb_port *port ) {
  2533. struct xhci_device *xhci = usb_hub_get_drvdata ( hub );
  2534. uint32_t portsc;
  2535. /* Disable port */
  2536. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2537. portsc &= XHCI_PORTSC_PRESERVE;
  2538. portsc |= XHCI_PORTSC_PED;
  2539. writel ( portsc, xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2540. return 0;
  2541. }
  2542. /**
  2543. * Update root hub port speed
  2544. *
  2545. * @v hub USB hub
  2546. * @v port USB port
  2547. * @ret rc Return status code
  2548. */
  2549. static int xhci_hub_speed ( struct usb_hub *hub, struct usb_port *port ) {
  2550. struct xhci_device *xhci = usb_hub_get_drvdata ( hub );
  2551. uint32_t portsc;
  2552. unsigned int psiv;
  2553. int ccs;
  2554. int ped;
  2555. int speed;
  2556. int rc;
  2557. /* Read port status */
  2558. portsc = readl ( xhci->op + XHCI_OP_PORTSC ( port->address ) );
  2559. DBGC2 ( xhci, "XHCI %p port %d status is %08x\n",
  2560. xhci, port->address, portsc );
  2561. /* Check whether or not port is connected */
  2562. ccs = ( portsc & XHCI_PORTSC_CCS );
  2563. if ( ! ccs ) {
  2564. port->speed = USB_SPEED_NONE;
  2565. return 0;
  2566. }
  2567. /* For USB2 ports, the PSIV field is not valid until the port
  2568. * completes reset and becomes enabled.
  2569. */
  2570. ped = ( portsc & XHCI_PORTSC_PED );
  2571. if ( ( port->protocol < USB_PROTO_3_0 ) && ! ped ) {
  2572. port->speed = USB_SPEED_FULL;
  2573. return 0;
  2574. }
  2575. /* Get port speed and map to generic USB speed */
  2576. psiv = XHCI_PORTSC_PSIV ( portsc );
  2577. speed = xhci_port_speed ( xhci, port->address, psiv );
  2578. if ( speed < 0 ) {
  2579. rc = speed;
  2580. return rc;
  2581. }
  2582. port->speed = speed;
  2583. return 0;
  2584. }
  2585. /******************************************************************************
  2586. *
  2587. * PCI interface
  2588. *
  2589. ******************************************************************************
  2590. */
  2591. /** USB host controller operations */
  2592. static struct usb_host_operations xhci_operations = {
  2593. .endpoint = {
  2594. .open = xhci_endpoint_open,
  2595. .close = xhci_endpoint_close,
  2596. .reset = xhci_endpoint_reset,
  2597. .mtu = xhci_endpoint_mtu,
  2598. .message = xhci_endpoint_message,
  2599. .stream = xhci_endpoint_stream,
  2600. },
  2601. .device = {
  2602. .open = xhci_device_open,
  2603. .close = xhci_device_close,
  2604. .address = xhci_device_address,
  2605. },
  2606. .bus = {
  2607. .open = xhci_bus_open,
  2608. .close = xhci_bus_close,
  2609. .poll = xhci_bus_poll,
  2610. },
  2611. .hub = {
  2612. .open = xhci_hub_open,
  2613. .close = xhci_hub_close,
  2614. .enable = xhci_hub_enable,
  2615. .disable = xhci_hub_disable,
  2616. .speed = xhci_hub_speed,
  2617. },
  2618. };
  2619. /**
  2620. * Probe PCI device
  2621. *
  2622. * @v pci PCI device
  2623. * @ret rc Return status code
  2624. */
  2625. static int xhci_probe ( struct pci_device *pci ) {
  2626. struct xhci_device *xhci;
  2627. struct usb_port *port;
  2628. unsigned long bar_start;
  2629. size_t bar_size;
  2630. unsigned int i;
  2631. int rc;
  2632. /* Allocate and initialise structure */
  2633. xhci = zalloc ( sizeof ( *xhci ) );
  2634. if ( ! xhci ) {
  2635. rc = -ENOMEM;
  2636. goto err_alloc;
  2637. }
  2638. /* Fix up PCI device */
  2639. adjust_pci_device ( pci );
  2640. /* Map registers */
  2641. bar_start = pci_bar_start ( pci, XHCI_BAR );
  2642. bar_size = pci_bar_size ( pci, XHCI_BAR );
  2643. xhci->regs = ioremap ( bar_start, bar_size );
  2644. if ( ! xhci->regs ) {
  2645. rc = -ENODEV;
  2646. goto err_ioremap;
  2647. }
  2648. /* Initialise xHCI device */
  2649. xhci_init ( xhci, xhci->regs );
  2650. /* Initialise USB legacy support and claim ownership */
  2651. xhci_legacy_init ( xhci );
  2652. if ( ( rc = xhci_legacy_claim ( xhci ) ) != 0 )
  2653. goto err_legacy_claim;
  2654. /* Reset device */
  2655. if ( ( rc = xhci_reset ( xhci ) ) != 0 )
  2656. goto err_reset;
  2657. /* Allocate USB bus */
  2658. xhci->bus = alloc_usb_bus ( &pci->dev, xhci->ports,
  2659. &xhci_operations );
  2660. if ( ! xhci->bus ) {
  2661. rc = -ENOMEM;
  2662. goto err_alloc_bus;
  2663. }
  2664. usb_bus_set_hostdata ( xhci->bus, xhci );
  2665. usb_hub_set_drvdata ( xhci->bus->hub, xhci );
  2666. /* Set port protocols */
  2667. for ( i = 1 ; i <= xhci->ports ; i++ ) {
  2668. port = usb_port ( xhci->bus->hub, i );
  2669. port->protocol = xhci_port_protocol ( xhci, i );
  2670. }
  2671. /* Register USB bus */
  2672. if ( ( rc = register_usb_bus ( xhci->bus ) ) != 0 )
  2673. goto err_register;
  2674. pci_set_drvdata ( pci, xhci );
  2675. return 0;
  2676. unregister_usb_bus ( xhci->bus );
  2677. err_register:
  2678. free_usb_bus ( xhci->bus );
  2679. err_alloc_bus:
  2680. xhci_reset ( xhci );
  2681. err_reset:
  2682. xhci_legacy_release ( xhci );
  2683. err_legacy_claim:
  2684. iounmap ( xhci->regs );
  2685. err_ioremap:
  2686. free ( xhci );
  2687. err_alloc:
  2688. return rc;
  2689. }
  2690. /**
  2691. * Remove PCI device
  2692. *
  2693. * @v pci PCI device
  2694. */
  2695. static void xhci_remove ( struct pci_device *pci ) {
  2696. struct xhci_device *xhci = pci_get_drvdata ( pci );
  2697. struct usb_bus *bus = xhci->bus;
  2698. unregister_usb_bus ( bus );
  2699. free_usb_bus ( bus );
  2700. xhci_reset ( xhci );
  2701. xhci_legacy_release ( xhci );
  2702. iounmap ( xhci->regs );
  2703. free ( xhci );
  2704. }
  2705. /** XHCI PCI device IDs */
  2706. static struct pci_device_id xhci_ids[] = {
  2707. PCI_ROM ( 0xffff, 0xffff, "xhci", "xHCI", 0 ),
  2708. };
  2709. /** XHCI PCI driver */
  2710. struct pci_driver xhci_driver __pci_driver = {
  2711. .ids = xhci_ids,
  2712. .id_count = ( sizeof ( xhci_ids ) / sizeof ( xhci_ids[0] ) ),
  2713. .class = PCI_CLASS ( PCI_CLASS_SERIAL, PCI_CLASS_SERIAL_USB,
  2714. PCI_CLASS_SERIAL_USB_XHCI ),
  2715. .probe = xhci_probe,
  2716. .remove = xhci_remove,
  2717. };