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phantom.h 8.7KB

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  1. #ifndef _PHANTOM_H
  2. #define _PHANTOM_H
  3. /*
  4. * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
  5. * Copyright (C) 2008 NetXen, Inc.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of the
  10. * License, or any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful, but
  13. * WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  20. * 02110-1301, USA.
  21. *
  22. * You can also choose to distribute this program under the terms of
  23. * the Unmodified Binary Distribution Licence (as given in the file
  24. * COPYING.UBDL), provided that you have satisfied its requirements.
  25. */
  26. FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
  27. /**
  28. * @file
  29. *
  30. * NetXen Phantom NICs
  31. *
  32. */
  33. #include <stdint.h>
  34. /* Drag in hardware definitions */
  35. #include "nx_bitops.h"
  36. #include "phantom_hw.h"
  37. struct phantom_rds { NX_PSEUDO_BIT_STRUCT ( struct phantom_rds_pb ) };
  38. struct phantom_sds { NX_PSEUDO_BIT_STRUCT ( struct phantom_sds_pb ) };
  39. union phantom_cds { NX_PSEUDO_BIT_STRUCT ( union phantom_cds_pb ) };
  40. /* Drag in firmware interface definitions */
  41. typedef uint8_t U8;
  42. typedef uint16_t U16;
  43. typedef uint32_t U32;
  44. typedef uint64_t U64;
  45. typedef uint32_t nx_rcode_t;
  46. #define NXHAL_VERSION 1
  47. #include "nxhal_nic_interface.h"
  48. /** DMA buffer alignment */
  49. #define UNM_DMA_BUFFER_ALIGN 16
  50. /** Mark structure as DMA-aligned */
  51. #define __unm_dma_aligned __attribute__ (( aligned ( UNM_DMA_BUFFER_ALIGN ) ))
  52. /******************************************************************************
  53. *
  54. * Register definitions
  55. *
  56. */
  57. #define UNM_128M_CRB_WINDOW 0x6110210UL
  58. #define UNM_32M_CRB_WINDOW 0x0110210UL
  59. #define UNM_2M_CRB_WINDOW 0x0130060UL
  60. /**
  61. * Phantom register blocks
  62. *
  63. * The upper address bits vary between cards. We define an abstract
  64. * address space in which the upper 8 bits of the 32-bit register
  65. * address encode the register block. This gets translated to a bus
  66. * address by the phantom_crb_access_xxx() methods.
  67. */
  68. enum unm_reg_blocks {
  69. UNM_CRB_BLK_PCIE = 0x01,
  70. UNM_CRB_BLK_CAM = 0x22,
  71. UNM_CRB_BLK_ROMUSB = 0x33,
  72. UNM_CRB_BLK_TEST = 0x02,
  73. UNM_CRB_BLK_PEG_0 = 0x11,
  74. UNM_CRB_BLK_PEG_1 = 0x12,
  75. UNM_CRB_BLK_PEG_2 = 0x13,
  76. UNM_CRB_BLK_PEG_3 = 0x14,
  77. UNM_CRB_BLK_PEG_4 = 0x0f,
  78. };
  79. #define UNM_CRB_BASE(blk) ( (blk) << 20 )
  80. #define UNM_CRB_BLK(reg) ( (reg) >> 20 )
  81. #define UNM_CRB_OFFSET(reg) ( (reg) & 0x000fffff )
  82. #define UNM_CRB_PCIE UNM_CRB_BASE ( UNM_CRB_BLK_PCIE )
  83. #define UNM_PCIE_SEM2_LOCK ( UNM_CRB_PCIE + 0x1c010 )
  84. #define UNM_PCIE_SEM2_UNLOCK ( UNM_CRB_PCIE + 0x1c014 )
  85. #define UNM_PCIE_IRQ_VECTOR ( UNM_CRB_PCIE + 0x10100 )
  86. #define UNM_PCIE_IRQ_VECTOR_BIT(n) ( 1 << ( (n) + 7 ) )
  87. #define UNM_PCIE_IRQ_STATE ( UNM_CRB_PCIE + 0x1206c )
  88. #define UNM_PCIE_IRQ_STATE_TRIGGERED(state) (( (state) & 0x300 ) == 0x200 )
  89. #define UNM_PCIE_IRQ_MASK_F0 ( UNM_CRB_PCIE + 0x10128 )
  90. #define UNM_PCIE_IRQ_MASK_F1 ( UNM_CRB_PCIE + 0x10170 )
  91. #define UNM_PCIE_IRQ_MASK_F2 ( UNM_CRB_PCIE + 0x10174 )
  92. #define UNM_PCIE_IRQ_MASK_F3 ( UNM_CRB_PCIE + 0x10178 )
  93. #define UNM_PCIE_IRQ_MASK_F4 ( UNM_CRB_PCIE + 0x10370 )
  94. #define UNM_PCIE_IRQ_MASK_F5 ( UNM_CRB_PCIE + 0x10374 )
  95. #define UNM_PCIE_IRQ_MASK_F6 ( UNM_CRB_PCIE + 0x10378 )
  96. #define UNM_PCIE_IRQ_MASK_F7 ( UNM_CRB_PCIE + 0x1037c )
  97. #define UNM_PCIE_IRQ_MASK_MAGIC 0x0000fbffUL
  98. #define UNM_PCIE_IRQ_STATUS_F0 ( UNM_CRB_PCIE + 0x10118 )
  99. #define UNM_PCIE_IRQ_STATUS_F1 ( UNM_CRB_PCIE + 0x10160 )
  100. #define UNM_PCIE_IRQ_STATUS_F2 ( UNM_CRB_PCIE + 0x10164 )
  101. #define UNM_PCIE_IRQ_STATUS_F3 ( UNM_CRB_PCIE + 0x10168 )
  102. #define UNM_PCIE_IRQ_STATUS_F4 ( UNM_CRB_PCIE + 0x10360 )
  103. #define UNM_PCIE_IRQ_STATUS_F5 ( UNM_CRB_PCIE + 0x10364 )
  104. #define UNM_PCIE_IRQ_STATUS_F6 ( UNM_CRB_PCIE + 0x10368 )
  105. #define UNM_PCIE_IRQ_STATUS_F7 ( UNM_CRB_PCIE + 0x1036c )
  106. #define UNM_PCIE_IRQ_STATUS_MAGIC 0xffffffffUL
  107. #define UNM_CRB_CAM UNM_CRB_BASE ( UNM_CRB_BLK_CAM )
  108. #define UNM_CAM_RAM ( UNM_CRB_CAM + 0x02000 )
  109. #define UNM_CAM_RAM_PORT_MODE ( UNM_CAM_RAM + 0x00024 )
  110. #define UNM_CAM_RAM_PORT_MODE_AUTO_NEG 4
  111. #define UNM_CAM_RAM_PORT_MODE_AUTO_NEG_1G 5
  112. #define UNM_CAM_RAM_DMESG_HEAD(n) ( UNM_CAM_RAM + 0x00030 + (n) * 0x10 )
  113. #define UNM_CAM_RAM_DMESG_LEN(n) ( UNM_CAM_RAM + 0x00034 + (n) * 0x10 )
  114. #define UNM_CAM_RAM_DMESG_TAIL(n) ( UNM_CAM_RAM + 0x00038 + (n) * 0x10 )
  115. #define UNM_CAM_RAM_DMESG_SIG(n) ( UNM_CAM_RAM + 0x0003c + (n) * 0x10 )
  116. #define UNM_CAM_RAM_DMESG_SIG_MAGIC 0xcafebabeUL
  117. #define UNM_CAM_RAM_NUM_DMESG_BUFFERS 5
  118. #define UNM_CAM_RAM_CLP_COMMAND ( UNM_CAM_RAM + 0x000c0 )
  119. #define UNM_CAM_RAM_CLP_COMMAND_LAST 0x00000080UL
  120. #define UNM_CAM_RAM_CLP_DATA_LO ( UNM_CAM_RAM + 0x000c4 )
  121. #define UNM_CAM_RAM_CLP_DATA_HI ( UNM_CAM_RAM + 0x000c8 )
  122. #define UNM_CAM_RAM_CLP_STATUS ( UNM_CAM_RAM + 0x000cc )
  123. #define UNM_CAM_RAM_CLP_STATUS_START 0x00000001UL
  124. #define UNM_CAM_RAM_CLP_STATUS_DONE 0x00000002UL
  125. #define UNM_CAM_RAM_CLP_STATUS_ERROR 0x0000ff00UL
  126. #define UNM_CAM_RAM_CLP_STATUS_UNINITIALISED 0xffffffffUL
  127. #define UNM_CAM_RAM_BOOT_ENABLE ( UNM_CAM_RAM + 0x000fc )
  128. #define UNM_CAM_RAM_WOL_PORT_MODE ( UNM_CAM_RAM + 0x00198 )
  129. #define UNM_CAM_RAM_MAC_ADDRS ( UNM_CAM_RAM + 0x001c0 )
  130. #define UNM_CAM_RAM_COLD_BOOT ( UNM_CAM_RAM + 0x001fc )
  131. #define UNM_CAM_RAM_COLD_BOOT_MAGIC 0x55555555UL
  132. #define UNM_NIC_REG ( UNM_CRB_CAM + 0x02200 )
  133. #define UNM_NIC_REG_NX_CDRP ( UNM_NIC_REG + 0x00018 )
  134. #define UNM_NIC_REG_NX_ARG1 ( UNM_NIC_REG + 0x0001c )
  135. #define UNM_NIC_REG_NX_ARG2 ( UNM_NIC_REG + 0x00020 )
  136. #define UNM_NIC_REG_NX_ARG3 ( UNM_NIC_REG + 0x00024 )
  137. #define UNM_NIC_REG_NX_SIGN ( UNM_NIC_REG + 0x00028 )
  138. #define UNM_NIC_REG_DUMMY_BUF_ADDR_HI ( UNM_NIC_REG + 0x0003c )
  139. #define UNM_NIC_REG_DUMMY_BUF_ADDR_LO ( UNM_NIC_REG + 0x00040 )
  140. #define UNM_NIC_REG_CMDPEG_STATE ( UNM_NIC_REG + 0x00050 )
  141. #define UNM_NIC_REG_CMDPEG_STATE_INITIALIZED 0xff01
  142. #define UNM_NIC_REG_CMDPEG_STATE_INITIALIZE_ACK 0xf00f
  143. #define UNM_NIC_REG_DUMMY_BUF ( UNM_NIC_REG + 0x000fc )
  144. #define UNM_NIC_REG_DUMMY_BUF_INIT 0
  145. #define UNM_NIC_REG_XG_STATE_P3 ( UNM_NIC_REG + 0x00098 )
  146. #define UNM_NIC_REG_XG_STATE_P3_LINK( port, state_p3 ) \
  147. ( ( (state_p3) >> ( (port) * 4 ) ) & 0x0f )
  148. #define UNM_NIC_REG_XG_STATE_P3_LINK_UP 0x01
  149. #define UNM_NIC_REG_XG_STATE_P3_LINK_DOWN 0x02
  150. #define UNM_NIC_REG_RCVPEG_STATE ( UNM_NIC_REG + 0x0013c )
  151. #define UNM_NIC_REG_RCVPEG_STATE_INITIALIZED 0xff01
  152. #define UNM_CRB_ROMUSB UNM_CRB_BASE ( UNM_CRB_BLK_ROMUSB )
  153. #define UNM_ROMUSB_GLB ( UNM_CRB_ROMUSB + 0x00000 )
  154. #define UNM_ROMUSB_GLB_STATUS ( UNM_ROMUSB_GLB + 0x00004 )
  155. #define UNM_ROMUSB_GLB_STATUS_ROM_DONE ( 1 << 1 )
  156. #define UNM_ROMUSB_GLB_SW_RESET ( UNM_ROMUSB_GLB + 0x00008 )
  157. #define UNM_ROMUSB_GLB_SW_RESET_MAGIC 0x0080000fUL
  158. #define UNM_ROMUSB_GLB_PEGTUNE_DONE ( UNM_ROMUSB_GLB + 0x0005c )
  159. #define UNM_ROMUSB_GLB_PEGTUNE_DONE_MAGIC 0x31
  160. #define UNM_ROMUSB_ROM ( UNM_CRB_ROMUSB + 0x10000 )
  161. #define UNM_ROMUSB_ROM_INSTR_OPCODE ( UNM_ROMUSB_ROM + 0x00004 )
  162. #define UNM_ROMUSB_ROM_ADDRESS ( UNM_ROMUSB_ROM + 0x00008 )
  163. #define UNM_ROMUSB_ROM_WDATA ( UNM_ROMUSB_ROM + 0x0000c )
  164. #define UNM_ROMUSB_ROM_ABYTE_CNT ( UNM_ROMUSB_ROM + 0x00010 )
  165. #define UNM_ROMUSB_ROM_DUMMY_BYTE_CNT ( UNM_ROMUSB_ROM + 0x00014 )
  166. #define UNM_ROMUSB_ROM_RDATA ( UNM_ROMUSB_ROM + 0x00018 )
  167. #define UNM_CRB_TEST UNM_CRB_BASE ( UNM_CRB_BLK_TEST )
  168. #define UNM_TEST_CONTROL ( UNM_CRB_TEST + 0x00090 )
  169. #define UNM_TEST_CONTROL_START 0x01
  170. #define UNM_TEST_CONTROL_ENABLE 0x02
  171. #define UNM_TEST_CONTROL_BUSY 0x08
  172. #define UNM_TEST_ADDR_LO ( UNM_CRB_TEST + 0x00094 )
  173. #define UNM_TEST_ADDR_HI ( UNM_CRB_TEST + 0x00098 )
  174. #define UNM_TEST_RDDATA_LO ( UNM_CRB_TEST + 0x000a8 )
  175. #define UNM_TEST_RDDATA_HI ( UNM_CRB_TEST + 0x000ac )
  176. #define UNM_CRB_PEG_0 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_0 )
  177. #define UNM_PEG_0_HALT_STATUS ( UNM_CRB_PEG_0 + 0x00030 )
  178. #define UNM_PEG_0_HALT ( UNM_CRB_PEG_0 + 0x0003c )
  179. #define UNM_CRB_PEG_1 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_1 )
  180. #define UNM_PEG_1_HALT_STATUS ( UNM_CRB_PEG_1 + 0x00030 )
  181. #define UNM_PEG_1_HALT ( UNM_CRB_PEG_1 + 0x0003c )
  182. #define UNM_CRB_PEG_2 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_2 )
  183. #define UNM_PEG_2_HALT_STATUS ( UNM_CRB_PEG_2 + 0x00030 )
  184. #define UNM_PEG_2_HALT ( UNM_CRB_PEG_2 + 0x0003c )
  185. #define UNM_CRB_PEG_3 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_3 )
  186. #define UNM_PEG_3_HALT_STATUS ( UNM_CRB_PEG_3 + 0x00030 )
  187. #define UNM_PEG_3_HALT ( UNM_CRB_PEG_3 + 0x0003c )
  188. #define UNM_CRB_PEG_4 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_4 )
  189. #define UNM_PEG_4_HALT_STATUS ( UNM_CRB_PEG_4 + 0x00030 )
  190. #define UNM_PEG_4_HALT ( UNM_CRB_PEG_4 + 0x0003c )
  191. #endif /* _PHANTOM_H */