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qib7322.h 9.9KB

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  1. #ifndef _QIB7322_H
  2. #define _QIB7322_H
  3. /*
  4. * Copyright (C) 2009 Michael Brown <mbrown@fensystems.co.uk>.
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation; either version 2 of the
  9. * License, or any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  19. * 02110-1301, USA.
  20. *
  21. * You can also choose to distribute this program under the terms of
  22. * the Unmodified Binary Distribution Licence (as given in the file
  23. * COPYING.UBDL), provided that you have satisfied its requirements.
  24. */
  25. FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
  26. /**
  27. * @file
  28. *
  29. * QLogic QIB7322 Infiniband HCA
  30. *
  31. */
  32. #define BITOPS_LITTLE_ENDIAN
  33. #include <ipxe/bitops.h>
  34. #include "qib_7322_regs.h"
  35. /** A QIB7322 GPIO register */
  36. struct QIB_7322_GPIO_pb {
  37. pseudo_bit_t GPIO[16];
  38. pseudo_bit_t Reserved[48];
  39. };
  40. struct QIB_7322_GPIO {
  41. PSEUDO_BIT_STRUCT ( struct QIB_7322_GPIO_pb );
  42. };
  43. /** A QIB7322 general scalar register */
  44. struct QIB_7322_scalar_pb {
  45. pseudo_bit_t Value[64];
  46. };
  47. struct QIB_7322_scalar {
  48. PSEUDO_BIT_STRUCT ( struct QIB_7322_scalar_pb );
  49. };
  50. /** QIB7322 feature mask */
  51. struct QIB_7322_feature_mask_pb {
  52. pseudo_bit_t Port0_Link_Speed_Supported[3];
  53. pseudo_bit_t Port1_Link_Speed_Supported[3];
  54. pseudo_bit_t _unused_0[58];
  55. };
  56. struct QIB_7322_feature_mask {
  57. PSEUDO_BIT_STRUCT ( struct QIB_7322_feature_mask_pb );
  58. };
  59. /** QIB7322 send per-buffer control word */
  60. struct QIB_7322_SendPbc_pb {
  61. pseudo_bit_t LengthP1_toibc[11];
  62. pseudo_bit_t Reserved1[4];
  63. pseudo_bit_t LengthP1_trigger[11];
  64. pseudo_bit_t Reserved2[3];
  65. pseudo_bit_t TestEbp[1];
  66. pseudo_bit_t Test[1];
  67. pseudo_bit_t Intr[1];
  68. pseudo_bit_t StaticRateControlCnt[14];
  69. pseudo_bit_t Reserved3[12];
  70. pseudo_bit_t Port[1];
  71. pseudo_bit_t VLane[3];
  72. pseudo_bit_t Reserved4[1];
  73. pseudo_bit_t VL15[1];
  74. };
  75. struct QIB_7322_SendPbc {
  76. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendPbc_pb );
  77. };
  78. /** QIB7322 send buffer availability */
  79. struct QIB_7322_SendBufAvail_pb {
  80. pseudo_bit_t InUseCheck[162][2];
  81. pseudo_bit_t Reserved[60];
  82. };
  83. struct QIB_7322_SendBufAvail {
  84. PSEUDO_BIT_STRUCT ( struct QIB_7322_SendBufAvail_pb );
  85. };
  86. /** DMA alignment for send buffer availability */
  87. #define QIB7322_SENDBUFAVAIL_ALIGN 64
  88. /** QIB7322 port-specific receive control */
  89. struct QIB_7322_RcvCtrl_P_pb {
  90. pseudo_bit_t ContextEnable[18];
  91. pseudo_bit_t _unused_1[21];
  92. pseudo_bit_t RcvIBPortEnable[1];
  93. pseudo_bit_t RcvQPMapEnable[1];
  94. pseudo_bit_t RcvPartitionKeyDisable[1];
  95. pseudo_bit_t RcvResetCredit[1];
  96. pseudo_bit_t _unused_2[21];
  97. };
  98. struct QIB_7322_RcvCtrl_P {
  99. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvCtrl_P_pb );
  100. };
  101. /** A QIB7322 eager receive descriptor */
  102. struct QIB_7322_RcvEgr_pb {
  103. pseudo_bit_t Addr[37];
  104. pseudo_bit_t BufSize[3];
  105. pseudo_bit_t Reserved[24];
  106. };
  107. struct QIB_7322_RcvEgr {
  108. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvEgr_pb );
  109. };
  110. /** QIB7322 receive header flags */
  111. struct QIB_7322_RcvHdrFlags_pb {
  112. pseudo_bit_t PktLen[11];
  113. pseudo_bit_t RcvType[3];
  114. pseudo_bit_t SoftB[1];
  115. pseudo_bit_t SoftA[1];
  116. pseudo_bit_t EgrIndex[12];
  117. pseudo_bit_t Reserved1[3];
  118. pseudo_bit_t UseEgrBfr[1];
  119. pseudo_bit_t RcvSeq[4];
  120. pseudo_bit_t HdrqOffset[11];
  121. pseudo_bit_t Reserved2[8];
  122. pseudo_bit_t IBErr[1];
  123. pseudo_bit_t MKErr[1];
  124. pseudo_bit_t TIDErr[1];
  125. pseudo_bit_t KHdrErr[1];
  126. pseudo_bit_t MTUErr[1];
  127. pseudo_bit_t LenErr[1];
  128. pseudo_bit_t ParityErr[1];
  129. pseudo_bit_t VCRCErr[1];
  130. pseudo_bit_t ICRCErr[1];
  131. };
  132. struct QIB_7322_RcvHdrFlags {
  133. PSEUDO_BIT_STRUCT ( struct QIB_7322_RcvHdrFlags_pb );
  134. };
  135. /** QIB7322 DDS tuning parameters */
  136. struct QIB_7322_IBSD_DDS_MAP_TABLE_pb {
  137. pseudo_bit_t Pre[3];
  138. pseudo_bit_t PreXtra[2];
  139. pseudo_bit_t Post[4];
  140. pseudo_bit_t Main[5];
  141. pseudo_bit_t Amp[4];
  142. pseudo_bit_t _unused_0[46];
  143. };
  144. struct QIB_7322_IBSD_DDS_MAP_TABLE {
  145. PSEUDO_BIT_STRUCT ( struct QIB_7322_IBSD_DDS_MAP_TABLE_pb );
  146. };
  147. /** QIB7322 memory BAR size */
  148. #define QIB7322_BAR0_SIZE 0x400000
  149. /** QIB7322 base port number */
  150. #define QIB7322_PORT_BASE 1
  151. /** QIB7322 maximum number of ports */
  152. #define QIB7322_MAX_PORTS 2
  153. /** QIB7322 maximum width */
  154. #define QIB7322_MAX_WIDTH 4
  155. /** QIB7322 board identifiers */
  156. enum qib7322_board_id {
  157. QIB7322_BOARD_QLE7342_EMULATION = 0,
  158. QIB7322_BOARD_QLE7340 = 1,
  159. QIB7322_BOARD_QLE7342 = 2,
  160. QIB7322_BOARD_QMI7342 = 3,
  161. QIB7322_BOARD_QMH7342_UNSUPPORTED = 4,
  162. QIB7322_BOARD_QME7342 = 5,
  163. QIB7322_BOARD_QMH7342 = 6,
  164. QIB7322_BOARD_QLE7342_TEST = 15,
  165. };
  166. /** QIB7322 I2C SCL line GPIO number */
  167. #define QIB7322_GPIO_SCL 0
  168. /** QIB7322 I2C SDA line GPIO number */
  169. #define QIB7322_GPIO_SDA 1
  170. /** GUID offset within EEPROM */
  171. #define QIB7322_EEPROM_GUID_OFFSET 3
  172. /** GUID size within EEPROM */
  173. #define QIB7322_EEPROM_GUID_SIZE 8
  174. /** Board serial number offset within EEPROM */
  175. #define QIB7322_EEPROM_SERIAL_OFFSET 12
  176. /** Board serial number size within EEPROM */
  177. #define QIB7322_EEPROM_SERIAL_SIZE 12
  178. /** QIB7322 small send buffer size */
  179. #define QIB7322_SMALL_SEND_BUF_SIZE 4096
  180. /** QIB7322 small send buffer starting index */
  181. #define QIB7322_SMALL_SEND_BUF_START 0
  182. /** QIB7322 small send buffer count */
  183. #define QIB7322_SMALL_SEND_BUF_COUNT 128
  184. /** QIB7322 large send buffer size */
  185. #define QIB7322_LARGE_SEND_BUF_SIZE 8192
  186. /** QIB7322 large send buffer starting index */
  187. #define QIB7322_LARGE_SEND_BUF_START 128
  188. /** QIB7322 large send buffer count */
  189. #define QIB7322_LARGE_SEND_BUF_COUNT 32
  190. /** QIB7322 VL15 port 0 send buffer starting index */
  191. #define QIB7322_VL15_PORT0_SEND_BUF_START 160
  192. /** QIB7322 VL15 port 0 send buffer count */
  193. #define QIB7322_VL15_PORT0_SEND_BUF_COUNT 1
  194. /** QIB7322 VL15 port 0 send buffer size */
  195. #define QIB7322_VL15_PORT0_SEND_BUF_SIZE 8192
  196. /** QIB7322 VL15 port 0 send buffer starting index */
  197. #define QIB7322_VL15_PORT1_SEND_BUF_START 161
  198. /** QIB7322 VL15 port 0 send buffer count */
  199. #define QIB7322_VL15_PORT1_SEND_BUF_COUNT 1
  200. /** QIB7322 VL15 port 0 send buffer size */
  201. #define QIB7322_VL15_PORT1_SEND_BUF_SIZE 8192
  202. /** Number of small send buffers used
  203. *
  204. * This is a policy decision. Must be less than or equal to the total
  205. * number of small send buffers supported by the hardware
  206. * (QIB7322_SMALL_SEND_BUF_COUNT).
  207. */
  208. #define QIB7322_SMALL_SEND_BUF_USED 32
  209. /** Number of contexts (including kernel context)
  210. *
  211. * This is a policy decision. Must be 6, 10 or 18.
  212. */
  213. #define QIB7322_NUM_CONTEXTS 6
  214. /** ContextCfg values for different numbers of contexts */
  215. enum qib7322_contextcfg {
  216. QIB7322_CONTEXTCFG_6CTX = 0,
  217. QIB7322_CONTEXTCFG_10CTX = 1,
  218. QIB7322_CONTEXTCFG_18CTX = 2,
  219. };
  220. /** ContextCfg values for different numbers of contexts */
  221. #define QIB7322_EAGER_ARRAY_SIZE_6CTX_KERNEL 1024
  222. #define QIB7322_EAGER_ARRAY_SIZE_6CTX_USER 4096
  223. #define QIB7322_EAGER_ARRAY_SIZE_10CTX_KERNEL 1024
  224. #define QIB7322_EAGER_ARRAY_SIZE_10CTX_USER 2048
  225. #define QIB7322_EAGER_ARRAY_SIZE_18CTX_KERNEL 1024
  226. #define QIB7322_EAGER_ARRAY_SIZE_18CTX_USER 1024
  227. /** Eager buffer required alignment */
  228. #define QIB7322_EAGER_BUFFER_ALIGN 2048
  229. /** Eager buffer size encodings */
  230. enum qib7322_eager_buffer_size {
  231. QIB7322_EAGER_BUFFER_NONE = 0,
  232. QIB7322_EAGER_BUFFER_2K = 1,
  233. QIB7322_EAGER_BUFFER_4K = 2,
  234. QIB7322_EAGER_BUFFER_8K = 3,
  235. QIB7322_EAGER_BUFFER_16K = 4,
  236. QIB7322_EAGER_BUFFER_32K = 5,
  237. QIB7322_EAGER_BUFFER_64K = 6,
  238. };
  239. /** Number of RX headers per context
  240. *
  241. * This is a policy decision.
  242. */
  243. #define QIB7322_RECV_HEADER_COUNT 8
  244. /** Maximum size of each RX header
  245. *
  246. * This is a policy decision. Must be divisible by 4.
  247. */
  248. #define QIB7322_RECV_HEADER_SIZE 96
  249. /** Total size of an RX header ring */
  250. #define QIB7322_RECV_HEADERS_SIZE \
  251. ( QIB7322_RECV_HEADER_SIZE * QIB7322_RECV_HEADER_COUNT )
  252. /** RX header alignment */
  253. #define QIB7322_RECV_HEADERS_ALIGN 64
  254. /** RX payload size
  255. *
  256. * This is a policy decision. Must be a valid eager buffer size.
  257. */
  258. #define QIB7322_RECV_PAYLOAD_SIZE 2048
  259. /** Maximum number of credits per port
  260. *
  261. * 64kB of internal RX buffer space, in units of 64 bytes, split
  262. * between two ports.
  263. */
  264. #define QIB7322_MAX_CREDITS ( ( 65536 / 64 ) / QIB7322_MAX_PORTS )
  265. /** Number of credits to advertise for VL15
  266. *
  267. * This is a policy decision. Using 9 credits allows for 9*64=576
  268. * bytes, which is enough for two MADs.
  269. */
  270. #define QIB7322_MAX_CREDITS_VL15 9
  271. /** Number of credits to advertise for VL0
  272. *
  273. * This is a policy decision.
  274. */
  275. #define QIB7322_MAX_CREDITS_VL0 \
  276. ( QIB7322_MAX_CREDITS - QIB7322_MAX_CREDITS_VL15 )
  277. /** QPN used for Infinipath Packets
  278. *
  279. * This is a policy decision. Must have bit 0 clear. Must not be a
  280. * QPN that we will use.
  281. */
  282. #define QIB7322_QP_IDETH 0xdead0
  283. /** Maximum time for wait for AHB, in us */
  284. #define QIB7322_AHB_MAX_WAIT_US 500
  285. /** QIB7322 AHB locations */
  286. #define QIB7322_AHB_LOC_ADDRESS( _location ) ( (_location) & 0xffff )
  287. #define QIB7322_AHB_LOC_TARGET( _location ) ( (_location) >> 16 )
  288. #define QIB7322_AHB_CHAN_0 0
  289. #define QIB7322_AHB_CHAN_1 1
  290. #define QIB7322_AHB_PLL 2
  291. #define QIB7322_AHB_CHAN_2 3
  292. #define QIB7322_AHB_CHAN_3 4
  293. #define QIB7322_AHB_SUBSYS 5
  294. #define QIB7322_AHB_CHAN( _channel ) ( (_channel) + ( (_channel) >> 1 ) )
  295. #define QIB7322_AHB_TARGET_0 2
  296. #define QIB7322_AHB_TARGET_1 3
  297. #define QIB7322_AHB_TARGET( _port ) ( (_port) + 2 )
  298. #define QIB7322_AHB_LOCATION( _port, _channel, _register ) \
  299. ( ( QIB7322_AHB_TARGET(_port) << 16 ) | \
  300. ( QIB7322_AHB_CHAN(_channel) << 7 ) | \
  301. ( (_register) << 1 ) )
  302. /** QIB7322 link states */
  303. enum qib7322_link_state {
  304. QIB7322_LINK_STATE_DOWN = 0,
  305. QIB7322_LINK_STATE_INIT = 1,
  306. QIB7322_LINK_STATE_ARM = 2,
  307. QIB7322_LINK_STATE_ACTIVE = 3,
  308. QIB7322_LINK_STATE_ACT_DEFER = 4,
  309. };
  310. /** Maximum time to wait for link state changes, in us */
  311. #define QIB7322_LINK_STATE_MAX_WAIT_US 20
  312. #endif /* _QIB7322_H */