You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

sky2.c 64KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031203220332034203520362037203820392040204120422043204420452046204720482049205020512052205320542055205620572058205920602061206220632064206520662067206820692070207120722073207420752076207720782079208020812082208320842085208620872088208920902091209220932094209520962097209820992100210121022103210421052106210721082109211021112112211321142115211621172118211921202121212221232124212521262127212821292130213121322133213421352136213721382139214021412142214321442145214621472148214921502151215221532154215521562157215821592160216121622163216421652166216721682169217021712172217321742175217621772178217921802181218221832184218521862187218821892190219121922193219421952196219721982199220022012202220322042205220622072208220922102211221222132214221522162217221822192220222122222223222422252226222722282229223022312232223322342235223622372238223922402241224222432244224522462247224822492250225122522253225422552256225722582259226022612262226322642265226622672268226922702271227222732274227522762277227822792280228122822283228422852286228722882289229022912292229322942295229622972298229923002301230223032304230523062307230823092310231123122313231423152316231723182319232023212322232323242325232623272328232923302331233223332334233523362337233823392340234123422343234423452346234723482349235023512352235323542355235623572358235923602361236223632364236523662367236823692370237123722373237423752376237723782379238023812382238323842385238623872388238923902391239223932394
  1. /*
  2. * iPXE driver for Marvell Yukon 2 chipset. Derived from Linux sky2 driver
  3. * (v1.22), which was based on earlier sk98lin and skge drivers.
  4. *
  5. * This driver intentionally does not support all the features
  6. * of the original driver such as link fail-over and link management because
  7. * those should be done at higher levels.
  8. *
  9. * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
  10. *
  11. * Modified for iPXE, April 2009 by Joshua Oreman
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License as published by
  15. * the Free Software Foundation; either version 2 of the License.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  25. * 02110-1301, USA.
  26. */
  27. FILE_LICENCE ( GPL2_ONLY );
  28. #include <stdint.h>
  29. #include <errno.h>
  30. #include <stdio.h>
  31. #include <unistd.h>
  32. #include <ipxe/ethernet.h>
  33. #include <ipxe/if_ether.h>
  34. #include <ipxe/iobuf.h>
  35. #include <ipxe/malloc.h>
  36. #include <ipxe/pci.h>
  37. #include <byteswap.h>
  38. #include <mii.h>
  39. #include "sky2.h"
  40. #define DRV_NAME "sky2"
  41. #define DRV_VERSION "1.22"
  42. #define PFX DRV_NAME " "
  43. /*
  44. * The Yukon II chipset takes 64 bit command blocks (called list elements)
  45. * that are organized into three (receive, transmit, status) different rings
  46. * similar to Tigon3.
  47. *
  48. * Each ring start must be aligned to a 4k boundary. You will get mysterious
  49. * "invalid LE" errors if they're not.
  50. *
  51. * The card silently forces each ring size to be at least 128. If you
  52. * act as though one of them is smaller (by setting the below
  53. * #defines) you'll get bad bugs.
  54. */
  55. #define RX_LE_SIZE 128
  56. #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
  57. #define RX_RING_ALIGN 4096
  58. #define RX_PENDING (RX_LE_SIZE/6 - 2)
  59. #define TX_RING_SIZE 128
  60. #define TX_PENDING (TX_RING_SIZE - 1)
  61. #define TX_RING_ALIGN 4096
  62. #define MAX_SKB_TX_LE 4
  63. #define STATUS_RING_SIZE 512 /* 2 ports * (TX + RX) */
  64. #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
  65. #define STATUS_RING_ALIGN 4096
  66. #define PHY_RETRIES 1000
  67. #define SKY2_EEPROM_MAGIC 0x9955aabb
  68. #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
  69. static struct pci_device_id sky2_id_table[] = {
  70. PCI_ROM(0x1148, 0x9000, "sk9sxx", "Syskonnect SK-9Sxx", 0),
  71. PCI_ROM(0x1148, 0x9e00, "sk9exx", "Syskonnect SK-9Exx", 0),
  72. PCI_ROM(0x1186, 0x4b00, "dge560t", "D-Link DGE-560T", 0),
  73. PCI_ROM(0x1186, 0x4001, "dge550sx", "D-Link DGE-550SX", 0),
  74. PCI_ROM(0x1186, 0x4b02, "dge560sx", "D-Link DGE-560SX", 0),
  75. PCI_ROM(0x1186, 0x4b03, "dge550t", "D-Link DGE-550T", 0),
  76. PCI_ROM(0x11ab, 0x4340, "m88e8021", "Marvell 88E8021", 0),
  77. PCI_ROM(0x11ab, 0x4341, "m88e8022", "Marvell 88E8022", 0),
  78. PCI_ROM(0x11ab, 0x4342, "m88e8061", "Marvell 88E8061", 0),
  79. PCI_ROM(0x11ab, 0x4343, "m88e8062", "Marvell 88E8062", 0),
  80. PCI_ROM(0x11ab, 0x4344, "m88e8021b", "Marvell 88E8021", 0),
  81. PCI_ROM(0x11ab, 0x4345, "m88e8022b", "Marvell 88E8022", 0),
  82. PCI_ROM(0x11ab, 0x4346, "m88e8061b", "Marvell 88E8061", 0),
  83. PCI_ROM(0x11ab, 0x4347, "m88e8062b", "Marvell 88E8062", 0),
  84. PCI_ROM(0x11ab, 0x4350, "m88e8035", "Marvell 88E8035", 0),
  85. PCI_ROM(0x11ab, 0x4351, "m88e8036", "Marvell 88E8036", 0),
  86. PCI_ROM(0x11ab, 0x4352, "m88e8038", "Marvell 88E8038", 0),
  87. PCI_ROM(0x11ab, 0x4353, "m88e8039", "Marvell 88E8039", 0),
  88. PCI_ROM(0x11ab, 0x4354, "m88e8040", "Marvell 88E8040", 0),
  89. PCI_ROM(0x11ab, 0x4355, "m88e8040t", "Marvell 88E8040T", 0),
  90. PCI_ROM(0x11ab, 0x4356, "m88ec033", "Marvel 88EC033", 0),
  91. PCI_ROM(0x11ab, 0x4357, "m88e8042", "Marvell 88E8042", 0),
  92. PCI_ROM(0x11ab, 0x435a, "m88e8048", "Marvell 88E8048", 0),
  93. PCI_ROM(0x11ab, 0x4360, "m88e8052", "Marvell 88E8052", 0),
  94. PCI_ROM(0x11ab, 0x4361, "m88e8050", "Marvell 88E8050", 0),
  95. PCI_ROM(0x11ab, 0x4362, "m88e8053", "Marvell 88E8053", 0),
  96. PCI_ROM(0x11ab, 0x4363, "m88e8055", "Marvell 88E8055", 0),
  97. PCI_ROM(0x11ab, 0x4364, "m88e8056", "Marvell 88E8056", 0),
  98. PCI_ROM(0x11ab, 0x4365, "m88e8070", "Marvell 88E8070", 0),
  99. PCI_ROM(0x11ab, 0x4366, "m88ec036", "Marvell 88EC036", 0),
  100. PCI_ROM(0x11ab, 0x4367, "m88ec032", "Marvell 88EC032", 0),
  101. PCI_ROM(0x11ab, 0x4368, "m88ec034", "Marvell 88EC034", 0),
  102. PCI_ROM(0x11ab, 0x4369, "m88ec042", "Marvell 88EC042", 0),
  103. PCI_ROM(0x11ab, 0x436a, "m88e8058", "Marvell 88E8058", 0),
  104. PCI_ROM(0x11ab, 0x436b, "m88e8071", "Marvell 88E8071", 0),
  105. PCI_ROM(0x11ab, 0x436c, "m88e8072", "Marvell 88E8072", 0),
  106. PCI_ROM(0x11ab, 0x436d, "m88e8055b", "Marvell 88E8055", 0),
  107. PCI_ROM(0x11ab, 0x4370, "m88e8075", "Marvell 88E8075", 0),
  108. PCI_ROM(0x11ab, 0x4380, "m88e8057", "Marvell 88E8057", 0)
  109. };
  110. /* Avoid conditionals by using array */
  111. static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
  112. static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
  113. static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
  114. static void sky2_set_multicast(struct net_device *dev);
  115. /* Access to PHY via serial interconnect */
  116. static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
  117. {
  118. int i;
  119. gma_write16(hw, port, GM_SMI_DATA, val);
  120. gma_write16(hw, port, GM_SMI_CTRL,
  121. GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
  122. for (i = 0; i < PHY_RETRIES; i++) {
  123. u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
  124. if (ctrl == 0xffff)
  125. goto io_error;
  126. if (!(ctrl & GM_SMI_CT_BUSY))
  127. return 0;
  128. udelay(10);
  129. }
  130. DBG(PFX "%s: phy write timeout\n", hw->dev[port]->name);
  131. return -ETIMEDOUT;
  132. io_error:
  133. DBG(PFX "%s: phy I/O error\n", hw->dev[port]->name);
  134. return -EIO;
  135. }
  136. static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
  137. {
  138. int i;
  139. gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
  140. | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
  141. for (i = 0; i < PHY_RETRIES; i++) {
  142. u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
  143. if (ctrl == 0xffff)
  144. goto io_error;
  145. if (ctrl & GM_SMI_CT_RD_VAL) {
  146. *val = gma_read16(hw, port, GM_SMI_DATA);
  147. return 0;
  148. }
  149. udelay(10);
  150. }
  151. DBG(PFX "%s: phy read timeout\n", hw->dev[port]->name);
  152. return -ETIMEDOUT;
  153. io_error:
  154. DBG(PFX "%s: phy I/O error\n", hw->dev[port]->name);
  155. return -EIO;
  156. }
  157. static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
  158. {
  159. u16 v = 0;
  160. __gm_phy_read(hw, port, reg, &v);
  161. return v;
  162. }
  163. static void sky2_power_on(struct sky2_hw *hw)
  164. {
  165. /* switch power to VCC (WA for VAUX problem) */
  166. sky2_write8(hw, B0_POWER_CTRL,
  167. PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
  168. /* disable Core Clock Division, */
  169. sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
  170. if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
  171. /* enable bits are inverted */
  172. sky2_write8(hw, B2_Y2_CLK_GATE,
  173. Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
  174. Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
  175. Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
  176. else
  177. sky2_write8(hw, B2_Y2_CLK_GATE, 0);
  178. if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
  179. u32 reg;
  180. sky2_pci_write32(hw, PCI_DEV_REG3, 0);
  181. reg = sky2_pci_read32(hw, PCI_DEV_REG4);
  182. /* set all bits to 0 except bits 15..12 and 8 */
  183. reg &= P_ASPM_CONTROL_MSK;
  184. sky2_pci_write32(hw, PCI_DEV_REG4, reg);
  185. reg = sky2_pci_read32(hw, PCI_DEV_REG5);
  186. /* set all bits to 0 except bits 28 & 27 */
  187. reg &= P_CTL_TIM_VMAIN_AV_MSK;
  188. sky2_pci_write32(hw, PCI_DEV_REG5, reg);
  189. sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
  190. /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
  191. reg = sky2_read32(hw, B2_GP_IO);
  192. reg |= GLB_GPIO_STAT_RACE_DIS;
  193. sky2_write32(hw, B2_GP_IO, reg);
  194. sky2_read32(hw, B2_GP_IO);
  195. }
  196. }
  197. static void sky2_power_aux(struct sky2_hw *hw)
  198. {
  199. if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
  200. sky2_write8(hw, B2_Y2_CLK_GATE, 0);
  201. else
  202. /* enable bits are inverted */
  203. sky2_write8(hw, B2_Y2_CLK_GATE,
  204. Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
  205. Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
  206. Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
  207. /* switch power to VAUX */
  208. if (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL)
  209. sky2_write8(hw, B0_POWER_CTRL,
  210. (PC_VAUX_ENA | PC_VCC_ENA |
  211. PC_VAUX_ON | PC_VCC_OFF));
  212. }
  213. static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
  214. {
  215. u16 reg;
  216. /* disable all GMAC IRQ's */
  217. sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
  218. gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
  219. gma_write16(hw, port, GM_MC_ADDR_H2, 0);
  220. gma_write16(hw, port, GM_MC_ADDR_H3, 0);
  221. gma_write16(hw, port, GM_MC_ADDR_H4, 0);
  222. reg = gma_read16(hw, port, GM_RX_CTRL);
  223. reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
  224. gma_write16(hw, port, GM_RX_CTRL, reg);
  225. }
  226. /* flow control to advertise bits */
  227. static const u16 copper_fc_adv[] = {
  228. [FC_NONE] = 0,
  229. [FC_TX] = PHY_M_AN_ASP,
  230. [FC_RX] = PHY_M_AN_PC,
  231. [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
  232. };
  233. /* flow control to advertise bits when using 1000BaseX */
  234. static const u16 fiber_fc_adv[] = {
  235. [FC_NONE] = PHY_M_P_NO_PAUSE_X,
  236. [FC_TX] = PHY_M_P_ASYM_MD_X,
  237. [FC_RX] = PHY_M_P_SYM_MD_X,
  238. [FC_BOTH] = PHY_M_P_BOTH_MD_X,
  239. };
  240. /* flow control to GMA disable bits */
  241. static const u16 gm_fc_disable[] = {
  242. [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
  243. [FC_TX] = GM_GPCR_FC_RX_DIS,
  244. [FC_RX] = GM_GPCR_FC_TX_DIS,
  245. [FC_BOTH] = 0,
  246. };
  247. static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
  248. {
  249. struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
  250. u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
  251. if (sky2->autoneg == AUTONEG_ENABLE &&
  252. !(hw->flags & SKY2_HW_NEWER_PHY)) {
  253. u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
  254. ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
  255. PHY_M_EC_MAC_S_MSK);
  256. ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
  257. /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
  258. if (hw->chip_id == CHIP_ID_YUKON_EC)
  259. /* set downshift counter to 3x and enable downshift */
  260. ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
  261. else
  262. /* set master & slave downshift counter to 1x */
  263. ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
  264. gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
  265. }
  266. ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  267. if (sky2_is_copper(hw)) {
  268. if (!(hw->flags & SKY2_HW_GIGABIT)) {
  269. /* enable automatic crossover */
  270. ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
  271. if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
  272. hw->chip_rev == CHIP_REV_YU_FE2_A0) {
  273. u16 spec;
  274. /* Enable Class A driver for FE+ A0 */
  275. spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
  276. spec |= PHY_M_FESC_SEL_CL_A;
  277. gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
  278. }
  279. } else {
  280. /* disable energy detect */
  281. ctrl &= ~PHY_M_PC_EN_DET_MSK;
  282. /* enable automatic crossover */
  283. ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
  284. /* downshift on PHY 88E1112 and 88E1149 is changed */
  285. if (sky2->autoneg == AUTONEG_ENABLE
  286. && (hw->flags & SKY2_HW_NEWER_PHY)) {
  287. /* set downshift counter to 3x and enable downshift */
  288. ctrl &= ~PHY_M_PC_DSC_MSK;
  289. ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
  290. }
  291. }
  292. } else {
  293. /* workaround for deviation #4.88 (CRC errors) */
  294. /* disable Automatic Crossover */
  295. ctrl &= ~PHY_M_PC_MDIX_MSK;
  296. }
  297. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
  298. /* special setup for PHY 88E1112 Fiber */
  299. if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
  300. pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  301. /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
  302. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
  303. ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  304. ctrl &= ~PHY_M_MAC_MD_MSK;
  305. ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
  306. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
  307. if (hw->pmd_type == 'P') {
  308. /* select page 1 to access Fiber registers */
  309. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
  310. /* for SFP-module set SIGDET polarity to low */
  311. ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  312. ctrl |= PHY_M_FIB_SIGD_POL;
  313. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
  314. }
  315. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  316. }
  317. ctrl = PHY_CT_RESET;
  318. ct1000 = 0;
  319. adv = PHY_AN_CSMA;
  320. reg = 0;
  321. if (sky2->autoneg == AUTONEG_ENABLE) {
  322. if (sky2_is_copper(hw)) {
  323. if (sky2->advertising & ADVERTISED_1000baseT_Full)
  324. ct1000 |= PHY_M_1000C_AFD;
  325. if (sky2->advertising & ADVERTISED_1000baseT_Half)
  326. ct1000 |= PHY_M_1000C_AHD;
  327. if (sky2->advertising & ADVERTISED_100baseT_Full)
  328. adv |= PHY_M_AN_100_FD;
  329. if (sky2->advertising & ADVERTISED_100baseT_Half)
  330. adv |= PHY_M_AN_100_HD;
  331. if (sky2->advertising & ADVERTISED_10baseT_Full)
  332. adv |= PHY_M_AN_10_FD;
  333. if (sky2->advertising & ADVERTISED_10baseT_Half)
  334. adv |= PHY_M_AN_10_HD;
  335. adv |= copper_fc_adv[sky2->flow_mode];
  336. } else { /* special defines for FIBER (88E1040S only) */
  337. if (sky2->advertising & ADVERTISED_1000baseT_Full)
  338. adv |= PHY_M_AN_1000X_AFD;
  339. if (sky2->advertising & ADVERTISED_1000baseT_Half)
  340. adv |= PHY_M_AN_1000X_AHD;
  341. adv |= fiber_fc_adv[sky2->flow_mode];
  342. }
  343. /* Restart Auto-negotiation */
  344. ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
  345. } else {
  346. /* forced speed/duplex settings */
  347. ct1000 = PHY_M_1000C_MSE;
  348. /* Disable auto update for duplex flow control and speed */
  349. reg |= GM_GPCR_AU_ALL_DIS;
  350. switch (sky2->speed) {
  351. case SPEED_1000:
  352. ctrl |= PHY_CT_SP1000;
  353. reg |= GM_GPCR_SPEED_1000;
  354. break;
  355. case SPEED_100:
  356. ctrl |= PHY_CT_SP100;
  357. reg |= GM_GPCR_SPEED_100;
  358. break;
  359. }
  360. if (sky2->duplex == DUPLEX_FULL) {
  361. reg |= GM_GPCR_DUP_FULL;
  362. ctrl |= PHY_CT_DUP_MD;
  363. } else if (sky2->speed < SPEED_1000)
  364. sky2->flow_mode = FC_NONE;
  365. reg |= gm_fc_disable[sky2->flow_mode];
  366. /* Forward pause packets to GMAC? */
  367. if (sky2->flow_mode & FC_RX)
  368. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
  369. else
  370. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
  371. }
  372. gma_write16(hw, port, GM_GP_CTRL, reg);
  373. if (hw->flags & SKY2_HW_GIGABIT)
  374. gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
  375. gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
  376. gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
  377. /* Setup Phy LED's */
  378. ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
  379. ledover = 0;
  380. switch (hw->chip_id) {
  381. case CHIP_ID_YUKON_FE:
  382. /* on 88E3082 these bits are at 11..9 (shifted left) */
  383. ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
  384. ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
  385. /* delete ACT LED control bits */
  386. ctrl &= ~PHY_M_FELP_LED1_MSK;
  387. /* change ACT LED control to blink mode */
  388. ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
  389. gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
  390. break;
  391. case CHIP_ID_YUKON_FE_P:
  392. /* Enable Link Partner Next Page */
  393. ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  394. ctrl |= PHY_M_PC_ENA_LIP_NP;
  395. /* disable Energy Detect and enable scrambler */
  396. ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
  397. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
  398. /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
  399. ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
  400. PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
  401. PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
  402. gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
  403. break;
  404. case CHIP_ID_YUKON_XL:
  405. pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  406. /* select page 3 to access LED control register */
  407. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
  408. /* set LED Function Control register */
  409. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
  410. (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
  411. PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
  412. PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
  413. PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
  414. /* set Polarity Control register */
  415. gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
  416. (PHY_M_POLC_LS1_P_MIX(4) |
  417. PHY_M_POLC_IS0_P_MIX(4) |
  418. PHY_M_POLC_LOS_CTRL(2) |
  419. PHY_M_POLC_INIT_CTRL(2) |
  420. PHY_M_POLC_STA1_CTRL(2) |
  421. PHY_M_POLC_STA0_CTRL(2)));
  422. /* restore page register */
  423. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  424. break;
  425. case CHIP_ID_YUKON_EC_U:
  426. case CHIP_ID_YUKON_EX:
  427. case CHIP_ID_YUKON_SUPR:
  428. pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
  429. /* select page 3 to access LED control register */
  430. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
  431. /* set LED Function Control register */
  432. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
  433. (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
  434. PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
  435. PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
  436. PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
  437. /* set Blink Rate in LED Timer Control Register */
  438. gm_phy_write(hw, port, PHY_MARV_INT_MASK,
  439. ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
  440. /* restore page register */
  441. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
  442. break;
  443. default:
  444. /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
  445. ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
  446. /* turn off the Rx LED (LED_RX) */
  447. ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
  448. }
  449. if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
  450. /* apply fixes in PHY AFE */
  451. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
  452. /* increase differential signal amplitude in 10BASE-T */
  453. gm_phy_write(hw, port, 0x18, 0xaa99);
  454. gm_phy_write(hw, port, 0x17, 0x2011);
  455. if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
  456. /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
  457. gm_phy_write(hw, port, 0x18, 0xa204);
  458. gm_phy_write(hw, port, 0x17, 0x2002);
  459. }
  460. /* set page register to 0 */
  461. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
  462. } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
  463. hw->chip_rev == CHIP_REV_YU_FE2_A0) {
  464. /* apply workaround for integrated resistors calibration */
  465. gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
  466. gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
  467. } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
  468. hw->chip_id < CHIP_ID_YUKON_SUPR) {
  469. /* no effect on Yukon-XL */
  470. gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
  471. if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
  472. /* turn on 100 Mbps LED (LED_LINK100) */
  473. ledover |= PHY_M_LED_MO_100(MO_LED_ON);
  474. }
  475. if (ledover)
  476. gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
  477. }
  478. /* Enable phy interrupt on auto-negotiation complete (or link up) */
  479. if (sky2->autoneg == AUTONEG_ENABLE)
  480. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
  481. else
  482. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
  483. }
  484. static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
  485. static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
  486. static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
  487. {
  488. u32 reg1;
  489. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  490. reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
  491. reg1 &= ~phy_power[port];
  492. if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
  493. reg1 |= coma_mode[port];
  494. sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
  495. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  496. sky2_pci_read32(hw, PCI_DEV_REG1);
  497. if (hw->chip_id == CHIP_ID_YUKON_FE)
  498. gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
  499. else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
  500. sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
  501. }
  502. static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
  503. {
  504. u32 reg1;
  505. u16 ctrl;
  506. /* release GPHY Control reset */
  507. sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
  508. /* release GMAC reset */
  509. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
  510. if (hw->flags & SKY2_HW_NEWER_PHY) {
  511. /* select page 2 to access MAC control register */
  512. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
  513. ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  514. /* allow GMII Power Down */
  515. ctrl &= ~PHY_M_MAC_GMIF_PUP;
  516. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
  517. /* set page register back to 0 */
  518. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
  519. }
  520. /* setup General Purpose Control Register */
  521. gma_write16(hw, port, GM_GP_CTRL,
  522. GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 | GM_GPCR_AU_ALL_DIS);
  523. if (hw->chip_id != CHIP_ID_YUKON_EC) {
  524. if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
  525. /* select page 2 to access MAC control register */
  526. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
  527. ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
  528. /* enable Power Down */
  529. ctrl |= PHY_M_PC_POW_D_ENA;
  530. gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
  531. /* set page register back to 0 */
  532. gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
  533. }
  534. /* set IEEE compatible Power Down Mode (dev. #4.99) */
  535. gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
  536. }
  537. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  538. reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
  539. reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
  540. sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
  541. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  542. }
  543. static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
  544. {
  545. if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
  546. hw->chip_rev != CHIP_REV_YU_EX_A0) ||
  547. hw->chip_id == CHIP_ID_YUKON_FE_P ||
  548. hw->chip_id == CHIP_ID_YUKON_SUPR) {
  549. /* disable jumbo frames on devices that support them */
  550. sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
  551. TX_JUMBO_DIS | TX_STFW_ENA);
  552. } else {
  553. sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
  554. }
  555. }
  556. static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
  557. {
  558. u16 reg;
  559. u32 rx_reg;
  560. int i;
  561. const u8 *addr = hw->dev[port]->ll_addr;
  562. sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
  563. sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
  564. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
  565. if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
  566. /* WA DEV_472 -- looks like crossed wires on port 2 */
  567. /* clear GMAC 1 Control reset */
  568. sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
  569. do {
  570. sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
  571. sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
  572. } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
  573. gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
  574. gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
  575. }
  576. sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
  577. /* Enable Transmit FIFO Underrun */
  578. sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
  579. sky2_phy_power_up(hw, port);
  580. sky2_phy_init(hw, port);
  581. /* MIB clear */
  582. reg = gma_read16(hw, port, GM_PHY_ADDR);
  583. gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
  584. for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
  585. gma_read16(hw, port, i);
  586. gma_write16(hw, port, GM_PHY_ADDR, reg);
  587. /* transmit control */
  588. gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
  589. /* receive control reg: unicast + multicast + no FCS */
  590. gma_write16(hw, port, GM_RX_CTRL,
  591. GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
  592. /* transmit flow control */
  593. gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
  594. /* transmit parameter */
  595. gma_write16(hw, port, GM_TX_PARAM,
  596. TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
  597. TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
  598. TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
  599. TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
  600. /* serial mode register */
  601. reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
  602. GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
  603. gma_write16(hw, port, GM_SERIAL_MODE, reg);
  604. /* virtual address for data */
  605. gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
  606. /* physical address: used for pause frames */
  607. gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
  608. /* ignore counter overflows */
  609. gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
  610. gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
  611. gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
  612. /* Configure Rx MAC FIFO */
  613. sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
  614. rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
  615. if (hw->chip_id == CHIP_ID_YUKON_EX ||
  616. hw->chip_id == CHIP_ID_YUKON_FE_P)
  617. rx_reg |= GMF_RX_OVER_ON;
  618. sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
  619. if (hw->chip_id == CHIP_ID_YUKON_XL) {
  620. /* Hardware errata - clear flush mask */
  621. sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
  622. } else {
  623. /* Flush Rx MAC FIFO on any flow control or error */
  624. sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
  625. }
  626. /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
  627. reg = RX_GMF_FL_THR_DEF + 1;
  628. /* Another magic mystery workaround from sk98lin */
  629. if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
  630. hw->chip_rev == CHIP_REV_YU_FE2_A0)
  631. reg = 0x178;
  632. sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
  633. /* Configure Tx MAC FIFO */
  634. sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
  635. sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
  636. /* On chips without ram buffer, pause is controlled by MAC level */
  637. if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
  638. sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
  639. sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
  640. sky2_set_tx_stfwd(hw, port);
  641. }
  642. if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
  643. hw->chip_rev == CHIP_REV_YU_FE2_A0) {
  644. /* disable dynamic watermark */
  645. reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
  646. reg &= ~TX_DYN_WM_ENA;
  647. sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
  648. }
  649. }
  650. /* Assign Ram Buffer allocation to queue */
  651. static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
  652. {
  653. u32 end;
  654. /* convert from K bytes to qwords used for hw register */
  655. start *= 1024/8;
  656. space *= 1024/8;
  657. end = start + space - 1;
  658. sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
  659. sky2_write32(hw, RB_ADDR(q, RB_START), start);
  660. sky2_write32(hw, RB_ADDR(q, RB_END), end);
  661. sky2_write32(hw, RB_ADDR(q, RB_WP), start);
  662. sky2_write32(hw, RB_ADDR(q, RB_RP), start);
  663. if (q == Q_R1 || q == Q_R2) {
  664. u32 tp = space - space/4;
  665. /* On receive queue's set the thresholds
  666. * give receiver priority when > 3/4 full
  667. * send pause when down to 2K
  668. */
  669. sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
  670. sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
  671. tp = space - 2048/8;
  672. sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
  673. sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
  674. } else {
  675. /* Enable store & forward on Tx queue's because
  676. * Tx FIFO is only 1K on Yukon
  677. */
  678. sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
  679. }
  680. sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
  681. sky2_read8(hw, RB_ADDR(q, RB_CTRL));
  682. }
  683. /* Setup Bus Memory Interface */
  684. static void sky2_qset(struct sky2_hw *hw, u16 q)
  685. {
  686. sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
  687. sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
  688. sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
  689. sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
  690. }
  691. /* Setup prefetch unit registers. This is the interface between
  692. * hardware and driver list elements
  693. */
  694. static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
  695. u64 addr, u32 last)
  696. {
  697. sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
  698. sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
  699. sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
  700. sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
  701. sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
  702. sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
  703. sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
  704. }
  705. static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
  706. {
  707. struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
  708. sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
  709. le->ctrl = 0;
  710. return le;
  711. }
  712. static void tx_init(struct sky2_port *sky2)
  713. {
  714. struct sky2_tx_le *le;
  715. sky2->tx_prod = sky2->tx_cons = 0;
  716. le = get_tx_le(sky2);
  717. le->addr = 0;
  718. le->opcode = OP_ADDR64 | HW_OWNER;
  719. }
  720. static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
  721. struct sky2_tx_le *le)
  722. {
  723. return sky2->tx_ring + (le - sky2->tx_le);
  724. }
  725. /* Update chip's next pointer */
  726. static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
  727. {
  728. /* Make sure write' to descriptors are complete before we tell hardware */
  729. wmb();
  730. sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
  731. DBGIO(PFX "queue %#x idx <- %d\n", q, idx);
  732. }
  733. static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
  734. {
  735. struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
  736. sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
  737. le->ctrl = 0;
  738. return le;
  739. }
  740. /* Build description to hardware for one receive segment */
  741. static void sky2_rx_add(struct sky2_port *sky2, u8 op,
  742. u32 map, unsigned len)
  743. {
  744. struct sky2_rx_le *le;
  745. le = sky2_next_rx(sky2);
  746. le->addr = cpu_to_le32(map);
  747. le->length = cpu_to_le16(len);
  748. le->opcode = op | HW_OWNER;
  749. }
  750. /* Build description to hardware for one possibly fragmented skb */
  751. static void sky2_rx_submit(struct sky2_port *sky2,
  752. const struct rx_ring_info *re)
  753. {
  754. sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
  755. }
  756. static void sky2_rx_map_iob(struct pci_device *pdev __unused,
  757. struct rx_ring_info *re,
  758. unsigned size __unused)
  759. {
  760. struct io_buffer *iob = re->iob;
  761. re->data_addr = virt_to_bus(iob->data);
  762. }
  763. /* Diable the checksum offloading.
  764. */
  765. static void rx_set_checksum(struct sky2_port *sky2)
  766. {
  767. struct sky2_rx_le *le = sky2_next_rx(sky2);
  768. le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
  769. le->ctrl = 0;
  770. le->opcode = OP_TCPSTART | HW_OWNER;
  771. sky2_write32(sky2->hw,
  772. Q_ADDR(rxqaddr[sky2->port], Q_CSR),
  773. BMU_DIS_RX_CHKSUM);
  774. }
  775. /*
  776. * The RX Stop command will not work for Yukon-2 if the BMU does not
  777. * reach the end of packet and since we can't make sure that we have
  778. * incoming data, we must reset the BMU while it is not doing a DMA
  779. * transfer. Since it is possible that the RX path is still active,
  780. * the RX RAM buffer will be stopped first, so any possible incoming
  781. * data will not trigger a DMA. After the RAM buffer is stopped, the
  782. * BMU is polled until any DMA in progress is ended and only then it
  783. * will be reset.
  784. */
  785. static void sky2_rx_stop(struct sky2_port *sky2)
  786. {
  787. struct sky2_hw *hw = sky2->hw;
  788. unsigned rxq = rxqaddr[sky2->port];
  789. int i;
  790. /* disable the RAM Buffer receive queue */
  791. sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
  792. for (i = 0; i < 0xffff; i++)
  793. if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
  794. == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
  795. goto stopped;
  796. DBG(PFX "%s: receiver stop failed\n", sky2->netdev->name);
  797. stopped:
  798. sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
  799. /* reset the Rx prefetch unit */
  800. sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
  801. wmb();
  802. }
  803. /* Clean out receive buffer area, assumes receiver hardware stopped */
  804. static void sky2_rx_clean(struct sky2_port *sky2)
  805. {
  806. unsigned i;
  807. memset(sky2->rx_le, 0, RX_LE_BYTES);
  808. for (i = 0; i < RX_PENDING; i++) {
  809. struct rx_ring_info *re = sky2->rx_ring + i;
  810. if (re->iob) {
  811. free_iob(re->iob);
  812. re->iob = NULL;
  813. }
  814. }
  815. }
  816. /*
  817. * Allocate an iob for receiving.
  818. */
  819. static struct io_buffer *sky2_rx_alloc(struct sky2_port *sky2)
  820. {
  821. struct io_buffer *iob;
  822. iob = alloc_iob(sky2->rx_data_size + ETH_DATA_ALIGN);
  823. if (!iob)
  824. return NULL;
  825. /*
  826. * Cards with a RAM buffer hang in the rx FIFO if the
  827. * receive buffer isn't aligned to (Linux module comments say
  828. * 64 bytes, Linux module code says 8 bytes). Since io_buffers
  829. * are always 2kb-aligned under iPXE, just leave it be
  830. * without ETH_DATA_ALIGN in those cases.
  831. *
  832. * XXX This causes unaligned access to the IP header,
  833. * which is undesirable, but it's less undesirable than the
  834. * card hanging.
  835. */
  836. if (!(sky2->hw->flags & SKY2_HW_RAM_BUFFER)) {
  837. iob_reserve(iob, ETH_DATA_ALIGN);
  838. }
  839. return iob;
  840. }
  841. static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
  842. {
  843. sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
  844. }
  845. /*
  846. * Allocate and setup receiver buffer pool.
  847. * Normal case this ends up creating one list element for skb
  848. * in the receive ring. One element is used for checksum
  849. * enable/disable, and one extra to avoid wrap.
  850. */
  851. static int sky2_rx_start(struct sky2_port *sky2)
  852. {
  853. struct sky2_hw *hw = sky2->hw;
  854. struct rx_ring_info *re;
  855. unsigned rxq = rxqaddr[sky2->port];
  856. unsigned i, size, thresh;
  857. sky2->rx_put = sky2->rx_next = 0;
  858. sky2_qset(hw, rxq);
  859. /* On PCI express lowering the watermark gives better performance */
  860. if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
  861. sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
  862. /* These chips have no ram buffer?
  863. * MAC Rx RAM Read is controlled by hardware */
  864. if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
  865. (hw->chip_rev == CHIP_REV_YU_EC_U_A1
  866. || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
  867. sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
  868. sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
  869. if (!(hw->flags & SKY2_HW_NEW_LE))
  870. rx_set_checksum(sky2);
  871. /* Space needed for frame data + headers rounded up */
  872. size = (ETH_FRAME_LEN + 8) & ~7;
  873. /* Stopping point for hardware truncation */
  874. thresh = (size - 8) / sizeof(u32);
  875. sky2->rx_data_size = size;
  876. /* Fill Rx ring */
  877. for (i = 0; i < RX_PENDING; i++) {
  878. re = sky2->rx_ring + i;
  879. re->iob = sky2_rx_alloc(sky2);
  880. if (!re->iob)
  881. goto nomem;
  882. sky2_rx_map_iob(hw->pdev, re, sky2->rx_data_size);
  883. sky2_rx_submit(sky2, re);
  884. }
  885. /*
  886. * The receiver hangs if it receives frames larger than the
  887. * packet buffer. As a workaround, truncate oversize frames, but
  888. * the register is limited to 9 bits, so if you do frames > 2052
  889. * you better get the MTU right!
  890. */
  891. if (thresh > 0x1ff)
  892. sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
  893. else {
  894. sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
  895. sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
  896. }
  897. /* Tell chip about available buffers */
  898. sky2_rx_update(sky2, rxq);
  899. return 0;
  900. nomem:
  901. sky2_rx_clean(sky2);
  902. return -ENOMEM;
  903. }
  904. /* Free the le and ring buffers */
  905. static void sky2_free_rings(struct sky2_port *sky2)
  906. {
  907. free_dma(sky2->rx_le, RX_LE_BYTES);
  908. free(sky2->rx_ring);
  909. free_dma(sky2->tx_le, TX_RING_SIZE * sizeof(struct sky2_tx_le));
  910. free(sky2->tx_ring);
  911. sky2->tx_le = NULL;
  912. sky2->rx_le = NULL;
  913. sky2->rx_ring = NULL;
  914. sky2->tx_ring = NULL;
  915. }
  916. /* Bring up network interface. */
  917. static int sky2_up(struct net_device *dev)
  918. {
  919. struct sky2_port *sky2 = netdev_priv(dev);
  920. struct sky2_hw *hw = sky2->hw;
  921. unsigned port = sky2->port;
  922. u32 imask, ramsize;
  923. int err = -ENOMEM;
  924. netdev_link_down(dev);
  925. /* must be power of 2 */
  926. sky2->tx_le = malloc_dma(TX_RING_SIZE * sizeof(struct sky2_tx_le), TX_RING_ALIGN);
  927. sky2->tx_le_map = virt_to_bus(sky2->tx_le);
  928. if (!sky2->tx_le)
  929. goto err_out;
  930. memset(sky2->tx_le, 0, TX_RING_SIZE * sizeof(struct sky2_tx_le));
  931. sky2->tx_ring = zalloc(TX_RING_SIZE * sizeof(struct tx_ring_info));
  932. if (!sky2->tx_ring)
  933. goto err_out;
  934. tx_init(sky2);
  935. sky2->rx_le = malloc_dma(RX_LE_BYTES, RX_RING_ALIGN);
  936. sky2->rx_le_map = virt_to_bus(sky2->rx_le);
  937. if (!sky2->rx_le)
  938. goto err_out;
  939. memset(sky2->rx_le, 0, RX_LE_BYTES);
  940. sky2->rx_ring = zalloc(RX_PENDING * sizeof(struct rx_ring_info));
  941. if (!sky2->rx_ring)
  942. goto err_out;
  943. sky2_mac_init(hw, port);
  944. /* Register is number of 4K blocks on internal RAM buffer. */
  945. ramsize = sky2_read8(hw, B2_E_0) * 4;
  946. if (ramsize > 0) {
  947. u32 rxspace;
  948. hw->flags |= SKY2_HW_RAM_BUFFER;
  949. DBG2(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
  950. if (ramsize < 16)
  951. rxspace = ramsize / 2;
  952. else
  953. rxspace = 8 + (2*(ramsize - 16))/3;
  954. sky2_ramset(hw, rxqaddr[port], 0, rxspace);
  955. sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
  956. /* Make sure SyncQ is disabled */
  957. sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
  958. RB_RST_SET);
  959. }
  960. sky2_qset(hw, txqaddr[port]);
  961. /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
  962. if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
  963. sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
  964. /* Set almost empty threshold */
  965. if (hw->chip_id == CHIP_ID_YUKON_EC_U
  966. && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
  967. sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
  968. sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
  969. TX_RING_SIZE - 1);
  970. err = sky2_rx_start(sky2);
  971. if (err)
  972. goto err_out;
  973. /* Enable interrupts from phy/mac for port */
  974. imask = sky2_read32(hw, B0_IMSK);
  975. imask |= portirq_msk[port];
  976. sky2_write32(hw, B0_IMSK, imask);
  977. DBGIO(PFX "%s: le bases: st %p [%x], rx %p [%x], tx %p [%x]\n",
  978. dev->name, hw->st_le, hw->st_dma, sky2->rx_le, sky2->rx_le_map,
  979. sky2->tx_le, sky2->tx_le_map);
  980. sky2_set_multicast(dev);
  981. return 0;
  982. err_out:
  983. sky2_free_rings(sky2);
  984. return err;
  985. }
  986. /* Modular subtraction in ring */
  987. static inline int tx_dist(unsigned tail, unsigned head)
  988. {
  989. return (head - tail) & (TX_RING_SIZE - 1);
  990. }
  991. /* Number of list elements available for next tx */
  992. static inline int tx_avail(const struct sky2_port *sky2)
  993. {
  994. return TX_PENDING - tx_dist(sky2->tx_cons, sky2->tx_prod);
  995. }
  996. /*
  997. * Put one packet in ring for transmit.
  998. * A single packet can generate multiple list elements, and
  999. * the number of ring elements will probably be less than the number
  1000. * of list elements used.
  1001. */
  1002. static int sky2_xmit_frame(struct net_device *dev, struct io_buffer *iob)
  1003. {
  1004. struct sky2_port *sky2 = netdev_priv(dev);
  1005. struct sky2_hw *hw = sky2->hw;
  1006. struct sky2_tx_le *le = NULL;
  1007. struct tx_ring_info *re;
  1008. unsigned len;
  1009. u32 mapping;
  1010. u8 ctrl;
  1011. if (tx_avail(sky2) < 1)
  1012. return -EBUSY;
  1013. len = iob_len(iob);
  1014. mapping = virt_to_bus(iob->data);
  1015. DBGIO(PFX "%s: tx queued, slot %d, len %d\n", dev->name,
  1016. sky2->tx_prod, len);
  1017. ctrl = 0;
  1018. le = get_tx_le(sky2);
  1019. le->addr = cpu_to_le32((u32) mapping);
  1020. le->length = cpu_to_le16(len);
  1021. le->ctrl = ctrl;
  1022. le->opcode = (OP_PACKET | HW_OWNER);
  1023. re = tx_le_re(sky2, le);
  1024. re->iob = iob;
  1025. le->ctrl |= EOP;
  1026. sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
  1027. return 0;
  1028. }
  1029. /*
  1030. * Free ring elements from starting at tx_cons until "done"
  1031. *
  1032. * NB: the hardware will tell us about partial completion of multi-part
  1033. * buffers so make sure not to free iob too early.
  1034. */
  1035. static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
  1036. {
  1037. struct net_device *dev = sky2->netdev;
  1038. unsigned idx;
  1039. assert(done < TX_RING_SIZE);
  1040. for (idx = sky2->tx_cons; idx != done;
  1041. idx = RING_NEXT(idx, TX_RING_SIZE)) {
  1042. struct sky2_tx_le *le = sky2->tx_le + idx;
  1043. struct tx_ring_info *re = sky2->tx_ring + idx;
  1044. if (le->ctrl & EOP) {
  1045. DBGIO(PFX "%s: tx done %d\n", dev->name, idx);
  1046. netdev_tx_complete(dev, re->iob);
  1047. }
  1048. }
  1049. sky2->tx_cons = idx;
  1050. mb();
  1051. }
  1052. /* Cleanup all untransmitted buffers, assume transmitter not running */
  1053. static void sky2_tx_clean(struct net_device *dev)
  1054. {
  1055. struct sky2_port *sky2 = netdev_priv(dev);
  1056. sky2_tx_complete(sky2, sky2->tx_prod);
  1057. }
  1058. /* Network shutdown */
  1059. static void sky2_down(struct net_device *dev)
  1060. {
  1061. struct sky2_port *sky2 = netdev_priv(dev);
  1062. struct sky2_hw *hw = sky2->hw;
  1063. unsigned port = sky2->port;
  1064. u16 ctrl;
  1065. u32 imask;
  1066. /* Never really got started! */
  1067. if (!sky2->tx_le)
  1068. return;
  1069. DBG2(PFX "%s: disabling interface\n", dev->name);
  1070. /* Disable port IRQ */
  1071. imask = sky2_read32(hw, B0_IMSK);
  1072. imask &= ~portirq_msk[port];
  1073. sky2_write32(hw, B0_IMSK, imask);
  1074. sky2_gmac_reset(hw, port);
  1075. /* Stop transmitter */
  1076. sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
  1077. sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
  1078. sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
  1079. RB_RST_SET | RB_DIS_OP_MD);
  1080. ctrl = gma_read16(hw, port, GM_GP_CTRL);
  1081. ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
  1082. gma_write16(hw, port, GM_GP_CTRL, ctrl);
  1083. sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
  1084. /* Workaround shared GMAC reset */
  1085. if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
  1086. && port == 0 && hw->dev[1]))
  1087. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
  1088. /* Disable Force Sync bit and Enable Alloc bit */
  1089. sky2_write8(hw, SK_REG(port, TXA_CTRL),
  1090. TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
  1091. /* Stop Interval Timer and Limit Counter of Tx Arbiter */
  1092. sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
  1093. sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
  1094. /* Reset the PCI FIFO of the async Tx queue */
  1095. sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
  1096. BMU_RST_SET | BMU_FIFO_RST);
  1097. /* Reset the Tx prefetch units */
  1098. sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
  1099. PREF_UNIT_RST_SET);
  1100. sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
  1101. sky2_rx_stop(sky2);
  1102. sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
  1103. sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
  1104. sky2_phy_power_down(hw, port);
  1105. /* turn off LED's */
  1106. sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
  1107. sky2_tx_clean(dev);
  1108. sky2_rx_clean(sky2);
  1109. sky2_free_rings(sky2);
  1110. return;
  1111. }
  1112. static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
  1113. {
  1114. if (hw->flags & SKY2_HW_FIBRE_PHY)
  1115. return SPEED_1000;
  1116. if (!(hw->flags & SKY2_HW_GIGABIT)) {
  1117. if (aux & PHY_M_PS_SPEED_100)
  1118. return SPEED_100;
  1119. else
  1120. return SPEED_10;
  1121. }
  1122. switch (aux & PHY_M_PS_SPEED_MSK) {
  1123. case PHY_M_PS_SPEED_1000:
  1124. return SPEED_1000;
  1125. case PHY_M_PS_SPEED_100:
  1126. return SPEED_100;
  1127. default:
  1128. return SPEED_10;
  1129. }
  1130. }
  1131. static void sky2_link_up(struct sky2_port *sky2)
  1132. {
  1133. struct sky2_hw *hw = sky2->hw;
  1134. unsigned port = sky2->port;
  1135. u16 reg;
  1136. static const char *fc_name[] = {
  1137. [FC_NONE] = "none",
  1138. [FC_TX] = "tx",
  1139. [FC_RX] = "rx",
  1140. [FC_BOTH] = "both",
  1141. };
  1142. /* enable Rx/Tx */
  1143. reg = gma_read16(hw, port, GM_GP_CTRL);
  1144. reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
  1145. gma_write16(hw, port, GM_GP_CTRL, reg);
  1146. gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
  1147. netdev_link_up(sky2->netdev);
  1148. /* Turn on link LED */
  1149. sky2_write8(hw, SK_REG(port, LNK_LED_REG),
  1150. LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
  1151. DBG(PFX "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
  1152. sky2->netdev->name, sky2->speed,
  1153. sky2->duplex == DUPLEX_FULL ? "full" : "half",
  1154. fc_name[sky2->flow_status]);
  1155. }
  1156. static void sky2_link_down(struct sky2_port *sky2)
  1157. {
  1158. struct sky2_hw *hw = sky2->hw;
  1159. unsigned port = sky2->port;
  1160. u16 reg;
  1161. gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
  1162. reg = gma_read16(hw, port, GM_GP_CTRL);
  1163. reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
  1164. gma_write16(hw, port, GM_GP_CTRL, reg);
  1165. netdev_link_down(sky2->netdev);
  1166. /* Turn on link LED */
  1167. sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
  1168. DBG(PFX "%s: Link is down.\n", sky2->netdev->name);
  1169. sky2_phy_init(hw, port);
  1170. }
  1171. static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
  1172. {
  1173. struct sky2_hw *hw = sky2->hw;
  1174. unsigned port = sky2->port;
  1175. u16 advert, lpa;
  1176. advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
  1177. lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
  1178. if (lpa & PHY_M_AN_RF) {
  1179. DBG(PFX "%s: remote fault\n", sky2->netdev->name);
  1180. return -1;
  1181. }
  1182. if (!(aux & PHY_M_PS_SPDUP_RES)) {
  1183. DBG(PFX "%s: speed/duplex mismatch\n", sky2->netdev->name);
  1184. return -1;
  1185. }
  1186. sky2->speed = sky2_phy_speed(hw, aux);
  1187. sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
  1188. /* Since the pause result bits seem to in different positions on
  1189. * different chips. look at registers.
  1190. */
  1191. sky2->flow_status = FC_NONE;
  1192. if (advert & ADVERTISE_PAUSE_CAP) {
  1193. if (lpa & LPA_PAUSE_CAP)
  1194. sky2->flow_status = FC_BOTH;
  1195. else if (advert & ADVERTISE_PAUSE_ASYM)
  1196. sky2->flow_status = FC_RX;
  1197. } else if (advert & ADVERTISE_PAUSE_ASYM) {
  1198. if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
  1199. sky2->flow_status = FC_TX;
  1200. }
  1201. if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
  1202. && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
  1203. sky2->flow_status = FC_NONE;
  1204. if (sky2->flow_status & FC_TX)
  1205. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
  1206. else
  1207. sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
  1208. return 0;
  1209. }
  1210. /* Interrupt from PHY */
  1211. static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
  1212. {
  1213. struct net_device *dev = hw->dev[port];
  1214. struct sky2_port *sky2 = netdev_priv(dev);
  1215. u16 istatus, phystat;
  1216. istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
  1217. phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
  1218. DBGIO(PFX "%s: phy interrupt status 0x%x 0x%x\n",
  1219. sky2->netdev->name, istatus, phystat);
  1220. if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
  1221. if (sky2_autoneg_done(sky2, phystat) == 0)
  1222. sky2_link_up(sky2);
  1223. return;
  1224. }
  1225. if (istatus & PHY_M_IS_LSP_CHANGE)
  1226. sky2->speed = sky2_phy_speed(hw, phystat);
  1227. if (istatus & PHY_M_IS_DUP_CHANGE)
  1228. sky2->duplex =
  1229. (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
  1230. if (istatus & PHY_M_IS_LST_CHANGE) {
  1231. if (phystat & PHY_M_PS_LINK_UP)
  1232. sky2_link_up(sky2);
  1233. else
  1234. sky2_link_down(sky2);
  1235. }
  1236. }
  1237. /* Normal packet - take iob from ring element and put in a new one */
  1238. static struct io_buffer *receive_new(struct sky2_port *sky2,
  1239. struct rx_ring_info *re,
  1240. unsigned int length)
  1241. {
  1242. struct io_buffer *iob, *niob;
  1243. unsigned hdr_space = sky2->rx_data_size;
  1244. /* Don't be tricky about reusing pages (yet) */
  1245. niob = sky2_rx_alloc(sky2);
  1246. if (!niob)
  1247. return NULL;
  1248. iob = re->iob;
  1249. re->iob = niob;
  1250. sky2_rx_map_iob(sky2->hw->pdev, re, hdr_space);
  1251. iob_put(iob, length);
  1252. return iob;
  1253. }
  1254. /*
  1255. * Receive one packet.
  1256. * For larger packets, get new buffer.
  1257. */
  1258. static struct io_buffer *sky2_receive(struct net_device *dev,
  1259. u16 length, u32 status)
  1260. {
  1261. struct sky2_port *sky2 = netdev_priv(dev);
  1262. struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
  1263. struct io_buffer *iob = NULL;
  1264. u16 count = (status & GMR_FS_LEN) >> 16;
  1265. DBGIO(PFX "%s: rx slot %d status 0x%x len %d\n",
  1266. dev->name, sky2->rx_next, status, length);
  1267. sky2->rx_next = (sky2->rx_next + 1) % RX_PENDING;
  1268. /* This chip has hardware problems that generates bogus status.
  1269. * So do only marginal checking and expect higher level protocols
  1270. * to handle crap frames.
  1271. */
  1272. if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
  1273. sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
  1274. length == count)
  1275. goto okay;
  1276. if (status & GMR_FS_ANY_ERR)
  1277. goto error;
  1278. if (!(status & GMR_FS_RX_OK))
  1279. goto resubmit;
  1280. /* if length reported by DMA does not match PHY, packet was truncated */
  1281. if (length != count)
  1282. goto len_error;
  1283. okay:
  1284. iob = receive_new(sky2, re, length);
  1285. resubmit:
  1286. sky2_rx_submit(sky2, re);
  1287. return iob;
  1288. len_error:
  1289. /* Truncation of overlength packets
  1290. causes PHY length to not match MAC length */
  1291. DBG2(PFX "%s: rx length error: status %#x length %d\n",
  1292. dev->name, status, length);
  1293. /* Pass NULL as iob because we want to keep our iob in the
  1294. ring for the next packet. */
  1295. netdev_rx_err(dev, NULL, -EINVAL);
  1296. goto resubmit;
  1297. error:
  1298. if (status & GMR_FS_RX_FF_OV) {
  1299. DBG2(PFX "%s: FIFO overflow error\n", dev->name);
  1300. netdev_rx_err(dev, NULL, -EBUSY);
  1301. goto resubmit;
  1302. }
  1303. DBG2(PFX "%s: rx error, status 0x%x length %d\n",
  1304. dev->name, status, length);
  1305. netdev_rx_err(dev, NULL, -EIO);
  1306. goto resubmit;
  1307. }
  1308. /* Transmit complete */
  1309. static inline void sky2_tx_done(struct net_device *dev, u16 last)
  1310. {
  1311. struct sky2_port *sky2 = netdev_priv(dev);
  1312. sky2_tx_complete(sky2, last);
  1313. }
  1314. /* Process status response ring */
  1315. static void sky2_status_intr(struct sky2_hw *hw, u16 idx)
  1316. {
  1317. unsigned rx[2] = { 0, 0 };
  1318. rmb();
  1319. do {
  1320. struct sky2_status_le *le = hw->st_le + hw->st_idx;
  1321. unsigned port;
  1322. struct net_device *dev;
  1323. struct io_buffer *iob;
  1324. u32 status;
  1325. u16 length;
  1326. u8 opcode = le->opcode;
  1327. if (!(opcode & HW_OWNER))
  1328. break;
  1329. port = le->css & CSS_LINK_BIT;
  1330. dev = hw->dev[port];
  1331. length = le16_to_cpu(le->length);
  1332. status = le32_to_cpu(le->status);
  1333. hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
  1334. le->opcode = 0;
  1335. switch (opcode & ~HW_OWNER) {
  1336. case OP_RXSTAT:
  1337. ++rx[port];
  1338. iob = sky2_receive(dev, length, status);
  1339. if (!iob) {
  1340. netdev_rx_err(dev, NULL, -ENOMEM);
  1341. break;
  1342. }
  1343. netdev_rx(dev, iob);
  1344. break;
  1345. case OP_RXCHKS:
  1346. DBG2(PFX "status OP_RXCHKS but checksum offloading disabled\n");
  1347. break;
  1348. case OP_TXINDEXLE:
  1349. /* TX index reports status for both ports */
  1350. assert(TX_RING_SIZE <= 0x1000);
  1351. sky2_tx_done(hw->dev[0], status & 0xfff);
  1352. if (hw->dev[1])
  1353. sky2_tx_done(hw->dev[1],
  1354. ((status >> 24) & 0xff)
  1355. | (u16)(length & 0xf) << 8);
  1356. break;
  1357. default:
  1358. DBG(PFX "unknown status opcode 0x%x\n", opcode);
  1359. }
  1360. } while (hw->st_idx != idx);
  1361. /* Fully processed status ring so clear irq */
  1362. sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
  1363. if (rx[0])
  1364. sky2_rx_update(netdev_priv(hw->dev[0]), Q_R1);
  1365. if (rx[1])
  1366. sky2_rx_update(netdev_priv(hw->dev[1]), Q_R2);
  1367. }
  1368. static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
  1369. {
  1370. struct net_device *dev = hw->dev[port];
  1371. DBGIO(PFX "%s: hw error interrupt status 0x%x\n", dev->name, status);
  1372. if (status & Y2_IS_PAR_RD1) {
  1373. DBG(PFX "%s: ram data read parity error\n", dev->name);
  1374. /* Clear IRQ */
  1375. sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
  1376. }
  1377. if (status & Y2_IS_PAR_WR1) {
  1378. DBG(PFX "%s: ram data write parity error\n", dev->name);
  1379. sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
  1380. }
  1381. if (status & Y2_IS_PAR_MAC1) {
  1382. DBG(PFX "%s: MAC parity error\n", dev->name);
  1383. sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
  1384. }
  1385. if (status & Y2_IS_PAR_RX1) {
  1386. DBG(PFX "%s: RX parity error\n", dev->name);
  1387. sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
  1388. }
  1389. if (status & Y2_IS_TCP_TXA1) {
  1390. DBG(PFX "%s: TCP segmentation error\n", dev->name);
  1391. sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
  1392. }
  1393. }
  1394. static void sky2_hw_intr(struct sky2_hw *hw)
  1395. {
  1396. u32 status = sky2_read32(hw, B0_HWE_ISRC);
  1397. u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
  1398. status &= hwmsk;
  1399. if (status & Y2_IS_TIST_OV)
  1400. sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
  1401. if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
  1402. u16 pci_err;
  1403. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  1404. pci_err = sky2_pci_read16(hw, PCI_STATUS);
  1405. DBG(PFX "PCI hardware error (0x%x)\n", pci_err);
  1406. sky2_pci_write16(hw, PCI_STATUS,
  1407. pci_err | PCI_STATUS_ERROR_BITS);
  1408. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  1409. }
  1410. if (status & Y2_IS_PCI_EXP) {
  1411. /* PCI-Express uncorrectable Error occurred */
  1412. u32 err;
  1413. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  1414. err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
  1415. sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
  1416. 0xfffffffful);
  1417. DBG(PFX "PCI-Express error (0x%x)\n", err);
  1418. sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
  1419. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  1420. }
  1421. if (status & Y2_HWE_L1_MASK)
  1422. sky2_hw_error(hw, 0, status);
  1423. status >>= 8;
  1424. if (status & Y2_HWE_L1_MASK)
  1425. sky2_hw_error(hw, 1, status);
  1426. }
  1427. static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
  1428. {
  1429. struct net_device *dev = hw->dev[port];
  1430. u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
  1431. DBGIO(PFX "%s: mac interrupt status 0x%x\n", dev->name, status);
  1432. if (status & GM_IS_RX_CO_OV)
  1433. gma_read16(hw, port, GM_RX_IRQ_SRC);
  1434. if (status & GM_IS_TX_CO_OV)
  1435. gma_read16(hw, port, GM_TX_IRQ_SRC);
  1436. if (status & GM_IS_RX_FF_OR) {
  1437. sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
  1438. }
  1439. if (status & GM_IS_TX_FF_UR) {
  1440. sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
  1441. }
  1442. }
  1443. /* This should never happen it is a bug. */
  1444. static void sky2_le_error(struct sky2_hw *hw, unsigned port,
  1445. u16 q, unsigned ring_size __unused)
  1446. {
  1447. struct net_device *dev = hw->dev[port];
  1448. struct sky2_port *sky2 = netdev_priv(dev);
  1449. int idx;
  1450. const u64 *le = (q == Q_R1 || q == Q_R2)
  1451. ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
  1452. idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
  1453. DBG(PFX "%s: descriptor error q=%#x get=%d [%llx] last=%d put=%d should be %d\n",
  1454. dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
  1455. (int) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_LAST_IDX)),
  1456. (int) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)),
  1457. le == (u64 *)sky2->rx_le? sky2->rx_put : sky2->tx_prod);
  1458. sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
  1459. }
  1460. /* Hardware/software error handling */
  1461. static void sky2_err_intr(struct sky2_hw *hw, u32 status)
  1462. {
  1463. DBG(PFX "error interrupt status=%#x\n", status);
  1464. if (status & Y2_IS_HW_ERR)
  1465. sky2_hw_intr(hw);
  1466. if (status & Y2_IS_IRQ_MAC1)
  1467. sky2_mac_intr(hw, 0);
  1468. if (status & Y2_IS_IRQ_MAC2)
  1469. sky2_mac_intr(hw, 1);
  1470. if (status & Y2_IS_CHK_RX1)
  1471. sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
  1472. if (status & Y2_IS_CHK_RX2)
  1473. sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
  1474. if (status & Y2_IS_CHK_TXA1)
  1475. sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
  1476. if (status & Y2_IS_CHK_TXA2)
  1477. sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
  1478. }
  1479. static void sky2_poll(struct net_device *dev)
  1480. {
  1481. struct sky2_port *sky2 = netdev_priv(dev);
  1482. struct sky2_hw *hw = sky2->hw;
  1483. u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
  1484. u16 idx;
  1485. if (status & Y2_IS_ERROR)
  1486. sky2_err_intr(hw, status);
  1487. if (status & Y2_IS_IRQ_PHY1)
  1488. sky2_phy_intr(hw, 0);
  1489. if (status & Y2_IS_IRQ_PHY2)
  1490. sky2_phy_intr(hw, 1);
  1491. while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
  1492. sky2_status_intr(hw, idx);
  1493. }
  1494. /* Bug/Errata workaround?
  1495. * Need to kick the TX irq moderation timer.
  1496. */
  1497. if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_START) {
  1498. sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
  1499. sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
  1500. }
  1501. sky2_read32(hw, B0_Y2_SP_LISR);
  1502. }
  1503. /* Chip internal frequency for clock calculations */
  1504. static u32 sky2_mhz(const struct sky2_hw *hw)
  1505. {
  1506. switch (hw->chip_id) {
  1507. case CHIP_ID_YUKON_EC:
  1508. case CHIP_ID_YUKON_EC_U:
  1509. case CHIP_ID_YUKON_EX:
  1510. case CHIP_ID_YUKON_SUPR:
  1511. case CHIP_ID_YUKON_UL_2:
  1512. return 125;
  1513. case CHIP_ID_YUKON_FE:
  1514. return 100;
  1515. case CHIP_ID_YUKON_FE_P:
  1516. return 50;
  1517. case CHIP_ID_YUKON_XL:
  1518. return 156;
  1519. default:
  1520. DBG(PFX "unknown chip ID!\n");
  1521. return 100; /* bogus */
  1522. }
  1523. }
  1524. static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
  1525. {
  1526. return sky2_mhz(hw) * us;
  1527. }
  1528. static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
  1529. {
  1530. return clk / sky2_mhz(hw);
  1531. }
  1532. static int sky2_init(struct sky2_hw *hw)
  1533. {
  1534. u8 t8;
  1535. /* Enable all clocks and check for bad PCI access */
  1536. sky2_pci_write32(hw, PCI_DEV_REG3, 0);
  1537. sky2_write8(hw, B0_CTST, CS_RST_CLR);
  1538. hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
  1539. hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
  1540. switch(hw->chip_id) {
  1541. case CHIP_ID_YUKON_XL:
  1542. hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
  1543. break;
  1544. case CHIP_ID_YUKON_EC_U:
  1545. hw->flags = SKY2_HW_GIGABIT
  1546. | SKY2_HW_NEWER_PHY
  1547. | SKY2_HW_ADV_POWER_CTL;
  1548. break;
  1549. case CHIP_ID_YUKON_EX:
  1550. hw->flags = SKY2_HW_GIGABIT
  1551. | SKY2_HW_NEWER_PHY
  1552. | SKY2_HW_NEW_LE
  1553. | SKY2_HW_ADV_POWER_CTL;
  1554. break;
  1555. case CHIP_ID_YUKON_EC:
  1556. /* This rev is really old, and requires untested workarounds */
  1557. if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
  1558. DBG(PFX "unsupported revision Yukon-EC rev A1\n");
  1559. return -EOPNOTSUPP;
  1560. }
  1561. hw->flags = SKY2_HW_GIGABIT;
  1562. break;
  1563. case CHIP_ID_YUKON_FE:
  1564. break;
  1565. case CHIP_ID_YUKON_FE_P:
  1566. hw->flags = SKY2_HW_NEWER_PHY
  1567. | SKY2_HW_NEW_LE
  1568. | SKY2_HW_AUTO_TX_SUM
  1569. | SKY2_HW_ADV_POWER_CTL;
  1570. break;
  1571. case CHIP_ID_YUKON_SUPR:
  1572. hw->flags = SKY2_HW_GIGABIT
  1573. | SKY2_HW_NEWER_PHY
  1574. | SKY2_HW_NEW_LE
  1575. | SKY2_HW_AUTO_TX_SUM
  1576. | SKY2_HW_ADV_POWER_CTL;
  1577. break;
  1578. case CHIP_ID_YUKON_UL_2:
  1579. hw->flags = SKY2_HW_GIGABIT
  1580. | SKY2_HW_ADV_POWER_CTL;
  1581. break;
  1582. default:
  1583. DBG(PFX "unsupported chip type 0x%x\n", hw->chip_id);
  1584. return -EOPNOTSUPP;
  1585. }
  1586. hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
  1587. if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
  1588. hw->flags |= SKY2_HW_FIBRE_PHY;
  1589. hw->ports = 1;
  1590. t8 = sky2_read8(hw, B2_Y2_HW_RES);
  1591. if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
  1592. if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
  1593. ++hw->ports;
  1594. }
  1595. return 0;
  1596. }
  1597. static void sky2_reset(struct sky2_hw *hw)
  1598. {
  1599. u16 status;
  1600. int i, cap;
  1601. u32 hwe_mask = Y2_HWE_ALL_MASK;
  1602. /* disable ASF */
  1603. if (hw->chip_id == CHIP_ID_YUKON_EX) {
  1604. status = sky2_read16(hw, HCU_CCSR);
  1605. status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
  1606. HCU_CCSR_UC_STATE_MSK);
  1607. sky2_write16(hw, HCU_CCSR, status);
  1608. } else
  1609. sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
  1610. sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
  1611. /* do a SW reset */
  1612. sky2_write8(hw, B0_CTST, CS_RST_SET);
  1613. sky2_write8(hw, B0_CTST, CS_RST_CLR);
  1614. /* allow writes to PCI config */
  1615. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
  1616. /* clear PCI errors, if any */
  1617. status = sky2_pci_read16(hw, PCI_STATUS);
  1618. status |= PCI_STATUS_ERROR_BITS;
  1619. sky2_pci_write16(hw, PCI_STATUS, status);
  1620. sky2_write8(hw, B0_CTST, CS_MRST_CLR);
  1621. cap = pci_find_capability(hw->pdev, PCI_CAP_ID_EXP);
  1622. if (cap) {
  1623. sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
  1624. 0xfffffffful);
  1625. /* If an error bit is stuck on ignore it */
  1626. if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
  1627. DBG(PFX "ignoring stuck error report bit\n");
  1628. else
  1629. hwe_mask |= Y2_IS_PCI_EXP;
  1630. }
  1631. sky2_power_on(hw);
  1632. sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
  1633. for (i = 0; i < hw->ports; i++) {
  1634. sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
  1635. sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
  1636. if (hw->chip_id == CHIP_ID_YUKON_EX ||
  1637. hw->chip_id == CHIP_ID_YUKON_SUPR)
  1638. sky2_write16(hw, SK_REG(i, GMAC_CTRL),
  1639. GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
  1640. | GMC_BYP_RETR_ON);
  1641. }
  1642. /* Clear I2C IRQ noise */
  1643. sky2_write32(hw, B2_I2C_IRQ, 1);
  1644. /* turn off hardware timer (unused) */
  1645. sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
  1646. sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
  1647. sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
  1648. /* Turn off descriptor polling */
  1649. sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
  1650. /* Turn off receive timestamp */
  1651. sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
  1652. sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
  1653. /* enable the Tx Arbiters */
  1654. for (i = 0; i < hw->ports; i++)
  1655. sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
  1656. /* Initialize ram interface */
  1657. for (i = 0; i < hw->ports; i++) {
  1658. sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
  1659. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
  1660. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
  1661. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
  1662. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
  1663. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
  1664. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
  1665. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
  1666. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
  1667. sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
  1668. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
  1669. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
  1670. sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
  1671. }
  1672. sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
  1673. for (i = 0; i < hw->ports; i++)
  1674. sky2_gmac_reset(hw, i);
  1675. memset(hw->st_le, 0, STATUS_LE_BYTES);
  1676. hw->st_idx = 0;
  1677. sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
  1678. sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
  1679. sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
  1680. sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
  1681. /* Set the list last index */
  1682. sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
  1683. sky2_write16(hw, STAT_TX_IDX_TH, 10);
  1684. sky2_write8(hw, STAT_FIFO_WM, 16);
  1685. /* set Status-FIFO ISR watermark */
  1686. if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
  1687. sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
  1688. else
  1689. sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
  1690. sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
  1691. sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
  1692. sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
  1693. /* enable status unit */
  1694. sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
  1695. sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
  1696. sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
  1697. sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
  1698. }
  1699. static u32 sky2_supported_modes(const struct sky2_hw *hw)
  1700. {
  1701. if (sky2_is_copper(hw)) {
  1702. u32 modes = SUPPORTED_10baseT_Half
  1703. | SUPPORTED_10baseT_Full
  1704. | SUPPORTED_100baseT_Half
  1705. | SUPPORTED_100baseT_Full
  1706. | SUPPORTED_Autoneg | SUPPORTED_TP;
  1707. if (hw->flags & SKY2_HW_GIGABIT)
  1708. modes |= SUPPORTED_1000baseT_Half
  1709. | SUPPORTED_1000baseT_Full;
  1710. return modes;
  1711. } else
  1712. return SUPPORTED_1000baseT_Half
  1713. | SUPPORTED_1000baseT_Full
  1714. | SUPPORTED_Autoneg
  1715. | SUPPORTED_FIBRE;
  1716. }
  1717. static void sky2_set_multicast(struct net_device *dev)
  1718. {
  1719. struct sky2_port *sky2 = netdev_priv(dev);
  1720. struct sky2_hw *hw = sky2->hw;
  1721. unsigned port = sky2->port;
  1722. u16 reg;
  1723. u8 filter[8];
  1724. reg = gma_read16(hw, port, GM_RX_CTRL);
  1725. reg |= GM_RXCR_UCF_ENA;
  1726. memset(filter, 0xff, sizeof(filter));
  1727. gma_write16(hw, port, GM_MC_ADDR_H1,
  1728. (u16) filter[0] | ((u16) filter[1] << 8));
  1729. gma_write16(hw, port, GM_MC_ADDR_H2,
  1730. (u16) filter[2] | ((u16) filter[3] << 8));
  1731. gma_write16(hw, port, GM_MC_ADDR_H3,
  1732. (u16) filter[4] | ((u16) filter[5] << 8));
  1733. gma_write16(hw, port, GM_MC_ADDR_H4,
  1734. (u16) filter[6] | ((u16) filter[7] << 8));
  1735. gma_write16(hw, port, GM_RX_CTRL, reg);
  1736. }
  1737. /* Initialize network device */
  1738. static struct net_device *sky2_init_netdev(struct sky2_hw *hw,
  1739. unsigned port)
  1740. {
  1741. struct sky2_port *sky2;
  1742. struct net_device *dev = alloc_etherdev(sizeof(*sky2));
  1743. if (!dev) {
  1744. DBG(PFX "etherdev alloc failed\n");
  1745. return NULL;
  1746. }
  1747. dev->dev = &hw->pdev->dev;
  1748. sky2 = netdev_priv(dev);
  1749. sky2->netdev = dev;
  1750. sky2->hw = hw;
  1751. /* Auto speed and flow control */
  1752. sky2->autoneg = AUTONEG_ENABLE;
  1753. sky2->flow_mode = FC_BOTH;
  1754. sky2->duplex = -1;
  1755. sky2->speed = -1;
  1756. sky2->advertising = sky2_supported_modes(hw);
  1757. hw->dev[port] = dev;
  1758. sky2->port = port;
  1759. /* read the mac address */
  1760. memcpy(dev->hw_addr, (void *)(hw->regs + B2_MAC_1 + port * 8), ETH_ALEN);
  1761. return dev;
  1762. }
  1763. static void sky2_show_addr(struct net_device *dev)
  1764. {
  1765. DBG2(PFX "%s: addr %s\n", dev->name, netdev_addr(dev));
  1766. }
  1767. #if DBGLVL_MAX
  1768. /* This driver supports yukon2 chipset only */
  1769. static const char *sky2_name(u8 chipid, char *buf, int sz)
  1770. {
  1771. const char *name[] = {
  1772. "XL", /* 0xb3 */
  1773. "EC Ultra", /* 0xb4 */
  1774. "Extreme", /* 0xb5 */
  1775. "EC", /* 0xb6 */
  1776. "FE", /* 0xb7 */
  1777. "FE+", /* 0xb8 */
  1778. "Supreme", /* 0xb9 */
  1779. "UL 2", /* 0xba */
  1780. };
  1781. if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_UL_2)
  1782. strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
  1783. else
  1784. snprintf(buf, sz, "(chip %#x)", chipid);
  1785. return buf;
  1786. }
  1787. #endif
  1788. static void sky2_net_irq(struct net_device *dev, int enable)
  1789. {
  1790. struct sky2_port *sky2 = netdev_priv(dev);
  1791. struct sky2_hw *hw = sky2->hw;
  1792. u32 imask = sky2_read32(hw, B0_IMSK);
  1793. if (enable)
  1794. imask |= portirq_msk[sky2->port];
  1795. else
  1796. imask &= ~portirq_msk[sky2->port];
  1797. sky2_write32(hw, B0_IMSK, imask);
  1798. }
  1799. static struct net_device_operations sky2_operations = {
  1800. .open = sky2_up,
  1801. .close = sky2_down,
  1802. .transmit = sky2_xmit_frame,
  1803. .poll = sky2_poll,
  1804. .irq = sky2_net_irq
  1805. };
  1806. static int sky2_probe(struct pci_device *pdev)
  1807. {
  1808. struct net_device *dev;
  1809. struct sky2_hw *hw;
  1810. int err;
  1811. char buf1[16] __unused; /* only for debugging */
  1812. adjust_pci_device(pdev);
  1813. err = -ENOMEM;
  1814. hw = zalloc(sizeof(*hw));
  1815. if (!hw) {
  1816. DBG(PFX "cannot allocate hardware struct\n");
  1817. goto err_out;
  1818. }
  1819. hw->pdev = pdev;
  1820. hw->regs = (unsigned long)ioremap(pci_bar_start(pdev, PCI_BASE_ADDRESS_0), 0x4000);
  1821. if (!hw->regs) {
  1822. DBG(PFX "cannot map device registers\n");
  1823. goto err_out_free_hw;
  1824. }
  1825. /* ring for status responses */
  1826. hw->st_le = malloc_dma(STATUS_LE_BYTES, STATUS_RING_ALIGN);
  1827. if (!hw->st_le)
  1828. goto err_out_iounmap;
  1829. hw->st_dma = virt_to_bus(hw->st_le);
  1830. memset(hw->st_le, 0, STATUS_LE_BYTES);
  1831. err = sky2_init(hw);
  1832. if (err)
  1833. goto err_out_iounmap;
  1834. #if DBGLVL_MAX
  1835. DBG2(PFX "Yukon-2 %s chip revision %d\n",
  1836. sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
  1837. #endif
  1838. sky2_reset(hw);
  1839. dev = sky2_init_netdev(hw, 0);
  1840. if (!dev) {
  1841. err = -ENOMEM;
  1842. goto err_out_free_pci;
  1843. }
  1844. netdev_init(dev, &sky2_operations);
  1845. err = register_netdev(dev);
  1846. if (err) {
  1847. DBG(PFX "cannot register net device\n");
  1848. goto err_out_free_netdev;
  1849. }
  1850. sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
  1851. sky2_show_addr(dev);
  1852. if (hw->ports > 1) {
  1853. struct net_device *dev1;
  1854. dev1 = sky2_init_netdev(hw, 1);
  1855. if (!dev1)
  1856. DBG(PFX "allocation for second device failed\n");
  1857. else if ((err = register_netdev(dev1))) {
  1858. DBG(PFX "register of second port failed (%d)\n", err);
  1859. hw->dev[1] = NULL;
  1860. netdev_nullify(dev1);
  1861. netdev_put(dev1);
  1862. } else
  1863. sky2_show_addr(dev1);
  1864. }
  1865. pci_set_drvdata(pdev, hw);
  1866. return 0;
  1867. err_out_free_netdev:
  1868. netdev_nullify(dev);
  1869. netdev_put(dev);
  1870. err_out_free_pci:
  1871. sky2_write8(hw, B0_CTST, CS_RST_SET);
  1872. free_dma(hw->st_le, STATUS_LE_BYTES);
  1873. err_out_iounmap:
  1874. iounmap((void *)hw->regs);
  1875. err_out_free_hw:
  1876. free(hw);
  1877. err_out:
  1878. pci_set_drvdata(pdev, NULL);
  1879. return err;
  1880. }
  1881. static void sky2_remove(struct pci_device *pdev)
  1882. {
  1883. struct sky2_hw *hw = pci_get_drvdata(pdev);
  1884. int i;
  1885. if (!hw)
  1886. return;
  1887. for (i = hw->ports-1; i >= 0; --i)
  1888. unregister_netdev(hw->dev[i]);
  1889. sky2_write32(hw, B0_IMSK, 0);
  1890. sky2_power_aux(hw);
  1891. sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
  1892. sky2_write8(hw, B0_CTST, CS_RST_SET);
  1893. sky2_read8(hw, B0_CTST);
  1894. free_dma(hw->st_le, STATUS_LE_BYTES);
  1895. for (i = hw->ports-1; i >= 0; --i) {
  1896. netdev_nullify(hw->dev[i]);
  1897. netdev_put(hw->dev[i]);
  1898. }
  1899. iounmap((void *)hw->regs);
  1900. free(hw);
  1901. pci_set_drvdata(pdev, NULL);
  1902. }
  1903. struct pci_driver sky2_driver __pci_driver = {
  1904. .ids = sky2_id_table,
  1905. .id_count = (sizeof (sky2_id_table) / sizeof (sky2_id_table[0])),
  1906. .probe = sky2_probe,
  1907. .remove = sky2_remove
  1908. };