You can not select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535
  1. /* epic100.c: A SMC 83c170 EPIC/100 fast ethernet driver for Etherboot */
  2. /* 05/06/2003 timlegge Fixed relocation and implemented Multicast */
  3. #define LINUX_OUT_MACROS
  4. #include "etherboot.h"
  5. #include <gpxe/pci.h>
  6. #include <gpxe/ethernet.h>
  7. #include "nic.h"
  8. #include "timer.h"
  9. #include "console.h"
  10. #include "epic100.h"
  11. /* Condensed operations for readability */
  12. #define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
  13. #define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
  14. #define TX_RING_SIZE 2 /* use at least 2 buffers for TX */
  15. #define RX_RING_SIZE 2
  16. #define PKT_BUF_SZ 1536 /* Size of each temporary Tx/Rx buffer.*/
  17. /*
  18. #define DEBUG_RX
  19. #define DEBUG_TX
  20. #define DEBUG_EEPROM
  21. */
  22. #define EPIC_DEBUG 0 /* debug level */
  23. /* The EPIC100 Rx and Tx buffer descriptors. */
  24. struct epic_rx_desc {
  25. unsigned long status;
  26. unsigned long bufaddr;
  27. unsigned long buflength;
  28. unsigned long next;
  29. };
  30. /* description of the tx descriptors control bits commonly used */
  31. #define TD_STDFLAGS TD_LASTDESC
  32. struct epic_tx_desc {
  33. unsigned long status;
  34. unsigned long bufaddr;
  35. unsigned long buflength;
  36. unsigned long next;
  37. };
  38. #define delay(nanosec) do { int _i = 3; while (--_i > 0) \
  39. { __SLOW_DOWN_IO; }} while (0)
  40. static void epic100_open(void);
  41. static void epic100_init_ring(void);
  42. static void epic100_disable(struct nic *nic);
  43. static int epic100_poll(struct nic *nic, int retrieve);
  44. static void epic100_transmit(struct nic *nic, const char *destaddr,
  45. unsigned int type, unsigned int len, const char *data);
  46. #ifdef DEBUG_EEPROM
  47. static int read_eeprom(int location);
  48. #endif
  49. static int mii_read(int phy_id, int location);
  50. static void epic100_irq(struct nic *nic, irq_action_t action);
  51. static struct nic_operations epic100_operations;
  52. static int ioaddr;
  53. static int command;
  54. static int intstat;
  55. static int intmask;
  56. static int genctl ;
  57. static int eectl ;
  58. static int test ;
  59. static int mmctl ;
  60. static int mmdata ;
  61. static int lan0 ;
  62. static int mc0 ;
  63. static int rxcon ;
  64. static int txcon ;
  65. static int prcdar ;
  66. static int ptcdar ;
  67. static int eththr ;
  68. static unsigned int cur_rx, cur_tx; /* The next free ring entry */
  69. #ifdef DEBUG_EEPROM
  70. static unsigned short eeprom[64];
  71. #endif
  72. static signed char phys[4]; /* MII device addresses. */
  73. struct {
  74. struct epic_rx_desc rx_ring[RX_RING_SIZE]
  75. __attribute__ ((aligned(4)));
  76. struct epic_tx_desc tx_ring[TX_RING_SIZE]
  77. __attribute__ ((aligned(4)));
  78. unsigned char rx_packet[PKT_BUF_SZ * RX_RING_SIZE];
  79. unsigned char tx_packet[PKT_BUF_SZ * TX_RING_SIZE];
  80. } epic100_bufs __shared;
  81. #define rx_ring epic100_bufs.rx_ring
  82. #define tx_ring epic100_bufs.tx_ring
  83. #define rx_packet epic100_bufs.rx_packet
  84. #define tx_packet epic100_bufs.tx_packet
  85. /***********************************************************************/
  86. /* Externally visible functions */
  87. /***********************************************************************/
  88. static int
  89. epic100_probe ( struct nic *nic, struct pci_device *pci ) {
  90. int i;
  91. unsigned short* ap;
  92. unsigned int phy, phy_idx;
  93. if (pci->ioaddr == 0)
  94. return 0;
  95. /* Ideally we would detect all network cards in slot order. That would
  96. be best done a central PCI probe dispatch, which wouldn't work
  97. well with the current structure. So instead we detect just the
  98. Epic cards in slot order. */
  99. ioaddr = pci->ioaddr;
  100. nic->irqno = 0;
  101. nic->ioaddr = pci->ioaddr & ~3;
  102. /* compute all used static epic100 registers address */
  103. command = ioaddr + COMMAND; /* Control Register */
  104. intstat = ioaddr + INTSTAT; /* Interrupt Status */
  105. intmask = ioaddr + INTMASK; /* Interrupt Mask */
  106. genctl = ioaddr + GENCTL; /* General Control */
  107. eectl = ioaddr + EECTL; /* EEPROM Control */
  108. test = ioaddr + TEST; /* Test register (clocks) */
  109. mmctl = ioaddr + MMCTL; /* MII Management Interface Control */
  110. mmdata = ioaddr + MMDATA; /* MII Management Interface Data */
  111. lan0 = ioaddr + LAN0; /* MAC address. (0x40-0x48) */
  112. mc0 = ioaddr + MC0; /* Multicast Control */
  113. rxcon = ioaddr + RXCON; /* Receive Control */
  114. txcon = ioaddr + TXCON; /* Transmit Control */
  115. prcdar = ioaddr + PRCDAR; /* PCI Receive Current Descr Address */
  116. ptcdar = ioaddr + PTCDAR; /* PCI Transmit Current Descr Address */
  117. eththr = ioaddr + ETHTHR; /* Early Transmit Threshold */
  118. /* Reset the chip & bring it out of low-power mode. */
  119. outl(GC_SOFT_RESET, genctl);
  120. /* Disable ALL interrupts by setting the interrupt mask. */
  121. outl(INTR_DISABLE, intmask);
  122. /*
  123. * set the internal clocks:
  124. * Application Note 7.15 says:
  125. * In order to set the CLOCK TEST bit in the TEST register,
  126. * perform the following:
  127. *
  128. * Write 0x0008 to the test register at least sixteen
  129. * consecutive times.
  130. *
  131. * The CLOCK TEST bit is Write-Only. Writing it several times
  132. * consecutively insures a successful write to the bit...
  133. */
  134. for (i = 0; i < 16; i++) {
  135. outl(0x00000008, test);
  136. }
  137. #ifdef DEBUG_EEPROM
  138. {
  139. unsigned short sum = 0;
  140. unsigned short value;
  141. for (i = 0; i < 64; i++) {
  142. value = read_eeprom(i);
  143. eeprom[i] = value;
  144. sum += value;
  145. }
  146. }
  147. #if (EPIC_DEBUG > 1)
  148. printf("EEPROM contents\n");
  149. for (i = 0; i < 64; i++) {
  150. printf(" %hhX%s", eeprom[i], i % 16 == 15 ? "\n" : "");
  151. }
  152. #endif
  153. #endif
  154. /* This could also be read from the EEPROM. */
  155. ap = (unsigned short*)nic->node_addr;
  156. for (i = 0; i < 3; i++)
  157. *ap++ = inw(lan0 + i*4);
  158. DBG ( " I/O %4.4x %s ", ioaddr, eth_ntoa ( nic->node_addr ) );
  159. /* Find the connected MII xcvrs. */
  160. for (phy = 0, phy_idx = 0; phy < 32 && phy_idx < sizeof(phys); phy++) {
  161. int mii_status = mii_read(phy, 0);
  162. if (mii_status != 0xffff && mii_status != 0x0000) {
  163. phys[phy_idx++] = phy;
  164. #if (EPIC_DEBUG > 1)
  165. printf("MII transceiver found at address %d.\n", phy);
  166. #endif
  167. }
  168. }
  169. if (phy_idx == 0) {
  170. #if (EPIC_DEBUG > 1)
  171. printf("***WARNING***: No MII transceiver found!\n");
  172. #endif
  173. /* Use the known PHY address of the EPII. */
  174. phys[0] = 3;
  175. }
  176. epic100_open();
  177. nic->nic_op = &epic100_operations;
  178. return 1;
  179. }
  180. static void set_rx_mode(void)
  181. {
  182. unsigned char mc_filter[8];
  183. int i;
  184. memset(mc_filter, 0xff, sizeof(mc_filter));
  185. outl(0x0C, rxcon);
  186. for(i = 0; i < 4; i++)
  187. outw(((unsigned short *)mc_filter)[i], mc0 + i*4);
  188. return;
  189. }
  190. static void
  191. epic100_open(void)
  192. {
  193. int mii_reg5;
  194. int full_duplex = 0;
  195. unsigned long tmp;
  196. epic100_init_ring();
  197. /* Pull the chip out of low-power mode, and set for PCI read multiple. */
  198. outl(GC_RX_FIFO_THR_64 | GC_MRC_READ_MULT | GC_ONE_COPY, genctl);
  199. outl(TX_FIFO_THRESH, eththr);
  200. tmp = TC_EARLY_TX_ENABLE | TX_SLOT_TIME;
  201. mii_reg5 = mii_read(phys[0], 5);
  202. if (mii_reg5 != 0xffff && (mii_reg5 & 0x0100)) {
  203. full_duplex = 1;
  204. printf(" full-duplex mode");
  205. tmp |= TC_LM_FULL_DPX;
  206. } else
  207. tmp |= TC_LM_NORMAL;
  208. outl(tmp, txcon);
  209. /* Give adress of RX and TX ring to the chip */
  210. outl(virt_to_le32desc(&rx_ring), prcdar);
  211. outl(virt_to_le32desc(&tx_ring), ptcdar);
  212. /* Start the chip's Rx process: receive unicast and broadcast */
  213. set_rx_mode();
  214. outl(CR_START_RX | CR_QUEUE_RX, command);
  215. putchar('\n');
  216. }
  217. /* Initialize the Rx and Tx rings. */
  218. static void
  219. epic100_init_ring(void)
  220. {
  221. int i;
  222. cur_rx = cur_tx = 0;
  223. for (i = 0; i < RX_RING_SIZE; i++) {
  224. rx_ring[i].status = cpu_to_le32(RRING_OWN); /* Owned by Epic chip */
  225. rx_ring[i].buflength = cpu_to_le32(PKT_BUF_SZ);
  226. rx_ring[i].bufaddr = virt_to_bus(&rx_packet[i * PKT_BUF_SZ]);
  227. rx_ring[i].next = virt_to_le32desc(&rx_ring[i + 1]) ;
  228. }
  229. /* Mark the last entry as wrapping the ring. */
  230. rx_ring[i-1].next = virt_to_le32desc(&rx_ring[0]);
  231. /*
  232. *The Tx buffer descriptor is filled in as needed,
  233. * but we do need to clear the ownership bit.
  234. */
  235. for (i = 0; i < TX_RING_SIZE; i++) {
  236. tx_ring[i].status = 0x0000; /* Owned by CPU */
  237. tx_ring[i].buflength = 0x0000 | cpu_to_le32(TD_STDFLAGS << 16);
  238. tx_ring[i].bufaddr = virt_to_bus(&tx_packet[i * PKT_BUF_SZ]);
  239. tx_ring[i].next = virt_to_le32desc(&tx_ring[i + 1]);
  240. }
  241. tx_ring[i-1].next = virt_to_le32desc(&tx_ring[0]);
  242. }
  243. /* function: epic100_transmit
  244. * This transmits a packet.
  245. *
  246. * Arguments: char d[6]: destination ethernet address.
  247. * unsigned short t: ethernet protocol type.
  248. * unsigned short s: size of the data-part of the packet.
  249. * char *p: the data for the packet.
  250. * returns: void.
  251. */
  252. static void
  253. epic100_transmit(struct nic *nic, const char *destaddr, unsigned int type,
  254. unsigned int len, const char *data)
  255. {
  256. unsigned short nstype;
  257. unsigned char *txp;
  258. int entry;
  259. /* Calculate the next Tx descriptor entry. */
  260. entry = cur_tx % TX_RING_SIZE;
  261. if ((tx_ring[entry].status & TRING_OWN) == TRING_OWN) {
  262. printf("eth_transmit: Unable to transmit. status=%4.4lx. Resetting...\n",
  263. tx_ring[entry].status);
  264. epic100_open();
  265. return;
  266. }
  267. txp = tx_packet + (entry * PKT_BUF_SZ);
  268. memcpy(txp, destaddr, ETH_ALEN);
  269. memcpy(txp + ETH_ALEN, nic->node_addr, ETH_ALEN);
  270. nstype = htons(type);
  271. memcpy(txp + 12, (char*)&nstype, 2);
  272. memcpy(txp + ETH_HLEN, data, len);
  273. len += ETH_HLEN;
  274. len &= 0x0FFF;
  275. while(len < ETH_ZLEN)
  276. txp[len++] = '\0';
  277. /*
  278. * Caution: the write order is important here,
  279. * set the base address with the "ownership"
  280. * bits last.
  281. */
  282. tx_ring[entry].buflength |= cpu_to_le32(len);
  283. tx_ring[entry].status = cpu_to_le32(len << 16) |
  284. cpu_to_le32(TRING_OWN); /* Pass ownership to the chip. */
  285. cur_tx++;
  286. /* Trigger an immediate transmit demand. */
  287. outl(CR_QUEUE_TX, command);
  288. load_timer2(10*TICKS_PER_MS); /* timeout 10 ms for transmit */
  289. while ((le32_to_cpu(tx_ring[entry].status) & (TRING_OWN)) && timer2_running())
  290. /* Wait */;
  291. if ((le32_to_cpu(tx_ring[entry].status) & TRING_OWN) != 0)
  292. printf("Oops, transmitter timeout, status=%4.4lX\n",
  293. tx_ring[entry].status);
  294. }
  295. /* function: epic100_poll / eth_poll
  296. * This receives a packet from the network.
  297. *
  298. * Arguments: none
  299. *
  300. * returns: 1 if a packet was received.
  301. * 0 if no pacet was received.
  302. * side effects:
  303. * returns the packet in the array nic->packet.
  304. * returns the length of the packet in nic->packetlen.
  305. */
  306. static int
  307. epic100_poll(struct nic *nic, int retrieve)
  308. {
  309. int entry;
  310. int retcode;
  311. int status;
  312. entry = cur_rx % RX_RING_SIZE;
  313. if ((rx_ring[entry].status & cpu_to_le32(RRING_OWN)) == RRING_OWN)
  314. return (0);
  315. if ( ! retrieve ) return 1;
  316. status = le32_to_cpu(rx_ring[entry].status);
  317. /* We own the next entry, it's a new packet. Send it up. */
  318. #if (EPIC_DEBUG > 4)
  319. printf("epic_poll: entry %d status %hX\n", entry, status);
  320. #endif
  321. cur_rx++;
  322. if (status & 0x2000) {
  323. printf("epic_poll: Giant packet\n");
  324. retcode = 0;
  325. } else if (status & 0x0006) {
  326. /* Rx Frame errors are counted in hardware. */
  327. printf("epic_poll: Frame received with errors\n");
  328. retcode = 0;
  329. } else {
  330. /* Omit the four octet CRC from the length. */
  331. nic->packetlen = le32_to_cpu((rx_ring[entry].buflength))- 4;
  332. memcpy(nic->packet, &rx_packet[entry * PKT_BUF_SZ], nic->packetlen);
  333. retcode = 1;
  334. }
  335. /* Clear all error sources. */
  336. outl(status & INTR_CLEARERRS, intstat);
  337. /* Give the descriptor back to the chip */
  338. rx_ring[entry].status = RRING_OWN;
  339. /* Restart Receiver */
  340. outl(CR_START_RX | CR_QUEUE_RX, command);
  341. return retcode;
  342. }
  343. static void epic100_disable ( struct nic *nic __unused ) {
  344. /* Soft reset the chip. */
  345. outl(GC_SOFT_RESET, genctl);
  346. }
  347. static void epic100_irq(struct nic *nic __unused, irq_action_t action __unused)
  348. {
  349. switch ( action ) {
  350. case DISABLE :
  351. break;
  352. case ENABLE :
  353. break;
  354. case FORCE :
  355. break;
  356. }
  357. }
  358. #ifdef DEBUG_EEPROM
  359. /* Serial EEPROM section. */
  360. /* EEPROM_Ctrl bits. */
  361. #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
  362. #define EE_CS 0x02 /* EEPROM chip select. */
  363. #define EE_DATA_WRITE 0x08 /* EEPROM chip data in. */
  364. #define EE_WRITE_0 0x01
  365. #define EE_WRITE_1 0x09
  366. #define EE_DATA_READ 0x10 /* EEPROM chip data out. */
  367. #define EE_ENB (0x0001 | EE_CS)
  368. /* The EEPROM commands include the alway-set leading bit. */
  369. #define EE_WRITE_CMD (5 << 6)
  370. #define EE_READ_CMD (6 << 6)
  371. #define EE_ERASE_CMD (7 << 6)
  372. #define eeprom_delay(n) delay(n)
  373. static int
  374. read_eeprom(int location)
  375. {
  376. int i;
  377. int retval = 0;
  378. int read_cmd = location | EE_READ_CMD;
  379. outl(EE_ENB & ~EE_CS, eectl);
  380. outl(EE_ENB, eectl);
  381. /* Shift the read command bits out. */
  382. for (i = 10; i >= 0; i--) {
  383. short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
  384. outl(EE_ENB | dataval, eectl);
  385. eeprom_delay(100);
  386. outl(EE_ENB | dataval | EE_SHIFT_CLK, eectl);
  387. eeprom_delay(150);
  388. outl(EE_ENB | dataval, eectl); /* Finish EEPROM a clock tick. */
  389. eeprom_delay(250);
  390. }
  391. outl(EE_ENB, eectl);
  392. for (i = 16; i > 0; i--) {
  393. outl(EE_ENB | EE_SHIFT_CLK, eectl);
  394. eeprom_delay(100);
  395. retval = (retval << 1) | ((inl(eectl) & EE_DATA_READ) ? 1 : 0);
  396. outl(EE_ENB, eectl);
  397. eeprom_delay(100);
  398. }
  399. /* Terminate the EEPROM access. */
  400. outl(EE_ENB & ~EE_CS, eectl);
  401. return retval;
  402. }
  403. #endif
  404. #define MII_READOP 1
  405. #define MII_WRITEOP 2
  406. static int
  407. mii_read(int phy_id, int location)
  408. {
  409. int i;
  410. outl((phy_id << 9) | (location << 4) | MII_READOP, mmctl);
  411. /* Typical operation takes < 50 ticks. */
  412. for (i = 4000; i > 0; i--)
  413. if ((inl(mmctl) & MII_READOP) == 0)
  414. break;
  415. return inw(mmdata);
  416. }
  417. static struct nic_operations epic100_operations = {
  418. .connect = dummy_connect,
  419. .poll = epic100_poll,
  420. .transmit = epic100_transmit,
  421. .irq = epic100_irq,
  422. };
  423. static struct pci_device_id epic100_nics[] = {
  424. PCI_ROM(0x10b8, 0x0005, "epic100", "SMC EtherPowerII"), /* SMC 83c170 EPIC/100 */
  425. PCI_ROM(0x10b8, 0x0006, "smc-83c175", "SMC EPIC/C 83c175"),
  426. };
  427. PCI_DRIVER ( epic100_driver, epic100_nics, PCI_NO_CLASS );
  428. DRIVER ( "EPIC100", nic_driver, pci_driver, epic100_driver,
  429. epic100_probe, epic100_disable );
  430. /*
  431. * Local variables:
  432. * c-basic-offset: 8
  433. * c-indent-level: 8
  434. * tab-width: 8
  435. * End:
  436. */