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bnx2.c 67KB

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  1. /* bnx2.c: Broadcom NX2 network driver.
  2. *
  3. * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Written by: Michael Chan (mchan@broadcom.com)
  10. *
  11. * Etherboot port by Ryan Jackson (rjackson@lnxi.com), based on driver
  12. * version 1.4.40 from linux 2.6.17
  13. */
  14. FILE_LICENCE ( GPL_ANY );
  15. #include "etherboot.h"
  16. #include "nic.h"
  17. #include <errno.h>
  18. #include <ipxe/pci.h>
  19. #include <ipxe/ethernet.h>
  20. #include "string.h"
  21. #include <mii.h>
  22. #include "bnx2.h"
  23. #include "bnx2_fw.h"
  24. #if 0
  25. /* Dummy defines for error handling */
  26. #define EBUSY 1
  27. #define ENODEV 2
  28. #define EINVAL 3
  29. #define ENOMEM 4
  30. #define EIO 5
  31. #endif
  32. /* The bnx2 seems to be picky about the alignment of the receive buffers
  33. * and possibly the status block.
  34. */
  35. static struct bss {
  36. struct tx_bd tx_desc_ring[TX_DESC_CNT];
  37. struct rx_bd rx_desc_ring[RX_DESC_CNT];
  38. unsigned char rx_buf[RX_BUF_CNT][RX_BUF_SIZE];
  39. struct status_block status_blk;
  40. struct statistics_block stats_blk;
  41. } bnx2_bss;
  42. static struct bnx2 bnx2;
  43. static struct flash_spec flash_table[] =
  44. {
  45. /* Slow EEPROM */
  46. {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
  47. 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
  48. SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
  49. "EEPROM - slow"},
  50. /* Expansion entry 0001 */
  51. {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
  52. 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  53. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  54. "Entry 0001"},
  55. /* Saifun SA25F010 (non-buffered flash) */
  56. /* strap, cfg1, & write1 need updates */
  57. {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
  58. 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  59. SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
  60. "Non-buffered flash (128kB)"},
  61. /* Saifun SA25F020 (non-buffered flash) */
  62. /* strap, cfg1, & write1 need updates */
  63. {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
  64. 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  65. SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
  66. "Non-buffered flash (256kB)"},
  67. /* Expansion entry 0100 */
  68. {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
  69. 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  70. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  71. "Entry 0100"},
  72. /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
  73. {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
  74. 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
  75. ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
  76. "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
  77. /* Entry 0110: ST M45PE20 (non-buffered flash)*/
  78. {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
  79. 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
  80. ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
  81. "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
  82. /* Saifun SA25F005 (non-buffered flash) */
  83. /* strap, cfg1, & write1 need updates */
  84. {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
  85. 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  86. SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
  87. "Non-buffered flash (64kB)"},
  88. /* Fast EEPROM */
  89. {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
  90. 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
  91. SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
  92. "EEPROM - fast"},
  93. /* Expansion entry 1001 */
  94. {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
  95. 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  96. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  97. "Entry 1001"},
  98. /* Expansion entry 1010 */
  99. {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
  100. 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  101. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  102. "Entry 1010"},
  103. /* ATMEL AT45DB011B (buffered flash) */
  104. {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
  105. 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
  106. BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
  107. "Buffered flash (128kB)"},
  108. /* Expansion entry 1100 */
  109. {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
  110. 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  111. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  112. "Entry 1100"},
  113. /* Expansion entry 1101 */
  114. {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
  115. 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
  116. SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
  117. "Entry 1101"},
  118. /* Ateml Expansion entry 1110 */
  119. {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
  120. 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
  121. BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
  122. "Entry 1110 (Atmel)"},
  123. /* ATMEL AT45DB021B (buffered flash) */
  124. {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
  125. 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
  126. BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
  127. "Buffered flash (256kB)"},
  128. };
  129. static u32
  130. bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
  131. {
  132. REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
  133. return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
  134. }
  135. static void
  136. bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
  137. {
  138. REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
  139. REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
  140. }
  141. static void
  142. bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
  143. {
  144. offset += cid_addr;
  145. REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
  146. REG_WR(bp, BNX2_CTX_DATA, val);
  147. }
  148. static int
  149. bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
  150. {
  151. u32 val1;
  152. int i, ret;
  153. if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
  154. val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  155. val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
  156. REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
  157. REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  158. udelay(40);
  159. }
  160. val1 = (bp->phy_addr << 21) | (reg << 16) |
  161. BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
  162. BNX2_EMAC_MDIO_COMM_START_BUSY;
  163. REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
  164. for (i = 0; i < 50; i++) {
  165. udelay(10);
  166. val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
  167. if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
  168. udelay(5);
  169. val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
  170. val1 &= BNX2_EMAC_MDIO_COMM_DATA;
  171. break;
  172. }
  173. }
  174. if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
  175. *val = 0x0;
  176. ret = -EBUSY;
  177. }
  178. else {
  179. *val = val1;
  180. ret = 0;
  181. }
  182. if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
  183. val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  184. val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
  185. REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
  186. REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  187. udelay(40);
  188. }
  189. return ret;
  190. }
  191. static int
  192. bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
  193. {
  194. u32 val1;
  195. int i, ret;
  196. if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
  197. val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  198. val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
  199. REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
  200. REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  201. udelay(40);
  202. }
  203. val1 = (bp->phy_addr << 21) | (reg << 16) | val |
  204. BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
  205. BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
  206. REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
  207. for (i = 0; i < 50; i++) {
  208. udelay(10);
  209. val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
  210. if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
  211. udelay(5);
  212. break;
  213. }
  214. }
  215. if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
  216. ret = -EBUSY;
  217. else
  218. ret = 0;
  219. if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
  220. val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  221. val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
  222. REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
  223. REG_RD(bp, BNX2_EMAC_MDIO_MODE);
  224. udelay(40);
  225. }
  226. return ret;
  227. }
  228. static void
  229. bnx2_disable_int(struct bnx2 *bp)
  230. {
  231. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  232. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  233. REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
  234. }
  235. static int
  236. bnx2_alloc_mem(struct bnx2 *bp)
  237. {
  238. bp->tx_desc_ring = bnx2_bss.tx_desc_ring;
  239. bp->tx_desc_mapping = virt_to_bus(bp->tx_desc_ring);
  240. bp->rx_desc_ring = bnx2_bss.rx_desc_ring;
  241. memset(bp->rx_desc_ring, 0, sizeof(struct rx_bd) * RX_DESC_CNT);
  242. bp->rx_desc_mapping = virt_to_bus(bp->rx_desc_ring);
  243. memset(&bnx2_bss.status_blk, 0, sizeof(struct status_block));
  244. bp->status_blk = &bnx2_bss.status_blk;
  245. bp->status_blk_mapping = virt_to_bus(&bnx2_bss.status_blk);
  246. bp->stats_blk = &bnx2_bss.stats_blk;
  247. memset(&bnx2_bss.stats_blk, 0, sizeof(struct statistics_block));
  248. bp->stats_blk_mapping = virt_to_bus(&bnx2_bss.stats_blk);
  249. return 0;
  250. }
  251. static void
  252. bnx2_report_fw_link(struct bnx2 *bp)
  253. {
  254. u32 fw_link_status = 0;
  255. if (bp->link_up) {
  256. u32 bmsr;
  257. switch (bp->line_speed) {
  258. case SPEED_10:
  259. if (bp->duplex == DUPLEX_HALF)
  260. fw_link_status = BNX2_LINK_STATUS_10HALF;
  261. else
  262. fw_link_status = BNX2_LINK_STATUS_10FULL;
  263. break;
  264. case SPEED_100:
  265. if (bp->duplex == DUPLEX_HALF)
  266. fw_link_status = BNX2_LINK_STATUS_100HALF;
  267. else
  268. fw_link_status = BNX2_LINK_STATUS_100FULL;
  269. break;
  270. case SPEED_1000:
  271. if (bp->duplex == DUPLEX_HALF)
  272. fw_link_status = BNX2_LINK_STATUS_1000HALF;
  273. else
  274. fw_link_status = BNX2_LINK_STATUS_1000FULL;
  275. break;
  276. case SPEED_2500:
  277. if (bp->duplex == DUPLEX_HALF)
  278. fw_link_status = BNX2_LINK_STATUS_2500HALF;
  279. else
  280. fw_link_status = BNX2_LINK_STATUS_2500FULL;
  281. break;
  282. }
  283. fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
  284. if (bp->autoneg) {
  285. fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
  286. bnx2_read_phy(bp, MII_BMSR, &bmsr);
  287. bnx2_read_phy(bp, MII_BMSR, &bmsr);
  288. if (!(bmsr & BMSR_ANEGCOMPLETE) ||
  289. bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
  290. fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
  291. else
  292. fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
  293. }
  294. }
  295. else
  296. fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
  297. REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
  298. }
  299. static void
  300. bnx2_report_link(struct bnx2 *bp)
  301. {
  302. if (bp->link_up) {
  303. printf("NIC Link is Up, ");
  304. printf("%d Mbps ", bp->line_speed);
  305. if (bp->duplex == DUPLEX_FULL)
  306. printf("full duplex");
  307. else
  308. printf("half duplex");
  309. if (bp->flow_ctrl) {
  310. if (bp->flow_ctrl & FLOW_CTRL_RX) {
  311. printf(", receive ");
  312. if (bp->flow_ctrl & FLOW_CTRL_TX)
  313. printf("& transmit ");
  314. }
  315. else {
  316. printf(", transmit ");
  317. }
  318. printf("flow control ON");
  319. }
  320. printf("\n");
  321. }
  322. else {
  323. printf("NIC Link is Down\n");
  324. }
  325. bnx2_report_fw_link(bp);
  326. }
  327. static void
  328. bnx2_resolve_flow_ctrl(struct bnx2 *bp)
  329. {
  330. u32 local_adv, remote_adv;
  331. bp->flow_ctrl = 0;
  332. if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
  333. (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
  334. if (bp->duplex == DUPLEX_FULL) {
  335. bp->flow_ctrl = bp->req_flow_ctrl;
  336. }
  337. return;
  338. }
  339. if (bp->duplex != DUPLEX_FULL) {
  340. return;
  341. }
  342. if ((bp->phy_flags & PHY_SERDES_FLAG) &&
  343. (CHIP_NUM(bp) == CHIP_NUM_5708)) {
  344. u32 val;
  345. bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
  346. if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
  347. bp->flow_ctrl |= FLOW_CTRL_TX;
  348. if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
  349. bp->flow_ctrl |= FLOW_CTRL_RX;
  350. return;
  351. }
  352. bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
  353. bnx2_read_phy(bp, MII_LPA, &remote_adv);
  354. if (bp->phy_flags & PHY_SERDES_FLAG) {
  355. u32 new_local_adv = 0;
  356. u32 new_remote_adv = 0;
  357. if (local_adv & ADVERTISE_1000XPAUSE)
  358. new_local_adv |= ADVERTISE_PAUSE_CAP;
  359. if (local_adv & ADVERTISE_1000XPSE_ASYM)
  360. new_local_adv |= ADVERTISE_PAUSE_ASYM;
  361. if (remote_adv & ADVERTISE_1000XPAUSE)
  362. new_remote_adv |= ADVERTISE_PAUSE_CAP;
  363. if (remote_adv & ADVERTISE_1000XPSE_ASYM)
  364. new_remote_adv |= ADVERTISE_PAUSE_ASYM;
  365. local_adv = new_local_adv;
  366. remote_adv = new_remote_adv;
  367. }
  368. /* See Table 28B-3 of 802.3ab-1999 spec. */
  369. if (local_adv & ADVERTISE_PAUSE_CAP) {
  370. if(local_adv & ADVERTISE_PAUSE_ASYM) {
  371. if (remote_adv & ADVERTISE_PAUSE_CAP) {
  372. bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
  373. }
  374. else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
  375. bp->flow_ctrl = FLOW_CTRL_RX;
  376. }
  377. }
  378. else {
  379. if (remote_adv & ADVERTISE_PAUSE_CAP) {
  380. bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
  381. }
  382. }
  383. }
  384. else if (local_adv & ADVERTISE_PAUSE_ASYM) {
  385. if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
  386. (remote_adv & ADVERTISE_PAUSE_ASYM)) {
  387. bp->flow_ctrl = FLOW_CTRL_TX;
  388. }
  389. }
  390. }
  391. static int
  392. bnx2_5708s_linkup(struct bnx2 *bp)
  393. {
  394. u32 val;
  395. bp->link_up = 1;
  396. bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
  397. switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
  398. case BCM5708S_1000X_STAT1_SPEED_10:
  399. bp->line_speed = SPEED_10;
  400. break;
  401. case BCM5708S_1000X_STAT1_SPEED_100:
  402. bp->line_speed = SPEED_100;
  403. break;
  404. case BCM5708S_1000X_STAT1_SPEED_1G:
  405. bp->line_speed = SPEED_1000;
  406. break;
  407. case BCM5708S_1000X_STAT1_SPEED_2G5:
  408. bp->line_speed = SPEED_2500;
  409. break;
  410. }
  411. if (val & BCM5708S_1000X_STAT1_FD)
  412. bp->duplex = DUPLEX_FULL;
  413. else
  414. bp->duplex = DUPLEX_HALF;
  415. return 0;
  416. }
  417. static int
  418. bnx2_5706s_linkup(struct bnx2 *bp)
  419. {
  420. u32 bmcr, local_adv, remote_adv, common;
  421. bp->link_up = 1;
  422. bp->line_speed = SPEED_1000;
  423. bnx2_read_phy(bp, MII_BMCR, &bmcr);
  424. if (bmcr & BMCR_FULLDPLX) {
  425. bp->duplex = DUPLEX_FULL;
  426. }
  427. else {
  428. bp->duplex = DUPLEX_HALF;
  429. }
  430. if (!(bmcr & BMCR_ANENABLE)) {
  431. return 0;
  432. }
  433. bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
  434. bnx2_read_phy(bp, MII_LPA, &remote_adv);
  435. common = local_adv & remote_adv;
  436. if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
  437. if (common & ADVERTISE_1000XFULL) {
  438. bp->duplex = DUPLEX_FULL;
  439. }
  440. else {
  441. bp->duplex = DUPLEX_HALF;
  442. }
  443. }
  444. return 0;
  445. }
  446. static int
  447. bnx2_copper_linkup(struct bnx2 *bp)
  448. {
  449. u32 bmcr;
  450. bnx2_read_phy(bp, MII_BMCR, &bmcr);
  451. if (bmcr & BMCR_ANENABLE) {
  452. u32 local_adv, remote_adv, common;
  453. bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
  454. bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
  455. common = local_adv & (remote_adv >> 2);
  456. if (common & ADVERTISE_1000FULL) {
  457. bp->line_speed = SPEED_1000;
  458. bp->duplex = DUPLEX_FULL;
  459. }
  460. else if (common & ADVERTISE_1000HALF) {
  461. bp->line_speed = SPEED_1000;
  462. bp->duplex = DUPLEX_HALF;
  463. }
  464. else {
  465. bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
  466. bnx2_read_phy(bp, MII_LPA, &remote_adv);
  467. common = local_adv & remote_adv;
  468. if (common & ADVERTISE_100FULL) {
  469. bp->line_speed = SPEED_100;
  470. bp->duplex = DUPLEX_FULL;
  471. }
  472. else if (common & ADVERTISE_100HALF) {
  473. bp->line_speed = SPEED_100;
  474. bp->duplex = DUPLEX_HALF;
  475. }
  476. else if (common & ADVERTISE_10FULL) {
  477. bp->line_speed = SPEED_10;
  478. bp->duplex = DUPLEX_FULL;
  479. }
  480. else if (common & ADVERTISE_10HALF) {
  481. bp->line_speed = SPEED_10;
  482. bp->duplex = DUPLEX_HALF;
  483. }
  484. else {
  485. bp->line_speed = 0;
  486. bp->link_up = 0;
  487. }
  488. }
  489. }
  490. else {
  491. if (bmcr & BMCR_SPEED100) {
  492. bp->line_speed = SPEED_100;
  493. }
  494. else {
  495. bp->line_speed = SPEED_10;
  496. }
  497. if (bmcr & BMCR_FULLDPLX) {
  498. bp->duplex = DUPLEX_FULL;
  499. }
  500. else {
  501. bp->duplex = DUPLEX_HALF;
  502. }
  503. }
  504. return 0;
  505. }
  506. static int
  507. bnx2_set_mac_link(struct bnx2 *bp)
  508. {
  509. u32 val;
  510. REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
  511. if (bp->link_up && (bp->line_speed == SPEED_1000) &&
  512. (bp->duplex == DUPLEX_HALF)) {
  513. REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
  514. }
  515. /* Configure the EMAC mode register. */
  516. val = REG_RD(bp, BNX2_EMAC_MODE);
  517. val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
  518. BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
  519. BNX2_EMAC_MODE_25G);
  520. if (bp->link_up) {
  521. switch (bp->line_speed) {
  522. case SPEED_10:
  523. if (CHIP_NUM(bp) == CHIP_NUM_5708) {
  524. val |= BNX2_EMAC_MODE_PORT_MII_10;
  525. break;
  526. }
  527. /* fall through */
  528. case SPEED_100:
  529. val |= BNX2_EMAC_MODE_PORT_MII;
  530. break;
  531. case SPEED_2500:
  532. val |= BNX2_EMAC_MODE_25G;
  533. /* fall through */
  534. case SPEED_1000:
  535. val |= BNX2_EMAC_MODE_PORT_GMII;
  536. break;
  537. }
  538. }
  539. else {
  540. val |= BNX2_EMAC_MODE_PORT_GMII;
  541. }
  542. /* Set the MAC to operate in the appropriate duplex mode. */
  543. if (bp->duplex == DUPLEX_HALF)
  544. val |= BNX2_EMAC_MODE_HALF_DUPLEX;
  545. REG_WR(bp, BNX2_EMAC_MODE, val);
  546. /* Enable/disable rx PAUSE. */
  547. bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
  548. if (bp->flow_ctrl & FLOW_CTRL_RX)
  549. bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
  550. REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
  551. /* Enable/disable tx PAUSE. */
  552. val = REG_RD(bp, BNX2_EMAC_TX_MODE);
  553. val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
  554. if (bp->flow_ctrl & FLOW_CTRL_TX)
  555. val |= BNX2_EMAC_TX_MODE_FLOW_EN;
  556. REG_WR(bp, BNX2_EMAC_TX_MODE, val);
  557. /* Acknowledge the interrupt. */
  558. REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
  559. return 0;
  560. }
  561. static int
  562. bnx2_set_link(struct bnx2 *bp)
  563. {
  564. u32 bmsr;
  565. u8 link_up;
  566. if (bp->loopback == MAC_LOOPBACK) {
  567. bp->link_up = 1;
  568. return 0;
  569. }
  570. link_up = bp->link_up;
  571. bnx2_read_phy(bp, MII_BMSR, &bmsr);
  572. bnx2_read_phy(bp, MII_BMSR, &bmsr);
  573. if ((bp->phy_flags & PHY_SERDES_FLAG) &&
  574. (CHIP_NUM(bp) == CHIP_NUM_5706)) {
  575. u32 val;
  576. val = REG_RD(bp, BNX2_EMAC_STATUS);
  577. if (val & BNX2_EMAC_STATUS_LINK)
  578. bmsr |= BMSR_LSTATUS;
  579. else
  580. bmsr &= ~BMSR_LSTATUS;
  581. }
  582. if (bmsr & BMSR_LSTATUS) {
  583. bp->link_up = 1;
  584. if (bp->phy_flags & PHY_SERDES_FLAG) {
  585. if (CHIP_NUM(bp) == CHIP_NUM_5706)
  586. bnx2_5706s_linkup(bp);
  587. else if (CHIP_NUM(bp) == CHIP_NUM_5708)
  588. bnx2_5708s_linkup(bp);
  589. }
  590. else {
  591. bnx2_copper_linkup(bp);
  592. }
  593. bnx2_resolve_flow_ctrl(bp);
  594. }
  595. else {
  596. if ((bp->phy_flags & PHY_SERDES_FLAG) &&
  597. (bp->autoneg & AUTONEG_SPEED)) {
  598. u32 bmcr;
  599. bnx2_read_phy(bp, MII_BMCR, &bmcr);
  600. if (!(bmcr & BMCR_ANENABLE)) {
  601. bnx2_write_phy(bp, MII_BMCR, bmcr |
  602. BMCR_ANENABLE);
  603. }
  604. }
  605. bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
  606. bp->link_up = 0;
  607. }
  608. if (bp->link_up != link_up) {
  609. bnx2_report_link(bp);
  610. }
  611. bnx2_set_mac_link(bp);
  612. return 0;
  613. }
  614. static int
  615. bnx2_reset_phy(struct bnx2 *bp)
  616. {
  617. int i;
  618. u32 reg;
  619. bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
  620. #define PHY_RESET_MAX_WAIT 100
  621. for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
  622. udelay(10);
  623. bnx2_read_phy(bp, MII_BMCR, &reg);
  624. if (!(reg & BMCR_RESET)) {
  625. udelay(20);
  626. break;
  627. }
  628. }
  629. if (i == PHY_RESET_MAX_WAIT) {
  630. return -EBUSY;
  631. }
  632. return 0;
  633. }
  634. static u32
  635. bnx2_phy_get_pause_adv(struct bnx2 *bp)
  636. {
  637. u32 adv = 0;
  638. if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
  639. (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
  640. if (bp->phy_flags & PHY_SERDES_FLAG) {
  641. adv = ADVERTISE_1000XPAUSE;
  642. }
  643. else {
  644. adv = ADVERTISE_PAUSE_CAP;
  645. }
  646. }
  647. else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
  648. if (bp->phy_flags & PHY_SERDES_FLAG) {
  649. adv = ADVERTISE_1000XPSE_ASYM;
  650. }
  651. else {
  652. adv = ADVERTISE_PAUSE_ASYM;
  653. }
  654. }
  655. else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
  656. if (bp->phy_flags & PHY_SERDES_FLAG) {
  657. adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
  658. }
  659. else {
  660. adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  661. }
  662. }
  663. return adv;
  664. }
  665. static int
  666. bnx2_setup_serdes_phy(struct bnx2 *bp)
  667. {
  668. u32 adv, bmcr, up1;
  669. u32 new_adv = 0;
  670. if (!(bp->autoneg & AUTONEG_SPEED)) {
  671. u32 new_bmcr;
  672. int force_link_down = 0;
  673. if (CHIP_NUM(bp) == CHIP_NUM_5708) {
  674. bnx2_read_phy(bp, BCM5708S_UP1, &up1);
  675. if (up1 & BCM5708S_UP1_2G5) {
  676. up1 &= ~BCM5708S_UP1_2G5;
  677. bnx2_write_phy(bp, BCM5708S_UP1, up1);
  678. force_link_down = 1;
  679. }
  680. }
  681. bnx2_read_phy(bp, MII_ADVERTISE, &adv);
  682. adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
  683. bnx2_read_phy(bp, MII_BMCR, &bmcr);
  684. new_bmcr = bmcr & ~BMCR_ANENABLE;
  685. new_bmcr |= BMCR_SPEED1000;
  686. if (bp->req_duplex == DUPLEX_FULL) {
  687. adv |= ADVERTISE_1000XFULL;
  688. new_bmcr |= BMCR_FULLDPLX;
  689. }
  690. else {
  691. adv |= ADVERTISE_1000XHALF;
  692. new_bmcr &= ~BMCR_FULLDPLX;
  693. }
  694. if ((new_bmcr != bmcr) || (force_link_down)) {
  695. /* Force a link down visible on the other side */
  696. if (bp->link_up) {
  697. bnx2_write_phy(bp, MII_ADVERTISE, adv &
  698. ~(ADVERTISE_1000XFULL |
  699. ADVERTISE_1000XHALF));
  700. bnx2_write_phy(bp, MII_BMCR, bmcr |
  701. BMCR_ANRESTART | BMCR_ANENABLE);
  702. bp->link_up = 0;
  703. bnx2_write_phy(bp, MII_BMCR, new_bmcr);
  704. }
  705. bnx2_write_phy(bp, MII_ADVERTISE, adv);
  706. bnx2_write_phy(bp, MII_BMCR, new_bmcr);
  707. }
  708. return 0;
  709. }
  710. if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
  711. bnx2_read_phy(bp, BCM5708S_UP1, &up1);
  712. up1 |= BCM5708S_UP1_2G5;
  713. bnx2_write_phy(bp, BCM5708S_UP1, up1);
  714. }
  715. if (bp->advertising & ADVERTISED_1000baseT_Full)
  716. new_adv |= ADVERTISE_1000XFULL;
  717. new_adv |= bnx2_phy_get_pause_adv(bp);
  718. bnx2_read_phy(bp, MII_ADVERTISE, &adv);
  719. bnx2_read_phy(bp, MII_BMCR, &bmcr);
  720. bp->serdes_an_pending = 0;
  721. if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
  722. /* Force a link down visible on the other side */
  723. if (bp->link_up) {
  724. int i;
  725. bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
  726. for (i = 0; i < 110; i++) {
  727. udelay(100);
  728. }
  729. }
  730. bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
  731. bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
  732. BMCR_ANENABLE);
  733. #if 0
  734. if (CHIP_NUM(bp) == CHIP_NUM_5706) {
  735. /* Speed up link-up time when the link partner
  736. * does not autonegotiate which is very common
  737. * in blade servers. Some blade servers use
  738. * IPMI for kerboard input and it's important
  739. * to minimize link disruptions. Autoneg. involves
  740. * exchanging base pages plus 3 next pages and
  741. * normally completes in about 120 msec.
  742. */
  743. bp->current_interval = SERDES_AN_TIMEOUT;
  744. bp->serdes_an_pending = 1;
  745. mod_timer(&bp->timer, jiffies + bp->current_interval);
  746. }
  747. #endif
  748. }
  749. return 0;
  750. }
  751. #define ETHTOOL_ALL_FIBRE_SPEED \
  752. (ADVERTISED_1000baseT_Full)
  753. #define ETHTOOL_ALL_COPPER_SPEED \
  754. (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
  755. ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
  756. ADVERTISED_1000baseT_Full)
  757. #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
  758. ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
  759. #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
  760. static int
  761. bnx2_setup_copper_phy(struct bnx2 *bp)
  762. {
  763. u32 bmcr;
  764. u32 new_bmcr;
  765. bnx2_read_phy(bp, MII_BMCR, &bmcr);
  766. if (bp->autoneg & AUTONEG_SPEED) {
  767. u32 adv_reg, adv1000_reg;
  768. u32 new_adv_reg = 0;
  769. u32 new_adv1000_reg = 0;
  770. bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
  771. adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
  772. ADVERTISE_PAUSE_ASYM);
  773. bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
  774. adv1000_reg &= PHY_ALL_1000_SPEED;
  775. if (bp->advertising & ADVERTISED_10baseT_Half)
  776. new_adv_reg |= ADVERTISE_10HALF;
  777. if (bp->advertising & ADVERTISED_10baseT_Full)
  778. new_adv_reg |= ADVERTISE_10FULL;
  779. if (bp->advertising & ADVERTISED_100baseT_Half)
  780. new_adv_reg |= ADVERTISE_100HALF;
  781. if (bp->advertising & ADVERTISED_100baseT_Full)
  782. new_adv_reg |= ADVERTISE_100FULL;
  783. if (bp->advertising & ADVERTISED_1000baseT_Full)
  784. new_adv1000_reg |= ADVERTISE_1000FULL;
  785. new_adv_reg |= ADVERTISE_CSMA;
  786. new_adv_reg |= bnx2_phy_get_pause_adv(bp);
  787. if ((adv1000_reg != new_adv1000_reg) ||
  788. (adv_reg != new_adv_reg) ||
  789. ((bmcr & BMCR_ANENABLE) == 0)) {
  790. bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
  791. bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
  792. bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
  793. BMCR_ANENABLE);
  794. }
  795. else if (bp->link_up) {
  796. /* Flow ctrl may have changed from auto to forced */
  797. /* or vice-versa. */
  798. bnx2_resolve_flow_ctrl(bp);
  799. bnx2_set_mac_link(bp);
  800. }
  801. return 0;
  802. }
  803. new_bmcr = 0;
  804. if (bp->req_line_speed == SPEED_100) {
  805. new_bmcr |= BMCR_SPEED100;
  806. }
  807. if (bp->req_duplex == DUPLEX_FULL) {
  808. new_bmcr |= BMCR_FULLDPLX;
  809. }
  810. if (new_bmcr != bmcr) {
  811. u32 bmsr;
  812. int i = 0;
  813. bnx2_read_phy(bp, MII_BMSR, &bmsr);
  814. bnx2_read_phy(bp, MII_BMSR, &bmsr);
  815. if (bmsr & BMSR_LSTATUS) {
  816. /* Force link down */
  817. bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
  818. do {
  819. udelay(100);
  820. bnx2_read_phy(bp, MII_BMSR, &bmsr);
  821. bnx2_read_phy(bp, MII_BMSR, &bmsr);
  822. i++;
  823. } while ((bmsr & BMSR_LSTATUS) && (i < 620));
  824. }
  825. bnx2_write_phy(bp, MII_BMCR, new_bmcr);
  826. /* Normally, the new speed is setup after the link has
  827. * gone down and up again. In some cases, link will not go
  828. * down so we need to set up the new speed here.
  829. */
  830. if (bmsr & BMSR_LSTATUS) {
  831. bp->line_speed = bp->req_line_speed;
  832. bp->duplex = bp->req_duplex;
  833. bnx2_resolve_flow_ctrl(bp);
  834. bnx2_set_mac_link(bp);
  835. }
  836. }
  837. return 0;
  838. }
  839. static int
  840. bnx2_setup_phy(struct bnx2 *bp)
  841. {
  842. if (bp->loopback == MAC_LOOPBACK)
  843. return 0;
  844. if (bp->phy_flags & PHY_SERDES_FLAG) {
  845. return (bnx2_setup_serdes_phy(bp));
  846. }
  847. else {
  848. return (bnx2_setup_copper_phy(bp));
  849. }
  850. }
  851. static int
  852. bnx2_init_5708s_phy(struct bnx2 *bp)
  853. {
  854. u32 val;
  855. bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
  856. bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
  857. bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
  858. bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
  859. val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
  860. bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
  861. bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
  862. val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
  863. bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
  864. if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
  865. bnx2_read_phy(bp, BCM5708S_UP1, &val);
  866. val |= BCM5708S_UP1_2G5;
  867. bnx2_write_phy(bp, BCM5708S_UP1, val);
  868. }
  869. if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
  870. (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
  871. (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
  872. /* increase tx signal amplitude */
  873. bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
  874. BCM5708S_BLK_ADDR_TX_MISC);
  875. bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
  876. val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
  877. bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
  878. bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
  879. }
  880. val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
  881. BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
  882. if (val) {
  883. u32 is_backplane;
  884. is_backplane = REG_RD_IND(bp, bp->shmem_base +
  885. BNX2_SHARED_HW_CFG_CONFIG);
  886. if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
  887. bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
  888. BCM5708S_BLK_ADDR_TX_MISC);
  889. bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
  890. bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
  891. BCM5708S_BLK_ADDR_DIG);
  892. }
  893. }
  894. return 0;
  895. }
  896. static int
  897. bnx2_init_5706s_phy(struct bnx2 *bp)
  898. {
  899. u32 val;
  900. bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
  901. if (CHIP_NUM(bp) == CHIP_NUM_5706) {
  902. REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
  903. }
  904. bnx2_write_phy(bp, 0x18, 0x7);
  905. bnx2_read_phy(bp, 0x18, &val);
  906. bnx2_write_phy(bp, 0x18, val & ~0x4007);
  907. bnx2_write_phy(bp, 0x1c, 0x6c00);
  908. bnx2_read_phy(bp, 0x1c, &val);
  909. bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
  910. return 0;
  911. }
  912. static int
  913. bnx2_init_copper_phy(struct bnx2 *bp)
  914. {
  915. u32 val;
  916. bp->phy_flags |= PHY_CRC_FIX_FLAG;
  917. if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
  918. bnx2_write_phy(bp, 0x18, 0x0c00);
  919. bnx2_write_phy(bp, 0x17, 0x000a);
  920. bnx2_write_phy(bp, 0x15, 0x310b);
  921. bnx2_write_phy(bp, 0x17, 0x201f);
  922. bnx2_write_phy(bp, 0x15, 0x9506);
  923. bnx2_write_phy(bp, 0x17, 0x401f);
  924. bnx2_write_phy(bp, 0x15, 0x14e2);
  925. bnx2_write_phy(bp, 0x18, 0x0400);
  926. }
  927. bnx2_write_phy(bp, 0x18, 0x7);
  928. bnx2_read_phy(bp, 0x18, &val);
  929. bnx2_write_phy(bp, 0x18, val & ~0x4007);
  930. bnx2_read_phy(bp, 0x10, &val);
  931. bnx2_write_phy(bp, 0x10, val & ~0x1);
  932. /* ethernet@wirespeed */
  933. bnx2_write_phy(bp, 0x18, 0x7007);
  934. bnx2_read_phy(bp, 0x18, &val);
  935. bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
  936. return 0;
  937. }
  938. static int
  939. bnx2_init_phy(struct bnx2 *bp)
  940. {
  941. u32 val;
  942. int rc = 0;
  943. bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
  944. bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
  945. REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
  946. bnx2_reset_phy(bp);
  947. bnx2_read_phy(bp, MII_PHYSID1, &val);
  948. bp->phy_id = val << 16;
  949. bnx2_read_phy(bp, MII_PHYSID2, &val);
  950. bp->phy_id |= val & 0xffff;
  951. if (bp->phy_flags & PHY_SERDES_FLAG) {
  952. if (CHIP_NUM(bp) == CHIP_NUM_5706)
  953. rc = bnx2_init_5706s_phy(bp);
  954. else if (CHIP_NUM(bp) == CHIP_NUM_5708)
  955. rc = bnx2_init_5708s_phy(bp);
  956. }
  957. else {
  958. rc = bnx2_init_copper_phy(bp);
  959. }
  960. bnx2_setup_phy(bp);
  961. return rc;
  962. }
  963. static int
  964. bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
  965. {
  966. int i;
  967. u32 val;
  968. bp->fw_wr_seq++;
  969. msg_data |= bp->fw_wr_seq;
  970. REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
  971. /* wait for an acknowledgement. */
  972. for (i = 0; i < (FW_ACK_TIME_OUT_MS / 50); i++) {
  973. mdelay(50);
  974. val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
  975. if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
  976. break;
  977. }
  978. if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
  979. return 0;
  980. /* If we timed out, inform the firmware that this is the case. */
  981. if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
  982. if (!silent)
  983. printf("fw sync timeout, reset code = %x\n", (unsigned int) msg_data);
  984. msg_data &= ~BNX2_DRV_MSG_CODE;
  985. msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
  986. REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
  987. return -EBUSY;
  988. }
  989. if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
  990. return -EIO;
  991. return 0;
  992. }
  993. static void
  994. bnx2_init_context(struct bnx2 *bp)
  995. {
  996. u32 vcid;
  997. vcid = 96;
  998. while (vcid) {
  999. u32 vcid_addr, pcid_addr, offset;
  1000. vcid--;
  1001. if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
  1002. u32 new_vcid;
  1003. vcid_addr = GET_PCID_ADDR(vcid);
  1004. if (vcid & 0x8) {
  1005. new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
  1006. }
  1007. else {
  1008. new_vcid = vcid;
  1009. }
  1010. pcid_addr = GET_PCID_ADDR(new_vcid);
  1011. }
  1012. else {
  1013. vcid_addr = GET_CID_ADDR(vcid);
  1014. pcid_addr = vcid_addr;
  1015. }
  1016. REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
  1017. REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
  1018. /* Zero out the context. */
  1019. for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
  1020. CTX_WR(bp, 0x00, offset, 0);
  1021. }
  1022. REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
  1023. REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
  1024. }
  1025. }
  1026. static int
  1027. bnx2_alloc_bad_rbuf(struct bnx2 *bp)
  1028. {
  1029. u16 good_mbuf[512];
  1030. u32 good_mbuf_cnt;
  1031. u32 val;
  1032. REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
  1033. BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
  1034. good_mbuf_cnt = 0;
  1035. /* Allocate a bunch of mbufs and save the good ones in an array. */
  1036. val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
  1037. while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
  1038. REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
  1039. val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
  1040. val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
  1041. /* The addresses with Bit 9 set are bad memory blocks. */
  1042. if (!(val & (1 << 9))) {
  1043. good_mbuf[good_mbuf_cnt] = (u16) val;
  1044. good_mbuf_cnt++;
  1045. }
  1046. val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
  1047. }
  1048. /* Free the good ones back to the mbuf pool thus discarding
  1049. * all the bad ones. */
  1050. while (good_mbuf_cnt) {
  1051. good_mbuf_cnt--;
  1052. val = good_mbuf[good_mbuf_cnt];
  1053. val = (val << 9) | val | 1;
  1054. REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
  1055. }
  1056. return 0;
  1057. }
  1058. static void
  1059. bnx2_set_mac_addr(struct bnx2 *bp)
  1060. {
  1061. u32 val;
  1062. u8 *mac_addr = bp->nic->node_addr;
  1063. val = (mac_addr[0] << 8) | mac_addr[1];
  1064. REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
  1065. val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
  1066. (mac_addr[4] << 8) | mac_addr[5];
  1067. REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
  1068. }
  1069. static void
  1070. bnx2_set_rx_mode(struct nic *nic __unused)
  1071. {
  1072. struct bnx2 *bp = &bnx2;
  1073. u32 rx_mode, sort_mode;
  1074. int i;
  1075. rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
  1076. BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
  1077. sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
  1078. if (!(bp->flags & ASF_ENABLE_FLAG)) {
  1079. rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
  1080. }
  1081. /* Accept all multicasts */
  1082. for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
  1083. REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
  1084. 0xffffffff);
  1085. }
  1086. sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
  1087. if (rx_mode != bp->rx_mode) {
  1088. bp->rx_mode = rx_mode;
  1089. REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
  1090. }
  1091. REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
  1092. REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
  1093. REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
  1094. }
  1095. static void
  1096. load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len, u32 rv2p_proc)
  1097. {
  1098. unsigned int i;
  1099. u32 val;
  1100. for (i = 0; i < rv2p_code_len; i += 8) {
  1101. REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
  1102. rv2p_code++;
  1103. REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
  1104. rv2p_code++;
  1105. if (rv2p_proc == RV2P_PROC1) {
  1106. val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
  1107. REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
  1108. }
  1109. else {
  1110. val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
  1111. REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
  1112. }
  1113. }
  1114. /* Reset the processor, un-stall is done later. */
  1115. if (rv2p_proc == RV2P_PROC1) {
  1116. REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
  1117. }
  1118. else {
  1119. REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
  1120. }
  1121. }
  1122. static void
  1123. load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
  1124. {
  1125. u32 offset;
  1126. u32 val;
  1127. /* Halt the CPU. */
  1128. val = REG_RD_IND(bp, cpu_reg->mode);
  1129. val |= cpu_reg->mode_value_halt;
  1130. REG_WR_IND(bp, cpu_reg->mode, val);
  1131. REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
  1132. /* Load the Text area. */
  1133. offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
  1134. if (fw->text) {
  1135. unsigned int j;
  1136. for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
  1137. REG_WR_IND(bp, offset, fw->text[j]);
  1138. }
  1139. }
  1140. /* Load the Data area. */
  1141. offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
  1142. if (fw->data) {
  1143. unsigned int j;
  1144. for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
  1145. REG_WR_IND(bp, offset, fw->data[j]);
  1146. }
  1147. }
  1148. /* Load the SBSS area. */
  1149. offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
  1150. if (fw->sbss) {
  1151. unsigned int j;
  1152. for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
  1153. REG_WR_IND(bp, offset, fw->sbss[j]);
  1154. }
  1155. }
  1156. /* Load the BSS area. */
  1157. offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
  1158. if (fw->bss) {
  1159. unsigned int j;
  1160. for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
  1161. REG_WR_IND(bp, offset, fw->bss[j]);
  1162. }
  1163. }
  1164. /* Load the Read-Only area. */
  1165. offset = cpu_reg->spad_base +
  1166. (fw->rodata_addr - cpu_reg->mips_view_base);
  1167. if (fw->rodata) {
  1168. unsigned int j;
  1169. for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
  1170. REG_WR_IND(bp, offset, fw->rodata[j]);
  1171. }
  1172. }
  1173. /* Clear the pre-fetch instruction. */
  1174. REG_WR_IND(bp, cpu_reg->inst, 0);
  1175. REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
  1176. /* Start the CPU. */
  1177. val = REG_RD_IND(bp, cpu_reg->mode);
  1178. val &= ~cpu_reg->mode_value_halt;
  1179. REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
  1180. REG_WR_IND(bp, cpu_reg->mode, val);
  1181. }
  1182. static void
  1183. bnx2_init_cpus(struct bnx2 *bp)
  1184. {
  1185. struct cpu_reg cpu_reg;
  1186. struct fw_info fw;
  1187. /* Unfortunately, it looks like we need to load the firmware
  1188. * before the card will work properly. That means this driver
  1189. * will be huge by Etherboot standards (approx. 50K compressed).
  1190. */
  1191. /* Initialize the RV2P processor. */
  1192. load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
  1193. load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
  1194. /* Initialize the RX Processor. */
  1195. cpu_reg.mode = BNX2_RXP_CPU_MODE;
  1196. cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
  1197. cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
  1198. cpu_reg.state = BNX2_RXP_CPU_STATE;
  1199. cpu_reg.state_value_clear = 0xffffff;
  1200. cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
  1201. cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
  1202. cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
  1203. cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
  1204. cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
  1205. cpu_reg.spad_base = BNX2_RXP_SCRATCH;
  1206. cpu_reg.mips_view_base = 0x8000000;
  1207. fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
  1208. fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
  1209. fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
  1210. fw.start_addr = bnx2_RXP_b06FwStartAddr;
  1211. fw.text_addr = bnx2_RXP_b06FwTextAddr;
  1212. fw.text_len = bnx2_RXP_b06FwTextLen;
  1213. fw.text_index = 0;
  1214. fw.text = bnx2_RXP_b06FwText;
  1215. fw.data_addr = bnx2_RXP_b06FwDataAddr;
  1216. fw.data_len = bnx2_RXP_b06FwDataLen;
  1217. fw.data_index = 0;
  1218. fw.data = bnx2_RXP_b06FwData;
  1219. fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
  1220. fw.sbss_len = bnx2_RXP_b06FwSbssLen;
  1221. fw.sbss_index = 0;
  1222. fw.sbss = bnx2_RXP_b06FwSbss;
  1223. fw.bss_addr = bnx2_RXP_b06FwBssAddr;
  1224. fw.bss_len = bnx2_RXP_b06FwBssLen;
  1225. fw.bss_index = 0;
  1226. fw.bss = bnx2_RXP_b06FwBss;
  1227. fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
  1228. fw.rodata_len = bnx2_RXP_b06FwRodataLen;
  1229. fw.rodata_index = 0;
  1230. fw.rodata = bnx2_RXP_b06FwRodata;
  1231. load_cpu_fw(bp, &cpu_reg, &fw);
  1232. /* Initialize the TX Processor. */
  1233. cpu_reg.mode = BNX2_TXP_CPU_MODE;
  1234. cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
  1235. cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
  1236. cpu_reg.state = BNX2_TXP_CPU_STATE;
  1237. cpu_reg.state_value_clear = 0xffffff;
  1238. cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
  1239. cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
  1240. cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
  1241. cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
  1242. cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
  1243. cpu_reg.spad_base = BNX2_TXP_SCRATCH;
  1244. cpu_reg.mips_view_base = 0x8000000;
  1245. fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
  1246. fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
  1247. fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
  1248. fw.start_addr = bnx2_TXP_b06FwStartAddr;
  1249. fw.text_addr = bnx2_TXP_b06FwTextAddr;
  1250. fw.text_len = bnx2_TXP_b06FwTextLen;
  1251. fw.text_index = 0;
  1252. fw.text = bnx2_TXP_b06FwText;
  1253. fw.data_addr = bnx2_TXP_b06FwDataAddr;
  1254. fw.data_len = bnx2_TXP_b06FwDataLen;
  1255. fw.data_index = 0;
  1256. fw.data = bnx2_TXP_b06FwData;
  1257. fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
  1258. fw.sbss_len = bnx2_TXP_b06FwSbssLen;
  1259. fw.sbss_index = 0;
  1260. fw.sbss = bnx2_TXP_b06FwSbss;
  1261. fw.bss_addr = bnx2_TXP_b06FwBssAddr;
  1262. fw.bss_len = bnx2_TXP_b06FwBssLen;
  1263. fw.bss_index = 0;
  1264. fw.bss = bnx2_TXP_b06FwBss;
  1265. fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
  1266. fw.rodata_len = bnx2_TXP_b06FwRodataLen;
  1267. fw.rodata_index = 0;
  1268. fw.rodata = bnx2_TXP_b06FwRodata;
  1269. load_cpu_fw(bp, &cpu_reg, &fw);
  1270. /* Initialize the TX Patch-up Processor. */
  1271. cpu_reg.mode = BNX2_TPAT_CPU_MODE;
  1272. cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
  1273. cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
  1274. cpu_reg.state = BNX2_TPAT_CPU_STATE;
  1275. cpu_reg.state_value_clear = 0xffffff;
  1276. cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
  1277. cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
  1278. cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
  1279. cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
  1280. cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
  1281. cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
  1282. cpu_reg.mips_view_base = 0x8000000;
  1283. fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
  1284. fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
  1285. fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
  1286. fw.start_addr = bnx2_TPAT_b06FwStartAddr;
  1287. fw.text_addr = bnx2_TPAT_b06FwTextAddr;
  1288. fw.text_len = bnx2_TPAT_b06FwTextLen;
  1289. fw.text_index = 0;
  1290. fw.text = bnx2_TPAT_b06FwText;
  1291. fw.data_addr = bnx2_TPAT_b06FwDataAddr;
  1292. fw.data_len = bnx2_TPAT_b06FwDataLen;
  1293. fw.data_index = 0;
  1294. fw.data = bnx2_TPAT_b06FwData;
  1295. fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
  1296. fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
  1297. fw.sbss_index = 0;
  1298. fw.sbss = bnx2_TPAT_b06FwSbss;
  1299. fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
  1300. fw.bss_len = bnx2_TPAT_b06FwBssLen;
  1301. fw.bss_index = 0;
  1302. fw.bss = bnx2_TPAT_b06FwBss;
  1303. fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
  1304. fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
  1305. fw.rodata_index = 0;
  1306. fw.rodata = bnx2_TPAT_b06FwRodata;
  1307. load_cpu_fw(bp, &cpu_reg, &fw);
  1308. /* Initialize the Completion Processor. */
  1309. cpu_reg.mode = BNX2_COM_CPU_MODE;
  1310. cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
  1311. cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
  1312. cpu_reg.state = BNX2_COM_CPU_STATE;
  1313. cpu_reg.state_value_clear = 0xffffff;
  1314. cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
  1315. cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
  1316. cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
  1317. cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
  1318. cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
  1319. cpu_reg.spad_base = BNX2_COM_SCRATCH;
  1320. cpu_reg.mips_view_base = 0x8000000;
  1321. fw.ver_major = bnx2_COM_b06FwReleaseMajor;
  1322. fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
  1323. fw.ver_fix = bnx2_COM_b06FwReleaseFix;
  1324. fw.start_addr = bnx2_COM_b06FwStartAddr;
  1325. fw.text_addr = bnx2_COM_b06FwTextAddr;
  1326. fw.text_len = bnx2_COM_b06FwTextLen;
  1327. fw.text_index = 0;
  1328. fw.text = bnx2_COM_b06FwText;
  1329. fw.data_addr = bnx2_COM_b06FwDataAddr;
  1330. fw.data_len = bnx2_COM_b06FwDataLen;
  1331. fw.data_index = 0;
  1332. fw.data = bnx2_COM_b06FwData;
  1333. fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
  1334. fw.sbss_len = bnx2_COM_b06FwSbssLen;
  1335. fw.sbss_index = 0;
  1336. fw.sbss = bnx2_COM_b06FwSbss;
  1337. fw.bss_addr = bnx2_COM_b06FwBssAddr;
  1338. fw.bss_len = bnx2_COM_b06FwBssLen;
  1339. fw.bss_index = 0;
  1340. fw.bss = bnx2_COM_b06FwBss;
  1341. fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
  1342. fw.rodata_len = bnx2_COM_b06FwRodataLen;
  1343. fw.rodata_index = 0;
  1344. fw.rodata = bnx2_COM_b06FwRodata;
  1345. load_cpu_fw(bp, &cpu_reg, &fw);
  1346. }
  1347. static int
  1348. bnx2_set_power_state_0(struct bnx2 *bp)
  1349. {
  1350. u16 pmcsr;
  1351. u32 val;
  1352. pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
  1353. pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
  1354. (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
  1355. PCI_PM_CTRL_PME_STATUS);
  1356. if (pmcsr & PCI_PM_CTRL_STATE_MASK)
  1357. /* delay required during transition out of D3hot */
  1358. mdelay(20);
  1359. val = REG_RD(bp, BNX2_EMAC_MODE);
  1360. val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
  1361. val &= ~BNX2_EMAC_MODE_MPKT;
  1362. REG_WR(bp, BNX2_EMAC_MODE, val);
  1363. val = REG_RD(bp, BNX2_RPM_CONFIG);
  1364. val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
  1365. REG_WR(bp, BNX2_RPM_CONFIG, val);
  1366. return 0;
  1367. }
  1368. static void
  1369. bnx2_enable_nvram_access(struct bnx2 *bp)
  1370. {
  1371. u32 val;
  1372. val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
  1373. /* Enable both bits, even on read. */
  1374. REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
  1375. val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
  1376. }
  1377. static void
  1378. bnx2_disable_nvram_access(struct bnx2 *bp)
  1379. {
  1380. u32 val;
  1381. val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
  1382. /* Disable both bits, even after read. */
  1383. REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
  1384. val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
  1385. BNX2_NVM_ACCESS_ENABLE_WR_EN));
  1386. }
  1387. static int
  1388. bnx2_init_nvram(struct bnx2 *bp)
  1389. {
  1390. u32 val;
  1391. int j, entry_count, rc;
  1392. struct flash_spec *flash;
  1393. /* Determine the selected interface. */
  1394. val = REG_RD(bp, BNX2_NVM_CFG1);
  1395. entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
  1396. rc = 0;
  1397. if (val & 0x40000000) {
  1398. /* Flash interface has been reconfigured */
  1399. for (j = 0, flash = &flash_table[0]; j < entry_count;
  1400. j++, flash++) {
  1401. if ((val & FLASH_BACKUP_STRAP_MASK) ==
  1402. (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
  1403. bp->flash_info = flash;
  1404. break;
  1405. }
  1406. }
  1407. }
  1408. else {
  1409. u32 mask;
  1410. /* Not yet been reconfigured */
  1411. if (val & (1 << 23))
  1412. mask = FLASH_BACKUP_STRAP_MASK;
  1413. else
  1414. mask = FLASH_STRAP_MASK;
  1415. for (j = 0, flash = &flash_table[0]; j < entry_count;
  1416. j++, flash++) {
  1417. if ((val & mask) == (flash->strapping & mask)) {
  1418. bp->flash_info = flash;
  1419. /* Enable access to flash interface */
  1420. bnx2_enable_nvram_access(bp);
  1421. /* Reconfigure the flash interface */
  1422. REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
  1423. REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
  1424. REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
  1425. REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
  1426. /* Disable access to flash interface */
  1427. bnx2_disable_nvram_access(bp);
  1428. break;
  1429. }
  1430. }
  1431. } /* if (val & 0x40000000) */
  1432. if (j == entry_count) {
  1433. bp->flash_info = NULL;
  1434. printf("Unknown flash/EEPROM type.\n");
  1435. return -ENODEV;
  1436. }
  1437. val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
  1438. val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
  1439. if (val) {
  1440. bp->flash_size = val;
  1441. }
  1442. else {
  1443. bp->flash_size = bp->flash_info->total_size;
  1444. }
  1445. return rc;
  1446. }
  1447. static int
  1448. bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
  1449. {
  1450. u32 val;
  1451. int i, rc = 0;
  1452. /* Wait for the current PCI transaction to complete before
  1453. * issuing a reset. */
  1454. REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
  1455. BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
  1456. BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
  1457. BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
  1458. BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
  1459. val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
  1460. udelay(5);
  1461. /* Wait for the firmware to tell us it is ok to issue a reset. */
  1462. bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
  1463. /* Deposit a driver reset signature so the firmware knows that
  1464. * this is a soft reset. */
  1465. REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
  1466. BNX2_DRV_RESET_SIGNATURE_MAGIC);
  1467. /* Do a dummy read to force the chip to complete all current transaction
  1468. * before we issue a reset. */
  1469. val = REG_RD(bp, BNX2_MISC_ID);
  1470. val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
  1471. BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
  1472. BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
  1473. /* Chip reset. */
  1474. REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
  1475. if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
  1476. (CHIP_ID(bp) == CHIP_ID_5706_A1))
  1477. mdelay(15);
  1478. /* Reset takes approximate 30 usec */
  1479. for (i = 0; i < 10; i++) {
  1480. val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
  1481. if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
  1482. BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
  1483. break;
  1484. }
  1485. udelay(10);
  1486. }
  1487. if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
  1488. BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
  1489. printf("Chip reset did not complete\n");
  1490. return -EBUSY;
  1491. }
  1492. /* Make sure byte swapping is properly configured. */
  1493. val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
  1494. if (val != 0x01020304) {
  1495. printf("Chip not in correct endian mode\n");
  1496. return -ENODEV;
  1497. }
  1498. /* Wait for the firmware to finish its initialization. */
  1499. rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
  1500. if (rc) {
  1501. return rc;
  1502. }
  1503. if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
  1504. /* Adjust the voltage regular to two steps lower. The default
  1505. * of this register is 0x0000000e. */
  1506. REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
  1507. /* Remove bad rbuf memory from the free pool. */
  1508. rc = bnx2_alloc_bad_rbuf(bp);
  1509. }
  1510. return rc;
  1511. }
  1512. static void
  1513. bnx2_disable(struct nic *nic __unused)
  1514. {
  1515. struct bnx2* bp = &bnx2;
  1516. if (bp->regview) {
  1517. bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_UNLOAD);
  1518. iounmap(bp->regview);
  1519. }
  1520. }
  1521. static int
  1522. bnx2_init_chip(struct bnx2 *bp)
  1523. {
  1524. u32 val;
  1525. int rc;
  1526. /* Make sure the interrupt is not active. */
  1527. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  1528. val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
  1529. BNX2_DMA_CONFIG_DATA_WORD_SWAP |
  1530. #if __BYTE_ORDER == __BIG_ENDIAN
  1531. BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
  1532. #endif
  1533. BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
  1534. DMA_READ_CHANS << 12 |
  1535. DMA_WRITE_CHANS << 16;
  1536. val |= (0x2 << 20) | (1 << 11);
  1537. if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
  1538. val |= (1 << 23);
  1539. if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
  1540. (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
  1541. val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
  1542. REG_WR(bp, BNX2_DMA_CONFIG, val);
  1543. if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
  1544. val = REG_RD(bp, BNX2_TDMA_CONFIG);
  1545. val |= BNX2_TDMA_CONFIG_ONE_DMA;
  1546. REG_WR(bp, BNX2_TDMA_CONFIG, val);
  1547. }
  1548. if (bp->flags & PCIX_FLAG) {
  1549. u16 val16;
  1550. pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
  1551. &val16);
  1552. pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
  1553. val16 & ~PCI_X_CMD_ERO);
  1554. }
  1555. REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
  1556. BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
  1557. BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
  1558. BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
  1559. /* Initialize context mapping and zero out the quick contexts. The
  1560. * context block must have already been enabled. */
  1561. bnx2_init_context(bp);
  1562. bnx2_init_nvram(bp);
  1563. bnx2_init_cpus(bp);
  1564. bnx2_set_mac_addr(bp);
  1565. val = REG_RD(bp, BNX2_MQ_CONFIG);
  1566. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  1567. val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
  1568. REG_WR(bp, BNX2_MQ_CONFIG, val);
  1569. val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
  1570. REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
  1571. REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
  1572. val = (BCM_PAGE_BITS - 8) << 24;
  1573. REG_WR(bp, BNX2_RV2P_CONFIG, val);
  1574. /* Configure page size. */
  1575. val = REG_RD(bp, BNX2_TBDR_CONFIG);
  1576. val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
  1577. val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
  1578. REG_WR(bp, BNX2_TBDR_CONFIG, val);
  1579. val = bp->mac_addr[0] +
  1580. (bp->mac_addr[1] << 8) +
  1581. (bp->mac_addr[2] << 16) +
  1582. bp->mac_addr[3] +
  1583. (bp->mac_addr[4] << 8) +
  1584. (bp->mac_addr[5] << 16);
  1585. REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
  1586. /* Program the MTU. Also include 4 bytes for CRC32. */
  1587. val = ETH_MAX_MTU + ETH_HLEN + 4;
  1588. if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
  1589. val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
  1590. REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
  1591. bp->last_status_idx = 0;
  1592. bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
  1593. /* Set up how to generate a link change interrupt. */
  1594. REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
  1595. REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
  1596. (u64) bp->status_blk_mapping & 0xffffffff);
  1597. REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
  1598. REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
  1599. (u64) bp->stats_blk_mapping & 0xffffffff);
  1600. REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
  1601. (u64) bp->stats_blk_mapping >> 32);
  1602. REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
  1603. (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
  1604. REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
  1605. (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
  1606. REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
  1607. (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
  1608. REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
  1609. REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
  1610. REG_WR(bp, BNX2_HC_COM_TICKS,
  1611. (bp->com_ticks_int << 16) | bp->com_ticks);
  1612. REG_WR(bp, BNX2_HC_CMD_TICKS,
  1613. (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
  1614. REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
  1615. REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
  1616. if (CHIP_ID(bp) == CHIP_ID_5706_A1)
  1617. REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
  1618. else {
  1619. REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
  1620. BNX2_HC_CONFIG_TX_TMR_MODE |
  1621. BNX2_HC_CONFIG_COLLECT_STATS);
  1622. }
  1623. /* Clear internal stats counters. */
  1624. REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
  1625. REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
  1626. if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &
  1627. BNX2_PORT_FEATURE_ASF_ENABLED)
  1628. bp->flags |= ASF_ENABLE_FLAG;
  1629. /* Initialize the receive filter. */
  1630. bnx2_set_rx_mode(bp->nic);
  1631. rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
  1632. 0);
  1633. REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
  1634. REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
  1635. udelay(20);
  1636. bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
  1637. return rc;
  1638. }
  1639. static void
  1640. bnx2_init_tx_ring(struct bnx2 *bp)
  1641. {
  1642. struct tx_bd *txbd;
  1643. u32 val;
  1644. txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
  1645. /* Etherboot lives below 4GB, so hi is always 0 */
  1646. txbd->tx_bd_haddr_hi = 0;
  1647. txbd->tx_bd_haddr_lo = bp->tx_desc_mapping;
  1648. bp->tx_prod = 0;
  1649. bp->tx_cons = 0;
  1650. bp->hw_tx_cons = 0;
  1651. bp->tx_prod_bseq = 0;
  1652. val = BNX2_L2CTX_TYPE_TYPE_L2;
  1653. val |= BNX2_L2CTX_TYPE_SIZE_L2;
  1654. CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
  1655. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
  1656. val |= 8 << 16;
  1657. CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
  1658. /* Etherboot lives below 4GB, so hi is always 0 */
  1659. CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, 0);
  1660. val = (u64) bp->tx_desc_mapping & 0xffffffff;
  1661. CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
  1662. }
  1663. static void
  1664. bnx2_init_rx_ring(struct bnx2 *bp)
  1665. {
  1666. struct rx_bd *rxbd;
  1667. unsigned int i;
  1668. u16 prod, ring_prod;
  1669. u32 val;
  1670. bp->rx_buf_use_size = RX_BUF_USE_SIZE;
  1671. bp->rx_buf_size = RX_BUF_SIZE;
  1672. ring_prod = prod = bp->rx_prod = 0;
  1673. bp->rx_cons = 0;
  1674. bp->hw_rx_cons = 0;
  1675. bp->rx_prod_bseq = 0;
  1676. memset(bnx2_bss.rx_buf, 0, sizeof(bnx2_bss.rx_buf));
  1677. rxbd = &bp->rx_desc_ring[0];
  1678. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  1679. rxbd->rx_bd_len = bp->rx_buf_use_size;
  1680. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  1681. }
  1682. rxbd->rx_bd_haddr_hi = 0;
  1683. rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
  1684. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
  1685. val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
  1686. val |= 0x02 << 8;
  1687. CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
  1688. /* Etherboot doesn't use memory above 4GB, so this is always 0 */
  1689. CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, 0);
  1690. val = bp->rx_desc_mapping & 0xffffffff;
  1691. CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
  1692. for (i = 0; (int) i < bp->rx_ring_size; i++) {
  1693. rxbd = &bp->rx_desc_ring[RX_RING_IDX(ring_prod)];
  1694. rxbd->rx_bd_haddr_hi = 0;
  1695. rxbd->rx_bd_haddr_lo = virt_to_bus(&bnx2_bss.rx_buf[ring_prod][0]);
  1696. bp->rx_prod_bseq += bp->rx_buf_use_size;
  1697. prod = NEXT_RX_BD(prod);
  1698. ring_prod = RX_RING_IDX(prod);
  1699. }
  1700. bp->rx_prod = prod;
  1701. REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, bp->rx_prod);
  1702. REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
  1703. }
  1704. static int
  1705. bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
  1706. {
  1707. int rc;
  1708. rc = bnx2_reset_chip(bp, reset_code);
  1709. if (rc) {
  1710. return rc;
  1711. }
  1712. bnx2_init_chip(bp);
  1713. bnx2_init_tx_ring(bp);
  1714. bnx2_init_rx_ring(bp);
  1715. return 0;
  1716. }
  1717. static int
  1718. bnx2_init_nic(struct bnx2 *bp)
  1719. {
  1720. int rc;
  1721. if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
  1722. return rc;
  1723. bnx2_init_phy(bp);
  1724. bnx2_set_link(bp);
  1725. return 0;
  1726. }
  1727. static int
  1728. bnx2_init_board(struct pci_device *pdev, struct nic *nic)
  1729. {
  1730. unsigned long bnx2reg_base, bnx2reg_len;
  1731. struct bnx2 *bp = &bnx2;
  1732. int rc;
  1733. u32 reg;
  1734. bp->flags = 0;
  1735. bp->phy_flags = 0;
  1736. /* enable device (incl. PCI PM wakeup), and bus-mastering */
  1737. adjust_pci_device(pdev);
  1738. nic->ioaddr = pdev->ioaddr & ~3;
  1739. nic->irqno = 0;
  1740. rc = 0;
  1741. bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
  1742. if (bp->pm_cap == 0) {
  1743. printf("Cannot find power management capability, aborting.\n");
  1744. rc = -EIO;
  1745. goto err_out_disable;
  1746. }
  1747. bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
  1748. if (bp->pcix_cap == 0) {
  1749. printf("Cannot find PCIX capability, aborting.\n");
  1750. rc = -EIO;
  1751. goto err_out_disable;
  1752. }
  1753. bp->pdev = pdev;
  1754. bp->nic = nic;
  1755. bnx2reg_base = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
  1756. bnx2reg_len = MB_GET_CID_ADDR(17);
  1757. bp->regview = ioremap(bnx2reg_base, bnx2reg_len);
  1758. if (!bp->regview) {
  1759. printf("Cannot map register space, aborting.\n");
  1760. rc = -EIO;
  1761. goto err_out_disable;
  1762. }
  1763. /* Configure byte swap and enable write to the reg_window registers.
  1764. * Rely on CPU to do target byte swapping on big endian systems
  1765. * The chip's target access swapping will not swap all accesses
  1766. */
  1767. pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
  1768. BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
  1769. BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
  1770. bnx2_set_power_state_0(bp);
  1771. bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
  1772. /* Get bus information. */
  1773. reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
  1774. if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
  1775. u32 clkreg;
  1776. bp->flags |= PCIX_FLAG;
  1777. clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
  1778. clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
  1779. switch (clkreg) {
  1780. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
  1781. bp->bus_speed_mhz = 133;
  1782. break;
  1783. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
  1784. bp->bus_speed_mhz = 100;
  1785. break;
  1786. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
  1787. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
  1788. bp->bus_speed_mhz = 66;
  1789. break;
  1790. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
  1791. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
  1792. bp->bus_speed_mhz = 50;
  1793. break;
  1794. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
  1795. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
  1796. case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
  1797. bp->bus_speed_mhz = 33;
  1798. break;
  1799. }
  1800. }
  1801. else {
  1802. if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
  1803. bp->bus_speed_mhz = 66;
  1804. else
  1805. bp->bus_speed_mhz = 33;
  1806. }
  1807. if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
  1808. bp->flags |= PCI_32BIT_FLAG;
  1809. /* 5706A0 may falsely detect SERR and PERR. */
  1810. if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
  1811. reg = REG_RD(bp, PCI_COMMAND);
  1812. reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
  1813. REG_WR(bp, PCI_COMMAND, reg);
  1814. }
  1815. else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
  1816. !(bp->flags & PCIX_FLAG)) {
  1817. printf("5706 A1 can only be used in a PCIX bus, aborting.\n");
  1818. goto err_out_disable;
  1819. }
  1820. bnx2_init_nvram(bp);
  1821. reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
  1822. if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
  1823. BNX2_SHM_HDR_SIGNATURE_SIG)
  1824. bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0);
  1825. else
  1826. bp->shmem_base = HOST_VIEW_SHMEM_BASE;
  1827. /* Get the permanent MAC address. First we need to make sure the
  1828. * firmware is actually running.
  1829. */
  1830. reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
  1831. if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
  1832. BNX2_DEV_INFO_SIGNATURE_MAGIC) {
  1833. printf("Firmware not running, aborting.\n");
  1834. rc = -ENODEV;
  1835. goto err_out_disable;
  1836. }
  1837. bp->fw_ver = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
  1838. reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
  1839. bp->mac_addr[0] = (u8) (reg >> 8);
  1840. bp->mac_addr[1] = (u8) reg;
  1841. reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
  1842. bp->mac_addr[2] = (u8) (reg >> 24);
  1843. bp->mac_addr[3] = (u8) (reg >> 16);
  1844. bp->mac_addr[4] = (u8) (reg >> 8);
  1845. bp->mac_addr[5] = (u8) reg;
  1846. bp->tx_ring_size = MAX_TX_DESC_CNT;
  1847. bp->rx_ring_size = RX_BUF_CNT;
  1848. bp->rx_max_ring_idx = MAX_RX_DESC_CNT;
  1849. bp->rx_offset = RX_OFFSET;
  1850. bp->tx_quick_cons_trip_int = 20;
  1851. bp->tx_quick_cons_trip = 20;
  1852. bp->tx_ticks_int = 80;
  1853. bp->tx_ticks = 80;
  1854. bp->rx_quick_cons_trip_int = 6;
  1855. bp->rx_quick_cons_trip = 6;
  1856. bp->rx_ticks_int = 18;
  1857. bp->rx_ticks = 18;
  1858. bp->stats_ticks = 1000000 & 0xffff00;
  1859. bp->phy_addr = 1;
  1860. /* No need for WOL support in Etherboot */
  1861. bp->flags |= NO_WOL_FLAG;
  1862. /* Disable WOL support if we are running on a SERDES chip. */
  1863. if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
  1864. bp->phy_flags |= PHY_SERDES_FLAG;
  1865. if (CHIP_NUM(bp) == CHIP_NUM_5708) {
  1866. bp->phy_addr = 2;
  1867. reg = REG_RD_IND(bp, bp->shmem_base +
  1868. BNX2_SHARED_HW_CFG_CONFIG);
  1869. if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
  1870. bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
  1871. }
  1872. }
  1873. if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
  1874. bp->tx_quick_cons_trip_int =
  1875. bp->tx_quick_cons_trip;
  1876. bp->tx_ticks_int = bp->tx_ticks;
  1877. bp->rx_quick_cons_trip_int =
  1878. bp->rx_quick_cons_trip;
  1879. bp->rx_ticks_int = bp->rx_ticks;
  1880. bp->comp_prod_trip_int = bp->comp_prod_trip;
  1881. bp->com_ticks_int = bp->com_ticks;
  1882. bp->cmd_ticks_int = bp->cmd_ticks;
  1883. }
  1884. bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
  1885. bp->req_line_speed = 0;
  1886. if (bp->phy_flags & PHY_SERDES_FLAG) {
  1887. bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
  1888. reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
  1889. reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
  1890. if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
  1891. bp->autoneg = 0;
  1892. bp->req_line_speed = bp->line_speed = SPEED_1000;
  1893. bp->req_duplex = DUPLEX_FULL;
  1894. }
  1895. }
  1896. else {
  1897. bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
  1898. }
  1899. bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
  1900. /* Disable driver heartbeat checking */
  1901. REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB,
  1902. BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE);
  1903. REG_RD_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB);
  1904. return 0;
  1905. err_out_disable:
  1906. bnx2_disable(nic);
  1907. return rc;
  1908. }
  1909. static void
  1910. bnx2_transmit(struct nic *nic, const char *dst_addr,
  1911. unsigned int type, unsigned int size, const char *packet)
  1912. {
  1913. /* Sometimes the nic will be behind by a frame. Using two transmit
  1914. * buffers prevents us from timing out in that case.
  1915. */
  1916. static struct eth_frame {
  1917. uint8_t dst_addr[ETH_ALEN];
  1918. uint8_t src_addr[ETH_ALEN];
  1919. uint16_t type;
  1920. uint8_t data [ETH_FRAME_LEN - ETH_HLEN];
  1921. } frame[2];
  1922. static int frame_idx = 0;
  1923. /* send the packet to destination */
  1924. struct tx_bd *txbd;
  1925. struct bnx2 *bp = &bnx2;
  1926. u16 prod, ring_prod;
  1927. u16 hw_cons;
  1928. int i = 0;
  1929. prod = bp->tx_prod;
  1930. ring_prod = TX_RING_IDX(prod);
  1931. hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
  1932. if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
  1933. hw_cons++;
  1934. }
  1935. while((hw_cons != prod) && (hw_cons != (PREV_TX_BD(prod)))) {
  1936. mdelay(10); /* give the nic a chance */
  1937. //poll_interruptions();
  1938. if (++i > 500) { /* timeout 5s for transmit */
  1939. printf("transmit timed out\n");
  1940. bnx2_disable(bp->nic);
  1941. bnx2_init_board(bp->pdev, bp->nic);
  1942. return;
  1943. }
  1944. }
  1945. if (i != 0) {
  1946. printf("#");
  1947. }
  1948. /* Copy the packet to the our local buffer */
  1949. memcpy(&frame[frame_idx].dst_addr, dst_addr, ETH_ALEN);
  1950. memcpy(&frame[frame_idx].src_addr, nic->node_addr, ETH_ALEN);
  1951. frame[frame_idx].type = htons(type);
  1952. memset(&frame[frame_idx].data, 0, sizeof(frame[frame_idx].data));
  1953. memcpy(&frame[frame_idx].data, packet, size);
  1954. /* Setup the ring buffer entry to transmit */
  1955. txbd = &bp->tx_desc_ring[ring_prod];
  1956. txbd->tx_bd_haddr_hi = 0; /* Etherboot runs under 4GB */
  1957. txbd->tx_bd_haddr_lo = virt_to_bus(&frame[frame_idx]);
  1958. txbd->tx_bd_mss_nbytes = (size + ETH_HLEN);
  1959. txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
  1960. /* Advance to the next entry */
  1961. prod = NEXT_TX_BD(prod);
  1962. frame_idx ^= 1;
  1963. bp->tx_prod_bseq += (size + ETH_HLEN);
  1964. REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
  1965. REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
  1966. wmb();
  1967. bp->tx_prod = prod;
  1968. }
  1969. static int
  1970. bnx2_poll_link(struct bnx2 *bp)
  1971. {
  1972. u32 new_link_state, old_link_state, emac_status;
  1973. new_link_state = bp->status_blk->status_attn_bits &
  1974. STATUS_ATTN_BITS_LINK_STATE;
  1975. old_link_state = bp->status_blk->status_attn_bits_ack &
  1976. STATUS_ATTN_BITS_LINK_STATE;
  1977. if (!new_link_state && !old_link_state) {
  1978. /* For some reason the card doesn't always update the link
  1979. * status bits properly. Kick the stupid thing and try again.
  1980. */
  1981. u32 bmsr;
  1982. bnx2_read_phy(bp, MII_BMSR, &bmsr);
  1983. bnx2_read_phy(bp, MII_BMSR, &bmsr);
  1984. if ((bp->phy_flags & PHY_SERDES_FLAG) &&
  1985. (CHIP_NUM(bp) == CHIP_NUM_5706)) {
  1986. REG_RD(bp, BNX2_EMAC_STATUS);
  1987. }
  1988. new_link_state = bp->status_blk->status_attn_bits &
  1989. STATUS_ATTN_BITS_LINK_STATE;
  1990. old_link_state = bp->status_blk->status_attn_bits_ack &
  1991. STATUS_ATTN_BITS_LINK_STATE;
  1992. /* Okay, for some reason the above doesn't work with some
  1993. * switches (like HP ProCurve). If the above doesn't work,
  1994. * check the MAC directly to see if we have a link. Perhaps we
  1995. * should always check the MAC instead probing the MII.
  1996. */
  1997. if (!new_link_state && !old_link_state) {
  1998. emac_status = REG_RD(bp, BNX2_EMAC_STATUS);
  1999. if (emac_status & BNX2_EMAC_STATUS_LINK_CHANGE) {
  2000. /* Acknowledge the link change */
  2001. REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
  2002. } else if (emac_status & BNX2_EMAC_STATUS_LINK) {
  2003. new_link_state = !old_link_state;
  2004. }
  2005. }
  2006. }
  2007. if (new_link_state != old_link_state) {
  2008. if (new_link_state) {
  2009. REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
  2010. STATUS_ATTN_BITS_LINK_STATE);
  2011. }
  2012. else {
  2013. REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
  2014. STATUS_ATTN_BITS_LINK_STATE);
  2015. }
  2016. bnx2_set_link(bp);
  2017. /* This is needed to take care of transient status
  2018. * during link changes.
  2019. */
  2020. REG_WR(bp, BNX2_HC_COMMAND,
  2021. bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  2022. REG_RD(bp, BNX2_HC_COMMAND);
  2023. }
  2024. return bp->link_up;
  2025. }
  2026. static int
  2027. bnx2_poll(struct nic* nic, int retrieve)
  2028. {
  2029. struct bnx2 *bp = &bnx2;
  2030. struct rx_bd *cons_bd, *prod_bd;
  2031. u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
  2032. struct l2_fhdr *rx_hdr;
  2033. int result = 0;
  2034. unsigned int len;
  2035. unsigned char *data;
  2036. u32 status;
  2037. #if 0
  2038. if ((bp->status_blk->status_idx == bp->last_status_idx) &&
  2039. (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
  2040. BNX2_PCICFG_MISC_STATUS_INTA_VALUE)) {
  2041. bp->last_status_idx = bp->status_blk->status_idx;
  2042. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  2043. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
  2044. BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
  2045. bp->last_status_idx);
  2046. return 0;
  2047. }
  2048. #endif
  2049. if ((bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) && !retrieve)
  2050. return 1;
  2051. if (bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) {
  2052. hw_cons = bp->hw_rx_cons = bp->status_blk->status_rx_quick_consumer_index0;
  2053. if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
  2054. hw_cons++;
  2055. }
  2056. sw_cons = bp->rx_cons;
  2057. sw_prod = bp->rx_prod;
  2058. rmb();
  2059. if (sw_cons != hw_cons) {
  2060. sw_ring_cons = RX_RING_IDX(sw_cons);
  2061. sw_ring_prod = RX_RING_IDX(sw_prod);
  2062. data = bus_to_virt(bp->rx_desc_ring[sw_ring_cons].rx_bd_haddr_lo);
  2063. rx_hdr = (struct l2_fhdr *)data;
  2064. len = rx_hdr->l2_fhdr_pkt_len - 4;
  2065. if ((len > (ETH_MAX_MTU + ETH_HLEN)) ||
  2066. ((status = rx_hdr->l2_fhdr_status) &
  2067. (L2_FHDR_ERRORS_BAD_CRC |
  2068. L2_FHDR_ERRORS_PHY_DECODE |
  2069. L2_FHDR_ERRORS_ALIGNMENT |
  2070. L2_FHDR_ERRORS_TOO_SHORT |
  2071. L2_FHDR_ERRORS_GIANT_FRAME))) {
  2072. result = 0;
  2073. }
  2074. else
  2075. {
  2076. nic->packetlen = len;
  2077. memcpy(nic->packet, data + bp->rx_offset, len);
  2078. result = 1;
  2079. }
  2080. /* Reuse the buffer */
  2081. bp->rx_prod_bseq += bp->rx_buf_use_size;
  2082. if (sw_cons != sw_prod) {
  2083. cons_bd = &bp->rx_desc_ring[sw_ring_cons];
  2084. prod_bd = &bp->rx_desc_ring[sw_ring_prod];
  2085. prod_bd->rx_bd_haddr_hi = 0; /* Etherboot runs under 4GB */
  2086. prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
  2087. }
  2088. sw_cons = NEXT_RX_BD(sw_cons);
  2089. sw_prod = NEXT_RX_BD(sw_prod);
  2090. }
  2091. bp->rx_cons = sw_cons;
  2092. bp->rx_prod = sw_prod;
  2093. REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, bp->rx_prod);
  2094. REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
  2095. wmb();
  2096. }
  2097. bnx2_poll_link(bp);
  2098. #if 0
  2099. bp->last_status_idx = bp->status_blk->status_idx;
  2100. rmb();
  2101. REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
  2102. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
  2103. BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
  2104. bp->last_status_idx);
  2105. REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  2106. #endif
  2107. return result;
  2108. }
  2109. static void
  2110. bnx2_irq(struct nic *nic __unused, irq_action_t action __unused)
  2111. {
  2112. switch ( action ) {
  2113. case DISABLE: break;
  2114. case ENABLE: break;
  2115. case FORCE: break;
  2116. }
  2117. }
  2118. static struct nic_operations bnx2_operations = {
  2119. .connect = dummy_connect,
  2120. .poll = bnx2_poll,
  2121. .transmit = bnx2_transmit,
  2122. .irq = bnx2_irq,
  2123. };
  2124. static int
  2125. bnx2_probe(struct nic *nic, struct pci_device *pdev)
  2126. {
  2127. struct bnx2 *bp = &bnx2;
  2128. int i, rc;
  2129. if (pdev == 0)
  2130. return 0;
  2131. memset(bp, 0, sizeof(*bp));
  2132. rc = bnx2_init_board(pdev, nic);
  2133. if (rc < 0) {
  2134. return 0;
  2135. }
  2136. /*
  2137. nic->disable = bnx2_disable;
  2138. nic->transmit = bnx2_transmit;
  2139. nic->poll = bnx2_poll;
  2140. nic->irq = bnx2_irq;
  2141. */
  2142. nic->nic_op = &bnx2_operations;
  2143. memcpy(nic->node_addr, bp->mac_addr, ETH_ALEN);
  2144. printf("Ethernet addr: %s\n", eth_ntoa( nic->node_addr ) );
  2145. printf("Broadcom NetXtreme II (%c%d) PCI%s %s %dMHz\n",
  2146. (int) ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
  2147. (int) ((CHIP_ID(bp) & 0x0ff0) >> 4),
  2148. ((bp->flags & PCIX_FLAG) ? "-X" : ""),
  2149. ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
  2150. bp->bus_speed_mhz);
  2151. bnx2_set_power_state_0(bp);
  2152. bnx2_disable_int(bp);
  2153. bnx2_alloc_mem(bp);
  2154. rc = bnx2_init_nic(bp);
  2155. if (rc) {
  2156. return 0;
  2157. }
  2158. bnx2_poll_link(bp);
  2159. for(i = 0; !bp->link_up && (i < VALID_LINK_TIMEOUT*100); i++) {
  2160. mdelay(1);
  2161. bnx2_poll_link(bp);
  2162. }
  2163. #if 1
  2164. if (!bp->link_up){
  2165. printf("Valid link not established\n");
  2166. goto err_out_disable;
  2167. }
  2168. #endif
  2169. return 1;
  2170. err_out_disable:
  2171. bnx2_disable(nic);
  2172. return 0;
  2173. }
  2174. static struct pci_device_id bnx2_nics[] = {
  2175. PCI_ROM(0x14e4, 0x164a, "bnx2-5706", "Broadcom NetXtreme II BCM5706", 0),
  2176. PCI_ROM(0x14e4, 0x164c, "bnx2-5708", "Broadcom NetXtreme II BCM5708", 0),
  2177. PCI_ROM(0x14e4, 0x16aa, "bnx2-5706S", "Broadcom NetXtreme II BCM5706S", 0),
  2178. PCI_ROM(0x14e4, 0x16ac, "bnx2-5708S", "Broadcom NetXtreme II BCM5708S", 0),
  2179. };
  2180. PCI_DRIVER ( bnx2_driver, bnx2_nics, PCI_NO_CLASS );
  2181. DRIVER ( "BNX2", nic_driver, pci_driver, bnx2_driver, bnx2_probe, bnx2_disable );
  2182. /*
  2183. static struct pci_driver bnx2_driver __pci_driver = {
  2184. .type = NIC_DRIVER,
  2185. .name = "BNX2",
  2186. .probe = bnx2_probe,
  2187. .ids = bnx2_nics,
  2188. .id_count = sizeof(bnx2_nics)/sizeof(bnx2_nics[0]),
  2189. .class = 0,
  2190. };
  2191. */