Du kan inte välja fler än 25 ämnen Ämnen måste starta med en bokstav eller siffra, kan innehålla bindestreck ('-') och vara max 35 tecken långa.

hermon.c 80KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728
  1. /*
  2. * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
  3. * Copyright (C) 2008 Mellanox Technologies Ltd.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License as
  7. * published by the Free Software Foundation; either version 2 of the
  8. * License, or any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. */
  19. FILE_LICENCE ( GPL2_OR_LATER );
  20. #include <stdint.h>
  21. #include <stdlib.h>
  22. #include <stdio.h>
  23. #include <string.h>
  24. #include <strings.h>
  25. #include <unistd.h>
  26. #include <errno.h>
  27. #include <byteswap.h>
  28. #include <gpxe/io.h>
  29. #include <gpxe/pci.h>
  30. #include <gpxe/malloc.h>
  31. #include <gpxe/umalloc.h>
  32. #include <gpxe/iobuf.h>
  33. #include <gpxe/netdevice.h>
  34. #include <gpxe/infiniband.h>
  35. #include <gpxe/ib_smc.h>
  36. #include "hermon.h"
  37. /**
  38. * @file
  39. *
  40. * Mellanox Hermon Infiniband HCA
  41. *
  42. */
  43. /***************************************************************************
  44. *
  45. * Queue number allocation
  46. *
  47. ***************************************************************************
  48. */
  49. /**
  50. * Allocate offsets within usage bitmask
  51. *
  52. * @v bits Usage bitmask
  53. * @v bits_len Length of usage bitmask
  54. * @v num_bits Number of contiguous bits to allocate within bitmask
  55. * @ret bit First free bit within bitmask, or negative error
  56. */
  57. static int hermon_bitmask_alloc ( hermon_bitmask_t *bits,
  58. unsigned int bits_len,
  59. unsigned int num_bits ) {
  60. unsigned int bit = 0;
  61. hermon_bitmask_t mask = 1;
  62. unsigned int found = 0;
  63. /* Search bits for num_bits contiguous free bits */
  64. while ( bit < bits_len ) {
  65. if ( ( mask & *bits ) == 0 ) {
  66. if ( ++found == num_bits )
  67. goto found;
  68. } else {
  69. found = 0;
  70. }
  71. bit++;
  72. mask = ( mask << 1 ) | ( mask >> ( 8 * sizeof ( mask ) - 1 ) );
  73. if ( mask == 1 )
  74. bits++;
  75. }
  76. return -ENFILE;
  77. found:
  78. /* Mark bits as in-use */
  79. do {
  80. *bits |= mask;
  81. if ( mask == 1 )
  82. bits--;
  83. mask = ( mask >> 1 ) | ( mask << ( 8 * sizeof ( mask ) - 1 ) );
  84. } while ( --found );
  85. return ( bit - num_bits + 1 );
  86. }
  87. /**
  88. * Free offsets within usage bitmask
  89. *
  90. * @v bits Usage bitmask
  91. * @v bit Starting bit within bitmask
  92. * @v num_bits Number of contiguous bits to free within bitmask
  93. */
  94. static void hermon_bitmask_free ( hermon_bitmask_t *bits,
  95. int bit, unsigned int num_bits ) {
  96. hermon_bitmask_t mask;
  97. for ( ; num_bits ; bit++, num_bits-- ) {
  98. mask = ( 1 << ( bit % ( 8 * sizeof ( mask ) ) ) );
  99. bits[ ( bit / ( 8 * sizeof ( mask ) ) ) ] &= ~mask;
  100. }
  101. }
  102. /***************************************************************************
  103. *
  104. * HCA commands
  105. *
  106. ***************************************************************************
  107. */
  108. /**
  109. * Wait for Hermon command completion
  110. *
  111. * @v hermon Hermon device
  112. * @v hcr HCA command registers
  113. * @ret rc Return status code
  114. */
  115. static int hermon_cmd_wait ( struct hermon *hermon,
  116. struct hermonprm_hca_command_register *hcr ) {
  117. unsigned int wait;
  118. for ( wait = HERMON_HCR_MAX_WAIT_MS ; wait ; wait-- ) {
  119. hcr->u.dwords[6] =
  120. readl ( hermon->config + HERMON_HCR_REG ( 6 ) );
  121. if ( ( MLX_GET ( hcr, go ) == 0 ) &&
  122. ( MLX_GET ( hcr, t ) == hermon->toggle ) )
  123. return 0;
  124. mdelay ( 1 );
  125. }
  126. return -EBUSY;
  127. }
  128. /**
  129. * Issue HCA command
  130. *
  131. * @v hermon Hermon device
  132. * @v command Command opcode, flags and input/output lengths
  133. * @v op_mod Opcode modifier (0 if no modifier applicable)
  134. * @v in Input parameters
  135. * @v in_mod Input modifier (0 if no modifier applicable)
  136. * @v out Output parameters
  137. * @ret rc Return status code
  138. */
  139. static int hermon_cmd ( struct hermon *hermon, unsigned long command,
  140. unsigned int op_mod, const void *in,
  141. unsigned int in_mod, void *out ) {
  142. struct hermonprm_hca_command_register hcr;
  143. unsigned int opcode = HERMON_HCR_OPCODE ( command );
  144. size_t in_len = HERMON_HCR_IN_LEN ( command );
  145. size_t out_len = HERMON_HCR_OUT_LEN ( command );
  146. void *in_buffer;
  147. void *out_buffer;
  148. unsigned int status;
  149. unsigned int i;
  150. int rc;
  151. assert ( in_len <= HERMON_MBOX_SIZE );
  152. assert ( out_len <= HERMON_MBOX_SIZE );
  153. DBGC2 ( hermon, "Hermon %p command %02x in %zx%s out %zx%s\n",
  154. hermon, opcode, in_len,
  155. ( ( command & HERMON_HCR_IN_MBOX ) ? "(mbox)" : "" ), out_len,
  156. ( ( command & HERMON_HCR_OUT_MBOX ) ? "(mbox)" : "" ) );
  157. /* Check that HCR is free */
  158. if ( ( rc = hermon_cmd_wait ( hermon, &hcr ) ) != 0 ) {
  159. DBGC ( hermon, "Hermon %p command interface locked\n",
  160. hermon );
  161. return rc;
  162. }
  163. /* Flip HCR toggle */
  164. hermon->toggle = ( 1 - hermon->toggle );
  165. /* Prepare HCR */
  166. memset ( &hcr, 0, sizeof ( hcr ) );
  167. in_buffer = &hcr.u.dwords[0];
  168. if ( in_len && ( command & HERMON_HCR_IN_MBOX ) ) {
  169. in_buffer = hermon->mailbox_in;
  170. MLX_FILL_1 ( &hcr, 1, in_param_l, virt_to_bus ( in_buffer ) );
  171. }
  172. memcpy ( in_buffer, in, in_len );
  173. MLX_FILL_1 ( &hcr, 2, input_modifier, in_mod );
  174. out_buffer = &hcr.u.dwords[3];
  175. if ( out_len && ( command & HERMON_HCR_OUT_MBOX ) ) {
  176. out_buffer = hermon->mailbox_out;
  177. MLX_FILL_1 ( &hcr, 4, out_param_l,
  178. virt_to_bus ( out_buffer ) );
  179. }
  180. MLX_FILL_4 ( &hcr, 6,
  181. opcode, opcode,
  182. opcode_modifier, op_mod,
  183. go, 1,
  184. t, hermon->toggle );
  185. DBGC ( hermon, "Hermon %p issuing command %04x\n",
  186. hermon, opcode );
  187. DBGC2_HDA ( hermon, virt_to_phys ( hermon->config + HERMON_HCR_BASE ),
  188. &hcr, sizeof ( hcr ) );
  189. if ( in_len && ( command & HERMON_HCR_IN_MBOX ) ) {
  190. DBGC2 ( hermon, "Input mailbox:\n" );
  191. DBGC2_HDA ( hermon, virt_to_phys ( in_buffer ), in_buffer,
  192. ( ( in_len < 512 ) ? in_len : 512 ) );
  193. }
  194. /* Issue command */
  195. for ( i = 0 ; i < ( sizeof ( hcr ) / sizeof ( hcr.u.dwords[0] ) ) ;
  196. i++ ) {
  197. writel ( hcr.u.dwords[i],
  198. hermon->config + HERMON_HCR_REG ( i ) );
  199. barrier();
  200. }
  201. /* Wait for command completion */
  202. if ( ( rc = hermon_cmd_wait ( hermon, &hcr ) ) != 0 ) {
  203. DBGC ( hermon, "Hermon %p timed out waiting for command:\n",
  204. hermon );
  205. DBGC_HDA ( hermon,
  206. virt_to_phys ( hermon->config + HERMON_HCR_BASE ),
  207. &hcr, sizeof ( hcr ) );
  208. return rc;
  209. }
  210. /* Check command status */
  211. status = MLX_GET ( &hcr, status );
  212. if ( status != 0 ) {
  213. DBGC ( hermon, "Hermon %p command failed with status %02x:\n",
  214. hermon, status );
  215. DBGC_HDA ( hermon,
  216. virt_to_phys ( hermon->config + HERMON_HCR_BASE ),
  217. &hcr, sizeof ( hcr ) );
  218. return -EIO;
  219. }
  220. /* Read output parameters, if any */
  221. hcr.u.dwords[3] = readl ( hermon->config + HERMON_HCR_REG ( 3 ) );
  222. hcr.u.dwords[4] = readl ( hermon->config + HERMON_HCR_REG ( 4 ) );
  223. memcpy ( out, out_buffer, out_len );
  224. if ( out_len ) {
  225. DBGC2 ( hermon, "Output%s:\n",
  226. ( command & HERMON_HCR_OUT_MBOX ) ? " mailbox" : "" );
  227. DBGC2_HDA ( hermon, virt_to_phys ( out_buffer ), out_buffer,
  228. ( ( out_len < 512 ) ? out_len : 512 ) );
  229. }
  230. return 0;
  231. }
  232. static inline int
  233. hermon_cmd_query_dev_cap ( struct hermon *hermon,
  234. struct hermonprm_query_dev_cap *dev_cap ) {
  235. return hermon_cmd ( hermon,
  236. HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_DEV_CAP,
  237. 1, sizeof ( *dev_cap ) ),
  238. 0, NULL, 0, dev_cap );
  239. }
  240. static inline int
  241. hermon_cmd_query_fw ( struct hermon *hermon, struct hermonprm_query_fw *fw ) {
  242. return hermon_cmd ( hermon,
  243. HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_FW,
  244. 1, sizeof ( *fw ) ),
  245. 0, NULL, 0, fw );
  246. }
  247. static inline int
  248. hermon_cmd_init_hca ( struct hermon *hermon,
  249. const struct hermonprm_init_hca *init_hca ) {
  250. return hermon_cmd ( hermon,
  251. HERMON_HCR_IN_CMD ( HERMON_HCR_INIT_HCA,
  252. 1, sizeof ( *init_hca ) ),
  253. 0, init_hca, 0, NULL );
  254. }
  255. static inline int
  256. hermon_cmd_close_hca ( struct hermon *hermon ) {
  257. return hermon_cmd ( hermon,
  258. HERMON_HCR_VOID_CMD ( HERMON_HCR_CLOSE_HCA ),
  259. 0, NULL, 0, NULL );
  260. }
  261. static inline int
  262. hermon_cmd_init_port ( struct hermon *hermon, unsigned int port,
  263. const struct hermonprm_init_port *init_port ) {
  264. return hermon_cmd ( hermon,
  265. HERMON_HCR_IN_CMD ( HERMON_HCR_INIT_PORT,
  266. 1, sizeof ( *init_port ) ),
  267. 0, init_port, port, NULL );
  268. }
  269. static inline int
  270. hermon_cmd_close_port ( struct hermon *hermon, unsigned int port ) {
  271. return hermon_cmd ( hermon,
  272. HERMON_HCR_VOID_CMD ( HERMON_HCR_CLOSE_PORT ),
  273. 0, NULL, port, NULL );
  274. }
  275. static inline int
  276. hermon_cmd_sw2hw_mpt ( struct hermon *hermon, unsigned int index,
  277. const struct hermonprm_mpt *mpt ) {
  278. return hermon_cmd ( hermon,
  279. HERMON_HCR_IN_CMD ( HERMON_HCR_SW2HW_MPT,
  280. 1, sizeof ( *mpt ) ),
  281. 0, mpt, index, NULL );
  282. }
  283. static inline int
  284. hermon_cmd_write_mtt ( struct hermon *hermon,
  285. const struct hermonprm_write_mtt *write_mtt ) {
  286. return hermon_cmd ( hermon,
  287. HERMON_HCR_IN_CMD ( HERMON_HCR_WRITE_MTT,
  288. 1, sizeof ( *write_mtt ) ),
  289. 0, write_mtt, 1, NULL );
  290. }
  291. static inline int
  292. hermon_cmd_map_eq ( struct hermon *hermon, unsigned long index_map,
  293. const struct hermonprm_event_mask *mask ) {
  294. return hermon_cmd ( hermon,
  295. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_EQ,
  296. 0, sizeof ( *mask ) ),
  297. 0, mask, index_map, NULL );
  298. }
  299. static inline int
  300. hermon_cmd_sw2hw_eq ( struct hermon *hermon, unsigned int index,
  301. const struct hermonprm_eqc *eqctx ) {
  302. return hermon_cmd ( hermon,
  303. HERMON_HCR_IN_CMD ( HERMON_HCR_SW2HW_EQ,
  304. 1, sizeof ( *eqctx ) ),
  305. 0, eqctx, index, NULL );
  306. }
  307. static inline int
  308. hermon_cmd_hw2sw_eq ( struct hermon *hermon, unsigned int index,
  309. struct hermonprm_eqc *eqctx ) {
  310. return hermon_cmd ( hermon,
  311. HERMON_HCR_OUT_CMD ( HERMON_HCR_HW2SW_EQ,
  312. 1, sizeof ( *eqctx ) ),
  313. 1, NULL, index, eqctx );
  314. }
  315. static inline int
  316. hermon_cmd_query_eq ( struct hermon *hermon, unsigned int index,
  317. struct hermonprm_eqc *eqctx ) {
  318. return hermon_cmd ( hermon,
  319. HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_EQ,
  320. 1, sizeof ( *eqctx ) ),
  321. 0, NULL, index, eqctx );
  322. }
  323. static inline int
  324. hermon_cmd_sw2hw_cq ( struct hermon *hermon, unsigned long cqn,
  325. const struct hermonprm_completion_queue_context *cqctx ){
  326. return hermon_cmd ( hermon,
  327. HERMON_HCR_IN_CMD ( HERMON_HCR_SW2HW_CQ,
  328. 1, sizeof ( *cqctx ) ),
  329. 0, cqctx, cqn, NULL );
  330. }
  331. static inline int
  332. hermon_cmd_hw2sw_cq ( struct hermon *hermon, unsigned long cqn,
  333. struct hermonprm_completion_queue_context *cqctx) {
  334. return hermon_cmd ( hermon,
  335. HERMON_HCR_OUT_CMD ( HERMON_HCR_HW2SW_CQ,
  336. 1, sizeof ( *cqctx ) ),
  337. 0, NULL, cqn, cqctx );
  338. }
  339. static inline int
  340. hermon_cmd_rst2init_qp ( struct hermon *hermon, unsigned long qpn,
  341. const struct hermonprm_qp_ee_state_transitions *ctx ){
  342. return hermon_cmd ( hermon,
  343. HERMON_HCR_IN_CMD ( HERMON_HCR_RST2INIT_QP,
  344. 1, sizeof ( *ctx ) ),
  345. 0, ctx, qpn, NULL );
  346. }
  347. static inline int
  348. hermon_cmd_init2rtr_qp ( struct hermon *hermon, unsigned long qpn,
  349. const struct hermonprm_qp_ee_state_transitions *ctx ){
  350. return hermon_cmd ( hermon,
  351. HERMON_HCR_IN_CMD ( HERMON_HCR_INIT2RTR_QP,
  352. 1, sizeof ( *ctx ) ),
  353. 0, ctx, qpn, NULL );
  354. }
  355. static inline int
  356. hermon_cmd_rtr2rts_qp ( struct hermon *hermon, unsigned long qpn,
  357. const struct hermonprm_qp_ee_state_transitions *ctx ) {
  358. return hermon_cmd ( hermon,
  359. HERMON_HCR_IN_CMD ( HERMON_HCR_RTR2RTS_QP,
  360. 1, sizeof ( *ctx ) ),
  361. 0, ctx, qpn, NULL );
  362. }
  363. static inline int
  364. hermon_cmd_rts2rts_qp ( struct hermon *hermon, unsigned long qpn,
  365. const struct hermonprm_qp_ee_state_transitions *ctx ) {
  366. return hermon_cmd ( hermon,
  367. HERMON_HCR_IN_CMD ( HERMON_HCR_RTS2RTS_QP,
  368. 1, sizeof ( *ctx ) ),
  369. 0, ctx, qpn, NULL );
  370. }
  371. static inline int
  372. hermon_cmd_2rst_qp ( struct hermon *hermon, unsigned long qpn ) {
  373. return hermon_cmd ( hermon,
  374. HERMON_HCR_VOID_CMD ( HERMON_HCR_2RST_QP ),
  375. 0x03, NULL, qpn, NULL );
  376. }
  377. static inline int
  378. hermon_cmd_query_qp ( struct hermon *hermon, unsigned long qpn,
  379. struct hermonprm_qp_ee_state_transitions *ctx ) {
  380. return hermon_cmd ( hermon,
  381. HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_QP,
  382. 1, sizeof ( *ctx ) ),
  383. 0, NULL, qpn, ctx );
  384. }
  385. static inline int
  386. hermon_cmd_conf_special_qp ( struct hermon *hermon, unsigned int internal_qps,
  387. unsigned long base_qpn ) {
  388. return hermon_cmd ( hermon,
  389. HERMON_HCR_VOID_CMD ( HERMON_HCR_CONF_SPECIAL_QP ),
  390. internal_qps, NULL, base_qpn, NULL );
  391. }
  392. static inline int
  393. hermon_cmd_mad_ifc ( struct hermon *hermon, unsigned int port,
  394. union hermonprm_mad *mad ) {
  395. return hermon_cmd ( hermon,
  396. HERMON_HCR_INOUT_CMD ( HERMON_HCR_MAD_IFC,
  397. 1, sizeof ( *mad ),
  398. 1, sizeof ( *mad ) ),
  399. 0x03, mad, port, mad );
  400. }
  401. static inline int
  402. hermon_cmd_read_mcg ( struct hermon *hermon, unsigned int index,
  403. struct hermonprm_mcg_entry *mcg ) {
  404. return hermon_cmd ( hermon,
  405. HERMON_HCR_OUT_CMD ( HERMON_HCR_READ_MCG,
  406. 1, sizeof ( *mcg ) ),
  407. 0, NULL, index, mcg );
  408. }
  409. static inline int
  410. hermon_cmd_write_mcg ( struct hermon *hermon, unsigned int index,
  411. const struct hermonprm_mcg_entry *mcg ) {
  412. return hermon_cmd ( hermon,
  413. HERMON_HCR_IN_CMD ( HERMON_HCR_WRITE_MCG,
  414. 1, sizeof ( *mcg ) ),
  415. 0, mcg, index, NULL );
  416. }
  417. static inline int
  418. hermon_cmd_mgid_hash ( struct hermon *hermon, const struct ib_gid *gid,
  419. struct hermonprm_mgm_hash *hash ) {
  420. return hermon_cmd ( hermon,
  421. HERMON_HCR_INOUT_CMD ( HERMON_HCR_MGID_HASH,
  422. 1, sizeof ( *gid ),
  423. 0, sizeof ( *hash ) ),
  424. 0, gid, 0, hash );
  425. }
  426. static inline int
  427. hermon_cmd_run_fw ( struct hermon *hermon ) {
  428. return hermon_cmd ( hermon,
  429. HERMON_HCR_VOID_CMD ( HERMON_HCR_RUN_FW ),
  430. 0, NULL, 0, NULL );
  431. }
  432. static inline int
  433. hermon_cmd_unmap_icm ( struct hermon *hermon, unsigned int page_count,
  434. const struct hermonprm_scalar_parameter *offset ) {
  435. return hermon_cmd ( hermon,
  436. HERMON_HCR_IN_CMD ( HERMON_HCR_UNMAP_ICM,
  437. 0, sizeof ( *offset ) ),
  438. 0, offset, page_count, NULL );
  439. }
  440. static inline int
  441. hermon_cmd_map_icm ( struct hermon *hermon,
  442. const struct hermonprm_virtual_physical_mapping *map ) {
  443. return hermon_cmd ( hermon,
  444. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_ICM,
  445. 1, sizeof ( *map ) ),
  446. 0, map, 1, NULL );
  447. }
  448. static inline int
  449. hermon_cmd_unmap_icm_aux ( struct hermon *hermon ) {
  450. return hermon_cmd ( hermon,
  451. HERMON_HCR_VOID_CMD ( HERMON_HCR_UNMAP_ICM_AUX ),
  452. 0, NULL, 0, NULL );
  453. }
  454. static inline int
  455. hermon_cmd_map_icm_aux ( struct hermon *hermon,
  456. const struct hermonprm_virtual_physical_mapping *map ) {
  457. return hermon_cmd ( hermon,
  458. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_ICM_AUX,
  459. 1, sizeof ( *map ) ),
  460. 0, map, 1, NULL );
  461. }
  462. static inline int
  463. hermon_cmd_set_icm_size ( struct hermon *hermon,
  464. const struct hermonprm_scalar_parameter *icm_size,
  465. struct hermonprm_scalar_parameter *icm_aux_size ) {
  466. return hermon_cmd ( hermon,
  467. HERMON_HCR_INOUT_CMD ( HERMON_HCR_SET_ICM_SIZE,
  468. 0, sizeof ( *icm_size ),
  469. 0, sizeof (*icm_aux_size) ),
  470. 0, icm_size, 0, icm_aux_size );
  471. }
  472. static inline int
  473. hermon_cmd_unmap_fa ( struct hermon *hermon ) {
  474. return hermon_cmd ( hermon,
  475. HERMON_HCR_VOID_CMD ( HERMON_HCR_UNMAP_FA ),
  476. 0, NULL, 0, NULL );
  477. }
  478. static inline int
  479. hermon_cmd_map_fa ( struct hermon *hermon,
  480. const struct hermonprm_virtual_physical_mapping *map ) {
  481. return hermon_cmd ( hermon,
  482. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_FA,
  483. 1, sizeof ( *map ) ),
  484. 0, map, 1, NULL );
  485. }
  486. static inline int
  487. hermon_cmd_sense_port ( struct hermon *hermon, unsigned int port,
  488. struct hermonprm_sense_port *port_type ) {
  489. return hermon_cmd ( hermon,
  490. HERMON_HCR_OUT_CMD ( HERMON_HCR_SENSE_PORT,
  491. 1, sizeof ( *port_type ) ),
  492. 0, NULL, port, port_type );
  493. }
  494. /***************************************************************************
  495. *
  496. * Memory translation table operations
  497. *
  498. ***************************************************************************
  499. */
  500. /**
  501. * Allocate MTT entries
  502. *
  503. * @v hermon Hermon device
  504. * @v memory Memory to map into MTT
  505. * @v len Length of memory to map
  506. * @v mtt MTT descriptor to fill in
  507. * @ret rc Return status code
  508. */
  509. static int hermon_alloc_mtt ( struct hermon *hermon,
  510. const void *memory, size_t len,
  511. struct hermon_mtt *mtt ) {
  512. struct hermonprm_write_mtt write_mtt;
  513. physaddr_t start;
  514. unsigned int page_offset;
  515. unsigned int num_pages;
  516. int mtt_offset;
  517. unsigned int mtt_base_addr;
  518. unsigned int i;
  519. int rc;
  520. /* Find available MTT entries */
  521. start = virt_to_phys ( memory );
  522. page_offset = ( start & ( HERMON_PAGE_SIZE - 1 ) );
  523. start -= page_offset;
  524. len += page_offset;
  525. num_pages = ( ( len + HERMON_PAGE_SIZE - 1 ) / HERMON_PAGE_SIZE );
  526. mtt_offset = hermon_bitmask_alloc ( hermon->mtt_inuse, HERMON_MAX_MTTS,
  527. num_pages );
  528. if ( mtt_offset < 0 ) {
  529. DBGC ( hermon, "Hermon %p could not allocate %d MTT entries\n",
  530. hermon, num_pages );
  531. rc = mtt_offset;
  532. goto err_mtt_offset;
  533. }
  534. mtt_base_addr = ( ( hermon->cap.reserved_mtts + mtt_offset ) *
  535. hermon->cap.mtt_entry_size );
  536. /* Fill in MTT structure */
  537. mtt->mtt_offset = mtt_offset;
  538. mtt->num_pages = num_pages;
  539. mtt->mtt_base_addr = mtt_base_addr;
  540. mtt->page_offset = page_offset;
  541. /* Construct and issue WRITE_MTT commands */
  542. for ( i = 0 ; i < num_pages ; i++ ) {
  543. memset ( &write_mtt, 0, sizeof ( write_mtt ) );
  544. MLX_FILL_1 ( &write_mtt.mtt_base_addr, 1,
  545. value, mtt_base_addr );
  546. MLX_FILL_2 ( &write_mtt.mtt, 1,
  547. p, 1,
  548. ptag_l, ( start >> 3 ) );
  549. if ( ( rc = hermon_cmd_write_mtt ( hermon,
  550. &write_mtt ) ) != 0 ) {
  551. DBGC ( hermon, "Hermon %p could not write MTT at %x\n",
  552. hermon, mtt_base_addr );
  553. goto err_write_mtt;
  554. }
  555. start += HERMON_PAGE_SIZE;
  556. mtt_base_addr += hermon->cap.mtt_entry_size;
  557. }
  558. return 0;
  559. err_write_mtt:
  560. hermon_bitmask_free ( hermon->mtt_inuse, mtt_offset, num_pages );
  561. err_mtt_offset:
  562. return rc;
  563. }
  564. /**
  565. * Free MTT entries
  566. *
  567. * @v hermon Hermon device
  568. * @v mtt MTT descriptor
  569. */
  570. static void hermon_free_mtt ( struct hermon *hermon,
  571. struct hermon_mtt *mtt ) {
  572. hermon_bitmask_free ( hermon->mtt_inuse, mtt->mtt_offset,
  573. mtt->num_pages );
  574. }
  575. /***************************************************************************
  576. *
  577. * MAD operations
  578. *
  579. ***************************************************************************
  580. */
  581. /**
  582. * Issue management datagram
  583. *
  584. * @v ibdev Infiniband device
  585. * @v mad Management datagram
  586. * @ret rc Return status code
  587. */
  588. static int hermon_mad ( struct ib_device *ibdev, union ib_mad *mad ) {
  589. struct hermon *hermon = ib_get_drvdata ( ibdev );
  590. union hermonprm_mad mad_ifc;
  591. int rc;
  592. linker_assert ( sizeof ( *mad ) == sizeof ( mad_ifc.mad ),
  593. mad_size_mismatch );
  594. /* Copy in request packet */
  595. memcpy ( &mad_ifc.mad, mad, sizeof ( mad_ifc.mad ) );
  596. /* Issue MAD */
  597. if ( ( rc = hermon_cmd_mad_ifc ( hermon, ibdev->port,
  598. &mad_ifc ) ) != 0 ) {
  599. DBGC ( hermon, "Hermon %p could not issue MAD IFC: %s\n",
  600. hermon, strerror ( rc ) );
  601. return rc;
  602. }
  603. /* Copy out reply packet */
  604. memcpy ( mad, &mad_ifc.mad, sizeof ( *mad ) );
  605. if ( mad->hdr.status != 0 ) {
  606. DBGC ( hermon, "Hermon %p MAD IFC status %04x\n",
  607. hermon, ntohs ( mad->hdr.status ) );
  608. return -EIO;
  609. }
  610. return 0;
  611. }
  612. /***************************************************************************
  613. *
  614. * Completion queue operations
  615. *
  616. ***************************************************************************
  617. */
  618. /**
  619. * Create completion queue
  620. *
  621. * @v ibdev Infiniband device
  622. * @v cq Completion queue
  623. * @ret rc Return status code
  624. */
  625. static int hermon_create_cq ( struct ib_device *ibdev,
  626. struct ib_completion_queue *cq ) {
  627. struct hermon *hermon = ib_get_drvdata ( ibdev );
  628. struct hermon_completion_queue *hermon_cq;
  629. struct hermonprm_completion_queue_context cqctx;
  630. int cqn_offset;
  631. unsigned int i;
  632. int rc;
  633. /* Find a free completion queue number */
  634. cqn_offset = hermon_bitmask_alloc ( hermon->cq_inuse,
  635. HERMON_MAX_CQS, 1 );
  636. if ( cqn_offset < 0 ) {
  637. DBGC ( hermon, "Hermon %p out of completion queues\n",
  638. hermon );
  639. rc = cqn_offset;
  640. goto err_cqn_offset;
  641. }
  642. cq->cqn = ( hermon->cap.reserved_cqs + cqn_offset );
  643. /* Allocate control structures */
  644. hermon_cq = zalloc ( sizeof ( *hermon_cq ) );
  645. if ( ! hermon_cq ) {
  646. rc = -ENOMEM;
  647. goto err_hermon_cq;
  648. }
  649. /* Allocate completion queue itself */
  650. hermon_cq->cqe_size = ( cq->num_cqes * sizeof ( hermon_cq->cqe[0] ) );
  651. hermon_cq->cqe = malloc_dma ( hermon_cq->cqe_size,
  652. sizeof ( hermon_cq->cqe[0] ) );
  653. if ( ! hermon_cq->cqe ) {
  654. rc = -ENOMEM;
  655. goto err_cqe;
  656. }
  657. memset ( hermon_cq->cqe, 0, hermon_cq->cqe_size );
  658. for ( i = 0 ; i < cq->num_cqes ; i++ ) {
  659. MLX_FILL_1 ( &hermon_cq->cqe[i].normal, 7, owner, 1 );
  660. }
  661. barrier();
  662. /* Allocate MTT entries */
  663. if ( ( rc = hermon_alloc_mtt ( hermon, hermon_cq->cqe,
  664. hermon_cq->cqe_size,
  665. &hermon_cq->mtt ) ) != 0 )
  666. goto err_alloc_mtt;
  667. /* Hand queue over to hardware */
  668. memset ( &cqctx, 0, sizeof ( cqctx ) );
  669. MLX_FILL_1 ( &cqctx, 0, st, 0xa /* "Event fired" */ );
  670. MLX_FILL_1 ( &cqctx, 2,
  671. page_offset, ( hermon_cq->mtt.page_offset >> 5 ) );
  672. MLX_FILL_2 ( &cqctx, 3,
  673. usr_page, HERMON_UAR_NON_EQ_PAGE,
  674. log_cq_size, fls ( cq->num_cqes - 1 ) );
  675. MLX_FILL_1 ( &cqctx, 7, mtt_base_addr_l,
  676. ( hermon_cq->mtt.mtt_base_addr >> 3 ) );
  677. MLX_FILL_1 ( &cqctx, 15, db_record_addr_l,
  678. ( virt_to_phys ( &hermon_cq->doorbell ) >> 3 ) );
  679. if ( ( rc = hermon_cmd_sw2hw_cq ( hermon, cq->cqn, &cqctx ) ) != 0 ) {
  680. DBGC ( hermon, "Hermon %p SW2HW_CQ failed: %s\n",
  681. hermon, strerror ( rc ) );
  682. goto err_sw2hw_cq;
  683. }
  684. DBGC ( hermon, "Hermon %p CQN %#lx ring at [%p,%p)\n",
  685. hermon, cq->cqn, hermon_cq->cqe,
  686. ( ( ( void * ) hermon_cq->cqe ) + hermon_cq->cqe_size ) );
  687. ib_cq_set_drvdata ( cq, hermon_cq );
  688. return 0;
  689. err_sw2hw_cq:
  690. hermon_free_mtt ( hermon, &hermon_cq->mtt );
  691. err_alloc_mtt:
  692. free_dma ( hermon_cq->cqe, hermon_cq->cqe_size );
  693. err_cqe:
  694. free ( hermon_cq );
  695. err_hermon_cq:
  696. hermon_bitmask_free ( hermon->cq_inuse, cqn_offset, 1 );
  697. err_cqn_offset:
  698. return rc;
  699. }
  700. /**
  701. * Destroy completion queue
  702. *
  703. * @v ibdev Infiniband device
  704. * @v cq Completion queue
  705. */
  706. static void hermon_destroy_cq ( struct ib_device *ibdev,
  707. struct ib_completion_queue *cq ) {
  708. struct hermon *hermon = ib_get_drvdata ( ibdev );
  709. struct hermon_completion_queue *hermon_cq = ib_cq_get_drvdata ( cq );
  710. struct hermonprm_completion_queue_context cqctx;
  711. int cqn_offset;
  712. int rc;
  713. /* Take ownership back from hardware */
  714. if ( ( rc = hermon_cmd_hw2sw_cq ( hermon, cq->cqn, &cqctx ) ) != 0 ) {
  715. DBGC ( hermon, "Hermon %p FATAL HW2SW_CQ failed on CQN %#lx: "
  716. "%s\n", hermon, cq->cqn, strerror ( rc ) );
  717. /* Leak memory and return; at least we avoid corruption */
  718. return;
  719. }
  720. /* Free MTT entries */
  721. hermon_free_mtt ( hermon, &hermon_cq->mtt );
  722. /* Free memory */
  723. free_dma ( hermon_cq->cqe, hermon_cq->cqe_size );
  724. free ( hermon_cq );
  725. /* Mark queue number as free */
  726. cqn_offset = ( cq->cqn - hermon->cap.reserved_cqs );
  727. hermon_bitmask_free ( hermon->cq_inuse, cqn_offset, 1 );
  728. ib_cq_set_drvdata ( cq, NULL );
  729. }
  730. /***************************************************************************
  731. *
  732. * Queue pair operations
  733. *
  734. ***************************************************************************
  735. */
  736. /**
  737. * Assign queue pair number
  738. *
  739. * @v ibdev Infiniband device
  740. * @v qp Queue pair
  741. * @ret rc Return status code
  742. */
  743. static int hermon_alloc_qpn ( struct ib_device *ibdev,
  744. struct ib_queue_pair *qp ) {
  745. struct hermon *hermon = ib_get_drvdata ( ibdev );
  746. unsigned int port_offset;
  747. int qpn_offset;
  748. /* Calculate queue pair number */
  749. port_offset = ( ibdev->port - HERMON_PORT_BASE );
  750. switch ( qp->type ) {
  751. case IB_QPT_SMI:
  752. qp->qpn = ( hermon->special_qpn_base + port_offset );
  753. return 0;
  754. case IB_QPT_GSI:
  755. qp->qpn = ( hermon->special_qpn_base + 2 + port_offset );
  756. return 0;
  757. case IB_QPT_UD:
  758. case IB_QPT_RC:
  759. /* Find a free queue pair number */
  760. qpn_offset = hermon_bitmask_alloc ( hermon->qp_inuse,
  761. HERMON_MAX_QPS, 1 );
  762. if ( qpn_offset < 0 ) {
  763. DBGC ( hermon, "Hermon %p out of queue pairs\n",
  764. hermon );
  765. return qpn_offset;
  766. }
  767. qp->qpn = ( hermon->qpn_base + qpn_offset );
  768. return 0;
  769. default:
  770. DBGC ( hermon, "Hermon %p unsupported QP type %d\n",
  771. hermon, qp->type );
  772. return -ENOTSUP;
  773. }
  774. }
  775. /**
  776. * Free queue pair number
  777. *
  778. * @v ibdev Infiniband device
  779. * @v qp Queue pair
  780. */
  781. static void hermon_free_qpn ( struct ib_device *ibdev,
  782. struct ib_queue_pair *qp ) {
  783. struct hermon *hermon = ib_get_drvdata ( ibdev );
  784. int qpn_offset;
  785. qpn_offset = ( qp->qpn - hermon->qpn_base );
  786. if ( qpn_offset >= 0 )
  787. hermon_bitmask_free ( hermon->qp_inuse, qpn_offset, 1 );
  788. }
  789. /**
  790. * Calculate transmission rate
  791. *
  792. * @v av Address vector
  793. * @ret hermon_rate Hermon rate
  794. */
  795. static unsigned int hermon_rate ( struct ib_address_vector *av ) {
  796. return ( ( ( av->rate >= IB_RATE_2_5 ) && ( av->rate <= IB_RATE_120 ) )
  797. ? ( av->rate + 5 ) : 0 );
  798. }
  799. /**
  800. * Calculate schedule queue
  801. *
  802. * @v ibdev Infiniband device
  803. * @v qp Queue pair
  804. * @ret sched_queue Schedule queue
  805. */
  806. static unsigned int hermon_sched_queue ( struct ib_device *ibdev,
  807. struct ib_queue_pair *qp ) {
  808. return ( ( ( qp->type == IB_QPT_SMI ) ?
  809. HERMON_SCHED_QP0 : HERMON_SCHED_DEFAULT ) |
  810. ( ( ibdev->port - 1 ) << 6 ) );
  811. }
  812. /** Queue pair transport service type map */
  813. static uint8_t hermon_qp_st[] = {
  814. [IB_QPT_SMI] = HERMON_ST_MLX,
  815. [IB_QPT_GSI] = HERMON_ST_MLX,
  816. [IB_QPT_UD] = HERMON_ST_UD,
  817. [IB_QPT_RC] = HERMON_ST_RC,
  818. };
  819. /**
  820. * Dump queue pair context (for debugging only)
  821. *
  822. * @v hermon Hermon device
  823. * @v qp Queue pair
  824. * @ret rc Return status code
  825. */
  826. static inline int hermon_dump_qpctx ( struct hermon *hermon,
  827. struct ib_queue_pair *qp ) {
  828. struct hermonprm_qp_ee_state_transitions qpctx;
  829. int rc;
  830. memset ( &qpctx, 0, sizeof ( qpctx ) );
  831. if ( ( rc = hermon_cmd_query_qp ( hermon, qp->qpn, &qpctx ) ) != 0 ) {
  832. DBGC ( hermon, "Hermon %p QUERY_QP failed: %s\n",
  833. hermon, strerror ( rc ) );
  834. return rc;
  835. }
  836. DBGC ( hermon, "Hermon %p QPN %lx context:\n", hermon, qp->qpn );
  837. DBGC_HDA ( hermon, 0, &qpctx.u.dwords[2],
  838. ( sizeof ( qpctx ) - 8 ) );
  839. return 0;
  840. }
  841. /**
  842. * Create queue pair
  843. *
  844. * @v ibdev Infiniband device
  845. * @v qp Queue pair
  846. * @ret rc Return status code
  847. */
  848. static int hermon_create_qp ( struct ib_device *ibdev,
  849. struct ib_queue_pair *qp ) {
  850. struct hermon *hermon = ib_get_drvdata ( ibdev );
  851. struct hermon_queue_pair *hermon_qp;
  852. struct hermonprm_qp_ee_state_transitions qpctx;
  853. int rc;
  854. /* Calculate queue pair number */
  855. if ( ( rc = hermon_alloc_qpn ( ibdev, qp ) ) != 0 )
  856. goto err_alloc_qpn;
  857. /* Allocate control structures */
  858. hermon_qp = zalloc ( sizeof ( *hermon_qp ) );
  859. if ( ! hermon_qp ) {
  860. rc = -ENOMEM;
  861. goto err_hermon_qp;
  862. }
  863. /* Calculate doorbell address */
  864. hermon_qp->send.doorbell =
  865. ( hermon->uar + HERMON_UAR_NON_EQ_PAGE * HERMON_PAGE_SIZE +
  866. HERMON_DB_POST_SND_OFFSET );
  867. /* Allocate work queue buffer */
  868. hermon_qp->send.num_wqes = ( qp->send.num_wqes /* headroom */ + 1 +
  869. ( 2048 / sizeof ( hermon_qp->send.wqe[0] ) ) );
  870. hermon_qp->send.num_wqes =
  871. ( 1 << fls ( hermon_qp->send.num_wqes - 1 ) ); /* round up */
  872. hermon_qp->send.wqe_size = ( hermon_qp->send.num_wqes *
  873. sizeof ( hermon_qp->send.wqe[0] ) );
  874. hermon_qp->recv.wqe_size = ( qp->recv.num_wqes *
  875. sizeof ( hermon_qp->recv.wqe[0] ) );
  876. hermon_qp->wqe_size = ( hermon_qp->send.wqe_size +
  877. hermon_qp->recv.wqe_size );
  878. hermon_qp->wqe = malloc_dma ( hermon_qp->wqe_size,
  879. sizeof ( hermon_qp->send.wqe[0] ) );
  880. if ( ! hermon_qp->wqe ) {
  881. rc = -ENOMEM;
  882. goto err_alloc_wqe;
  883. }
  884. hermon_qp->send.wqe = hermon_qp->wqe;
  885. memset ( hermon_qp->send.wqe, 0xff, hermon_qp->send.wqe_size );
  886. hermon_qp->recv.wqe = ( hermon_qp->wqe + hermon_qp->send.wqe_size );
  887. memset ( hermon_qp->recv.wqe, 0, hermon_qp->recv.wqe_size );
  888. /* Allocate MTT entries */
  889. if ( ( rc = hermon_alloc_mtt ( hermon, hermon_qp->wqe,
  890. hermon_qp->wqe_size,
  891. &hermon_qp->mtt ) ) != 0 ) {
  892. goto err_alloc_mtt;
  893. }
  894. /* Transition queue to INIT state */
  895. memset ( &qpctx, 0, sizeof ( qpctx ) );
  896. MLX_FILL_2 ( &qpctx, 2,
  897. qpc_eec_data.pm_state, HERMON_PM_STATE_MIGRATED,
  898. qpc_eec_data.st, hermon_qp_st[qp->type] );
  899. MLX_FILL_1 ( &qpctx, 3, qpc_eec_data.pd, HERMON_GLOBAL_PD );
  900. MLX_FILL_4 ( &qpctx, 4,
  901. qpc_eec_data.log_rq_size, fls ( qp->recv.num_wqes - 1 ),
  902. qpc_eec_data.log_rq_stride,
  903. ( fls ( sizeof ( hermon_qp->recv.wqe[0] ) - 1 ) - 4 ),
  904. qpc_eec_data.log_sq_size,
  905. fls ( hermon_qp->send.num_wqes - 1 ),
  906. qpc_eec_data.log_sq_stride,
  907. ( fls ( sizeof ( hermon_qp->send.wqe[0] ) - 1 ) - 4 ) );
  908. MLX_FILL_1 ( &qpctx, 5,
  909. qpc_eec_data.usr_page, HERMON_UAR_NON_EQ_PAGE );
  910. MLX_FILL_1 ( &qpctx, 33, qpc_eec_data.cqn_snd, qp->send.cq->cqn );
  911. MLX_FILL_4 ( &qpctx, 38,
  912. qpc_eec_data.rre, 1,
  913. qpc_eec_data.rwe, 1,
  914. qpc_eec_data.rae, 1,
  915. qpc_eec_data.page_offset,
  916. ( hermon_qp->mtt.page_offset >> 6 ) );
  917. MLX_FILL_1 ( &qpctx, 41, qpc_eec_data.cqn_rcv, qp->recv.cq->cqn );
  918. MLX_FILL_1 ( &qpctx, 43, qpc_eec_data.db_record_addr_l,
  919. ( virt_to_phys ( &hermon_qp->recv.doorbell ) >> 2 ) );
  920. MLX_FILL_1 ( &qpctx, 53, qpc_eec_data.mtt_base_addr_l,
  921. ( hermon_qp->mtt.mtt_base_addr >> 3 ) );
  922. if ( ( rc = hermon_cmd_rst2init_qp ( hermon, qp->qpn,
  923. &qpctx ) ) != 0 ) {
  924. DBGC ( hermon, "Hermon %p RST2INIT_QP failed: %s\n",
  925. hermon, strerror ( rc ) );
  926. goto err_rst2init_qp;
  927. }
  928. hermon_qp->state = HERMON_QP_ST_INIT;
  929. DBGC ( hermon, "Hermon %p QPN %#lx send ring at [%p,%p)\n",
  930. hermon, qp->qpn, hermon_qp->send.wqe,
  931. ( ((void *)hermon_qp->send.wqe ) + hermon_qp->send.wqe_size ) );
  932. DBGC ( hermon, "Hermon %p QPN %#lx receive ring at [%p,%p)\n",
  933. hermon, qp->qpn, hermon_qp->recv.wqe,
  934. ( ((void *)hermon_qp->recv.wqe ) + hermon_qp->recv.wqe_size ) );
  935. ib_qp_set_drvdata ( qp, hermon_qp );
  936. return 0;
  937. hermon_cmd_2rst_qp ( hermon, qp->qpn );
  938. err_rst2init_qp:
  939. hermon_free_mtt ( hermon, &hermon_qp->mtt );
  940. err_alloc_mtt:
  941. free_dma ( hermon_qp->wqe, hermon_qp->wqe_size );
  942. err_alloc_wqe:
  943. free ( hermon_qp );
  944. err_hermon_qp:
  945. hermon_free_qpn ( ibdev, qp );
  946. err_alloc_qpn:
  947. return rc;
  948. }
  949. /**
  950. * Modify queue pair
  951. *
  952. * @v ibdev Infiniband device
  953. * @v qp Queue pair
  954. * @ret rc Return status code
  955. */
  956. static int hermon_modify_qp ( struct ib_device *ibdev,
  957. struct ib_queue_pair *qp ) {
  958. struct hermon *hermon = ib_get_drvdata ( ibdev );
  959. struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp );
  960. struct hermonprm_qp_ee_state_transitions qpctx;
  961. int rc;
  962. /* Transition queue to RTR state, if applicable */
  963. if ( hermon_qp->state < HERMON_QP_ST_RTR ) {
  964. memset ( &qpctx, 0, sizeof ( qpctx ) );
  965. MLX_FILL_2 ( &qpctx, 4,
  966. qpc_eec_data.mtu, HERMON_MTU_2048,
  967. qpc_eec_data.msg_max, 31 );
  968. MLX_FILL_1 ( &qpctx, 7,
  969. qpc_eec_data.remote_qpn_een, qp->av.qpn );
  970. MLX_FILL_1 ( &qpctx, 9,
  971. qpc_eec_data.primary_address_path.rlid,
  972. qp->av.lid );
  973. MLX_FILL_1 ( &qpctx, 10,
  974. qpc_eec_data.primary_address_path.max_stat_rate,
  975. hermon_rate ( &qp->av ) );
  976. memcpy ( &qpctx.u.dwords[12], &qp->av.gid,
  977. sizeof ( qp->av.gid ) );
  978. MLX_FILL_1 ( &qpctx, 16,
  979. qpc_eec_data.primary_address_path.sched_queue,
  980. hermon_sched_queue ( ibdev, qp ) );
  981. MLX_FILL_1 ( &qpctx, 39,
  982. qpc_eec_data.next_rcv_psn, qp->recv.psn );
  983. if ( ( rc = hermon_cmd_init2rtr_qp ( hermon, qp->qpn,
  984. &qpctx ) ) != 0 ) {
  985. DBGC ( hermon, "Hermon %p INIT2RTR_QP failed: %s\n",
  986. hermon, strerror ( rc ) );
  987. return rc;
  988. }
  989. hermon_qp->state = HERMON_QP_ST_RTR;
  990. }
  991. /* Transition queue to RTS state */
  992. if ( hermon_qp->state < HERMON_QP_ST_RTS ) {
  993. memset ( &qpctx, 0, sizeof ( qpctx ) );
  994. MLX_FILL_1 ( &qpctx, 10,
  995. qpc_eec_data.primary_address_path.ack_timeout,
  996. 0x13 );
  997. MLX_FILL_2 ( &qpctx, 30,
  998. qpc_eec_data.retry_count, HERMON_RETRY_MAX,
  999. qpc_eec_data.rnr_retry, HERMON_RETRY_MAX );
  1000. MLX_FILL_1 ( &qpctx, 32,
  1001. qpc_eec_data.next_send_psn, qp->send.psn );
  1002. if ( ( rc = hermon_cmd_rtr2rts_qp ( hermon, qp->qpn,
  1003. &qpctx ) ) != 0 ) {
  1004. DBGC ( hermon, "Hermon %p RTR2RTS_QP failed: %s\n",
  1005. hermon, strerror ( rc ) );
  1006. return rc;
  1007. }
  1008. hermon_qp->state = HERMON_QP_ST_RTS;
  1009. }
  1010. /* Update parameters in RTS state */
  1011. memset ( &qpctx, 0, sizeof ( qpctx ) );
  1012. MLX_FILL_1 ( &qpctx, 0, opt_param_mask, HERMON_QP_OPT_PARAM_QKEY );
  1013. MLX_FILL_1 ( &qpctx, 44, qpc_eec_data.q_key, qp->qkey );
  1014. if ( ( rc = hermon_cmd_rts2rts_qp ( hermon, qp->qpn, &qpctx ) ) != 0 ){
  1015. DBGC ( hermon, "Hermon %p RTS2RTS_QP failed: %s\n",
  1016. hermon, strerror ( rc ) );
  1017. return rc;
  1018. }
  1019. return 0;
  1020. }
  1021. /**
  1022. * Destroy queue pair
  1023. *
  1024. * @v ibdev Infiniband device
  1025. * @v qp Queue pair
  1026. */
  1027. static void hermon_destroy_qp ( struct ib_device *ibdev,
  1028. struct ib_queue_pair *qp ) {
  1029. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1030. struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp );
  1031. int rc;
  1032. /* Take ownership back from hardware */
  1033. if ( ( rc = hermon_cmd_2rst_qp ( hermon, qp->qpn ) ) != 0 ) {
  1034. DBGC ( hermon, "Hermon %p FATAL 2RST_QP failed on QPN %#lx: "
  1035. "%s\n", hermon, qp->qpn, strerror ( rc ) );
  1036. /* Leak memory and return; at least we avoid corruption */
  1037. return;
  1038. }
  1039. /* Free MTT entries */
  1040. hermon_free_mtt ( hermon, &hermon_qp->mtt );
  1041. /* Free memory */
  1042. free_dma ( hermon_qp->wqe, hermon_qp->wqe_size );
  1043. free ( hermon_qp );
  1044. /* Mark queue number as free */
  1045. hermon_free_qpn ( ibdev, qp );
  1046. ib_qp_set_drvdata ( qp, NULL );
  1047. }
  1048. /***************************************************************************
  1049. *
  1050. * Work request operations
  1051. *
  1052. ***************************************************************************
  1053. */
  1054. /**
  1055. * Construct UD send work queue entry
  1056. *
  1057. * @v ibdev Infiniband device
  1058. * @v qp Queue pair
  1059. * @v av Address vector
  1060. * @v iobuf I/O buffer
  1061. * @v wqe Send work queue entry
  1062. * @ret opcode Control opcode
  1063. */
  1064. static unsigned int
  1065. hermon_fill_ud_send_wqe ( struct ib_device *ibdev,
  1066. struct ib_queue_pair *qp __unused,
  1067. struct ib_address_vector *av,
  1068. struct io_buffer *iobuf,
  1069. union hermon_send_wqe *wqe ) {
  1070. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1071. MLX_FILL_1 ( &wqe->ud.ctrl, 1, ds,
  1072. ( ( offsetof ( typeof ( wqe->ud ), data[1] ) / 16 ) ) );
  1073. MLX_FILL_1 ( &wqe->ud.ctrl, 2, c, 0x03 /* generate completion */ );
  1074. MLX_FILL_2 ( &wqe->ud.ud, 0,
  1075. ud_address_vector.pd, HERMON_GLOBAL_PD,
  1076. ud_address_vector.port_number, ibdev->port );
  1077. MLX_FILL_2 ( &wqe->ud.ud, 1,
  1078. ud_address_vector.rlid, av->lid,
  1079. ud_address_vector.g, av->gid_present );
  1080. MLX_FILL_1 ( &wqe->ud.ud, 2,
  1081. ud_address_vector.max_stat_rate, hermon_rate ( av ) );
  1082. MLX_FILL_1 ( &wqe->ud.ud, 3, ud_address_vector.sl, av->sl );
  1083. memcpy ( &wqe->ud.ud.u.dwords[4], &av->gid, sizeof ( av->gid ) );
  1084. MLX_FILL_1 ( &wqe->ud.ud, 8, destination_qp, av->qpn );
  1085. MLX_FILL_1 ( &wqe->ud.ud, 9, q_key, av->qkey );
  1086. MLX_FILL_1 ( &wqe->ud.data[0], 0, byte_count, iob_len ( iobuf ) );
  1087. MLX_FILL_1 ( &wqe->ud.data[0], 1, l_key, hermon->lkey );
  1088. MLX_FILL_1 ( &wqe->ud.data[0], 3,
  1089. local_address_l, virt_to_bus ( iobuf->data ) );
  1090. return HERMON_OPCODE_SEND;
  1091. }
  1092. /**
  1093. * Construct MLX send work queue entry
  1094. *
  1095. * @v ibdev Infiniband device
  1096. * @v qp Queue pair
  1097. * @v av Address vector
  1098. * @v iobuf I/O buffer
  1099. * @v wqe Send work queue entry
  1100. * @ret opcode Control opcode
  1101. */
  1102. static unsigned int
  1103. hermon_fill_mlx_send_wqe ( struct ib_device *ibdev,
  1104. struct ib_queue_pair *qp,
  1105. struct ib_address_vector *av,
  1106. struct io_buffer *iobuf,
  1107. union hermon_send_wqe *wqe ) {
  1108. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1109. struct io_buffer headers;
  1110. /* Construct IB headers */
  1111. iob_populate ( &headers, &wqe->mlx.headers, 0,
  1112. sizeof ( wqe->mlx.headers ) );
  1113. iob_reserve ( &headers, sizeof ( wqe->mlx.headers ) );
  1114. ib_push ( ibdev, &headers, qp, iob_len ( iobuf ), av );
  1115. /* Fill work queue entry */
  1116. MLX_FILL_1 ( &wqe->mlx.ctrl, 1, ds,
  1117. ( ( offsetof ( typeof ( wqe->mlx ), data[2] ) / 16 ) ) );
  1118. MLX_FILL_5 ( &wqe->mlx.ctrl, 2,
  1119. c, 0x03 /* generate completion */,
  1120. icrc, 0 /* generate ICRC */,
  1121. max_statrate, hermon_rate ( av ),
  1122. slr, 0,
  1123. v15, ( ( qp->ext_qpn == IB_QPN_SMI ) ? 1 : 0 ) );
  1124. MLX_FILL_1 ( &wqe->mlx.ctrl, 3, rlid, av->lid );
  1125. MLX_FILL_1 ( &wqe->mlx.data[0], 0,
  1126. byte_count, iob_len ( &headers ) );
  1127. MLX_FILL_1 ( &wqe->mlx.data[0], 1, l_key, hermon->lkey );
  1128. MLX_FILL_1 ( &wqe->mlx.data[0], 3,
  1129. local_address_l, virt_to_bus ( headers.data ) );
  1130. MLX_FILL_1 ( &wqe->mlx.data[1], 0,
  1131. byte_count, ( iob_len ( iobuf ) + 4 /* ICRC */ ) );
  1132. MLX_FILL_1 ( &wqe->mlx.data[1], 1, l_key, hermon->lkey );
  1133. MLX_FILL_1 ( &wqe->mlx.data[1], 3,
  1134. local_address_l, virt_to_bus ( iobuf->data ) );
  1135. return HERMON_OPCODE_SEND;
  1136. }
  1137. /**
  1138. * Construct RC send work queue entry
  1139. *
  1140. * @v ibdev Infiniband device
  1141. * @v qp Queue pair
  1142. * @v av Address vector
  1143. * @v iobuf I/O buffer
  1144. * @v wqe Send work queue entry
  1145. * @ret opcode Control opcode
  1146. */
  1147. static unsigned int
  1148. hermon_fill_rc_send_wqe ( struct ib_device *ibdev,
  1149. struct ib_queue_pair *qp __unused,
  1150. struct ib_address_vector *av __unused,
  1151. struct io_buffer *iobuf,
  1152. union hermon_send_wqe *wqe ) {
  1153. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1154. MLX_FILL_1 ( &wqe->rc.ctrl, 1, ds,
  1155. ( ( offsetof ( typeof ( wqe->rc ), data[1] ) / 16 ) ) );
  1156. MLX_FILL_1 ( &wqe->rc.ctrl, 2, c, 0x03 /* generate completion */ );
  1157. MLX_FILL_1 ( &wqe->rc.data[0], 0, byte_count, iob_len ( iobuf ) );
  1158. MLX_FILL_1 ( &wqe->rc.data[0], 1, l_key, hermon->lkey );
  1159. MLX_FILL_1 ( &wqe->rc.data[0], 3,
  1160. local_address_l, virt_to_bus ( iobuf->data ) );
  1161. return HERMON_OPCODE_SEND;
  1162. }
  1163. /** Work queue entry constructors */
  1164. static unsigned int
  1165. ( * hermon_fill_send_wqe[] ) ( struct ib_device *ibdev,
  1166. struct ib_queue_pair *qp,
  1167. struct ib_address_vector *av,
  1168. struct io_buffer *iobuf,
  1169. union hermon_send_wqe *wqe ) = {
  1170. [IB_QPT_SMI] = hermon_fill_mlx_send_wqe,
  1171. [IB_QPT_GSI] = hermon_fill_mlx_send_wqe,
  1172. [IB_QPT_UD] = hermon_fill_ud_send_wqe,
  1173. [IB_QPT_RC] = hermon_fill_rc_send_wqe,
  1174. };
  1175. /**
  1176. * Post send work queue entry
  1177. *
  1178. * @v ibdev Infiniband device
  1179. * @v qp Queue pair
  1180. * @v av Address vector
  1181. * @v iobuf I/O buffer
  1182. * @ret rc Return status code
  1183. */
  1184. static int hermon_post_send ( struct ib_device *ibdev,
  1185. struct ib_queue_pair *qp,
  1186. struct ib_address_vector *av,
  1187. struct io_buffer *iobuf ) {
  1188. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1189. struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp );
  1190. struct ib_work_queue *wq = &qp->send;
  1191. struct hermon_send_work_queue *hermon_send_wq = &hermon_qp->send;
  1192. union hermon_send_wqe *wqe;
  1193. union hermonprm_doorbell_register db_reg;
  1194. unsigned int wqe_idx_mask;
  1195. unsigned int opcode;
  1196. /* Allocate work queue entry */
  1197. wqe_idx_mask = ( wq->num_wqes - 1 );
  1198. if ( wq->iobufs[wq->next_idx & wqe_idx_mask] ) {
  1199. DBGC ( hermon, "Hermon %p send queue full", hermon );
  1200. return -ENOBUFS;
  1201. }
  1202. wq->iobufs[wq->next_idx & wqe_idx_mask] = iobuf;
  1203. wqe = &hermon_send_wq->wqe[ wq->next_idx &
  1204. ( hermon_send_wq->num_wqes - 1 ) ];
  1205. /* Construct work queue entry */
  1206. memset ( ( ( ( void * ) wqe ) + 4 /* avoid ctrl.owner */ ), 0,
  1207. ( sizeof ( *wqe ) - 4 ) );
  1208. assert ( qp->type < ( sizeof ( hermon_fill_send_wqe ) /
  1209. sizeof ( hermon_fill_send_wqe[0] ) ) );
  1210. assert ( hermon_fill_send_wqe[qp->type] != NULL );
  1211. opcode = hermon_fill_send_wqe[qp->type] ( ibdev, qp, av, iobuf, wqe );
  1212. barrier();
  1213. MLX_FILL_2 ( &wqe->ctrl, 0,
  1214. opcode, opcode,
  1215. owner,
  1216. ( ( wq->next_idx & hermon_send_wq->num_wqes ) ? 1 : 0 ) );
  1217. DBGCP ( hermon, "Hermon %p posting send WQE:\n", hermon );
  1218. DBGCP_HD ( hermon, wqe, sizeof ( *wqe ) );
  1219. barrier();
  1220. /* Ring doorbell register */
  1221. MLX_FILL_1 ( &db_reg.send, 0, qn, qp->qpn );
  1222. DBGCP ( hermon, "Ringing doorbell %08lx with %08x\n",
  1223. virt_to_phys ( hermon_send_wq->doorbell ), db_reg.dword[0] );
  1224. writel ( db_reg.dword[0], ( hermon_send_wq->doorbell ) );
  1225. /* Update work queue's index */
  1226. wq->next_idx++;
  1227. return 0;
  1228. }
  1229. /**
  1230. * Post receive work queue entry
  1231. *
  1232. * @v ibdev Infiniband device
  1233. * @v qp Queue pair
  1234. * @v iobuf I/O buffer
  1235. * @ret rc Return status code
  1236. */
  1237. static int hermon_post_recv ( struct ib_device *ibdev,
  1238. struct ib_queue_pair *qp,
  1239. struct io_buffer *iobuf ) {
  1240. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1241. struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp );
  1242. struct ib_work_queue *wq = &qp->recv;
  1243. struct hermon_recv_work_queue *hermon_recv_wq = &hermon_qp->recv;
  1244. struct hermonprm_recv_wqe *wqe;
  1245. unsigned int wqe_idx_mask;
  1246. /* Allocate work queue entry */
  1247. wqe_idx_mask = ( wq->num_wqes - 1 );
  1248. if ( wq->iobufs[wq->next_idx & wqe_idx_mask] ) {
  1249. DBGC ( hermon, "Hermon %p receive queue full", hermon );
  1250. return -ENOBUFS;
  1251. }
  1252. wq->iobufs[wq->next_idx & wqe_idx_mask] = iobuf;
  1253. wqe = &hermon_recv_wq->wqe[wq->next_idx & wqe_idx_mask].recv;
  1254. /* Construct work queue entry */
  1255. MLX_FILL_1 ( &wqe->data[0], 0, byte_count, iob_tailroom ( iobuf ) );
  1256. MLX_FILL_1 ( &wqe->data[0], 1, l_key, hermon->lkey );
  1257. MLX_FILL_1 ( &wqe->data[0], 3,
  1258. local_address_l, virt_to_bus ( iobuf->data ) );
  1259. /* Update work queue's index */
  1260. wq->next_idx++;
  1261. /* Update doorbell record */
  1262. barrier();
  1263. MLX_FILL_1 ( &hermon_recv_wq->doorbell, 0, receive_wqe_counter,
  1264. ( wq->next_idx & 0xffff ) );
  1265. return 0;
  1266. }
  1267. /**
  1268. * Handle completion
  1269. *
  1270. * @v ibdev Infiniband device
  1271. * @v cq Completion queue
  1272. * @v cqe Hardware completion queue entry
  1273. * @ret rc Return status code
  1274. */
  1275. static int hermon_complete ( struct ib_device *ibdev,
  1276. struct ib_completion_queue *cq,
  1277. union hermonprm_completion_entry *cqe ) {
  1278. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1279. struct ib_work_queue *wq;
  1280. struct ib_queue_pair *qp;
  1281. struct hermon_queue_pair *hermon_qp;
  1282. struct io_buffer *iobuf;
  1283. struct ib_address_vector recv_av;
  1284. struct ib_global_route_header *grh;
  1285. struct ib_address_vector *av;
  1286. unsigned int opcode;
  1287. unsigned long qpn;
  1288. int is_send;
  1289. unsigned int wqe_idx;
  1290. size_t len;
  1291. int rc = 0;
  1292. /* Parse completion */
  1293. qpn = MLX_GET ( &cqe->normal, qpn );
  1294. is_send = MLX_GET ( &cqe->normal, s_r );
  1295. opcode = MLX_GET ( &cqe->normal, opcode );
  1296. if ( opcode >= HERMON_OPCODE_RECV_ERROR ) {
  1297. /* "s" field is not valid for error opcodes */
  1298. is_send = ( opcode == HERMON_OPCODE_SEND_ERROR );
  1299. DBGC ( hermon, "Hermon %p CQN %lx syndrome %x vendor %x\n",
  1300. hermon, cq->cqn, MLX_GET ( &cqe->error, syndrome ),
  1301. MLX_GET ( &cqe->error, vendor_error_syndrome ) );
  1302. rc = -EIO;
  1303. /* Don't return immediately; propagate error to completer */
  1304. }
  1305. /* Identify work queue */
  1306. wq = ib_find_wq ( cq, qpn, is_send );
  1307. if ( ! wq ) {
  1308. DBGC ( hermon, "Hermon %p CQN %lx unknown %s QPN %lx\n",
  1309. hermon, cq->cqn, ( is_send ? "send" : "recv" ), qpn );
  1310. return -EIO;
  1311. }
  1312. qp = wq->qp;
  1313. hermon_qp = ib_qp_get_drvdata ( qp );
  1314. /* Identify I/O buffer */
  1315. wqe_idx = ( MLX_GET ( &cqe->normal, wqe_counter ) &
  1316. ( wq->num_wqes - 1 ) );
  1317. iobuf = wq->iobufs[wqe_idx];
  1318. if ( ! iobuf ) {
  1319. DBGC ( hermon, "Hermon %p CQN %lx QPN %lx empty WQE %x\n",
  1320. hermon, cq->cqn, qp->qpn, wqe_idx );
  1321. return -EIO;
  1322. }
  1323. wq->iobufs[wqe_idx] = NULL;
  1324. if ( is_send ) {
  1325. /* Hand off to completion handler */
  1326. ib_complete_send ( ibdev, qp, iobuf, rc );
  1327. } else {
  1328. /* Set received length */
  1329. len = MLX_GET ( &cqe->normal, byte_cnt );
  1330. assert ( len <= iob_tailroom ( iobuf ) );
  1331. iob_put ( iobuf, len );
  1332. switch ( qp->type ) {
  1333. case IB_QPT_SMI:
  1334. case IB_QPT_GSI:
  1335. case IB_QPT_UD:
  1336. assert ( iob_len ( iobuf ) >= sizeof ( *grh ) );
  1337. grh = iobuf->data;
  1338. iob_pull ( iobuf, sizeof ( *grh ) );
  1339. /* Construct address vector */
  1340. av = &recv_av;
  1341. memset ( av, 0, sizeof ( *av ) );
  1342. av->qpn = MLX_GET ( &cqe->normal, srq_rqpn );
  1343. av->lid = MLX_GET ( &cqe->normal, slid_smac47_32 );
  1344. av->sl = MLX_GET ( &cqe->normal, sl );
  1345. av->gid_present = MLX_GET ( &cqe->normal, g );
  1346. memcpy ( &av->gid, &grh->sgid, sizeof ( av->gid ) );
  1347. break;
  1348. case IB_QPT_RC:
  1349. av = &qp->av;
  1350. break;
  1351. default:
  1352. assert ( 0 );
  1353. return -EINVAL;
  1354. }
  1355. /* Hand off to completion handler */
  1356. ib_complete_recv ( ibdev, qp, av, iobuf, rc );
  1357. }
  1358. return rc;
  1359. }
  1360. /**
  1361. * Poll completion queue
  1362. *
  1363. * @v ibdev Infiniband device
  1364. * @v cq Completion queue
  1365. */
  1366. static void hermon_poll_cq ( struct ib_device *ibdev,
  1367. struct ib_completion_queue *cq ) {
  1368. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1369. struct hermon_completion_queue *hermon_cq = ib_cq_get_drvdata ( cq );
  1370. union hermonprm_completion_entry *cqe;
  1371. unsigned int cqe_idx_mask;
  1372. int rc;
  1373. while ( 1 ) {
  1374. /* Look for completion entry */
  1375. cqe_idx_mask = ( cq->num_cqes - 1 );
  1376. cqe = &hermon_cq->cqe[cq->next_idx & cqe_idx_mask];
  1377. if ( MLX_GET ( &cqe->normal, owner ) ^
  1378. ( ( cq->next_idx & cq->num_cqes ) ? 1 : 0 ) ) {
  1379. /* Entry still owned by hardware; end of poll */
  1380. break;
  1381. }
  1382. DBGCP ( hermon, "Hermon %p completion:\n", hermon );
  1383. DBGCP_HD ( hermon, cqe, sizeof ( *cqe ) );
  1384. /* Handle completion */
  1385. if ( ( rc = hermon_complete ( ibdev, cq, cqe ) ) != 0 ) {
  1386. DBGC ( hermon, "Hermon %p failed to complete: %s\n",
  1387. hermon, strerror ( rc ) );
  1388. DBGC_HD ( hermon, cqe, sizeof ( *cqe ) );
  1389. }
  1390. /* Update completion queue's index */
  1391. cq->next_idx++;
  1392. /* Update doorbell record */
  1393. MLX_FILL_1 ( &hermon_cq->doorbell, 0, update_ci,
  1394. ( cq->next_idx & 0x00ffffffUL ) );
  1395. }
  1396. }
  1397. /***************************************************************************
  1398. *
  1399. * Event queues
  1400. *
  1401. ***************************************************************************
  1402. */
  1403. /**
  1404. * Create event queue
  1405. *
  1406. * @v hermon Hermon device
  1407. * @ret rc Return status code
  1408. */
  1409. static int hermon_create_eq ( struct hermon *hermon ) {
  1410. struct hermon_event_queue *hermon_eq = &hermon->eq;
  1411. struct hermonprm_eqc eqctx;
  1412. struct hermonprm_event_mask mask;
  1413. unsigned int i;
  1414. int rc;
  1415. /* Select event queue number */
  1416. hermon_eq->eqn = ( 4 * hermon->cap.reserved_uars );
  1417. if ( hermon_eq->eqn < hermon->cap.reserved_eqs )
  1418. hermon_eq->eqn = hermon->cap.reserved_eqs;
  1419. /* Calculate doorbell address */
  1420. hermon_eq->doorbell =
  1421. ( hermon->uar + HERMON_DB_EQ_OFFSET ( hermon_eq->eqn ) );
  1422. /* Allocate event queue itself */
  1423. hermon_eq->eqe_size =
  1424. ( HERMON_NUM_EQES * sizeof ( hermon_eq->eqe[0] ) );
  1425. hermon_eq->eqe = malloc_dma ( hermon_eq->eqe_size,
  1426. sizeof ( hermon_eq->eqe[0] ) );
  1427. if ( ! hermon_eq->eqe ) {
  1428. rc = -ENOMEM;
  1429. goto err_eqe;
  1430. }
  1431. memset ( hermon_eq->eqe, 0, hermon_eq->eqe_size );
  1432. for ( i = 0 ; i < HERMON_NUM_EQES ; i++ ) {
  1433. MLX_FILL_1 ( &hermon_eq->eqe[i].generic, 7, owner, 1 );
  1434. }
  1435. barrier();
  1436. /* Allocate MTT entries */
  1437. if ( ( rc = hermon_alloc_mtt ( hermon, hermon_eq->eqe,
  1438. hermon_eq->eqe_size,
  1439. &hermon_eq->mtt ) ) != 0 )
  1440. goto err_alloc_mtt;
  1441. /* Hand queue over to hardware */
  1442. memset ( &eqctx, 0, sizeof ( eqctx ) );
  1443. MLX_FILL_1 ( &eqctx, 0, st, 0xa /* "Fired" */ );
  1444. MLX_FILL_1 ( &eqctx, 2,
  1445. page_offset, ( hermon_eq->mtt.page_offset >> 5 ) );
  1446. MLX_FILL_1 ( &eqctx, 3, log_eq_size, fls ( HERMON_NUM_EQES - 1 ) );
  1447. MLX_FILL_1 ( &eqctx, 7, mtt_base_addr_l,
  1448. ( hermon_eq->mtt.mtt_base_addr >> 3 ) );
  1449. if ( ( rc = hermon_cmd_sw2hw_eq ( hermon, hermon_eq->eqn,
  1450. &eqctx ) ) != 0 ) {
  1451. DBGC ( hermon, "Hermon %p SW2HW_EQ failed: %s\n",
  1452. hermon, strerror ( rc ) );
  1453. goto err_sw2hw_eq;
  1454. }
  1455. /* Map events to this event queue */
  1456. memset ( &mask, 0, sizeof ( mask ) );
  1457. MLX_FILL_1 ( &mask, 1, port_state_change, 1 );
  1458. if ( ( rc = hermon_cmd_map_eq ( hermon,
  1459. ( HERMON_MAP_EQ | hermon_eq->eqn ),
  1460. &mask ) ) != 0 ) {
  1461. DBGC ( hermon, "Hermon %p MAP_EQ failed: %s\n",
  1462. hermon, strerror ( rc ) );
  1463. goto err_map_eq;
  1464. }
  1465. DBGC ( hermon, "Hermon %p EQN %#lx ring at [%p,%p])\n",
  1466. hermon, hermon_eq->eqn, hermon_eq->eqe,
  1467. ( ( ( void * ) hermon_eq->eqe ) + hermon_eq->eqe_size ) );
  1468. return 0;
  1469. err_map_eq:
  1470. hermon_cmd_hw2sw_eq ( hermon, hermon_eq->eqn, &eqctx );
  1471. err_sw2hw_eq:
  1472. hermon_free_mtt ( hermon, &hermon_eq->mtt );
  1473. err_alloc_mtt:
  1474. free_dma ( hermon_eq->eqe, hermon_eq->eqe_size );
  1475. err_eqe:
  1476. memset ( hermon_eq, 0, sizeof ( *hermon_eq ) );
  1477. return rc;
  1478. }
  1479. /**
  1480. * Destroy event queue
  1481. *
  1482. * @v hermon Hermon device
  1483. */
  1484. static void hermon_destroy_eq ( struct hermon *hermon ) {
  1485. struct hermon_event_queue *hermon_eq = &hermon->eq;
  1486. struct hermonprm_eqc eqctx;
  1487. struct hermonprm_event_mask mask;
  1488. int rc;
  1489. /* Unmap events from event queue */
  1490. memset ( &mask, 0, sizeof ( mask ) );
  1491. MLX_FILL_1 ( &mask, 1, port_state_change, 1 );
  1492. if ( ( rc = hermon_cmd_map_eq ( hermon,
  1493. ( HERMON_UNMAP_EQ | hermon_eq->eqn ),
  1494. &mask ) ) != 0 ) {
  1495. DBGC ( hermon, "Hermon %p FATAL MAP_EQ failed to unmap: %s\n",
  1496. hermon, strerror ( rc ) );
  1497. /* Continue; HCA may die but system should survive */
  1498. }
  1499. /* Take ownership back from hardware */
  1500. if ( ( rc = hermon_cmd_hw2sw_eq ( hermon, hermon_eq->eqn,
  1501. &eqctx ) ) != 0 ) {
  1502. DBGC ( hermon, "Hermon %p FATAL HW2SW_EQ failed: %s\n",
  1503. hermon, strerror ( rc ) );
  1504. /* Leak memory and return; at least we avoid corruption */
  1505. return;
  1506. }
  1507. /* Free MTT entries */
  1508. hermon_free_mtt ( hermon, &hermon_eq->mtt );
  1509. /* Free memory */
  1510. free_dma ( hermon_eq->eqe, hermon_eq->eqe_size );
  1511. memset ( hermon_eq, 0, sizeof ( *hermon_eq ) );
  1512. }
  1513. /**
  1514. * Handle port state event
  1515. *
  1516. * @v hermon Hermon device
  1517. * @v eqe Port state change event queue entry
  1518. */
  1519. static void hermon_event_port_state_change ( struct hermon *hermon,
  1520. union hermonprm_event_entry *eqe){
  1521. unsigned int port;
  1522. int link_up;
  1523. /* Get port and link status */
  1524. port = ( MLX_GET ( &eqe->port_state_change, data.p ) - 1 );
  1525. link_up = ( MLX_GET ( &eqe->generic, event_sub_type ) & 0x04 );
  1526. DBGC ( hermon, "Hermon %p port %d link %s\n", hermon, ( port + 1 ),
  1527. ( link_up ? "up" : "down" ) );
  1528. /* Sanity check */
  1529. if ( port >= hermon->cap.num_ports ) {
  1530. DBGC ( hermon, "Hermon %p port %d does not exist!\n",
  1531. hermon, ( port + 1 ) );
  1532. return;
  1533. }
  1534. /* Update MAD parameters */
  1535. ib_smc_update ( hermon->ibdev[port], hermon_mad );
  1536. /* Notify Infiniband core of link state change */
  1537. ib_link_state_changed ( hermon->ibdev[port] );
  1538. }
  1539. /**
  1540. * Poll event queue
  1541. *
  1542. * @v ibdev Infiniband device
  1543. */
  1544. static void hermon_poll_eq ( struct ib_device *ibdev ) {
  1545. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1546. struct hermon_event_queue *hermon_eq = &hermon->eq;
  1547. union hermonprm_event_entry *eqe;
  1548. union hermonprm_doorbell_register db_reg;
  1549. unsigned int eqe_idx_mask;
  1550. unsigned int event_type;
  1551. while ( 1 ) {
  1552. /* Look for event entry */
  1553. eqe_idx_mask = ( HERMON_NUM_EQES - 1 );
  1554. eqe = &hermon_eq->eqe[hermon_eq->next_idx & eqe_idx_mask];
  1555. if ( MLX_GET ( &eqe->generic, owner ) ^
  1556. ( ( hermon_eq->next_idx & HERMON_NUM_EQES ) ? 1 : 0 ) ) {
  1557. /* Entry still owned by hardware; end of poll */
  1558. break;
  1559. }
  1560. DBGCP ( hermon, "Hermon %p event:\n", hermon );
  1561. DBGCP_HD ( hermon, eqe, sizeof ( *eqe ) );
  1562. /* Handle event */
  1563. event_type = MLX_GET ( &eqe->generic, event_type );
  1564. switch ( event_type ) {
  1565. case HERMON_EV_PORT_STATE_CHANGE:
  1566. hermon_event_port_state_change ( hermon, eqe );
  1567. break;
  1568. default:
  1569. DBGC ( hermon, "Hermon %p unrecognised event type "
  1570. "%#x:\n", hermon, event_type );
  1571. DBGC_HD ( hermon, eqe, sizeof ( *eqe ) );
  1572. break;
  1573. }
  1574. /* Update event queue's index */
  1575. hermon_eq->next_idx++;
  1576. /* Ring doorbell */
  1577. MLX_FILL_1 ( &db_reg.event, 0,
  1578. ci, ( hermon_eq->next_idx & 0x00ffffffUL ) );
  1579. DBGCP ( hermon, "Ringing doorbell %08lx with %08x\n",
  1580. virt_to_phys ( hermon_eq->doorbell ),
  1581. db_reg.dword[0] );
  1582. writel ( db_reg.dword[0], hermon_eq->doorbell );
  1583. }
  1584. }
  1585. /***************************************************************************
  1586. *
  1587. * Infiniband link-layer operations
  1588. *
  1589. ***************************************************************************
  1590. */
  1591. /**
  1592. * Sense port type
  1593. *
  1594. * @v ibdev Infiniband device
  1595. * @ret port_type Port type, or negative error
  1596. */
  1597. static int hermon_sense_port_type ( struct ib_device *ibdev ) {
  1598. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1599. struct hermonprm_sense_port sense_port;
  1600. int port_type;
  1601. int rc;
  1602. /* If DPDP is not supported, always assume Infiniband */
  1603. if ( ! hermon->cap.dpdp )
  1604. return HERMON_PORT_TYPE_IB;
  1605. /* Sense the port type */
  1606. if ( ( rc = hermon_cmd_sense_port ( hermon, ibdev->port,
  1607. &sense_port ) ) != 0 ) {
  1608. DBGC ( hermon, "Hermon %p port %d sense failed: %s\n",
  1609. hermon, ibdev->port, strerror ( rc ) );
  1610. return rc;
  1611. }
  1612. port_type = MLX_GET ( &sense_port, port_type );
  1613. DBGC ( hermon, "Hermon %p port %d type %d\n",
  1614. hermon, ibdev->port, port_type );
  1615. return port_type;
  1616. }
  1617. /**
  1618. * Initialise Infiniband link
  1619. *
  1620. * @v ibdev Infiniband device
  1621. * @ret rc Return status code
  1622. */
  1623. static int hermon_open ( struct ib_device *ibdev ) {
  1624. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1625. struct hermonprm_init_port init_port;
  1626. int port_type;
  1627. int rc;
  1628. /* Check we are connected to an Infiniband network */
  1629. if ( ( rc = port_type = hermon_sense_port_type ( ibdev ) ) < 0 )
  1630. return rc;
  1631. if ( port_type != HERMON_PORT_TYPE_IB ) {
  1632. DBGC ( hermon, "Hermon %p port %d not connected to an "
  1633. "Infiniband network", hermon, ibdev->port );
  1634. return -ENOTCONN;
  1635. }
  1636. /* Init Port */
  1637. memset ( &init_port, 0, sizeof ( init_port ) );
  1638. MLX_FILL_2 ( &init_port, 0,
  1639. port_width_cap, 3,
  1640. vl_cap, 1 );
  1641. MLX_FILL_2 ( &init_port, 1,
  1642. mtu, HERMON_MTU_2048,
  1643. max_gid, 1 );
  1644. MLX_FILL_1 ( &init_port, 2, max_pkey, 64 );
  1645. if ( ( rc = hermon_cmd_init_port ( hermon, ibdev->port,
  1646. &init_port ) ) != 0 ) {
  1647. DBGC ( hermon, "Hermon %p could not intialise port: %s\n",
  1648. hermon, strerror ( rc ) );
  1649. return rc;
  1650. }
  1651. /* Update MAD parameters */
  1652. ib_smc_update ( ibdev, hermon_mad );
  1653. return 0;
  1654. }
  1655. /**
  1656. * Close Infiniband link
  1657. *
  1658. * @v ibdev Infiniband device
  1659. */
  1660. static void hermon_close ( struct ib_device *ibdev ) {
  1661. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1662. int rc;
  1663. if ( ( rc = hermon_cmd_close_port ( hermon, ibdev->port ) ) != 0 ) {
  1664. DBGC ( hermon, "Hermon %p could not close port: %s\n",
  1665. hermon, strerror ( rc ) );
  1666. /* Nothing we can do about this */
  1667. }
  1668. }
  1669. /**
  1670. * Inform embedded subnet management agent of a received MAD
  1671. *
  1672. * @v ibdev Infiniband device
  1673. * @v mad MAD
  1674. * @ret rc Return status code
  1675. */
  1676. static int hermon_inform_sma ( struct ib_device *ibdev,
  1677. union ib_mad *mad ) {
  1678. int rc;
  1679. /* Send the MAD to the embedded SMA */
  1680. if ( ( rc = hermon_mad ( ibdev, mad ) ) != 0 )
  1681. return rc;
  1682. /* Update parameters held in software */
  1683. ib_smc_update ( ibdev, hermon_mad );
  1684. return 0;
  1685. }
  1686. /***************************************************************************
  1687. *
  1688. * Multicast group operations
  1689. *
  1690. ***************************************************************************
  1691. */
  1692. /**
  1693. * Attach to multicast group
  1694. *
  1695. * @v ibdev Infiniband device
  1696. * @v qp Queue pair
  1697. * @v gid Multicast GID
  1698. * @ret rc Return status code
  1699. */
  1700. static int hermon_mcast_attach ( struct ib_device *ibdev,
  1701. struct ib_queue_pair *qp,
  1702. struct ib_gid *gid ) {
  1703. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1704. struct hermonprm_mgm_hash hash;
  1705. struct hermonprm_mcg_entry mcg;
  1706. unsigned int index;
  1707. int rc;
  1708. /* Generate hash table index */
  1709. if ( ( rc = hermon_cmd_mgid_hash ( hermon, gid, &hash ) ) != 0 ) {
  1710. DBGC ( hermon, "Hermon %p could not hash GID: %s\n",
  1711. hermon, strerror ( rc ) );
  1712. return rc;
  1713. }
  1714. index = MLX_GET ( &hash, hash );
  1715. /* Check for existing hash table entry */
  1716. if ( ( rc = hermon_cmd_read_mcg ( hermon, index, &mcg ) ) != 0 ) {
  1717. DBGC ( hermon, "Hermon %p could not read MCG %#x: %s\n",
  1718. hermon, index, strerror ( rc ) );
  1719. return rc;
  1720. }
  1721. if ( MLX_GET ( &mcg, hdr.members_count ) != 0 ) {
  1722. /* FIXME: this implementation allows only a single QP
  1723. * per multicast group, and doesn't handle hash
  1724. * collisions. Sufficient for IPoIB but may need to
  1725. * be extended in future.
  1726. */
  1727. DBGC ( hermon, "Hermon %p MGID index %#x already in use\n",
  1728. hermon, index );
  1729. return -EBUSY;
  1730. }
  1731. /* Update hash table entry */
  1732. MLX_FILL_1 ( &mcg, 1, hdr.members_count, 1 );
  1733. MLX_FILL_1 ( &mcg, 8, qp[0].qpn, qp->qpn );
  1734. memcpy ( &mcg.u.dwords[4], gid, sizeof ( *gid ) );
  1735. if ( ( rc = hermon_cmd_write_mcg ( hermon, index, &mcg ) ) != 0 ) {
  1736. DBGC ( hermon, "Hermon %p could not write MCG %#x: %s\n",
  1737. hermon, index, strerror ( rc ) );
  1738. return rc;
  1739. }
  1740. return 0;
  1741. }
  1742. /**
  1743. * Detach from multicast group
  1744. *
  1745. * @v ibdev Infiniband device
  1746. * @v qp Queue pair
  1747. * @v gid Multicast GID
  1748. */
  1749. static void hermon_mcast_detach ( struct ib_device *ibdev,
  1750. struct ib_queue_pair *qp __unused,
  1751. struct ib_gid *gid ) {
  1752. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1753. struct hermonprm_mgm_hash hash;
  1754. struct hermonprm_mcg_entry mcg;
  1755. unsigned int index;
  1756. int rc;
  1757. /* Generate hash table index */
  1758. if ( ( rc = hermon_cmd_mgid_hash ( hermon, gid, &hash ) ) != 0 ) {
  1759. DBGC ( hermon, "Hermon %p could not hash GID: %s\n",
  1760. hermon, strerror ( rc ) );
  1761. return;
  1762. }
  1763. index = MLX_GET ( &hash, hash );
  1764. /* Clear hash table entry */
  1765. memset ( &mcg, 0, sizeof ( mcg ) );
  1766. if ( ( rc = hermon_cmd_write_mcg ( hermon, index, &mcg ) ) != 0 ) {
  1767. DBGC ( hermon, "Hermon %p could not write MCG %#x: %s\n",
  1768. hermon, index, strerror ( rc ) );
  1769. return;
  1770. }
  1771. }
  1772. /** Hermon Infiniband operations */
  1773. static struct ib_device_operations hermon_ib_operations = {
  1774. .create_cq = hermon_create_cq,
  1775. .destroy_cq = hermon_destroy_cq,
  1776. .create_qp = hermon_create_qp,
  1777. .modify_qp = hermon_modify_qp,
  1778. .destroy_qp = hermon_destroy_qp,
  1779. .post_send = hermon_post_send,
  1780. .post_recv = hermon_post_recv,
  1781. .poll_cq = hermon_poll_cq,
  1782. .poll_eq = hermon_poll_eq,
  1783. .open = hermon_open,
  1784. .close = hermon_close,
  1785. .mcast_attach = hermon_mcast_attach,
  1786. .mcast_detach = hermon_mcast_detach,
  1787. .set_port_info = hermon_inform_sma,
  1788. .set_pkey_table = hermon_inform_sma,
  1789. };
  1790. /***************************************************************************
  1791. *
  1792. * Firmware control
  1793. *
  1794. ***************************************************************************
  1795. */
  1796. /**
  1797. * Map virtual to physical address for firmware usage
  1798. *
  1799. * @v hermon Hermon device
  1800. * @v map Mapping function
  1801. * @v va Virtual address
  1802. * @v pa Physical address
  1803. * @v len Length of region
  1804. * @ret rc Return status code
  1805. */
  1806. static int hermon_map_vpm ( struct hermon *hermon,
  1807. int ( *map ) ( struct hermon *hermon,
  1808. const struct hermonprm_virtual_physical_mapping* ),
  1809. uint64_t va, physaddr_t pa, size_t len ) {
  1810. struct hermonprm_virtual_physical_mapping mapping;
  1811. int rc;
  1812. assert ( ( va & ( HERMON_PAGE_SIZE - 1 ) ) == 0 );
  1813. assert ( ( pa & ( HERMON_PAGE_SIZE - 1 ) ) == 0 );
  1814. assert ( ( len & ( HERMON_PAGE_SIZE - 1 ) ) == 0 );
  1815. /* These mappings tend to generate huge volumes of
  1816. * uninteresting debug data, which basically makes it
  1817. * impossible to use debugging otherwise.
  1818. */
  1819. DBG_DISABLE ( DBGLVL_LOG | DBGLVL_EXTRA );
  1820. while ( len ) {
  1821. memset ( &mapping, 0, sizeof ( mapping ) );
  1822. MLX_FILL_1 ( &mapping, 0, va_h, ( va >> 32 ) );
  1823. MLX_FILL_1 ( &mapping, 1, va_l, ( va >> 12 ) );
  1824. MLX_FILL_2 ( &mapping, 3,
  1825. log2size, 0,
  1826. pa_l, ( pa >> 12 ) );
  1827. if ( ( rc = map ( hermon, &mapping ) ) != 0 ) {
  1828. DBG_ENABLE ( DBGLVL_LOG | DBGLVL_EXTRA );
  1829. DBGC ( hermon, "Hermon %p could not map %llx => %lx: "
  1830. "%s\n", hermon, va, pa, strerror ( rc ) );
  1831. return rc;
  1832. }
  1833. pa += HERMON_PAGE_SIZE;
  1834. va += HERMON_PAGE_SIZE;
  1835. len -= HERMON_PAGE_SIZE;
  1836. }
  1837. DBG_ENABLE ( DBGLVL_LOG | DBGLVL_EXTRA );
  1838. return 0;
  1839. }
  1840. /**
  1841. * Start firmware running
  1842. *
  1843. * @v hermon Hermon device
  1844. * @ret rc Return status code
  1845. */
  1846. static int hermon_start_firmware ( struct hermon *hermon ) {
  1847. struct hermonprm_query_fw fw;
  1848. unsigned int fw_pages;
  1849. size_t fw_size;
  1850. physaddr_t fw_base;
  1851. int rc;
  1852. /* Get firmware parameters */
  1853. if ( ( rc = hermon_cmd_query_fw ( hermon, &fw ) ) != 0 ) {
  1854. DBGC ( hermon, "Hermon %p could not query firmware: %s\n",
  1855. hermon, strerror ( rc ) );
  1856. goto err_query_fw;
  1857. }
  1858. DBGC ( hermon, "Hermon %p firmware version %d.%d.%d\n", hermon,
  1859. MLX_GET ( &fw, fw_rev_major ), MLX_GET ( &fw, fw_rev_minor ),
  1860. MLX_GET ( &fw, fw_rev_subminor ) );
  1861. fw_pages = MLX_GET ( &fw, fw_pages );
  1862. DBGC ( hermon, "Hermon %p requires %d pages (%d kB) for firmware\n",
  1863. hermon, fw_pages, ( fw_pages * ( HERMON_PAGE_SIZE / 1024 ) ) );
  1864. /* Allocate firmware pages and map firmware area */
  1865. fw_size = ( fw_pages * HERMON_PAGE_SIZE );
  1866. hermon->firmware_area = umalloc ( fw_size );
  1867. if ( ! hermon->firmware_area ) {
  1868. rc = -ENOMEM;
  1869. goto err_alloc_fa;
  1870. }
  1871. fw_base = user_to_phys ( hermon->firmware_area, 0 );
  1872. DBGC ( hermon, "Hermon %p firmware area at physical [%lx,%lx)\n",
  1873. hermon, fw_base, ( fw_base + fw_size ) );
  1874. if ( ( rc = hermon_map_vpm ( hermon, hermon_cmd_map_fa,
  1875. 0, fw_base, fw_size ) ) != 0 ) {
  1876. DBGC ( hermon, "Hermon %p could not map firmware: %s\n",
  1877. hermon, strerror ( rc ) );
  1878. goto err_map_fa;
  1879. }
  1880. /* Start firmware */
  1881. if ( ( rc = hermon_cmd_run_fw ( hermon ) ) != 0 ) {
  1882. DBGC ( hermon, "Hermon %p could not run firmware: %s\n",
  1883. hermon, strerror ( rc ) );
  1884. goto err_run_fw;
  1885. }
  1886. DBGC ( hermon, "Hermon %p firmware started\n", hermon );
  1887. return 0;
  1888. err_run_fw:
  1889. err_map_fa:
  1890. hermon_cmd_unmap_fa ( hermon );
  1891. ufree ( hermon->firmware_area );
  1892. hermon->firmware_area = UNULL;
  1893. err_alloc_fa:
  1894. err_query_fw:
  1895. return rc;
  1896. }
  1897. /**
  1898. * Stop firmware running
  1899. *
  1900. * @v hermon Hermon device
  1901. */
  1902. static void hermon_stop_firmware ( struct hermon *hermon ) {
  1903. int rc;
  1904. if ( ( rc = hermon_cmd_unmap_fa ( hermon ) ) != 0 ) {
  1905. DBGC ( hermon, "Hermon %p FATAL could not stop firmware: %s\n",
  1906. hermon, strerror ( rc ) );
  1907. /* Leak memory and return; at least we avoid corruption */
  1908. return;
  1909. }
  1910. ufree ( hermon->firmware_area );
  1911. hermon->firmware_area = UNULL;
  1912. }
  1913. /***************************************************************************
  1914. *
  1915. * Infinihost Context Memory management
  1916. *
  1917. ***************************************************************************
  1918. */
  1919. /**
  1920. * Get device limits
  1921. *
  1922. * @v hermon Hermon device
  1923. * @ret rc Return status code
  1924. */
  1925. static int hermon_get_cap ( struct hermon *hermon ) {
  1926. struct hermonprm_query_dev_cap dev_cap;
  1927. int rc;
  1928. if ( ( rc = hermon_cmd_query_dev_cap ( hermon, &dev_cap ) ) != 0 ) {
  1929. DBGC ( hermon, "Hermon %p could not get device limits: %s\n",
  1930. hermon, strerror ( rc ) );
  1931. return rc;
  1932. }
  1933. hermon->cap.cmpt_entry_size = MLX_GET ( &dev_cap, c_mpt_entry_sz );
  1934. hermon->cap.reserved_qps =
  1935. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_qps ) );
  1936. hermon->cap.qpc_entry_size = MLX_GET ( &dev_cap, qpc_entry_sz );
  1937. hermon->cap.altc_entry_size = MLX_GET ( &dev_cap, altc_entry_sz );
  1938. hermon->cap.auxc_entry_size = MLX_GET ( &dev_cap, aux_entry_sz );
  1939. hermon->cap.reserved_srqs =
  1940. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_srqs ) );
  1941. hermon->cap.srqc_entry_size = MLX_GET ( &dev_cap, srq_entry_sz );
  1942. hermon->cap.reserved_cqs =
  1943. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_cqs ) );
  1944. hermon->cap.cqc_entry_size = MLX_GET ( &dev_cap, cqc_entry_sz );
  1945. hermon->cap.reserved_eqs = MLX_GET ( &dev_cap, num_rsvd_eqs );
  1946. hermon->cap.eqc_entry_size = MLX_GET ( &dev_cap, eqc_entry_sz );
  1947. hermon->cap.reserved_mtts =
  1948. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_mtts ) );
  1949. hermon->cap.mtt_entry_size = MLX_GET ( &dev_cap, mtt_entry_sz );
  1950. hermon->cap.reserved_mrws =
  1951. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_mrws ) );
  1952. hermon->cap.dmpt_entry_size = MLX_GET ( &dev_cap, d_mpt_entry_sz );
  1953. hermon->cap.reserved_uars = MLX_GET ( &dev_cap, num_rsvd_uars );
  1954. hermon->cap.num_ports = MLX_GET ( &dev_cap, num_ports );
  1955. hermon->cap.dpdp = MLX_GET ( &dev_cap, dpdp );
  1956. /* Sanity check */
  1957. if ( hermon->cap.num_ports > HERMON_MAX_PORTS ) {
  1958. DBGC ( hermon, "Hermon %p has %d ports (only %d supported)\n",
  1959. hermon, hermon->cap.num_ports, HERMON_MAX_PORTS );
  1960. hermon->cap.num_ports = HERMON_MAX_PORTS;
  1961. }
  1962. return 0;
  1963. }
  1964. /**
  1965. * Get ICM usage
  1966. *
  1967. * @v log_num_entries Log2 of the number of entries
  1968. * @v entry_size Entry size
  1969. * @ret usage Usage size in ICM
  1970. */
  1971. static size_t icm_usage ( unsigned int log_num_entries, size_t entry_size ) {
  1972. size_t usage;
  1973. usage = ( ( 1 << log_num_entries ) * entry_size );
  1974. usage = ( ( usage + HERMON_PAGE_SIZE - 1 ) &
  1975. ~( HERMON_PAGE_SIZE - 1 ) );
  1976. return usage;
  1977. }
  1978. /**
  1979. * Allocate ICM
  1980. *
  1981. * @v hermon Hermon device
  1982. * @v init_hca INIT_HCA structure to fill in
  1983. * @ret rc Return status code
  1984. */
  1985. static int hermon_alloc_icm ( struct hermon *hermon,
  1986. struct hermonprm_init_hca *init_hca ) {
  1987. struct hermonprm_scalar_parameter icm_size;
  1988. struct hermonprm_scalar_parameter icm_aux_size;
  1989. uint64_t icm_offset = 0;
  1990. unsigned int log_num_qps, log_num_srqs, log_num_cqs, log_num_eqs;
  1991. unsigned int log_num_mtts, log_num_mpts;
  1992. size_t cmpt_max_len;
  1993. size_t qp_cmpt_len, srq_cmpt_len, cq_cmpt_len, eq_cmpt_len;
  1994. size_t icm_len, icm_aux_len;
  1995. physaddr_t icm_phys;
  1996. int i;
  1997. int rc;
  1998. /*
  1999. * Start by carving up the ICM virtual address space
  2000. *
  2001. */
  2002. /* Calculate number of each object type within ICM */
  2003. log_num_qps = fls ( hermon->cap.reserved_qps +
  2004. HERMON_RSVD_SPECIAL_QPS + HERMON_MAX_QPS - 1 );
  2005. log_num_srqs = fls ( hermon->cap.reserved_srqs - 1 );
  2006. log_num_cqs = fls ( hermon->cap.reserved_cqs + HERMON_MAX_CQS - 1 );
  2007. log_num_eqs = fls ( hermon->cap.reserved_eqs + HERMON_MAX_EQS - 1 );
  2008. log_num_mtts = fls ( hermon->cap.reserved_mtts + HERMON_MAX_MTTS - 1 );
  2009. /* ICM starts with the cMPT tables, which are sparse */
  2010. cmpt_max_len = ( HERMON_CMPT_MAX_ENTRIES *
  2011. ( ( uint64_t ) hermon->cap.cmpt_entry_size ) );
  2012. qp_cmpt_len = icm_usage ( log_num_qps, hermon->cap.cmpt_entry_size );
  2013. hermon->icm_map[HERMON_ICM_QP_CMPT].offset = icm_offset;
  2014. hermon->icm_map[HERMON_ICM_QP_CMPT].len = qp_cmpt_len;
  2015. icm_offset += cmpt_max_len;
  2016. srq_cmpt_len = icm_usage ( log_num_srqs, hermon->cap.cmpt_entry_size );
  2017. hermon->icm_map[HERMON_ICM_SRQ_CMPT].offset = icm_offset;
  2018. hermon->icm_map[HERMON_ICM_SRQ_CMPT].len = srq_cmpt_len;
  2019. icm_offset += cmpt_max_len;
  2020. cq_cmpt_len = icm_usage ( log_num_cqs, hermon->cap.cmpt_entry_size );
  2021. hermon->icm_map[HERMON_ICM_CQ_CMPT].offset = icm_offset;
  2022. hermon->icm_map[HERMON_ICM_CQ_CMPT].len = cq_cmpt_len;
  2023. icm_offset += cmpt_max_len;
  2024. eq_cmpt_len = icm_usage ( log_num_eqs, hermon->cap.cmpt_entry_size );
  2025. hermon->icm_map[HERMON_ICM_EQ_CMPT].offset = icm_offset;
  2026. hermon->icm_map[HERMON_ICM_EQ_CMPT].len = eq_cmpt_len;
  2027. icm_offset += cmpt_max_len;
  2028. hermon->icm_map[HERMON_ICM_OTHER].offset = icm_offset;
  2029. /* Queue pair contexts */
  2030. MLX_FILL_1 ( init_hca, 12,
  2031. qpc_eec_cqc_eqc_rdb_parameters.qpc_base_addr_h,
  2032. ( icm_offset >> 32 ) );
  2033. MLX_FILL_2 ( init_hca, 13,
  2034. qpc_eec_cqc_eqc_rdb_parameters.qpc_base_addr_l,
  2035. ( icm_offset >> 5 ),
  2036. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_qp,
  2037. log_num_qps );
  2038. DBGC ( hermon, "Hermon %p ICM QPC base = %llx\n", hermon, icm_offset );
  2039. icm_offset += icm_usage ( log_num_qps, hermon->cap.qpc_entry_size );
  2040. /* Extended alternate path contexts */
  2041. MLX_FILL_1 ( init_hca, 24,
  2042. qpc_eec_cqc_eqc_rdb_parameters.altc_base_addr_h,
  2043. ( icm_offset >> 32 ) );
  2044. MLX_FILL_1 ( init_hca, 25,
  2045. qpc_eec_cqc_eqc_rdb_parameters.altc_base_addr_l,
  2046. icm_offset );
  2047. DBGC ( hermon, "Hermon %p ICM ALTC base = %llx\n", hermon, icm_offset);
  2048. icm_offset += icm_usage ( log_num_qps,
  2049. hermon->cap.altc_entry_size );
  2050. /* Extended auxiliary contexts */
  2051. MLX_FILL_1 ( init_hca, 28,
  2052. qpc_eec_cqc_eqc_rdb_parameters.auxc_base_addr_h,
  2053. ( icm_offset >> 32 ) );
  2054. MLX_FILL_1 ( init_hca, 29,
  2055. qpc_eec_cqc_eqc_rdb_parameters.auxc_base_addr_l,
  2056. icm_offset );
  2057. DBGC ( hermon, "Hermon %p ICM AUXC base = %llx\n", hermon, icm_offset);
  2058. icm_offset += icm_usage ( log_num_qps,
  2059. hermon->cap.auxc_entry_size );
  2060. /* Shared receive queue contexts */
  2061. MLX_FILL_1 ( init_hca, 18,
  2062. qpc_eec_cqc_eqc_rdb_parameters.srqc_base_addr_h,
  2063. ( icm_offset >> 32 ) );
  2064. MLX_FILL_2 ( init_hca, 19,
  2065. qpc_eec_cqc_eqc_rdb_parameters.srqc_base_addr_l,
  2066. ( icm_offset >> 5 ),
  2067. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_srq,
  2068. log_num_srqs );
  2069. DBGC ( hermon, "Hermon %p ICM SRQC base = %llx\n", hermon, icm_offset);
  2070. icm_offset += icm_usage ( log_num_srqs,
  2071. hermon->cap.srqc_entry_size );
  2072. /* Completion queue contexts */
  2073. MLX_FILL_1 ( init_hca, 20,
  2074. qpc_eec_cqc_eqc_rdb_parameters.cqc_base_addr_h,
  2075. ( icm_offset >> 32 ) );
  2076. MLX_FILL_2 ( init_hca, 21,
  2077. qpc_eec_cqc_eqc_rdb_parameters.cqc_base_addr_l,
  2078. ( icm_offset >> 5 ),
  2079. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_cq,
  2080. log_num_cqs );
  2081. DBGC ( hermon, "Hermon %p ICM CQC base = %llx\n", hermon, icm_offset );
  2082. icm_offset += icm_usage ( log_num_cqs, hermon->cap.cqc_entry_size );
  2083. /* Event queue contexts */
  2084. MLX_FILL_1 ( init_hca, 32,
  2085. qpc_eec_cqc_eqc_rdb_parameters.eqc_base_addr_h,
  2086. ( icm_offset >> 32 ) );
  2087. MLX_FILL_2 ( init_hca, 33,
  2088. qpc_eec_cqc_eqc_rdb_parameters.eqc_base_addr_l,
  2089. ( icm_offset >> 5 ),
  2090. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_eq,
  2091. log_num_eqs );
  2092. DBGC ( hermon, "Hermon %p ICM EQC base = %llx\n", hermon, icm_offset );
  2093. icm_offset += icm_usage ( log_num_eqs, hermon->cap.eqc_entry_size );
  2094. /* Memory translation table */
  2095. MLX_FILL_1 ( init_hca, 64,
  2096. tpt_parameters.mtt_base_addr_h, ( icm_offset >> 32 ) );
  2097. MLX_FILL_1 ( init_hca, 65,
  2098. tpt_parameters.mtt_base_addr_l, icm_offset );
  2099. DBGC ( hermon, "Hermon %p ICM MTT base = %llx\n", hermon, icm_offset );
  2100. icm_offset += icm_usage ( log_num_mtts,
  2101. hermon->cap.mtt_entry_size );
  2102. /* Memory protection table */
  2103. log_num_mpts = fls ( hermon->cap.reserved_mrws + 1 - 1 );
  2104. MLX_FILL_1 ( init_hca, 60,
  2105. tpt_parameters.dmpt_base_adr_h, ( icm_offset >> 32 ) );
  2106. MLX_FILL_1 ( init_hca, 61,
  2107. tpt_parameters.dmpt_base_adr_l, icm_offset );
  2108. MLX_FILL_1 ( init_hca, 62,
  2109. tpt_parameters.log_dmpt_sz, log_num_mpts );
  2110. DBGC ( hermon, "Hermon %p ICM DMPT base = %llx\n", hermon, icm_offset);
  2111. icm_offset += icm_usage ( log_num_mpts,
  2112. hermon->cap.dmpt_entry_size );
  2113. /* Multicast table */
  2114. MLX_FILL_1 ( init_hca, 48,
  2115. multicast_parameters.mc_base_addr_h,
  2116. ( icm_offset >> 32 ) );
  2117. MLX_FILL_1 ( init_hca, 49,
  2118. multicast_parameters.mc_base_addr_l, icm_offset );
  2119. MLX_FILL_1 ( init_hca, 52,
  2120. multicast_parameters.log_mc_table_entry_sz,
  2121. fls ( sizeof ( struct hermonprm_mcg_entry ) - 1 ) );
  2122. MLX_FILL_1 ( init_hca, 53,
  2123. multicast_parameters.log_mc_table_hash_sz, 3 );
  2124. MLX_FILL_1 ( init_hca, 54,
  2125. multicast_parameters.log_mc_table_sz, 3 );
  2126. DBGC ( hermon, "Hermon %p ICM MC base = %llx\n", hermon, icm_offset );
  2127. icm_offset += ( ( 8 * sizeof ( struct hermonprm_mcg_entry ) +
  2128. HERMON_PAGE_SIZE - 1 ) & ~( HERMON_PAGE_SIZE - 1 ) );
  2129. hermon->icm_map[HERMON_ICM_OTHER].len =
  2130. ( icm_offset - hermon->icm_map[HERMON_ICM_OTHER].offset );
  2131. /*
  2132. * Allocate and map physical memory for (portions of) ICM
  2133. *
  2134. * Map is:
  2135. * ICM AUX area (aligned to its own size)
  2136. * cMPT areas
  2137. * Other areas
  2138. */
  2139. /* Calculate physical memory required for ICM */
  2140. icm_len = 0;
  2141. for ( i = 0 ; i < HERMON_ICM_NUM_REGIONS ; i++ ) {
  2142. icm_len += hermon->icm_map[i].len;
  2143. }
  2144. /* Get ICM auxiliary area size */
  2145. memset ( &icm_size, 0, sizeof ( icm_size ) );
  2146. MLX_FILL_1 ( &icm_size, 0, value_hi, ( icm_offset >> 32 ) );
  2147. MLX_FILL_1 ( &icm_size, 1, value, icm_offset );
  2148. if ( ( rc = hermon_cmd_set_icm_size ( hermon, &icm_size,
  2149. &icm_aux_size ) ) != 0 ) {
  2150. DBGC ( hermon, "Hermon %p could not set ICM size: %s\n",
  2151. hermon, strerror ( rc ) );
  2152. goto err_set_icm_size;
  2153. }
  2154. icm_aux_len = ( MLX_GET ( &icm_aux_size, value ) * HERMON_PAGE_SIZE );
  2155. /* Allocate ICM data and auxiliary area */
  2156. DBGC ( hermon, "Hermon %p requires %zd kB ICM and %zd kB AUX ICM\n",
  2157. hermon, ( icm_len / 1024 ), ( icm_aux_len / 1024 ) );
  2158. hermon->icm = umalloc ( icm_aux_len + icm_len );
  2159. if ( ! hermon->icm ) {
  2160. rc = -ENOMEM;
  2161. goto err_alloc;
  2162. }
  2163. icm_phys = user_to_phys ( hermon->icm, 0 );
  2164. /* Map ICM auxiliary area */
  2165. DBGC ( hermon, "Hermon %p mapping ICM AUX => %08lx\n",
  2166. hermon, icm_phys );
  2167. if ( ( rc = hermon_map_vpm ( hermon, hermon_cmd_map_icm_aux,
  2168. 0, icm_phys, icm_aux_len ) ) != 0 ) {
  2169. DBGC ( hermon, "Hermon %p could not map AUX ICM: %s\n",
  2170. hermon, strerror ( rc ) );
  2171. goto err_map_icm_aux;
  2172. }
  2173. icm_phys += icm_aux_len;
  2174. /* MAP ICM area */
  2175. for ( i = 0 ; i < HERMON_ICM_NUM_REGIONS ; i++ ) {
  2176. DBGC ( hermon, "Hermon %p mapping ICM %llx+%zx => %08lx\n",
  2177. hermon, hermon->icm_map[i].offset,
  2178. hermon->icm_map[i].len, icm_phys );
  2179. if ( ( rc = hermon_map_vpm ( hermon, hermon_cmd_map_icm,
  2180. hermon->icm_map[i].offset,
  2181. icm_phys,
  2182. hermon->icm_map[i].len ) ) != 0 ){
  2183. DBGC ( hermon, "Hermon %p could not map ICM: %s\n",
  2184. hermon, strerror ( rc ) );
  2185. goto err_map_icm;
  2186. }
  2187. icm_phys += hermon->icm_map[i].len;
  2188. }
  2189. return 0;
  2190. err_map_icm:
  2191. assert ( i == 0 ); /* We don't handle partial failure at present */
  2192. err_map_icm_aux:
  2193. hermon_cmd_unmap_icm_aux ( hermon );
  2194. ufree ( hermon->icm );
  2195. hermon->icm = UNULL;
  2196. err_alloc:
  2197. err_set_icm_size:
  2198. return rc;
  2199. }
  2200. /**
  2201. * Free ICM
  2202. *
  2203. * @v hermon Hermon device
  2204. */
  2205. static void hermon_free_icm ( struct hermon *hermon ) {
  2206. struct hermonprm_scalar_parameter unmap_icm;
  2207. int i;
  2208. for ( i = ( HERMON_ICM_NUM_REGIONS - 1 ) ; i >= 0 ; i-- ) {
  2209. memset ( &unmap_icm, 0, sizeof ( unmap_icm ) );
  2210. MLX_FILL_1 ( &unmap_icm, 0, value_hi,
  2211. ( hermon->icm_map[i].offset >> 32 ) );
  2212. MLX_FILL_1 ( &unmap_icm, 1, value,
  2213. hermon->icm_map[i].offset );
  2214. hermon_cmd_unmap_icm ( hermon,
  2215. ( 1 << fls ( ( hermon->icm_map[i].len /
  2216. HERMON_PAGE_SIZE ) - 1)),
  2217. &unmap_icm );
  2218. }
  2219. hermon_cmd_unmap_icm_aux ( hermon );
  2220. ufree ( hermon->icm );
  2221. hermon->icm = UNULL;
  2222. }
  2223. /***************************************************************************
  2224. *
  2225. * PCI interface
  2226. *
  2227. ***************************************************************************
  2228. */
  2229. /**
  2230. * Set up memory protection table
  2231. *
  2232. * @v hermon Hermon device
  2233. * @ret rc Return status code
  2234. */
  2235. static int hermon_setup_mpt ( struct hermon *hermon ) {
  2236. struct hermonprm_mpt mpt;
  2237. uint32_t key;
  2238. int rc;
  2239. /* Derive key */
  2240. key = ( hermon->cap.reserved_mrws | HERMON_MKEY_PREFIX );
  2241. hermon->lkey = ( ( key << 8 ) | ( key >> 24 ) );
  2242. /* Initialise memory protection table */
  2243. memset ( &mpt, 0, sizeof ( mpt ) );
  2244. MLX_FILL_7 ( &mpt, 0,
  2245. atomic, 1,
  2246. rw, 1,
  2247. rr, 1,
  2248. lw, 1,
  2249. lr, 1,
  2250. pa, 1,
  2251. r_w, 1 );
  2252. MLX_FILL_1 ( &mpt, 2, mem_key, key );
  2253. MLX_FILL_1 ( &mpt, 3,
  2254. pd, HERMON_GLOBAL_PD );
  2255. MLX_FILL_1 ( &mpt, 10, len64, 1 );
  2256. if ( ( rc = hermon_cmd_sw2hw_mpt ( hermon,
  2257. hermon->cap.reserved_mrws,
  2258. &mpt ) ) != 0 ) {
  2259. DBGC ( hermon, "Hermon %p could not set up MPT: %s\n",
  2260. hermon, strerror ( rc ) );
  2261. return rc;
  2262. }
  2263. return 0;
  2264. }
  2265. /**
  2266. * Configure special queue pairs
  2267. *
  2268. * @v hermon Hermon device
  2269. * @ret rc Return status code
  2270. */
  2271. static int hermon_configure_special_qps ( struct hermon *hermon ) {
  2272. int rc;
  2273. /* Special QP block must be aligned on its own size */
  2274. hermon->special_qpn_base = ( ( HERMON_QPN_BASE +
  2275. hermon->cap.reserved_qps +
  2276. HERMON_NUM_SPECIAL_QPS - 1 )
  2277. & ~( HERMON_NUM_SPECIAL_QPS - 1 ) );
  2278. hermon->qpn_base = ( hermon->special_qpn_base +
  2279. HERMON_NUM_SPECIAL_QPS );
  2280. DBGC ( hermon, "Hermon %p special QPs at [%lx,%lx]\n", hermon,
  2281. hermon->special_qpn_base, ( hermon->qpn_base - 1 ) );
  2282. /* Issue command to configure special QPs */
  2283. if ( ( rc = hermon_cmd_conf_special_qp ( hermon, 0x00,
  2284. hermon->special_qpn_base ) ) != 0 ) {
  2285. DBGC ( hermon, "Hermon %p could not configure special QPs: "
  2286. "%s\n", hermon, strerror ( rc ) );
  2287. return rc;
  2288. }
  2289. return 0;
  2290. }
  2291. /**
  2292. * Probe PCI device
  2293. *
  2294. * @v pci PCI device
  2295. * @v id PCI ID
  2296. * @ret rc Return status code
  2297. */
  2298. static int hermon_probe ( struct pci_device *pci,
  2299. const struct pci_device_id *id __unused ) {
  2300. struct hermon *hermon;
  2301. struct ib_device *ibdev;
  2302. struct hermonprm_init_hca init_hca;
  2303. unsigned int i;
  2304. int rc;
  2305. /* Allocate Hermon device */
  2306. hermon = zalloc ( sizeof ( *hermon ) );
  2307. if ( ! hermon ) {
  2308. rc = -ENOMEM;
  2309. goto err_alloc_hermon;
  2310. }
  2311. pci_set_drvdata ( pci, hermon );
  2312. /* Fix up PCI device */
  2313. adjust_pci_device ( pci );
  2314. /* Get PCI BARs */
  2315. hermon->config = ioremap ( pci_bar_start ( pci, HERMON_PCI_CONFIG_BAR),
  2316. HERMON_PCI_CONFIG_BAR_SIZE );
  2317. hermon->uar = ioremap ( pci_bar_start ( pci, HERMON_PCI_UAR_BAR ),
  2318. HERMON_UAR_NON_EQ_PAGE * HERMON_PAGE_SIZE );
  2319. /* Allocate space for mailboxes */
  2320. hermon->mailbox_in = malloc_dma ( HERMON_MBOX_SIZE,
  2321. HERMON_MBOX_ALIGN );
  2322. if ( ! hermon->mailbox_in ) {
  2323. rc = -ENOMEM;
  2324. goto err_mailbox_in;
  2325. }
  2326. hermon->mailbox_out = malloc_dma ( HERMON_MBOX_SIZE,
  2327. HERMON_MBOX_ALIGN );
  2328. if ( ! hermon->mailbox_out ) {
  2329. rc = -ENOMEM;
  2330. goto err_mailbox_out;
  2331. }
  2332. /* Start firmware */
  2333. if ( ( rc = hermon_start_firmware ( hermon ) ) != 0 )
  2334. goto err_start_firmware;
  2335. /* Get device limits */
  2336. if ( ( rc = hermon_get_cap ( hermon ) ) != 0 )
  2337. goto err_get_cap;
  2338. /* Allocate Infiniband devices */
  2339. for ( i = 0 ; i < hermon->cap.num_ports ; i++ ) {
  2340. ibdev = alloc_ibdev ( 0 );
  2341. if ( ! ibdev ) {
  2342. rc = -ENOMEM;
  2343. goto err_alloc_ibdev;
  2344. }
  2345. hermon->ibdev[i] = ibdev;
  2346. ibdev->op = &hermon_ib_operations;
  2347. ibdev->dev = &pci->dev;
  2348. ibdev->port = ( HERMON_PORT_BASE + i );
  2349. ib_set_drvdata ( ibdev, hermon );
  2350. }
  2351. /* Allocate ICM */
  2352. memset ( &init_hca, 0, sizeof ( init_hca ) );
  2353. if ( ( rc = hermon_alloc_icm ( hermon, &init_hca ) ) != 0 )
  2354. goto err_alloc_icm;
  2355. /* Initialise HCA */
  2356. MLX_FILL_1 ( &init_hca, 0, version, 0x02 /* "Must be 0x02" */ );
  2357. MLX_FILL_1 ( &init_hca, 5, udp, 1 );
  2358. MLX_FILL_1 ( &init_hca, 74, uar_parameters.log_max_uars, 8 );
  2359. if ( ( rc = hermon_cmd_init_hca ( hermon, &init_hca ) ) != 0 ) {
  2360. DBGC ( hermon, "Hermon %p could not initialise HCA: %s\n",
  2361. hermon, strerror ( rc ) );
  2362. goto err_init_hca;
  2363. }
  2364. /* Set up memory protection */
  2365. if ( ( rc = hermon_setup_mpt ( hermon ) ) != 0 )
  2366. goto err_setup_mpt;
  2367. for ( i = 0 ; i < hermon->cap.num_ports ; i++ )
  2368. hermon->ibdev[i]->rdma_key = hermon->lkey;
  2369. /* Set up event queue */
  2370. if ( ( rc = hermon_create_eq ( hermon ) ) != 0 )
  2371. goto err_create_eq;
  2372. /* Configure special QPs */
  2373. if ( ( rc = hermon_configure_special_qps ( hermon ) ) != 0 )
  2374. goto err_conf_special_qps;
  2375. /* Update IPoIB MAC address */
  2376. for ( i = 0 ; i < hermon->cap.num_ports ; i++ ) {
  2377. ib_smc_update ( hermon->ibdev[i], hermon_mad );
  2378. }
  2379. /* Register Infiniband devices */
  2380. for ( i = 0 ; i < hermon->cap.num_ports ; i++ ) {
  2381. if ( ( rc = register_ibdev ( hermon->ibdev[i] ) ) != 0 ) {
  2382. DBGC ( hermon, "Hermon %p could not register IB "
  2383. "device: %s\n", hermon, strerror ( rc ) );
  2384. goto err_register_ibdev;
  2385. }
  2386. }
  2387. return 0;
  2388. i = hermon->cap.num_ports;
  2389. err_register_ibdev:
  2390. for ( i-- ; ( signed int ) i >= 0 ; i-- )
  2391. unregister_ibdev ( hermon->ibdev[i] );
  2392. err_conf_special_qps:
  2393. hermon_destroy_eq ( hermon );
  2394. err_create_eq:
  2395. err_setup_mpt:
  2396. hermon_cmd_close_hca ( hermon );
  2397. err_init_hca:
  2398. hermon_free_icm ( hermon );
  2399. err_alloc_icm:
  2400. i = hermon->cap.num_ports;
  2401. err_alloc_ibdev:
  2402. for ( i-- ; ( signed int ) i >= 0 ; i-- )
  2403. ibdev_put ( hermon->ibdev[i] );
  2404. err_get_cap:
  2405. hermon_stop_firmware ( hermon );
  2406. err_start_firmware:
  2407. free_dma ( hermon->mailbox_out, HERMON_MBOX_SIZE );
  2408. err_mailbox_out:
  2409. free_dma ( hermon->mailbox_in, HERMON_MBOX_SIZE );
  2410. err_mailbox_in:
  2411. free ( hermon );
  2412. err_alloc_hermon:
  2413. return rc;
  2414. }
  2415. /**
  2416. * Remove PCI device
  2417. *
  2418. * @v pci PCI device
  2419. */
  2420. static void hermon_remove ( struct pci_device *pci ) {
  2421. struct hermon *hermon = pci_get_drvdata ( pci );
  2422. int i;
  2423. for ( i = ( hermon->cap.num_ports - 1 ) ; i >= 0 ; i-- )
  2424. unregister_ibdev ( hermon->ibdev[i] );
  2425. hermon_destroy_eq ( hermon );
  2426. hermon_cmd_close_hca ( hermon );
  2427. hermon_free_icm ( hermon );
  2428. hermon_stop_firmware ( hermon );
  2429. hermon_stop_firmware ( hermon );
  2430. free_dma ( hermon->mailbox_out, HERMON_MBOX_SIZE );
  2431. free_dma ( hermon->mailbox_in, HERMON_MBOX_SIZE );
  2432. for ( i = ( hermon->cap.num_ports - 1 ) ; i >= 0 ; i-- )
  2433. ibdev_put ( hermon->ibdev[i] );
  2434. free ( hermon );
  2435. }
  2436. static struct pci_device_id hermon_nics[] = {
  2437. PCI_ROM ( 0x15b3, 0x6340, "mt25408", "MT25408 HCA driver", 0 ),
  2438. PCI_ROM ( 0x15b3, 0x634a, "mt25418", "MT25418 HCA driver", 0 ),
  2439. PCI_ROM ( 0x15b3, 0x6732, "mt26418", "MT26418 HCA driver", 0 ),
  2440. PCI_ROM ( 0x15b3, 0x673c, "mt26428", "MT26428 HCA driver", 0 ),
  2441. };
  2442. struct pci_driver hermon_driver __pci_driver = {
  2443. .ids = hermon_nics,
  2444. .id_count = ( sizeof ( hermon_nics ) / sizeof ( hermon_nics[0] ) ),
  2445. .probe = hermon_probe,
  2446. .remove = hermon_remove,
  2447. };