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hermon.c 68KB

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  1. /*
  2. * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
  3. * Copyright (C) 2008 Mellanox Technologies Ltd.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License as
  7. * published by the Free Software Foundation; either version 2 of the
  8. * License, or any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18. */
  19. #include <stdint.h>
  20. #include <stdlib.h>
  21. #include <stdio.h>
  22. #include <string.h>
  23. #include <strings.h>
  24. #include <unistd.h>
  25. #include <errno.h>
  26. #include <byteswap.h>
  27. #include <gpxe/io.h>
  28. #include <gpxe/pci.h>
  29. #include <gpxe/malloc.h>
  30. #include <gpxe/umalloc.h>
  31. #include <gpxe/iobuf.h>
  32. #include <gpxe/netdevice.h>
  33. #include <gpxe/infiniband.h>
  34. #include <gpxe/ib_smc.h>
  35. #include "hermon.h"
  36. /**
  37. * @file
  38. *
  39. * Mellanox Hermon Infiniband HCA
  40. *
  41. */
  42. /***************************************************************************
  43. *
  44. * Queue number allocation
  45. *
  46. ***************************************************************************
  47. */
  48. /**
  49. * Allocate offsets within usage bitmask
  50. *
  51. * @v bits Usage bitmask
  52. * @v bits_len Length of usage bitmask
  53. * @v num_bits Number of contiguous bits to allocate within bitmask
  54. * @ret bit First free bit within bitmask, or negative error
  55. */
  56. static int hermon_bitmask_alloc ( hermon_bitmask_t *bits,
  57. unsigned int bits_len,
  58. unsigned int num_bits ) {
  59. unsigned int bit = 0;
  60. hermon_bitmask_t mask = 1;
  61. unsigned int found = 0;
  62. /* Search bits for num_bits contiguous free bits */
  63. while ( bit < bits_len ) {
  64. if ( ( mask & *bits ) == 0 ) {
  65. if ( ++found == num_bits )
  66. goto found;
  67. } else {
  68. found = 0;
  69. }
  70. bit++;
  71. mask = ( mask << 1 ) | ( mask >> ( 8 * sizeof ( mask ) - 1 ) );
  72. if ( mask == 1 )
  73. bits++;
  74. }
  75. return -ENFILE;
  76. found:
  77. /* Mark bits as in-use */
  78. do {
  79. *bits |= mask;
  80. if ( mask == 1 )
  81. bits--;
  82. mask = ( mask >> 1 ) | ( mask << ( 8 * sizeof ( mask ) - 1 ) );
  83. } while ( --found );
  84. return ( bit - num_bits + 1 );
  85. }
  86. /**
  87. * Free offsets within usage bitmask
  88. *
  89. * @v bits Usage bitmask
  90. * @v bit Starting bit within bitmask
  91. * @v num_bits Number of contiguous bits to free within bitmask
  92. */
  93. static void hermon_bitmask_free ( hermon_bitmask_t *bits,
  94. int bit, unsigned int num_bits ) {
  95. hermon_bitmask_t mask;
  96. for ( ; num_bits ; bit++, num_bits-- ) {
  97. mask = ( 1 << ( bit % ( 8 * sizeof ( mask ) ) ) );
  98. bits[ ( bit / ( 8 * sizeof ( mask ) ) ) ] &= ~mask;
  99. }
  100. }
  101. /***************************************************************************
  102. *
  103. * HCA commands
  104. *
  105. ***************************************************************************
  106. */
  107. /**
  108. * Wait for Hermon command completion
  109. *
  110. * @v hermon Hermon device
  111. * @v hcr HCA command registers
  112. * @ret rc Return status code
  113. */
  114. static int hermon_cmd_wait ( struct hermon *hermon,
  115. struct hermonprm_hca_command_register *hcr ) {
  116. unsigned int wait;
  117. for ( wait = HERMON_HCR_MAX_WAIT_MS ; wait ; wait-- ) {
  118. hcr->u.dwords[6] =
  119. readl ( hermon->config + HERMON_HCR_REG ( 6 ) );
  120. if ( ( MLX_GET ( hcr, go ) == 0 ) &&
  121. ( MLX_GET ( hcr, t ) == hermon->toggle ) )
  122. return 0;
  123. mdelay ( 1 );
  124. }
  125. return -EBUSY;
  126. }
  127. /**
  128. * Issue HCA command
  129. *
  130. * @v hermon Hermon device
  131. * @v command Command opcode, flags and input/output lengths
  132. * @v op_mod Opcode modifier (0 if no modifier applicable)
  133. * @v in Input parameters
  134. * @v in_mod Input modifier (0 if no modifier applicable)
  135. * @v out Output parameters
  136. * @ret rc Return status code
  137. */
  138. static int hermon_cmd ( struct hermon *hermon, unsigned long command,
  139. unsigned int op_mod, const void *in,
  140. unsigned int in_mod, void *out ) {
  141. struct hermonprm_hca_command_register hcr;
  142. unsigned int opcode = HERMON_HCR_OPCODE ( command );
  143. size_t in_len = HERMON_HCR_IN_LEN ( command );
  144. size_t out_len = HERMON_HCR_OUT_LEN ( command );
  145. void *in_buffer;
  146. void *out_buffer;
  147. unsigned int status;
  148. unsigned int i;
  149. int rc;
  150. assert ( in_len <= HERMON_MBOX_SIZE );
  151. assert ( out_len <= HERMON_MBOX_SIZE );
  152. DBGC2 ( hermon, "Hermon %p command %02x in %zx%s out %zx%s\n",
  153. hermon, opcode, in_len,
  154. ( ( command & HERMON_HCR_IN_MBOX ) ? "(mbox)" : "" ), out_len,
  155. ( ( command & HERMON_HCR_OUT_MBOX ) ? "(mbox)" : "" ) );
  156. /* Check that HCR is free */
  157. if ( ( rc = hermon_cmd_wait ( hermon, &hcr ) ) != 0 ) {
  158. DBGC ( hermon, "Hermon %p command interface locked\n",
  159. hermon );
  160. return rc;
  161. }
  162. /* Flip HCR toggle */
  163. hermon->toggle = ( 1 - hermon->toggle );
  164. /* Prepare HCR */
  165. memset ( &hcr, 0, sizeof ( hcr ) );
  166. in_buffer = &hcr.u.dwords[0];
  167. if ( in_len && ( command & HERMON_HCR_IN_MBOX ) ) {
  168. in_buffer = hermon->mailbox_in;
  169. MLX_FILL_1 ( &hcr, 1, in_param_l, virt_to_bus ( in_buffer ) );
  170. }
  171. memcpy ( in_buffer, in, in_len );
  172. MLX_FILL_1 ( &hcr, 2, input_modifier, in_mod );
  173. out_buffer = &hcr.u.dwords[3];
  174. if ( out_len && ( command & HERMON_HCR_OUT_MBOX ) ) {
  175. out_buffer = hermon->mailbox_out;
  176. MLX_FILL_1 ( &hcr, 4, out_param_l,
  177. virt_to_bus ( out_buffer ) );
  178. }
  179. MLX_FILL_4 ( &hcr, 6,
  180. opcode, opcode,
  181. opcode_modifier, op_mod,
  182. go, 1,
  183. t, hermon->toggle );
  184. DBGC ( hermon, "Hermon %p issuing command:\n", hermon );
  185. DBGC_HDA ( hermon, virt_to_phys ( hermon->config + HERMON_HCR_BASE ),
  186. &hcr, sizeof ( hcr ) );
  187. if ( in_len && ( command & HERMON_HCR_IN_MBOX ) ) {
  188. DBGC2 ( hermon, "Input mailbox:\n" );
  189. DBGC2_HDA ( hermon, virt_to_phys ( in_buffer ), in_buffer,
  190. ( ( in_len < 512 ) ? in_len : 512 ) );
  191. }
  192. /* Issue command */
  193. for ( i = 0 ; i < ( sizeof ( hcr ) / sizeof ( hcr.u.dwords[0] ) ) ;
  194. i++ ) {
  195. writel ( hcr.u.dwords[i],
  196. hermon->config + HERMON_HCR_REG ( i ) );
  197. barrier();
  198. }
  199. /* Wait for command completion */
  200. if ( ( rc = hermon_cmd_wait ( hermon, &hcr ) ) != 0 ) {
  201. DBGC ( hermon, "Hermon %p timed out waiting for command:\n",
  202. hermon );
  203. DBGC_HDA ( hermon,
  204. virt_to_phys ( hermon->config + HERMON_HCR_BASE ),
  205. &hcr, sizeof ( hcr ) );
  206. return rc;
  207. }
  208. /* Check command status */
  209. status = MLX_GET ( &hcr, status );
  210. if ( status != 0 ) {
  211. DBGC ( hermon, "Hermon %p command failed with status %02x:\n",
  212. hermon, status );
  213. DBGC_HDA ( hermon,
  214. virt_to_phys ( hermon->config + HERMON_HCR_BASE ),
  215. &hcr, sizeof ( hcr ) );
  216. return -EIO;
  217. }
  218. /* Read output parameters, if any */
  219. hcr.u.dwords[3] = readl ( hermon->config + HERMON_HCR_REG ( 3 ) );
  220. hcr.u.dwords[4] = readl ( hermon->config + HERMON_HCR_REG ( 4 ) );
  221. memcpy ( out, out_buffer, out_len );
  222. if ( out_len ) {
  223. DBGC2 ( hermon, "Output%s:\n",
  224. ( command & HERMON_HCR_OUT_MBOX ) ? " mailbox" : "" );
  225. DBGC2_HDA ( hermon, virt_to_phys ( out_buffer ), out_buffer,
  226. ( ( out_len < 512 ) ? out_len : 512 ) );
  227. }
  228. return 0;
  229. }
  230. static inline int
  231. hermon_cmd_query_dev_cap ( struct hermon *hermon,
  232. struct hermonprm_query_dev_cap *dev_cap ) {
  233. return hermon_cmd ( hermon,
  234. HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_DEV_CAP,
  235. 1, sizeof ( *dev_cap ) ),
  236. 0, NULL, 0, dev_cap );
  237. }
  238. static inline int
  239. hermon_cmd_query_fw ( struct hermon *hermon, struct hermonprm_query_fw *fw ) {
  240. return hermon_cmd ( hermon,
  241. HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_FW,
  242. 1, sizeof ( *fw ) ),
  243. 0, NULL, 0, fw );
  244. }
  245. static inline int
  246. hermon_cmd_init_hca ( struct hermon *hermon,
  247. const struct hermonprm_init_hca *init_hca ) {
  248. return hermon_cmd ( hermon,
  249. HERMON_HCR_IN_CMD ( HERMON_HCR_INIT_HCA,
  250. 1, sizeof ( *init_hca ) ),
  251. 0, init_hca, 0, NULL );
  252. }
  253. static inline int
  254. hermon_cmd_close_hca ( struct hermon *hermon ) {
  255. return hermon_cmd ( hermon,
  256. HERMON_HCR_VOID_CMD ( HERMON_HCR_CLOSE_HCA ),
  257. 0, NULL, 0, NULL );
  258. }
  259. static inline int
  260. hermon_cmd_init_port ( struct hermon *hermon, unsigned int port,
  261. const struct hermonprm_init_port *init_port ) {
  262. return hermon_cmd ( hermon,
  263. HERMON_HCR_IN_CMD ( HERMON_HCR_INIT_PORT,
  264. 1, sizeof ( *init_port ) ),
  265. 0, init_port, port, NULL );
  266. }
  267. static inline int
  268. hermon_cmd_close_port ( struct hermon *hermon, unsigned int port ) {
  269. return hermon_cmd ( hermon,
  270. HERMON_HCR_VOID_CMD ( HERMON_HCR_CLOSE_PORT ),
  271. 0, NULL, port, NULL );
  272. }
  273. static inline int
  274. hermon_cmd_sw2hw_mpt ( struct hermon *hermon, unsigned int index,
  275. const struct hermonprm_mpt *mpt ) {
  276. return hermon_cmd ( hermon,
  277. HERMON_HCR_IN_CMD ( HERMON_HCR_SW2HW_MPT,
  278. 1, sizeof ( *mpt ) ),
  279. 0, mpt, index, NULL );
  280. }
  281. static inline int
  282. hermon_cmd_write_mtt ( struct hermon *hermon,
  283. const struct hermonprm_write_mtt *write_mtt ) {
  284. return hermon_cmd ( hermon,
  285. HERMON_HCR_IN_CMD ( HERMON_HCR_WRITE_MTT,
  286. 1, sizeof ( *write_mtt ) ),
  287. 0, write_mtt, 1, NULL );
  288. }
  289. static inline int
  290. hermon_cmd_map_eq ( struct hermon *hermon, unsigned long index_map,
  291. const struct hermonprm_event_mask *mask ) {
  292. return hermon_cmd ( hermon,
  293. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_EQ,
  294. 0, sizeof ( *mask ) ),
  295. 0, mask, index_map, NULL );
  296. }
  297. static inline int
  298. hermon_cmd_sw2hw_eq ( struct hermon *hermon, unsigned int index,
  299. const struct hermonprm_eqc *eqctx ) {
  300. return hermon_cmd ( hermon,
  301. HERMON_HCR_IN_CMD ( HERMON_HCR_SW2HW_EQ,
  302. 1, sizeof ( *eqctx ) ),
  303. 0, eqctx, index, NULL );
  304. }
  305. static inline int
  306. hermon_cmd_hw2sw_eq ( struct hermon *hermon, unsigned int index,
  307. struct hermonprm_eqc *eqctx ) {
  308. return hermon_cmd ( hermon,
  309. HERMON_HCR_OUT_CMD ( HERMON_HCR_HW2SW_EQ,
  310. 1, sizeof ( *eqctx ) ),
  311. 1, NULL, index, eqctx );
  312. }
  313. static inline int
  314. hermon_cmd_query_eq ( struct hermon *hermon, unsigned int index,
  315. struct hermonprm_eqc *eqctx ) {
  316. return hermon_cmd ( hermon,
  317. HERMON_HCR_OUT_CMD ( HERMON_HCR_QUERY_EQ,
  318. 1, sizeof ( *eqctx ) ),
  319. 0, NULL, index, eqctx );
  320. }
  321. static inline int
  322. hermon_cmd_sw2hw_cq ( struct hermon *hermon, unsigned long cqn,
  323. const struct hermonprm_completion_queue_context *cqctx ){
  324. return hermon_cmd ( hermon,
  325. HERMON_HCR_IN_CMD ( HERMON_HCR_SW2HW_CQ,
  326. 1, sizeof ( *cqctx ) ),
  327. 0, cqctx, cqn, NULL );
  328. }
  329. static inline int
  330. hermon_cmd_hw2sw_cq ( struct hermon *hermon, unsigned long cqn,
  331. struct hermonprm_completion_queue_context *cqctx) {
  332. return hermon_cmd ( hermon,
  333. HERMON_HCR_OUT_CMD ( HERMON_HCR_HW2SW_CQ,
  334. 1, sizeof ( *cqctx ) ),
  335. 0, NULL, cqn, cqctx );
  336. }
  337. static inline int
  338. hermon_cmd_rst2init_qp ( struct hermon *hermon, unsigned long qpn,
  339. const struct hermonprm_qp_ee_state_transitions *ctx ){
  340. return hermon_cmd ( hermon,
  341. HERMON_HCR_IN_CMD ( HERMON_HCR_RST2INIT_QP,
  342. 1, sizeof ( *ctx ) ),
  343. 0, ctx, qpn, NULL );
  344. }
  345. static inline int
  346. hermon_cmd_init2rtr_qp ( struct hermon *hermon, unsigned long qpn,
  347. const struct hermonprm_qp_ee_state_transitions *ctx ){
  348. return hermon_cmd ( hermon,
  349. HERMON_HCR_IN_CMD ( HERMON_HCR_INIT2RTR_QP,
  350. 1, sizeof ( *ctx ) ),
  351. 0, ctx, qpn, NULL );
  352. }
  353. static inline int
  354. hermon_cmd_rtr2rts_qp ( struct hermon *hermon, unsigned long qpn,
  355. const struct hermonprm_qp_ee_state_transitions *ctx ) {
  356. return hermon_cmd ( hermon,
  357. HERMON_HCR_IN_CMD ( HERMON_HCR_RTR2RTS_QP,
  358. 1, sizeof ( *ctx ) ),
  359. 0, ctx, qpn, NULL );
  360. }
  361. static inline int
  362. hermon_cmd_rts2rts_qp ( struct hermon *hermon, unsigned long qpn,
  363. const struct hermonprm_qp_ee_state_transitions *ctx ) {
  364. return hermon_cmd ( hermon,
  365. HERMON_HCR_IN_CMD ( HERMON_HCR_RTS2RTS_QP,
  366. 1, sizeof ( *ctx ) ),
  367. 0, ctx, qpn, NULL );
  368. }
  369. static inline int
  370. hermon_cmd_2rst_qp ( struct hermon *hermon, unsigned long qpn ) {
  371. return hermon_cmd ( hermon,
  372. HERMON_HCR_VOID_CMD ( HERMON_HCR_2RST_QP ),
  373. 0x03, NULL, qpn, NULL );
  374. }
  375. static inline int
  376. hermon_cmd_mad_ifc ( struct hermon *hermon, unsigned int port,
  377. union hermonprm_mad *mad ) {
  378. return hermon_cmd ( hermon,
  379. HERMON_HCR_INOUT_CMD ( HERMON_HCR_MAD_IFC,
  380. 1, sizeof ( *mad ),
  381. 1, sizeof ( *mad ) ),
  382. 0x03, mad, port, mad );
  383. }
  384. static inline int
  385. hermon_cmd_read_mcg ( struct hermon *hermon, unsigned int index,
  386. struct hermonprm_mcg_entry *mcg ) {
  387. return hermon_cmd ( hermon,
  388. HERMON_HCR_OUT_CMD ( HERMON_HCR_READ_MCG,
  389. 1, sizeof ( *mcg ) ),
  390. 0, NULL, index, mcg );
  391. }
  392. static inline int
  393. hermon_cmd_write_mcg ( struct hermon *hermon, unsigned int index,
  394. const struct hermonprm_mcg_entry *mcg ) {
  395. return hermon_cmd ( hermon,
  396. HERMON_HCR_IN_CMD ( HERMON_HCR_WRITE_MCG,
  397. 1, sizeof ( *mcg ) ),
  398. 0, mcg, index, NULL );
  399. }
  400. static inline int
  401. hermon_cmd_mgid_hash ( struct hermon *hermon, const struct ib_gid *gid,
  402. struct hermonprm_mgm_hash *hash ) {
  403. return hermon_cmd ( hermon,
  404. HERMON_HCR_INOUT_CMD ( HERMON_HCR_MGID_HASH,
  405. 1, sizeof ( *gid ),
  406. 0, sizeof ( *hash ) ),
  407. 0, gid, 0, hash );
  408. }
  409. static inline int
  410. hermon_cmd_run_fw ( struct hermon *hermon ) {
  411. return hermon_cmd ( hermon,
  412. HERMON_HCR_VOID_CMD ( HERMON_HCR_RUN_FW ),
  413. 0, NULL, 0, NULL );
  414. }
  415. static inline int
  416. hermon_cmd_unmap_icm ( struct hermon *hermon, unsigned int page_count,
  417. const struct hermonprm_scalar_parameter *offset ) {
  418. return hermon_cmd ( hermon,
  419. HERMON_HCR_IN_CMD ( HERMON_HCR_UNMAP_ICM,
  420. 0, sizeof ( *offset ) ),
  421. 0, offset, page_count, NULL );
  422. }
  423. static inline int
  424. hermon_cmd_map_icm ( struct hermon *hermon,
  425. const struct hermonprm_virtual_physical_mapping *map ) {
  426. return hermon_cmd ( hermon,
  427. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_ICM,
  428. 1, sizeof ( *map ) ),
  429. 0, map, 1, NULL );
  430. }
  431. static inline int
  432. hermon_cmd_unmap_icm_aux ( struct hermon *hermon ) {
  433. return hermon_cmd ( hermon,
  434. HERMON_HCR_VOID_CMD ( HERMON_HCR_UNMAP_ICM_AUX ),
  435. 0, NULL, 0, NULL );
  436. }
  437. static inline int
  438. hermon_cmd_map_icm_aux ( struct hermon *hermon,
  439. const struct hermonprm_virtual_physical_mapping *map ) {
  440. return hermon_cmd ( hermon,
  441. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_ICM_AUX,
  442. 1, sizeof ( *map ) ),
  443. 0, map, 1, NULL );
  444. }
  445. static inline int
  446. hermon_cmd_set_icm_size ( struct hermon *hermon,
  447. const struct hermonprm_scalar_parameter *icm_size,
  448. struct hermonprm_scalar_parameter *icm_aux_size ) {
  449. return hermon_cmd ( hermon,
  450. HERMON_HCR_INOUT_CMD ( HERMON_HCR_SET_ICM_SIZE,
  451. 0, sizeof ( *icm_size ),
  452. 0, sizeof (*icm_aux_size) ),
  453. 0, icm_size, 0, icm_aux_size );
  454. }
  455. static inline int
  456. hermon_cmd_unmap_fa ( struct hermon *hermon ) {
  457. return hermon_cmd ( hermon,
  458. HERMON_HCR_VOID_CMD ( HERMON_HCR_UNMAP_FA ),
  459. 0, NULL, 0, NULL );
  460. }
  461. static inline int
  462. hermon_cmd_map_fa ( struct hermon *hermon,
  463. const struct hermonprm_virtual_physical_mapping *map ) {
  464. return hermon_cmd ( hermon,
  465. HERMON_HCR_IN_CMD ( HERMON_HCR_MAP_FA,
  466. 1, sizeof ( *map ) ),
  467. 0, map, 1, NULL );
  468. }
  469. /***************************************************************************
  470. *
  471. * Memory translation table operations
  472. *
  473. ***************************************************************************
  474. */
  475. /**
  476. * Allocate MTT entries
  477. *
  478. * @v hermon Hermon device
  479. * @v memory Memory to map into MTT
  480. * @v len Length of memory to map
  481. * @v mtt MTT descriptor to fill in
  482. * @ret rc Return status code
  483. */
  484. static int hermon_alloc_mtt ( struct hermon *hermon,
  485. const void *memory, size_t len,
  486. struct hermon_mtt *mtt ) {
  487. struct hermonprm_write_mtt write_mtt;
  488. physaddr_t start;
  489. unsigned int page_offset;
  490. unsigned int num_pages;
  491. int mtt_offset;
  492. unsigned int mtt_base_addr;
  493. unsigned int i;
  494. int rc;
  495. /* Find available MTT entries */
  496. start = virt_to_phys ( memory );
  497. page_offset = ( start & ( HERMON_PAGE_SIZE - 1 ) );
  498. start -= page_offset;
  499. len += page_offset;
  500. num_pages = ( ( len + HERMON_PAGE_SIZE - 1 ) / HERMON_PAGE_SIZE );
  501. mtt_offset = hermon_bitmask_alloc ( hermon->mtt_inuse, HERMON_MAX_MTTS,
  502. num_pages );
  503. if ( mtt_offset < 0 ) {
  504. DBGC ( hermon, "Hermon %p could not allocate %d MTT entries\n",
  505. hermon, num_pages );
  506. rc = mtt_offset;
  507. goto err_mtt_offset;
  508. }
  509. mtt_base_addr = ( ( hermon->cap.reserved_mtts + mtt_offset ) *
  510. hermon->cap.mtt_entry_size );
  511. /* Fill in MTT structure */
  512. mtt->mtt_offset = mtt_offset;
  513. mtt->num_pages = num_pages;
  514. mtt->mtt_base_addr = mtt_base_addr;
  515. mtt->page_offset = page_offset;
  516. /* Construct and issue WRITE_MTT commands */
  517. for ( i = 0 ; i < num_pages ; i++ ) {
  518. memset ( &write_mtt, 0, sizeof ( write_mtt ) );
  519. MLX_FILL_1 ( &write_mtt.mtt_base_addr, 1,
  520. value, mtt_base_addr );
  521. MLX_FILL_2 ( &write_mtt.mtt, 1,
  522. p, 1,
  523. ptag_l, ( start >> 3 ) );
  524. if ( ( rc = hermon_cmd_write_mtt ( hermon,
  525. &write_mtt ) ) != 0 ) {
  526. DBGC ( hermon, "Hermon %p could not write MTT at %x\n",
  527. hermon, mtt_base_addr );
  528. goto err_write_mtt;
  529. }
  530. start += HERMON_PAGE_SIZE;
  531. mtt_base_addr += hermon->cap.mtt_entry_size;
  532. }
  533. return 0;
  534. err_write_mtt:
  535. hermon_bitmask_free ( hermon->mtt_inuse, mtt_offset, num_pages );
  536. err_mtt_offset:
  537. return rc;
  538. }
  539. /**
  540. * Free MTT entries
  541. *
  542. * @v hermon Hermon device
  543. * @v mtt MTT descriptor
  544. */
  545. static void hermon_free_mtt ( struct hermon *hermon,
  546. struct hermon_mtt *mtt ) {
  547. hermon_bitmask_free ( hermon->mtt_inuse, mtt->mtt_offset,
  548. mtt->num_pages );
  549. }
  550. /***************************************************************************
  551. *
  552. * MAD operations
  553. *
  554. ***************************************************************************
  555. */
  556. /**
  557. * Issue management datagram
  558. *
  559. * @v ibdev Infiniband device
  560. * @v mad Management datagram
  561. * @ret rc Return status code
  562. */
  563. static int hermon_mad ( struct ib_device *ibdev, union ib_mad *mad ) {
  564. struct hermon *hermon = ib_get_drvdata ( ibdev );
  565. union hermonprm_mad mad_ifc;
  566. int rc;
  567. linker_assert ( sizeof ( *mad ) == sizeof ( mad_ifc.mad ),
  568. mad_size_mismatch );
  569. /* Copy in request packet */
  570. memcpy ( &mad_ifc.mad, mad, sizeof ( mad_ifc.mad ) );
  571. /* Issue MAD */
  572. if ( ( rc = hermon_cmd_mad_ifc ( hermon, ibdev->port,
  573. &mad_ifc ) ) != 0 ) {
  574. DBGC ( hermon, "Hermon %p could not issue MAD IFC: %s\n",
  575. hermon, strerror ( rc ) );
  576. return rc;
  577. }
  578. /* Copy out reply packet */
  579. memcpy ( mad, &mad_ifc.mad, sizeof ( *mad ) );
  580. if ( mad->hdr.status != 0 ) {
  581. DBGC ( hermon, "Hermon %p MAD IFC status %04x\n",
  582. hermon, ntohs ( mad->hdr.status ) );
  583. return -EIO;
  584. }
  585. return 0;
  586. }
  587. /***************************************************************************
  588. *
  589. * Completion queue operations
  590. *
  591. ***************************************************************************
  592. */
  593. /**
  594. * Create completion queue
  595. *
  596. * @v ibdev Infiniband device
  597. * @v cq Completion queue
  598. * @ret rc Return status code
  599. */
  600. static int hermon_create_cq ( struct ib_device *ibdev,
  601. struct ib_completion_queue *cq ) {
  602. struct hermon *hermon = ib_get_drvdata ( ibdev );
  603. struct hermon_completion_queue *hermon_cq;
  604. struct hermonprm_completion_queue_context cqctx;
  605. int cqn_offset;
  606. unsigned int i;
  607. int rc;
  608. /* Find a free completion queue number */
  609. cqn_offset = hermon_bitmask_alloc ( hermon->cq_inuse,
  610. HERMON_MAX_CQS, 1 );
  611. if ( cqn_offset < 0 ) {
  612. DBGC ( hermon, "Hermon %p out of completion queues\n",
  613. hermon );
  614. rc = cqn_offset;
  615. goto err_cqn_offset;
  616. }
  617. cq->cqn = ( hermon->cap.reserved_cqs + cqn_offset );
  618. /* Allocate control structures */
  619. hermon_cq = zalloc ( sizeof ( *hermon_cq ) );
  620. if ( ! hermon_cq ) {
  621. rc = -ENOMEM;
  622. goto err_hermon_cq;
  623. }
  624. /* Allocate completion queue itself */
  625. hermon_cq->cqe_size = ( cq->num_cqes * sizeof ( hermon_cq->cqe[0] ) );
  626. hermon_cq->cqe = malloc_dma ( hermon_cq->cqe_size,
  627. sizeof ( hermon_cq->cqe[0] ) );
  628. if ( ! hermon_cq->cqe ) {
  629. rc = -ENOMEM;
  630. goto err_cqe;
  631. }
  632. memset ( hermon_cq->cqe, 0, hermon_cq->cqe_size );
  633. for ( i = 0 ; i < cq->num_cqes ; i++ ) {
  634. MLX_FILL_1 ( &hermon_cq->cqe[i].normal, 7, owner, 1 );
  635. }
  636. barrier();
  637. /* Allocate MTT entries */
  638. if ( ( rc = hermon_alloc_mtt ( hermon, hermon_cq->cqe,
  639. hermon_cq->cqe_size,
  640. &hermon_cq->mtt ) ) != 0 )
  641. goto err_alloc_mtt;
  642. /* Hand queue over to hardware */
  643. memset ( &cqctx, 0, sizeof ( cqctx ) );
  644. MLX_FILL_1 ( &cqctx, 0, st, 0xa /* "Event fired" */ );
  645. MLX_FILL_1 ( &cqctx, 2,
  646. page_offset, ( hermon_cq->mtt.page_offset >> 5 ) );
  647. MLX_FILL_2 ( &cqctx, 3,
  648. usr_page, HERMON_UAR_NON_EQ_PAGE,
  649. log_cq_size, fls ( cq->num_cqes - 1 ) );
  650. MLX_FILL_1 ( &cqctx, 7, mtt_base_addr_l,
  651. ( hermon_cq->mtt.mtt_base_addr >> 3 ) );
  652. MLX_FILL_1 ( &cqctx, 15, db_record_addr_l,
  653. ( virt_to_phys ( &hermon_cq->doorbell ) >> 3 ) );
  654. if ( ( rc = hermon_cmd_sw2hw_cq ( hermon, cq->cqn, &cqctx ) ) != 0 ) {
  655. DBGC ( hermon, "Hermon %p SW2HW_CQ failed: %s\n",
  656. hermon, strerror ( rc ) );
  657. goto err_sw2hw_cq;
  658. }
  659. DBGC ( hermon, "Hermon %p CQN %#lx ring at [%p,%p)\n",
  660. hermon, cq->cqn, hermon_cq->cqe,
  661. ( ( ( void * ) hermon_cq->cqe ) + hermon_cq->cqe_size ) );
  662. ib_cq_set_drvdata ( cq, hermon_cq );
  663. return 0;
  664. err_sw2hw_cq:
  665. hermon_free_mtt ( hermon, &hermon_cq->mtt );
  666. err_alloc_mtt:
  667. free_dma ( hermon_cq->cqe, hermon_cq->cqe_size );
  668. err_cqe:
  669. free ( hermon_cq );
  670. err_hermon_cq:
  671. hermon_bitmask_free ( hermon->cq_inuse, cqn_offset, 1 );
  672. err_cqn_offset:
  673. return rc;
  674. }
  675. /**
  676. * Destroy completion queue
  677. *
  678. * @v ibdev Infiniband device
  679. * @v cq Completion queue
  680. */
  681. static void hermon_destroy_cq ( struct ib_device *ibdev,
  682. struct ib_completion_queue *cq ) {
  683. struct hermon *hermon = ib_get_drvdata ( ibdev );
  684. struct hermon_completion_queue *hermon_cq = ib_cq_get_drvdata ( cq );
  685. struct hermonprm_completion_queue_context cqctx;
  686. int cqn_offset;
  687. int rc;
  688. /* Take ownership back from hardware */
  689. if ( ( rc = hermon_cmd_hw2sw_cq ( hermon, cq->cqn, &cqctx ) ) != 0 ) {
  690. DBGC ( hermon, "Hermon %p FATAL HW2SW_CQ failed on CQN %#lx: "
  691. "%s\n", hermon, cq->cqn, strerror ( rc ) );
  692. /* Leak memory and return; at least we avoid corruption */
  693. return;
  694. }
  695. /* Free MTT entries */
  696. hermon_free_mtt ( hermon, &hermon_cq->mtt );
  697. /* Free memory */
  698. free_dma ( hermon_cq->cqe, hermon_cq->cqe_size );
  699. free ( hermon_cq );
  700. /* Mark queue number as free */
  701. cqn_offset = ( cq->cqn - hermon->cap.reserved_cqs );
  702. hermon_bitmask_free ( hermon->cq_inuse, cqn_offset, 1 );
  703. ib_cq_set_drvdata ( cq, NULL );
  704. }
  705. /***************************************************************************
  706. *
  707. * Queue pair operations
  708. *
  709. ***************************************************************************
  710. */
  711. /**
  712. * Create queue pair
  713. *
  714. * @v ibdev Infiniband device
  715. * @v qp Queue pair
  716. * @ret rc Return status code
  717. */
  718. static int hermon_create_qp ( struct ib_device *ibdev,
  719. struct ib_queue_pair *qp ) {
  720. struct hermon *hermon = ib_get_drvdata ( ibdev );
  721. struct hermon_queue_pair *hermon_qp;
  722. struct hermonprm_qp_ee_state_transitions qpctx;
  723. int qpn_offset;
  724. int rc;
  725. /* Find a free queue pair number */
  726. qpn_offset = hermon_bitmask_alloc ( hermon->qp_inuse,
  727. HERMON_MAX_QPS, 1 );
  728. if ( qpn_offset < 0 ) {
  729. DBGC ( hermon, "Hermon %p out of queue pairs\n", hermon );
  730. rc = qpn_offset;
  731. goto err_qpn_offset;
  732. }
  733. qp->qpn = ( HERMON_QPN_BASE + hermon->cap.reserved_qps +
  734. qpn_offset );
  735. /* Allocate control structures */
  736. hermon_qp = zalloc ( sizeof ( *hermon_qp ) );
  737. if ( ! hermon_qp ) {
  738. rc = -ENOMEM;
  739. goto err_hermon_qp;
  740. }
  741. /* Calculate doorbell address */
  742. hermon_qp->send.doorbell =
  743. ( hermon->uar + HERMON_UAR_NON_EQ_PAGE * HERMON_PAGE_SIZE +
  744. HERMON_DB_POST_SND_OFFSET );
  745. /* Allocate work queue buffer */
  746. hermon_qp->send.num_wqes = ( qp->send.num_wqes /* headroom */ + 1 +
  747. ( 2048 / sizeof ( hermon_qp->send.wqe[0] ) ) );
  748. hermon_qp->send.num_wqes =
  749. ( 1 << fls ( hermon_qp->send.num_wqes - 1 ) ); /* round up */
  750. hermon_qp->send.wqe_size = ( hermon_qp->send.num_wqes *
  751. sizeof ( hermon_qp->send.wqe[0] ) );
  752. hermon_qp->recv.wqe_size = ( qp->recv.num_wqes *
  753. sizeof ( hermon_qp->recv.wqe[0] ) );
  754. hermon_qp->wqe_size = ( hermon_qp->send.wqe_size +
  755. hermon_qp->recv.wqe_size );
  756. hermon_qp->wqe = malloc_dma ( hermon_qp->wqe_size,
  757. sizeof ( hermon_qp->send.wqe[0] ) );
  758. if ( ! hermon_qp->wqe ) {
  759. rc = -ENOMEM;
  760. goto err_alloc_wqe;
  761. }
  762. hermon_qp->send.wqe = hermon_qp->wqe;
  763. memset ( hermon_qp->send.wqe, 0xff, hermon_qp->send.wqe_size );
  764. hermon_qp->recv.wqe = ( hermon_qp->wqe + hermon_qp->send.wqe_size );
  765. memset ( hermon_qp->recv.wqe, 0, hermon_qp->recv.wqe_size );
  766. /* Allocate MTT entries */
  767. if ( ( rc = hermon_alloc_mtt ( hermon, hermon_qp->wqe,
  768. hermon_qp->wqe_size,
  769. &hermon_qp->mtt ) ) != 0 ) {
  770. goto err_alloc_mtt;
  771. }
  772. /* Transition queue to INIT state */
  773. memset ( &qpctx, 0, sizeof ( qpctx ) );
  774. MLX_FILL_2 ( &qpctx, 2,
  775. qpc_eec_data.pm_state, 0x03 /* Always 0x03 for UD */,
  776. qpc_eec_data.st, HERMON_ST_UD );
  777. MLX_FILL_1 ( &qpctx, 3, qpc_eec_data.pd, HERMON_GLOBAL_PD );
  778. MLX_FILL_4 ( &qpctx, 4,
  779. qpc_eec_data.log_rq_size, fls ( qp->recv.num_wqes - 1 ),
  780. qpc_eec_data.log_rq_stride,
  781. ( fls ( sizeof ( hermon_qp->recv.wqe[0] ) - 1 ) - 4 ),
  782. qpc_eec_data.log_sq_size,
  783. fls ( hermon_qp->send.num_wqes - 1 ),
  784. qpc_eec_data.log_sq_stride,
  785. ( fls ( sizeof ( hermon_qp->send.wqe[0] ) - 1 ) - 4 ) );
  786. MLX_FILL_1 ( &qpctx, 5,
  787. qpc_eec_data.usr_page, HERMON_UAR_NON_EQ_PAGE );
  788. MLX_FILL_1 ( &qpctx, 33, qpc_eec_data.cqn_snd, qp->send.cq->cqn );
  789. MLX_FILL_1 ( &qpctx, 38, qpc_eec_data.page_offset,
  790. ( hermon_qp->mtt.page_offset >> 6 ) );
  791. MLX_FILL_1 ( &qpctx, 41, qpc_eec_data.cqn_rcv, qp->recv.cq->cqn );
  792. MLX_FILL_1 ( &qpctx, 43, qpc_eec_data.db_record_addr_l,
  793. ( virt_to_phys ( &hermon_qp->recv.doorbell ) >> 2 ) );
  794. MLX_FILL_1 ( &qpctx, 44, qpc_eec_data.q_key, qp->qkey );
  795. MLX_FILL_1 ( &qpctx, 53, qpc_eec_data.mtt_base_addr_l,
  796. ( hermon_qp->mtt.mtt_base_addr >> 3 ) );
  797. if ( ( rc = hermon_cmd_rst2init_qp ( hermon, qp->qpn,
  798. &qpctx ) ) != 0 ) {
  799. DBGC ( hermon, "Hermon %p RST2INIT_QP failed: %s\n",
  800. hermon, strerror ( rc ) );
  801. goto err_rst2init_qp;
  802. }
  803. /* Transition queue to RTR state */
  804. memset ( &qpctx, 0, sizeof ( qpctx ) );
  805. MLX_FILL_2 ( &qpctx, 4,
  806. qpc_eec_data.mtu, HERMON_MTU_2048,
  807. qpc_eec_data.msg_max, 11 /* 2^11 = 2048 */ );
  808. MLX_FILL_1 ( &qpctx, 16,
  809. qpc_eec_data.primary_address_path.sched_queue,
  810. ( 0x83 /* default policy */ |
  811. ( ( ibdev->port - 1 ) << 6 ) ) );
  812. if ( ( rc = hermon_cmd_init2rtr_qp ( hermon, qp->qpn,
  813. &qpctx ) ) != 0 ) {
  814. DBGC ( hermon, "Hermon %p INIT2RTR_QP failed: %s\n",
  815. hermon, strerror ( rc ) );
  816. goto err_init2rtr_qp;
  817. }
  818. memset ( &qpctx, 0, sizeof ( qpctx ) );
  819. if ( ( rc = hermon_cmd_rtr2rts_qp ( hermon, qp->qpn, &qpctx ) ) != 0 ){
  820. DBGC ( hermon, "Hermon %p RTR2RTS_QP failed: %s\n",
  821. hermon, strerror ( rc ) );
  822. goto err_rtr2rts_qp;
  823. }
  824. DBGC ( hermon, "Hermon %p QPN %#lx send ring at [%p,%p)\n",
  825. hermon, qp->qpn, hermon_qp->send.wqe,
  826. ( ((void *)hermon_qp->send.wqe ) + hermon_qp->send.wqe_size ) );
  827. DBGC ( hermon, "Hermon %p QPN %#lx receive ring at [%p,%p)\n",
  828. hermon, qp->qpn, hermon_qp->recv.wqe,
  829. ( ((void *)hermon_qp->recv.wqe ) + hermon_qp->recv.wqe_size ) );
  830. ib_qp_set_drvdata ( qp, hermon_qp );
  831. return 0;
  832. err_rtr2rts_qp:
  833. err_init2rtr_qp:
  834. hermon_cmd_2rst_qp ( hermon, qp->qpn );
  835. err_rst2init_qp:
  836. hermon_free_mtt ( hermon, &hermon_qp->mtt );
  837. err_alloc_mtt:
  838. free_dma ( hermon_qp->wqe, hermon_qp->wqe_size );
  839. err_alloc_wqe:
  840. free ( hermon_qp );
  841. err_hermon_qp:
  842. hermon_bitmask_free ( hermon->qp_inuse, qpn_offset, 1 );
  843. err_qpn_offset:
  844. return rc;
  845. }
  846. /**
  847. * Modify queue pair
  848. *
  849. * @v ibdev Infiniband device
  850. * @v qp Queue pair
  851. * @v mod_list Modification list
  852. * @ret rc Return status code
  853. */
  854. static int hermon_modify_qp ( struct ib_device *ibdev,
  855. struct ib_queue_pair *qp,
  856. unsigned long mod_list ) {
  857. struct hermon *hermon = ib_get_drvdata ( ibdev );
  858. struct hermonprm_qp_ee_state_transitions qpctx;
  859. unsigned long optparammask = 0;
  860. int rc;
  861. /* Construct optparammask */
  862. if ( mod_list & IB_MODIFY_QKEY )
  863. optparammask |= HERMON_QP_OPT_PARAM_QKEY;
  864. /* Issue RTS2RTS_QP */
  865. memset ( &qpctx, 0, sizeof ( qpctx ) );
  866. MLX_FILL_1 ( &qpctx, 0, opt_param_mask, optparammask );
  867. MLX_FILL_1 ( &qpctx, 44, qpc_eec_data.q_key, qp->qkey );
  868. if ( ( rc = hermon_cmd_rts2rts_qp ( hermon, qp->qpn, &qpctx ) ) != 0 ){
  869. DBGC ( hermon, "Hermon %p RTS2RTS_QP failed: %s\n",
  870. hermon, strerror ( rc ) );
  871. return rc;
  872. }
  873. return 0;
  874. }
  875. /**
  876. * Destroy queue pair
  877. *
  878. * @v ibdev Infiniband device
  879. * @v qp Queue pair
  880. */
  881. static void hermon_destroy_qp ( struct ib_device *ibdev,
  882. struct ib_queue_pair *qp ) {
  883. struct hermon *hermon = ib_get_drvdata ( ibdev );
  884. struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp );
  885. int qpn_offset;
  886. int rc;
  887. /* Take ownership back from hardware */
  888. if ( ( rc = hermon_cmd_2rst_qp ( hermon, qp->qpn ) ) != 0 ) {
  889. DBGC ( hermon, "Hermon %p FATAL 2RST_QP failed on QPN %#lx: "
  890. "%s\n", hermon, qp->qpn, strerror ( rc ) );
  891. /* Leak memory and return; at least we avoid corruption */
  892. return;
  893. }
  894. /* Free MTT entries */
  895. hermon_free_mtt ( hermon, &hermon_qp->mtt );
  896. /* Free memory */
  897. free_dma ( hermon_qp->wqe, hermon_qp->wqe_size );
  898. free ( hermon_qp );
  899. /* Mark queue number as free */
  900. qpn_offset = ( qp->qpn - HERMON_QPN_BASE -
  901. hermon->cap.reserved_qps );
  902. hermon_bitmask_free ( hermon->qp_inuse, qpn_offset, 1 );
  903. ib_qp_set_drvdata ( qp, NULL );
  904. }
  905. /***************************************************************************
  906. *
  907. * Work request operations
  908. *
  909. ***************************************************************************
  910. */
  911. /** GID used for GID-less send work queue entries */
  912. static const struct ib_gid hermon_no_gid = {
  913. { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }
  914. };
  915. /**
  916. * Post send work queue entry
  917. *
  918. * @v ibdev Infiniband device
  919. * @v qp Queue pair
  920. * @v av Address vector
  921. * @v iobuf I/O buffer
  922. * @ret rc Return status code
  923. */
  924. static int hermon_post_send ( struct ib_device *ibdev,
  925. struct ib_queue_pair *qp,
  926. struct ib_address_vector *av,
  927. struct io_buffer *iobuf ) {
  928. struct hermon *hermon = ib_get_drvdata ( ibdev );
  929. struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp );
  930. struct ib_work_queue *wq = &qp->send;
  931. struct hermon_send_work_queue *hermon_send_wq = &hermon_qp->send;
  932. struct hermonprm_ud_send_wqe *wqe;
  933. const struct ib_gid *gid;
  934. union hermonprm_doorbell_register db_reg;
  935. unsigned int wqe_idx_mask;
  936. /* Allocate work queue entry */
  937. wqe_idx_mask = ( wq->num_wqes - 1 );
  938. if ( wq->iobufs[wq->next_idx & wqe_idx_mask] ) {
  939. DBGC ( hermon, "Hermon %p send queue full", hermon );
  940. return -ENOBUFS;
  941. }
  942. wq->iobufs[wq->next_idx & wqe_idx_mask] = iobuf;
  943. wqe = &hermon_send_wq->wqe[ wq->next_idx &
  944. ( hermon_send_wq->num_wqes - 1 ) ].ud;
  945. /* Construct work queue entry */
  946. memset ( ( ( ( void * ) wqe ) + 4 /* avoid ctrl.owner */ ), 0,
  947. ( sizeof ( *wqe ) - 4 ) );
  948. MLX_FILL_1 ( &wqe->ctrl, 1, ds, ( sizeof ( *wqe ) / 16 ) );
  949. MLX_FILL_1 ( &wqe->ctrl, 2, c, 0x03 /* generate completion */ );
  950. MLX_FILL_2 ( &wqe->ud, 0,
  951. ud_address_vector.pd, HERMON_GLOBAL_PD,
  952. ud_address_vector.port_number, ibdev->port );
  953. MLX_FILL_2 ( &wqe->ud, 1,
  954. ud_address_vector.rlid, av->lid,
  955. ud_address_vector.g, av->gid_present );
  956. MLX_FILL_1 ( &wqe->ud, 2,
  957. ud_address_vector.max_stat_rate,
  958. ( ( ( av->rate < 2 ) || ( av->rate > 10 ) ) ?
  959. 8 : ( av->rate + 5 ) ) );
  960. MLX_FILL_1 ( &wqe->ud, 3, ud_address_vector.sl, av->sl );
  961. gid = ( av->gid_present ? &av->gid : &hermon_no_gid );
  962. memcpy ( &wqe->ud.u.dwords[4], gid, sizeof ( *gid ) );
  963. MLX_FILL_1 ( &wqe->ud, 8, destination_qp, av->qpn );
  964. MLX_FILL_1 ( &wqe->ud, 9, q_key, av->qkey );
  965. MLX_FILL_1 ( &wqe->data[0], 0, byte_count, iob_len ( iobuf ) );
  966. MLX_FILL_1 ( &wqe->data[0], 1, l_key, hermon->reserved_lkey );
  967. MLX_FILL_1 ( &wqe->data[0], 3,
  968. local_address_l, virt_to_bus ( iobuf->data ) );
  969. barrier();
  970. MLX_FILL_2 ( &wqe->ctrl, 0,
  971. opcode, HERMON_OPCODE_SEND,
  972. owner,
  973. ( ( wq->next_idx & hermon_send_wq->num_wqes ) ? 1 : 0 ) );
  974. DBGCP ( hermon, "Hermon %p posting send WQE:\n", hermon );
  975. DBGCP_HD ( hermon, wqe, sizeof ( *wqe ) );
  976. barrier();
  977. /* Ring doorbell register */
  978. MLX_FILL_1 ( &db_reg.send, 0, qn, qp->qpn );
  979. DBGCP ( hermon, "Ringing doorbell %08lx with %08x\n",
  980. virt_to_phys ( hermon_send_wq->doorbell ), db_reg.dword[0] );
  981. writel ( db_reg.dword[0], ( hermon_send_wq->doorbell ) );
  982. /* Update work queue's index */
  983. wq->next_idx++;
  984. return 0;
  985. }
  986. /**
  987. * Post receive work queue entry
  988. *
  989. * @v ibdev Infiniband device
  990. * @v qp Queue pair
  991. * @v iobuf I/O buffer
  992. * @ret rc Return status code
  993. */
  994. static int hermon_post_recv ( struct ib_device *ibdev,
  995. struct ib_queue_pair *qp,
  996. struct io_buffer *iobuf ) {
  997. struct hermon *hermon = ib_get_drvdata ( ibdev );
  998. struct hermon_queue_pair *hermon_qp = ib_qp_get_drvdata ( qp );
  999. struct ib_work_queue *wq = &qp->recv;
  1000. struct hermon_recv_work_queue *hermon_recv_wq = &hermon_qp->recv;
  1001. struct hermonprm_recv_wqe *wqe;
  1002. unsigned int wqe_idx_mask;
  1003. /* Allocate work queue entry */
  1004. wqe_idx_mask = ( wq->num_wqes - 1 );
  1005. if ( wq->iobufs[wq->next_idx & wqe_idx_mask] ) {
  1006. DBGC ( hermon, "Hermon %p receive queue full", hermon );
  1007. return -ENOBUFS;
  1008. }
  1009. wq->iobufs[wq->next_idx & wqe_idx_mask] = iobuf;
  1010. wqe = &hermon_recv_wq->wqe[wq->next_idx & wqe_idx_mask].recv;
  1011. /* Construct work queue entry */
  1012. MLX_FILL_1 ( &wqe->data[0], 0, byte_count, iob_tailroom ( iobuf ) );
  1013. MLX_FILL_1 ( &wqe->data[0], 1, l_key, hermon->reserved_lkey );
  1014. MLX_FILL_1 ( &wqe->data[0], 3,
  1015. local_address_l, virt_to_bus ( iobuf->data ) );
  1016. /* Update work queue's index */
  1017. wq->next_idx++;
  1018. /* Update doorbell record */
  1019. barrier();
  1020. MLX_FILL_1 ( &hermon_recv_wq->doorbell, 0, receive_wqe_counter,
  1021. ( wq->next_idx & 0xffff ) );
  1022. return 0;
  1023. }
  1024. /**
  1025. * Handle completion
  1026. *
  1027. * @v ibdev Infiniband device
  1028. * @v cq Completion queue
  1029. * @v cqe Hardware completion queue entry
  1030. * @ret rc Return status code
  1031. */
  1032. static int hermon_complete ( struct ib_device *ibdev,
  1033. struct ib_completion_queue *cq,
  1034. union hermonprm_completion_entry *cqe ) {
  1035. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1036. struct ib_work_queue *wq;
  1037. struct ib_queue_pair *qp;
  1038. struct hermon_queue_pair *hermon_qp;
  1039. struct io_buffer *iobuf;
  1040. struct ib_address_vector av;
  1041. struct ib_global_route_header *grh;
  1042. unsigned int opcode;
  1043. unsigned long qpn;
  1044. int is_send;
  1045. unsigned int wqe_idx;
  1046. size_t len;
  1047. int rc = 0;
  1048. /* Parse completion */
  1049. qpn = MLX_GET ( &cqe->normal, qpn );
  1050. is_send = MLX_GET ( &cqe->normal, s_r );
  1051. opcode = MLX_GET ( &cqe->normal, opcode );
  1052. if ( opcode >= HERMON_OPCODE_RECV_ERROR ) {
  1053. /* "s" field is not valid for error opcodes */
  1054. is_send = ( opcode == HERMON_OPCODE_SEND_ERROR );
  1055. DBGC ( hermon, "Hermon %p CQN %lx syndrome %x vendor %x\n",
  1056. hermon, cq->cqn, MLX_GET ( &cqe->error, syndrome ),
  1057. MLX_GET ( &cqe->error, vendor_error_syndrome ) );
  1058. rc = -EIO;
  1059. /* Don't return immediately; propagate error to completer */
  1060. }
  1061. /* Identify work queue */
  1062. wq = ib_find_wq ( cq, qpn, is_send );
  1063. if ( ! wq ) {
  1064. DBGC ( hermon, "Hermon %p CQN %lx unknown %s QPN %lx\n",
  1065. hermon, cq->cqn, ( is_send ? "send" : "recv" ), qpn );
  1066. return -EIO;
  1067. }
  1068. qp = wq->qp;
  1069. hermon_qp = ib_qp_get_drvdata ( qp );
  1070. /* Identify I/O buffer */
  1071. wqe_idx = ( MLX_GET ( &cqe->normal, wqe_counter ) &
  1072. ( wq->num_wqes - 1 ) );
  1073. iobuf = wq->iobufs[wqe_idx];
  1074. if ( ! iobuf ) {
  1075. DBGC ( hermon, "Hermon %p CQN %lx QPN %lx empty WQE %x\n",
  1076. hermon, cq->cqn, qpn, wqe_idx );
  1077. return -EIO;
  1078. }
  1079. wq->iobufs[wqe_idx] = NULL;
  1080. if ( is_send ) {
  1081. /* Hand off to completion handler */
  1082. ib_complete_send ( ibdev, qp, iobuf, rc );
  1083. } else {
  1084. /* Set received length */
  1085. len = MLX_GET ( &cqe->normal, byte_cnt );
  1086. assert ( len <= iob_tailroom ( iobuf ) );
  1087. iob_put ( iobuf, len );
  1088. assert ( iob_len ( iobuf ) >= sizeof ( *grh ) );
  1089. grh = iobuf->data;
  1090. iob_pull ( iobuf, sizeof ( *grh ) );
  1091. /* Construct address vector */
  1092. memset ( &av, 0, sizeof ( av ) );
  1093. av.qpn = MLX_GET ( &cqe->normal, srq_rqpn );
  1094. av.lid = MLX_GET ( &cqe->normal, slid_smac47_32 );
  1095. av.sl = MLX_GET ( &cqe->normal, sl );
  1096. av.gid_present = MLX_GET ( &cqe->normal, g );
  1097. memcpy ( &av.gid, &grh->sgid, sizeof ( av.gid ) );
  1098. /* Hand off to completion handler */
  1099. ib_complete_recv ( ibdev, qp, &av, iobuf, rc );
  1100. }
  1101. return rc;
  1102. }
  1103. /**
  1104. * Poll completion queue
  1105. *
  1106. * @v ibdev Infiniband device
  1107. * @v cq Completion queue
  1108. */
  1109. static void hermon_poll_cq ( struct ib_device *ibdev,
  1110. struct ib_completion_queue *cq ) {
  1111. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1112. struct hermon_completion_queue *hermon_cq = ib_cq_get_drvdata ( cq );
  1113. union hermonprm_completion_entry *cqe;
  1114. unsigned int cqe_idx_mask;
  1115. int rc;
  1116. while ( 1 ) {
  1117. /* Look for completion entry */
  1118. cqe_idx_mask = ( cq->num_cqes - 1 );
  1119. cqe = &hermon_cq->cqe[cq->next_idx & cqe_idx_mask];
  1120. if ( MLX_GET ( &cqe->normal, owner ) ^
  1121. ( ( cq->next_idx & cq->num_cqes ) ? 1 : 0 ) ) {
  1122. /* Entry still owned by hardware; end of poll */
  1123. break;
  1124. }
  1125. DBGCP ( hermon, "Hermon %p completion:\n", hermon );
  1126. DBGCP_HD ( hermon, cqe, sizeof ( *cqe ) );
  1127. /* Handle completion */
  1128. if ( ( rc = hermon_complete ( ibdev, cq, cqe ) ) != 0 ) {
  1129. DBGC ( hermon, "Hermon %p failed to complete: %s\n",
  1130. hermon, strerror ( rc ) );
  1131. DBGC_HD ( hermon, cqe, sizeof ( *cqe ) );
  1132. }
  1133. /* Update completion queue's index */
  1134. cq->next_idx++;
  1135. /* Update doorbell record */
  1136. MLX_FILL_1 ( &hermon_cq->doorbell, 0, update_ci,
  1137. ( cq->next_idx & 0x00ffffffUL ) );
  1138. }
  1139. }
  1140. /***************************************************************************
  1141. *
  1142. * Event queues
  1143. *
  1144. ***************************************************************************
  1145. */
  1146. /**
  1147. * Create event queue
  1148. *
  1149. * @v hermon Hermon device
  1150. * @ret rc Return status code
  1151. */
  1152. static int hermon_create_eq ( struct hermon *hermon ) {
  1153. struct hermon_event_queue *hermon_eq = &hermon->eq;
  1154. struct hermonprm_eqc eqctx;
  1155. struct hermonprm_event_mask mask;
  1156. unsigned int i;
  1157. int rc;
  1158. /* Select event queue number */
  1159. hermon_eq->eqn = ( 4 * hermon->cap.reserved_uars );
  1160. if ( hermon_eq->eqn < hermon->cap.reserved_eqs )
  1161. hermon_eq->eqn = hermon->cap.reserved_eqs;
  1162. /* Calculate doorbell address */
  1163. hermon_eq->doorbell =
  1164. ( hermon->uar + HERMON_DB_EQ_OFFSET ( hermon_eq->eqn ) );
  1165. /* Allocate event queue itself */
  1166. hermon_eq->eqe_size =
  1167. ( HERMON_NUM_EQES * sizeof ( hermon_eq->eqe[0] ) );
  1168. hermon_eq->eqe = malloc_dma ( hermon_eq->eqe_size,
  1169. sizeof ( hermon_eq->eqe[0] ) );
  1170. if ( ! hermon_eq->eqe ) {
  1171. rc = -ENOMEM;
  1172. goto err_eqe;
  1173. }
  1174. memset ( hermon_eq->eqe, 0, hermon_eq->eqe_size );
  1175. for ( i = 0 ; i < HERMON_NUM_EQES ; i++ ) {
  1176. MLX_FILL_1 ( &hermon_eq->eqe[i].generic, 7, owner, 1 );
  1177. }
  1178. barrier();
  1179. /* Allocate MTT entries */
  1180. if ( ( rc = hermon_alloc_mtt ( hermon, hermon_eq->eqe,
  1181. hermon_eq->eqe_size,
  1182. &hermon_eq->mtt ) ) != 0 )
  1183. goto err_alloc_mtt;
  1184. /* Hand queue over to hardware */
  1185. memset ( &eqctx, 0, sizeof ( eqctx ) );
  1186. MLX_FILL_1 ( &eqctx, 0, st, 0xa /* "Fired" */ );
  1187. MLX_FILL_1 ( &eqctx, 2,
  1188. page_offset, ( hermon_eq->mtt.page_offset >> 5 ) );
  1189. MLX_FILL_1 ( &eqctx, 3, log_eq_size, fls ( HERMON_NUM_EQES - 1 ) );
  1190. MLX_FILL_1 ( &eqctx, 7, mtt_base_addr_l,
  1191. ( hermon_eq->mtt.mtt_base_addr >> 3 ) );
  1192. if ( ( rc = hermon_cmd_sw2hw_eq ( hermon, hermon_eq->eqn,
  1193. &eqctx ) ) != 0 ) {
  1194. DBGC ( hermon, "Hermon %p SW2HW_EQ failed: %s\n",
  1195. hermon, strerror ( rc ) );
  1196. goto err_sw2hw_eq;
  1197. }
  1198. /* Map events to this event queue */
  1199. memset ( &mask, 0, sizeof ( mask ) );
  1200. MLX_FILL_1 ( &mask, 1, port_state_change, 1 );
  1201. if ( ( rc = hermon_cmd_map_eq ( hermon,
  1202. ( HERMON_MAP_EQ | hermon_eq->eqn ),
  1203. &mask ) ) != 0 ) {
  1204. DBGC ( hermon, "Hermon %p MAP_EQ failed: %s\n",
  1205. hermon, strerror ( rc ) );
  1206. goto err_map_eq;
  1207. }
  1208. DBGC ( hermon, "Hermon %p EQN %#lx ring at [%p,%p])\n",
  1209. hermon, hermon_eq->eqn, hermon_eq->eqe,
  1210. ( ( ( void * ) hermon_eq->eqe ) + hermon_eq->eqe_size ) );
  1211. return 0;
  1212. err_map_eq:
  1213. hermon_cmd_hw2sw_eq ( hermon, hermon_eq->eqn, &eqctx );
  1214. err_sw2hw_eq:
  1215. hermon_free_mtt ( hermon, &hermon_eq->mtt );
  1216. err_alloc_mtt:
  1217. free_dma ( hermon_eq->eqe, hermon_eq->eqe_size );
  1218. err_eqe:
  1219. memset ( hermon_eq, 0, sizeof ( *hermon_eq ) );
  1220. return rc;
  1221. }
  1222. /**
  1223. * Destroy event queue
  1224. *
  1225. * @v hermon Hermon device
  1226. */
  1227. static void hermon_destroy_eq ( struct hermon *hermon ) {
  1228. struct hermon_event_queue *hermon_eq = &hermon->eq;
  1229. struct hermonprm_eqc eqctx;
  1230. struct hermonprm_event_mask mask;
  1231. int rc;
  1232. /* Unmap events from event queue */
  1233. memset ( &mask, 0, sizeof ( mask ) );
  1234. MLX_FILL_1 ( &mask, 1, port_state_change, 1 );
  1235. if ( ( rc = hermon_cmd_map_eq ( hermon,
  1236. ( HERMON_UNMAP_EQ | hermon_eq->eqn ),
  1237. &mask ) ) != 0 ) {
  1238. DBGC ( hermon, "Hermon %p FATAL MAP_EQ failed to unmap: %s\n",
  1239. hermon, strerror ( rc ) );
  1240. /* Continue; HCA may die but system should survive */
  1241. }
  1242. /* Take ownership back from hardware */
  1243. if ( ( rc = hermon_cmd_hw2sw_eq ( hermon, hermon_eq->eqn,
  1244. &eqctx ) ) != 0 ) {
  1245. DBGC ( hermon, "Hermon %p FATAL HW2SW_EQ failed: %s\n",
  1246. hermon, strerror ( rc ) );
  1247. /* Leak memory and return; at least we avoid corruption */
  1248. return;
  1249. }
  1250. /* Free MTT entries */
  1251. hermon_free_mtt ( hermon, &hermon_eq->mtt );
  1252. /* Free memory */
  1253. free_dma ( hermon_eq->eqe, hermon_eq->eqe_size );
  1254. memset ( hermon_eq, 0, sizeof ( *hermon_eq ) );
  1255. }
  1256. /**
  1257. * Handle port state event
  1258. *
  1259. * @v hermon Hermon device
  1260. * @v eqe Port state change event queue entry
  1261. */
  1262. static void hermon_event_port_state_change ( struct hermon *hermon,
  1263. union hermonprm_event_entry *eqe){
  1264. unsigned int port;
  1265. int link_up;
  1266. /* Get port and link status */
  1267. port = ( MLX_GET ( &eqe->port_state_change, data.p ) - 1 );
  1268. link_up = ( MLX_GET ( &eqe->generic, event_sub_type ) & 0x04 );
  1269. DBGC ( hermon, "Hermon %p port %d link %s\n", hermon, ( port + 1 ),
  1270. ( link_up ? "up" : "down" ) );
  1271. /* Sanity check */
  1272. if ( port >= HERMON_NUM_PORTS ) {
  1273. DBGC ( hermon, "Hermon %p port %d does not exist!\n",
  1274. hermon, ( port + 1 ) );
  1275. return;
  1276. }
  1277. /* Update MAD parameters */
  1278. ib_smc_update ( hermon->ibdev[port], hermon_mad );
  1279. /* Notify Infiniband core of link state change */
  1280. ib_link_state_changed ( hermon->ibdev[port] );
  1281. }
  1282. /**
  1283. * Poll event queue
  1284. *
  1285. * @v ibdev Infiniband device
  1286. */
  1287. static void hermon_poll_eq ( struct ib_device *ibdev ) {
  1288. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1289. struct hermon_event_queue *hermon_eq = &hermon->eq;
  1290. union hermonprm_event_entry *eqe;
  1291. union hermonprm_doorbell_register db_reg;
  1292. unsigned int eqe_idx_mask;
  1293. unsigned int event_type;
  1294. while ( 1 ) {
  1295. /* Look for event entry */
  1296. eqe_idx_mask = ( HERMON_NUM_EQES - 1 );
  1297. eqe = &hermon_eq->eqe[hermon_eq->next_idx & eqe_idx_mask];
  1298. if ( MLX_GET ( &eqe->generic, owner ) ^
  1299. ( ( hermon_eq->next_idx & HERMON_NUM_EQES ) ? 1 : 0 ) ) {
  1300. /* Entry still owned by hardware; end of poll */
  1301. break;
  1302. }
  1303. DBGCP ( hermon, "Hermon %p event:\n", hermon );
  1304. DBGCP_HD ( hermon, eqe, sizeof ( *eqe ) );
  1305. /* Handle event */
  1306. event_type = MLX_GET ( &eqe->generic, event_type );
  1307. switch ( event_type ) {
  1308. case HERMON_EV_PORT_STATE_CHANGE:
  1309. hermon_event_port_state_change ( hermon, eqe );
  1310. break;
  1311. default:
  1312. DBGC ( hermon, "Hermon %p unrecognised event type "
  1313. "%#x:\n", hermon, event_type );
  1314. DBGC_HD ( hermon, eqe, sizeof ( *eqe ) );
  1315. break;
  1316. }
  1317. /* Update event queue's index */
  1318. hermon_eq->next_idx++;
  1319. /* Ring doorbell */
  1320. MLX_FILL_1 ( &db_reg.event, 0,
  1321. ci, ( hermon_eq->next_idx & 0x00ffffffUL ) );
  1322. DBGCP ( hermon, "Ringing doorbell %08lx with %08x\n",
  1323. virt_to_phys ( hermon_eq->doorbell ),
  1324. db_reg.dword[0] );
  1325. writel ( db_reg.dword[0], hermon_eq->doorbell );
  1326. }
  1327. }
  1328. /***************************************************************************
  1329. *
  1330. * Infiniband link-layer operations
  1331. *
  1332. ***************************************************************************
  1333. */
  1334. /**
  1335. * Initialise Infiniband link
  1336. *
  1337. * @v ibdev Infiniband device
  1338. * @ret rc Return status code
  1339. */
  1340. static int hermon_open ( struct ib_device *ibdev ) {
  1341. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1342. struct hermonprm_init_port init_port;
  1343. int rc;
  1344. memset ( &init_port, 0, sizeof ( init_port ) );
  1345. MLX_FILL_2 ( &init_port, 0,
  1346. port_width_cap, 3,
  1347. vl_cap, 1 );
  1348. MLX_FILL_2 ( &init_port, 1,
  1349. mtu, HERMON_MTU_2048,
  1350. max_gid, 1 );
  1351. MLX_FILL_1 ( &init_port, 2, max_pkey, 64 );
  1352. if ( ( rc = hermon_cmd_init_port ( hermon, ibdev->port,
  1353. &init_port ) ) != 0 ) {
  1354. DBGC ( hermon, "Hermon %p could not intialise port: %s\n",
  1355. hermon, strerror ( rc ) );
  1356. return rc;
  1357. }
  1358. /* Update MAD parameters */
  1359. ib_smc_update ( ibdev, hermon_mad );
  1360. return 0;
  1361. }
  1362. /**
  1363. * Close Infiniband link
  1364. *
  1365. * @v ibdev Infiniband device
  1366. */
  1367. static void hermon_close ( struct ib_device *ibdev ) {
  1368. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1369. int rc;
  1370. if ( ( rc = hermon_cmd_close_port ( hermon, ibdev->port ) ) != 0 ) {
  1371. DBGC ( hermon, "Hermon %p could not close port: %s\n",
  1372. hermon, strerror ( rc ) );
  1373. /* Nothing we can do about this */
  1374. }
  1375. }
  1376. /***************************************************************************
  1377. *
  1378. * Multicast group operations
  1379. *
  1380. ***************************************************************************
  1381. */
  1382. /**
  1383. * Attach to multicast group
  1384. *
  1385. * @v ibdev Infiniband device
  1386. * @v qp Queue pair
  1387. * @v gid Multicast GID
  1388. * @ret rc Return status code
  1389. */
  1390. static int hermon_mcast_attach ( struct ib_device *ibdev,
  1391. struct ib_queue_pair *qp,
  1392. struct ib_gid *gid ) {
  1393. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1394. struct hermonprm_mgm_hash hash;
  1395. struct hermonprm_mcg_entry mcg;
  1396. unsigned int index;
  1397. int rc;
  1398. /* Generate hash table index */
  1399. if ( ( rc = hermon_cmd_mgid_hash ( hermon, gid, &hash ) ) != 0 ) {
  1400. DBGC ( hermon, "Hermon %p could not hash GID: %s\n",
  1401. hermon, strerror ( rc ) );
  1402. return rc;
  1403. }
  1404. index = MLX_GET ( &hash, hash );
  1405. /* Check for existing hash table entry */
  1406. if ( ( rc = hermon_cmd_read_mcg ( hermon, index, &mcg ) ) != 0 ) {
  1407. DBGC ( hermon, "Hermon %p could not read MCG %#x: %s\n",
  1408. hermon, index, strerror ( rc ) );
  1409. return rc;
  1410. }
  1411. if ( MLX_GET ( &mcg, hdr.members_count ) != 0 ) {
  1412. /* FIXME: this implementation allows only a single QP
  1413. * per multicast group, and doesn't handle hash
  1414. * collisions. Sufficient for IPoIB but may need to
  1415. * be extended in future.
  1416. */
  1417. DBGC ( hermon, "Hermon %p MGID index %#x already in use\n",
  1418. hermon, index );
  1419. return -EBUSY;
  1420. }
  1421. /* Update hash table entry */
  1422. MLX_FILL_1 ( &mcg, 1, hdr.members_count, 1 );
  1423. MLX_FILL_1 ( &mcg, 8, qp[0].qpn, qp->qpn );
  1424. memcpy ( &mcg.u.dwords[4], gid, sizeof ( *gid ) );
  1425. if ( ( rc = hermon_cmd_write_mcg ( hermon, index, &mcg ) ) != 0 ) {
  1426. DBGC ( hermon, "Hermon %p could not write MCG %#x: %s\n",
  1427. hermon, index, strerror ( rc ) );
  1428. return rc;
  1429. }
  1430. return 0;
  1431. }
  1432. /**
  1433. * Detach from multicast group
  1434. *
  1435. * @v ibdev Infiniband device
  1436. * @v qp Queue pair
  1437. * @v gid Multicast GID
  1438. */
  1439. static void hermon_mcast_detach ( struct ib_device *ibdev,
  1440. struct ib_queue_pair *qp __unused,
  1441. struct ib_gid *gid ) {
  1442. struct hermon *hermon = ib_get_drvdata ( ibdev );
  1443. struct hermonprm_mgm_hash hash;
  1444. struct hermonprm_mcg_entry mcg;
  1445. unsigned int index;
  1446. int rc;
  1447. /* Generate hash table index */
  1448. if ( ( rc = hermon_cmd_mgid_hash ( hermon, gid, &hash ) ) != 0 ) {
  1449. DBGC ( hermon, "Hermon %p could not hash GID: %s\n",
  1450. hermon, strerror ( rc ) );
  1451. return;
  1452. }
  1453. index = MLX_GET ( &hash, hash );
  1454. /* Clear hash table entry */
  1455. memset ( &mcg, 0, sizeof ( mcg ) );
  1456. if ( ( rc = hermon_cmd_write_mcg ( hermon, index, &mcg ) ) != 0 ) {
  1457. DBGC ( hermon, "Hermon %p could not write MCG %#x: %s\n",
  1458. hermon, index, strerror ( rc ) );
  1459. return;
  1460. }
  1461. }
  1462. /** Hermon Infiniband operations */
  1463. static struct ib_device_operations hermon_ib_operations = {
  1464. .create_cq = hermon_create_cq,
  1465. .destroy_cq = hermon_destroy_cq,
  1466. .create_qp = hermon_create_qp,
  1467. .modify_qp = hermon_modify_qp,
  1468. .destroy_qp = hermon_destroy_qp,
  1469. .post_send = hermon_post_send,
  1470. .post_recv = hermon_post_recv,
  1471. .poll_cq = hermon_poll_cq,
  1472. .poll_eq = hermon_poll_eq,
  1473. .open = hermon_open,
  1474. .close = hermon_close,
  1475. .mcast_attach = hermon_mcast_attach,
  1476. .mcast_detach = hermon_mcast_detach,
  1477. };
  1478. /***************************************************************************
  1479. *
  1480. * Firmware control
  1481. *
  1482. ***************************************************************************
  1483. */
  1484. /**
  1485. * Map virtual to physical address for firmware usage
  1486. *
  1487. * @v hermon Hermon device
  1488. * @v map Mapping function
  1489. * @v va Virtual address
  1490. * @v pa Physical address
  1491. * @v len Length of region
  1492. * @ret rc Return status code
  1493. */
  1494. static int hermon_map_vpm ( struct hermon *hermon,
  1495. int ( *map ) ( struct hermon *hermon,
  1496. const struct hermonprm_virtual_physical_mapping* ),
  1497. uint64_t va, physaddr_t pa, size_t len ) {
  1498. struct hermonprm_virtual_physical_mapping mapping;
  1499. int rc;
  1500. assert ( ( va & ( HERMON_PAGE_SIZE - 1 ) ) == 0 );
  1501. assert ( ( pa & ( HERMON_PAGE_SIZE - 1 ) ) == 0 );
  1502. assert ( ( len & ( HERMON_PAGE_SIZE - 1 ) ) == 0 );
  1503. while ( len ) {
  1504. memset ( &mapping, 0, sizeof ( mapping ) );
  1505. MLX_FILL_1 ( &mapping, 0, va_h, ( va >> 32 ) );
  1506. MLX_FILL_1 ( &mapping, 1, va_l, ( va >> 12 ) );
  1507. MLX_FILL_2 ( &mapping, 3,
  1508. log2size, 0,
  1509. pa_l, ( pa >> 12 ) );
  1510. if ( ( rc = map ( hermon, &mapping ) ) != 0 ) {
  1511. DBGC ( hermon, "Hermon %p could not map %llx => %lx: "
  1512. "%s\n", hermon, va, pa, strerror ( rc ) );
  1513. return rc;
  1514. }
  1515. pa += HERMON_PAGE_SIZE;
  1516. va += HERMON_PAGE_SIZE;
  1517. len -= HERMON_PAGE_SIZE;
  1518. }
  1519. return 0;
  1520. }
  1521. /**
  1522. * Start firmware running
  1523. *
  1524. * @v hermon Hermon device
  1525. * @ret rc Return status code
  1526. */
  1527. static int hermon_start_firmware ( struct hermon *hermon ) {
  1528. struct hermonprm_query_fw fw;
  1529. unsigned int fw_pages;
  1530. size_t fw_size;
  1531. physaddr_t fw_base;
  1532. int rc;
  1533. /* Get firmware parameters */
  1534. if ( ( rc = hermon_cmd_query_fw ( hermon, &fw ) ) != 0 ) {
  1535. DBGC ( hermon, "Hermon %p could not query firmware: %s\n",
  1536. hermon, strerror ( rc ) );
  1537. goto err_query_fw;
  1538. }
  1539. DBGC ( hermon, "Hermon %p firmware version %d.%d.%d\n", hermon,
  1540. MLX_GET ( &fw, fw_rev_major ), MLX_GET ( &fw, fw_rev_minor ),
  1541. MLX_GET ( &fw, fw_rev_subminor ) );
  1542. fw_pages = MLX_GET ( &fw, fw_pages );
  1543. DBGC ( hermon, "Hermon %p requires %d pages (%d kB) for firmware\n",
  1544. hermon, fw_pages, ( fw_pages * ( HERMON_PAGE_SIZE / 1024 ) ) );
  1545. /* Allocate firmware pages and map firmware area */
  1546. fw_size = ( fw_pages * HERMON_PAGE_SIZE );
  1547. hermon->firmware_area = umalloc ( fw_size );
  1548. if ( ! hermon->firmware_area ) {
  1549. rc = -ENOMEM;
  1550. goto err_alloc_fa;
  1551. }
  1552. fw_base = user_to_phys ( hermon->firmware_area, 0 );
  1553. DBGC ( hermon, "Hermon %p firmware area at physical [%lx,%lx)\n",
  1554. hermon, fw_base, ( fw_base + fw_size ) );
  1555. if ( ( rc = hermon_map_vpm ( hermon, hermon_cmd_map_fa,
  1556. 0, fw_base, fw_size ) ) != 0 ) {
  1557. DBGC ( hermon, "Hermon %p could not map firmware: %s\n",
  1558. hermon, strerror ( rc ) );
  1559. goto err_map_fa;
  1560. }
  1561. /* Start firmware */
  1562. if ( ( rc = hermon_cmd_run_fw ( hermon ) ) != 0 ) {
  1563. DBGC ( hermon, "Hermon %p could not run firmware: %s\n",
  1564. hermon, strerror ( rc ) );
  1565. goto err_run_fw;
  1566. }
  1567. DBGC ( hermon, "Hermon %p firmware started\n", hermon );
  1568. return 0;
  1569. err_run_fw:
  1570. err_map_fa:
  1571. hermon_cmd_unmap_fa ( hermon );
  1572. ufree ( hermon->firmware_area );
  1573. hermon->firmware_area = UNULL;
  1574. err_alloc_fa:
  1575. err_query_fw:
  1576. return rc;
  1577. }
  1578. /**
  1579. * Stop firmware running
  1580. *
  1581. * @v hermon Hermon device
  1582. */
  1583. static void hermon_stop_firmware ( struct hermon *hermon ) {
  1584. int rc;
  1585. if ( ( rc = hermon_cmd_unmap_fa ( hermon ) ) != 0 ) {
  1586. DBGC ( hermon, "Hermon %p FATAL could not stop firmware: %s\n",
  1587. hermon, strerror ( rc ) );
  1588. /* Leak memory and return; at least we avoid corruption */
  1589. return;
  1590. }
  1591. ufree ( hermon->firmware_area );
  1592. hermon->firmware_area = UNULL;
  1593. }
  1594. /***************************************************************************
  1595. *
  1596. * Infinihost Context Memory management
  1597. *
  1598. ***************************************************************************
  1599. */
  1600. /**
  1601. * Get device limits
  1602. *
  1603. * @v hermon Hermon device
  1604. * @ret rc Return status code
  1605. */
  1606. static int hermon_get_cap ( struct hermon *hermon ) {
  1607. struct hermonprm_query_dev_cap dev_cap;
  1608. int rc;
  1609. if ( ( rc = hermon_cmd_query_dev_cap ( hermon, &dev_cap ) ) != 0 ) {
  1610. DBGC ( hermon, "Hermon %p could not get device limits: %s\n",
  1611. hermon, strerror ( rc ) );
  1612. return rc;
  1613. }
  1614. hermon->cap.cmpt_entry_size = MLX_GET ( &dev_cap, c_mpt_entry_sz );
  1615. hermon->cap.reserved_qps =
  1616. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_qps ) );
  1617. hermon->cap.qpc_entry_size = MLX_GET ( &dev_cap, qpc_entry_sz );
  1618. hermon->cap.altc_entry_size = MLX_GET ( &dev_cap, altc_entry_sz );
  1619. hermon->cap.auxc_entry_size = MLX_GET ( &dev_cap, aux_entry_sz );
  1620. hermon->cap.reserved_srqs =
  1621. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_srqs ) );
  1622. hermon->cap.srqc_entry_size = MLX_GET ( &dev_cap, srq_entry_sz );
  1623. hermon->cap.reserved_cqs =
  1624. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_cqs ) );
  1625. hermon->cap.cqc_entry_size = MLX_GET ( &dev_cap, cqc_entry_sz );
  1626. hermon->cap.reserved_eqs = MLX_GET ( &dev_cap, num_rsvd_eqs );
  1627. hermon->cap.eqc_entry_size = MLX_GET ( &dev_cap, eqc_entry_sz );
  1628. hermon->cap.reserved_mtts =
  1629. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_mtts ) );
  1630. hermon->cap.mtt_entry_size = MLX_GET ( &dev_cap, mtt_entry_sz );
  1631. hermon->cap.reserved_mrws =
  1632. ( 1 << MLX_GET ( &dev_cap, log2_rsvd_mrws ) );
  1633. hermon->cap.dmpt_entry_size = MLX_GET ( &dev_cap, d_mpt_entry_sz );
  1634. hermon->cap.reserved_uars = MLX_GET ( &dev_cap, num_rsvd_uars );
  1635. return 0;
  1636. }
  1637. /**
  1638. * Get ICM usage
  1639. *
  1640. * @v log_num_entries Log2 of the number of entries
  1641. * @v entry_size Entry size
  1642. * @ret usage Usage size in ICM
  1643. */
  1644. static size_t icm_usage ( unsigned int log_num_entries, size_t entry_size ) {
  1645. size_t usage;
  1646. usage = ( ( 1 << log_num_entries ) * entry_size );
  1647. usage = ( ( usage + HERMON_PAGE_SIZE - 1 ) &
  1648. ~( HERMON_PAGE_SIZE - 1 ) );
  1649. return usage;
  1650. }
  1651. /**
  1652. * Allocate ICM
  1653. *
  1654. * @v hermon Hermon device
  1655. * @v init_hca INIT_HCA structure to fill in
  1656. * @ret rc Return status code
  1657. */
  1658. static int hermon_alloc_icm ( struct hermon *hermon,
  1659. struct hermonprm_init_hca *init_hca ) {
  1660. struct hermonprm_scalar_parameter icm_size;
  1661. struct hermonprm_scalar_parameter icm_aux_size;
  1662. uint64_t icm_offset = 0;
  1663. unsigned int log_num_qps, log_num_srqs, log_num_cqs, log_num_eqs;
  1664. unsigned int log_num_mtts, log_num_mpts;
  1665. size_t cmpt_max_len;
  1666. size_t qp_cmpt_len, srq_cmpt_len, cq_cmpt_len, eq_cmpt_len;
  1667. size_t icm_len, icm_aux_len;
  1668. physaddr_t icm_phys;
  1669. int i;
  1670. int rc;
  1671. /*
  1672. * Start by carving up the ICM virtual address space
  1673. *
  1674. */
  1675. /* Calculate number of each object type within ICM */
  1676. log_num_qps = fls ( hermon->cap.reserved_qps + HERMON_MAX_QPS - 1 );
  1677. log_num_srqs = fls ( hermon->cap.reserved_srqs - 1 );
  1678. log_num_cqs = fls ( hermon->cap.reserved_cqs + HERMON_MAX_CQS - 1 );
  1679. log_num_eqs = fls ( hermon->cap.reserved_eqs + HERMON_MAX_EQS - 1 );
  1680. log_num_mtts = fls ( hermon->cap.reserved_mtts + HERMON_MAX_MTTS - 1 );
  1681. /* ICM starts with the cMPT tables, which are sparse */
  1682. cmpt_max_len = ( HERMON_CMPT_MAX_ENTRIES *
  1683. ( ( uint64_t ) hermon->cap.cmpt_entry_size ) );
  1684. qp_cmpt_len = icm_usage ( log_num_qps, hermon->cap.cmpt_entry_size );
  1685. hermon->icm_map[HERMON_ICM_QP_CMPT].offset = icm_offset;
  1686. hermon->icm_map[HERMON_ICM_QP_CMPT].len = qp_cmpt_len;
  1687. icm_offset += cmpt_max_len;
  1688. srq_cmpt_len = icm_usage ( log_num_srqs, hermon->cap.cmpt_entry_size );
  1689. hermon->icm_map[HERMON_ICM_SRQ_CMPT].offset = icm_offset;
  1690. hermon->icm_map[HERMON_ICM_SRQ_CMPT].len = srq_cmpt_len;
  1691. icm_offset += cmpt_max_len;
  1692. cq_cmpt_len = icm_usage ( log_num_cqs, hermon->cap.cmpt_entry_size );
  1693. hermon->icm_map[HERMON_ICM_CQ_CMPT].offset = icm_offset;
  1694. hermon->icm_map[HERMON_ICM_CQ_CMPT].len = cq_cmpt_len;
  1695. icm_offset += cmpt_max_len;
  1696. eq_cmpt_len = icm_usage ( log_num_eqs, hermon->cap.cmpt_entry_size );
  1697. hermon->icm_map[HERMON_ICM_EQ_CMPT].offset = icm_offset;
  1698. hermon->icm_map[HERMON_ICM_EQ_CMPT].len = eq_cmpt_len;
  1699. icm_offset += cmpt_max_len;
  1700. hermon->icm_map[HERMON_ICM_OTHER].offset = icm_offset;
  1701. /* Queue pair contexts */
  1702. MLX_FILL_1 ( init_hca, 12,
  1703. qpc_eec_cqc_eqc_rdb_parameters.qpc_base_addr_h,
  1704. ( icm_offset >> 32 ) );
  1705. MLX_FILL_2 ( init_hca, 13,
  1706. qpc_eec_cqc_eqc_rdb_parameters.qpc_base_addr_l,
  1707. ( icm_offset >> 5 ),
  1708. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_qp,
  1709. log_num_qps );
  1710. DBGC ( hermon, "Hermon %p ICM QPC base = %llx\n", hermon, icm_offset );
  1711. icm_offset += icm_usage ( log_num_qps, hermon->cap.qpc_entry_size );
  1712. /* Extended alternate path contexts */
  1713. MLX_FILL_1 ( init_hca, 24,
  1714. qpc_eec_cqc_eqc_rdb_parameters.altc_base_addr_h,
  1715. ( icm_offset >> 32 ) );
  1716. MLX_FILL_1 ( init_hca, 25,
  1717. qpc_eec_cqc_eqc_rdb_parameters.altc_base_addr_l,
  1718. icm_offset );
  1719. DBGC ( hermon, "Hermon %p ICM ALTC base = %llx\n", hermon, icm_offset);
  1720. icm_offset += icm_usage ( log_num_qps,
  1721. hermon->cap.altc_entry_size );
  1722. /* Extended auxiliary contexts */
  1723. MLX_FILL_1 ( init_hca, 28,
  1724. qpc_eec_cqc_eqc_rdb_parameters.auxc_base_addr_h,
  1725. ( icm_offset >> 32 ) );
  1726. MLX_FILL_1 ( init_hca, 29,
  1727. qpc_eec_cqc_eqc_rdb_parameters.auxc_base_addr_l,
  1728. icm_offset );
  1729. DBGC ( hermon, "Hermon %p ICM AUXC base = %llx\n", hermon, icm_offset);
  1730. icm_offset += icm_usage ( log_num_qps,
  1731. hermon->cap.auxc_entry_size );
  1732. /* Shared receive queue contexts */
  1733. MLX_FILL_1 ( init_hca, 18,
  1734. qpc_eec_cqc_eqc_rdb_parameters.srqc_base_addr_h,
  1735. ( icm_offset >> 32 ) );
  1736. MLX_FILL_2 ( init_hca, 19,
  1737. qpc_eec_cqc_eqc_rdb_parameters.srqc_base_addr_l,
  1738. ( icm_offset >> 5 ),
  1739. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_srq,
  1740. log_num_srqs );
  1741. DBGC ( hermon, "Hermon %p ICM SRQC base = %llx\n", hermon, icm_offset);
  1742. icm_offset += icm_usage ( log_num_srqs,
  1743. hermon->cap.srqc_entry_size );
  1744. /* Completion queue contexts */
  1745. MLX_FILL_1 ( init_hca, 20,
  1746. qpc_eec_cqc_eqc_rdb_parameters.cqc_base_addr_h,
  1747. ( icm_offset >> 32 ) );
  1748. MLX_FILL_2 ( init_hca, 21,
  1749. qpc_eec_cqc_eqc_rdb_parameters.cqc_base_addr_l,
  1750. ( icm_offset >> 5 ),
  1751. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_cq,
  1752. log_num_cqs );
  1753. DBGC ( hermon, "Hermon %p ICM CQC base = %llx\n", hermon, icm_offset );
  1754. icm_offset += icm_usage ( log_num_cqs, hermon->cap.cqc_entry_size );
  1755. /* Event queue contexts */
  1756. MLX_FILL_1 ( init_hca, 32,
  1757. qpc_eec_cqc_eqc_rdb_parameters.eqc_base_addr_h,
  1758. ( icm_offset >> 32 ) );
  1759. MLX_FILL_2 ( init_hca, 33,
  1760. qpc_eec_cqc_eqc_rdb_parameters.eqc_base_addr_l,
  1761. ( icm_offset >> 5 ),
  1762. qpc_eec_cqc_eqc_rdb_parameters.log_num_of_eq,
  1763. log_num_eqs );
  1764. DBGC ( hermon, "Hermon %p ICM EQC base = %llx\n", hermon, icm_offset );
  1765. icm_offset += icm_usage ( log_num_eqs, hermon->cap.eqc_entry_size );
  1766. /* Memory translation table */
  1767. MLX_FILL_1 ( init_hca, 64,
  1768. tpt_parameters.mtt_base_addr_h, ( icm_offset >> 32 ) );
  1769. MLX_FILL_1 ( init_hca, 65,
  1770. tpt_parameters.mtt_base_addr_l, icm_offset );
  1771. DBGC ( hermon, "Hermon %p ICM MTT base = %llx\n", hermon, icm_offset );
  1772. icm_offset += icm_usage ( log_num_mtts,
  1773. hermon->cap.mtt_entry_size );
  1774. /* Memory protection table */
  1775. log_num_mpts = fls ( hermon->cap.reserved_mrws + 1 - 1 );
  1776. MLX_FILL_1 ( init_hca, 60,
  1777. tpt_parameters.dmpt_base_adr_h, ( icm_offset >> 32 ) );
  1778. MLX_FILL_1 ( init_hca, 61,
  1779. tpt_parameters.dmpt_base_adr_l, icm_offset );
  1780. MLX_FILL_1 ( init_hca, 62,
  1781. tpt_parameters.log_dmpt_sz, log_num_mpts );
  1782. DBGC ( hermon, "Hermon %p ICM DMPT base = %llx\n", hermon, icm_offset);
  1783. icm_offset += icm_usage ( log_num_mpts,
  1784. hermon->cap.dmpt_entry_size );
  1785. /* Multicast table */
  1786. MLX_FILL_1 ( init_hca, 48,
  1787. multicast_parameters.mc_base_addr_h,
  1788. ( icm_offset >> 32 ) );
  1789. MLX_FILL_1 ( init_hca, 49,
  1790. multicast_parameters.mc_base_addr_l, icm_offset );
  1791. MLX_FILL_1 ( init_hca, 52,
  1792. multicast_parameters.log_mc_table_entry_sz,
  1793. fls ( sizeof ( struct hermonprm_mcg_entry ) - 1 ) );
  1794. MLX_FILL_1 ( init_hca, 53,
  1795. multicast_parameters.log_mc_table_hash_sz, 3 );
  1796. MLX_FILL_1 ( init_hca, 54,
  1797. multicast_parameters.log_mc_table_sz, 3 );
  1798. DBGC ( hermon, "Hermon %p ICM MC base = %llx\n", hermon, icm_offset );
  1799. icm_offset += ( ( 8 * sizeof ( struct hermonprm_mcg_entry ) +
  1800. HERMON_PAGE_SIZE - 1 ) & ~( HERMON_PAGE_SIZE - 1 ) );
  1801. hermon->icm_map[HERMON_ICM_OTHER].len =
  1802. ( icm_offset - hermon->icm_map[HERMON_ICM_OTHER].offset );
  1803. /*
  1804. * Allocate and map physical memory for (portions of) ICM
  1805. *
  1806. * Map is:
  1807. * ICM AUX area (aligned to its own size)
  1808. * cMPT areas
  1809. * Other areas
  1810. */
  1811. /* Calculate physical memory required for ICM */
  1812. icm_len = 0;
  1813. for ( i = 0 ; i < HERMON_ICM_NUM_REGIONS ; i++ ) {
  1814. icm_len += hermon->icm_map[i].len;
  1815. }
  1816. /* Get ICM auxiliary area size */
  1817. memset ( &icm_size, 0, sizeof ( icm_size ) );
  1818. MLX_FILL_1 ( &icm_size, 0, value_hi, ( icm_offset >> 32 ) );
  1819. MLX_FILL_1 ( &icm_size, 1, value, icm_offset );
  1820. if ( ( rc = hermon_cmd_set_icm_size ( hermon, &icm_size,
  1821. &icm_aux_size ) ) != 0 ) {
  1822. DBGC ( hermon, "Hermon %p could not set ICM size: %s\n",
  1823. hermon, strerror ( rc ) );
  1824. goto err_set_icm_size;
  1825. }
  1826. icm_aux_len = ( MLX_GET ( &icm_aux_size, value ) * HERMON_PAGE_SIZE );
  1827. /* Allocate ICM data and auxiliary area */
  1828. DBGC ( hermon, "Hermon %p requires %zd kB ICM and %zd kB AUX ICM\n",
  1829. hermon, ( icm_len / 1024 ), ( icm_aux_len / 1024 ) );
  1830. hermon->icm = umalloc ( icm_aux_len + icm_len );
  1831. if ( ! hermon->icm ) {
  1832. rc = -ENOMEM;
  1833. goto err_alloc;
  1834. }
  1835. icm_phys = user_to_phys ( hermon->icm, 0 );
  1836. /* Map ICM auxiliary area */
  1837. DBGC ( hermon, "Hermon %p mapping ICM AUX => %08lx\n",
  1838. hermon, icm_phys );
  1839. if ( ( rc = hermon_map_vpm ( hermon, hermon_cmd_map_icm_aux,
  1840. 0, icm_phys, icm_aux_len ) ) != 0 ) {
  1841. DBGC ( hermon, "Hermon %p could not map AUX ICM: %s\n",
  1842. hermon, strerror ( rc ) );
  1843. goto err_map_icm_aux;
  1844. }
  1845. icm_phys += icm_aux_len;
  1846. /* MAP ICM area */
  1847. for ( i = 0 ; i < HERMON_ICM_NUM_REGIONS ; i++ ) {
  1848. DBGC ( hermon, "Hermon %p mapping ICM %llx+%zx => %08lx\n",
  1849. hermon, hermon->icm_map[i].offset,
  1850. hermon->icm_map[i].len, icm_phys );
  1851. if ( ( rc = hermon_map_vpm ( hermon, hermon_cmd_map_icm,
  1852. hermon->icm_map[i].offset,
  1853. icm_phys,
  1854. hermon->icm_map[i].len ) ) != 0 ){
  1855. DBGC ( hermon, "Hermon %p could not map ICM: %s\n",
  1856. hermon, strerror ( rc ) );
  1857. goto err_map_icm;
  1858. }
  1859. icm_phys += hermon->icm_map[i].len;
  1860. }
  1861. return 0;
  1862. err_map_icm:
  1863. assert ( i == 0 ); /* We don't handle partial failure at present */
  1864. err_map_icm_aux:
  1865. hermon_cmd_unmap_icm_aux ( hermon );
  1866. ufree ( hermon->icm );
  1867. hermon->icm = UNULL;
  1868. err_alloc:
  1869. err_set_icm_size:
  1870. return rc;
  1871. }
  1872. /**
  1873. * Free ICM
  1874. *
  1875. * @v hermon Hermon device
  1876. */
  1877. static void hermon_free_icm ( struct hermon *hermon ) {
  1878. struct hermonprm_scalar_parameter unmap_icm;
  1879. int i;
  1880. for ( i = ( HERMON_ICM_NUM_REGIONS - 1 ) ; i >= 0 ; i-- ) {
  1881. memset ( &unmap_icm, 0, sizeof ( unmap_icm ) );
  1882. MLX_FILL_1 ( &unmap_icm, 0, value_hi,
  1883. ( hermon->icm_map[i].offset >> 32 ) );
  1884. MLX_FILL_1 ( &unmap_icm, 1, value,
  1885. hermon->icm_map[i].offset );
  1886. hermon_cmd_unmap_icm ( hermon,
  1887. ( 1 << fls ( ( hermon->icm_map[i].len /
  1888. HERMON_PAGE_SIZE ) - 1)),
  1889. &unmap_icm );
  1890. }
  1891. hermon_cmd_unmap_icm_aux ( hermon );
  1892. ufree ( hermon->icm );
  1893. hermon->icm = UNULL;
  1894. }
  1895. /***************************************************************************
  1896. *
  1897. * PCI interface
  1898. *
  1899. ***************************************************************************
  1900. */
  1901. /**
  1902. * Set up memory protection table
  1903. *
  1904. * @v hermon Hermon device
  1905. * @ret rc Return status code
  1906. */
  1907. static int hermon_setup_mpt ( struct hermon *hermon ) {
  1908. struct hermonprm_mpt mpt;
  1909. uint32_t key;
  1910. int rc;
  1911. /* Derive key */
  1912. key = ( hermon->cap.reserved_mrws | HERMON_MKEY_PREFIX );
  1913. hermon->reserved_lkey = ( ( key << 8 ) | ( key >> 24 ) );
  1914. /* Initialise memory protection table */
  1915. memset ( &mpt, 0, sizeof ( mpt ) );
  1916. MLX_FILL_4 ( &mpt, 0,
  1917. r_w, 1,
  1918. pa, 1,
  1919. lr, 1,
  1920. lw, 1 );
  1921. MLX_FILL_1 ( &mpt, 2, mem_key, key );
  1922. MLX_FILL_1 ( &mpt, 3, pd, HERMON_GLOBAL_PD );
  1923. MLX_FILL_1 ( &mpt, 10, len64, 1 );
  1924. if ( ( rc = hermon_cmd_sw2hw_mpt ( hermon,
  1925. hermon->cap.reserved_mrws,
  1926. &mpt ) ) != 0 ) {
  1927. DBGC ( hermon, "Hermon %p could not set up MPT: %s\n",
  1928. hermon, strerror ( rc ) );
  1929. return rc;
  1930. }
  1931. return 0;
  1932. }
  1933. /**
  1934. * Probe PCI device
  1935. *
  1936. * @v pci PCI device
  1937. * @v id PCI ID
  1938. * @ret rc Return status code
  1939. */
  1940. static int hermon_probe ( struct pci_device *pci,
  1941. const struct pci_device_id *id __unused ) {
  1942. struct hermon *hermon;
  1943. struct ib_device *ibdev;
  1944. struct hermonprm_init_hca init_hca;
  1945. int i;
  1946. int rc;
  1947. /* Allocate Hermon device */
  1948. hermon = zalloc ( sizeof ( *hermon ) );
  1949. if ( ! hermon ) {
  1950. rc = -ENOMEM;
  1951. goto err_alloc_hermon;
  1952. }
  1953. pci_set_drvdata ( pci, hermon );
  1954. /* Allocate Infiniband devices */
  1955. for ( i = 0 ; i < HERMON_NUM_PORTS ; i++ ) {
  1956. ibdev = alloc_ibdev ( 0 );
  1957. if ( ! ibdev ) {
  1958. rc = -ENOMEM;
  1959. goto err_alloc_ibdev;
  1960. }
  1961. hermon->ibdev[i] = ibdev;
  1962. ibdev->op = &hermon_ib_operations;
  1963. ibdev->dev = &pci->dev;
  1964. ibdev->port = ( HERMON_PORT_BASE + i );
  1965. ib_set_drvdata ( ibdev, hermon );
  1966. }
  1967. /* Fix up PCI device */
  1968. adjust_pci_device ( pci );
  1969. /* Get PCI BARs */
  1970. hermon->config = ioremap ( pci_bar_start ( pci, HERMON_PCI_CONFIG_BAR),
  1971. HERMON_PCI_CONFIG_BAR_SIZE );
  1972. hermon->uar = ioremap ( pci_bar_start ( pci, HERMON_PCI_UAR_BAR ),
  1973. HERMON_UAR_NON_EQ_PAGE * HERMON_PAGE_SIZE );
  1974. /* Allocate space for mailboxes */
  1975. hermon->mailbox_in = malloc_dma ( HERMON_MBOX_SIZE,
  1976. HERMON_MBOX_ALIGN );
  1977. if ( ! hermon->mailbox_in ) {
  1978. rc = -ENOMEM;
  1979. goto err_mailbox_in;
  1980. }
  1981. hermon->mailbox_out = malloc_dma ( HERMON_MBOX_SIZE,
  1982. HERMON_MBOX_ALIGN );
  1983. if ( ! hermon->mailbox_out ) {
  1984. rc = -ENOMEM;
  1985. goto err_mailbox_out;
  1986. }
  1987. /* Start firmware */
  1988. if ( ( rc = hermon_start_firmware ( hermon ) ) != 0 )
  1989. goto err_start_firmware;
  1990. /* Get device limits */
  1991. if ( ( rc = hermon_get_cap ( hermon ) ) != 0 )
  1992. goto err_get_cap;
  1993. /* Allocate ICM */
  1994. memset ( &init_hca, 0, sizeof ( init_hca ) );
  1995. if ( ( rc = hermon_alloc_icm ( hermon, &init_hca ) ) != 0 )
  1996. goto err_alloc_icm;
  1997. /* Initialise HCA */
  1998. MLX_FILL_1 ( &init_hca, 0, version, 0x02 /* "Must be 0x02" */ );
  1999. MLX_FILL_1 ( &init_hca, 5, udp, 1 );
  2000. MLX_FILL_1 ( &init_hca, 74, uar_parameters.log_max_uars, 8 );
  2001. if ( ( rc = hermon_cmd_init_hca ( hermon, &init_hca ) ) != 0 ) {
  2002. DBGC ( hermon, "Hermon %p could not initialise HCA: %s\n",
  2003. hermon, strerror ( rc ) );
  2004. goto err_init_hca;
  2005. }
  2006. /* Set up memory protection */
  2007. if ( ( rc = hermon_setup_mpt ( hermon ) ) != 0 )
  2008. goto err_setup_mpt;
  2009. /* Set up event queue */
  2010. if ( ( rc = hermon_create_eq ( hermon ) ) != 0 )
  2011. goto err_create_eq;
  2012. /* Register Infiniband devices */
  2013. for ( i = 0 ; i < HERMON_NUM_PORTS ; i++ ) {
  2014. if ( ( rc = register_ibdev ( hermon->ibdev[i] ) ) != 0 ) {
  2015. DBGC ( hermon, "Hermon %p could not register IB "
  2016. "device: %s\n", hermon, strerror ( rc ) );
  2017. goto err_register_ibdev;
  2018. }
  2019. }
  2020. return 0;
  2021. i = HERMON_NUM_PORTS;
  2022. err_register_ibdev:
  2023. for ( i-- ; i >= 0 ; i-- )
  2024. unregister_ibdev ( hermon->ibdev[i] );
  2025. hermon_destroy_eq ( hermon );
  2026. err_create_eq:
  2027. err_setup_mpt:
  2028. hermon_cmd_close_hca ( hermon );
  2029. err_init_hca:
  2030. hermon_free_icm ( hermon );
  2031. err_alloc_icm:
  2032. err_get_cap:
  2033. hermon_stop_firmware ( hermon );
  2034. err_start_firmware:
  2035. free_dma ( hermon->mailbox_out, HERMON_MBOX_SIZE );
  2036. err_mailbox_out:
  2037. free_dma ( hermon->mailbox_in, HERMON_MBOX_SIZE );
  2038. err_mailbox_in:
  2039. i = HERMON_NUM_PORTS;
  2040. err_alloc_ibdev:
  2041. for ( i-- ; i >= 0 ; i-- )
  2042. ibdev_put ( hermon->ibdev[i] );
  2043. free ( hermon );
  2044. err_alloc_hermon:
  2045. return rc;
  2046. }
  2047. /**
  2048. * Remove PCI device
  2049. *
  2050. * @v pci PCI device
  2051. */
  2052. static void hermon_remove ( struct pci_device *pci ) {
  2053. struct hermon *hermon = pci_get_drvdata ( pci );
  2054. int i;
  2055. for ( i = ( HERMON_NUM_PORTS - 1 ) ; i >= 0 ; i-- )
  2056. unregister_ibdev ( hermon->ibdev[i] );
  2057. hermon_destroy_eq ( hermon );
  2058. hermon_cmd_close_hca ( hermon );
  2059. hermon_free_icm ( hermon );
  2060. hermon_stop_firmware ( hermon );
  2061. hermon_stop_firmware ( hermon );
  2062. free_dma ( hermon->mailbox_out, HERMON_MBOX_SIZE );
  2063. free_dma ( hermon->mailbox_in, HERMON_MBOX_SIZE );
  2064. for ( i = ( HERMON_NUM_PORTS - 1 ) ; i >= 0 ; i-- )
  2065. ibdev_put ( hermon->ibdev[i] );
  2066. free ( hermon );
  2067. }
  2068. static struct pci_device_id hermon_nics[] = {
  2069. PCI_ROM ( 0x15b3, 0x6340, "mt25408", "MT25408 HCA driver" ),
  2070. PCI_ROM ( 0x15b3, 0x634a, "mt25418", "MT25418 HCA driver" ),
  2071. PCI_ROM ( 0x15b3, 0x6732, "mt26418", "MT26418 HCA driver" ),
  2072. };
  2073. struct pci_driver hermon_driver __pci_driver = {
  2074. .ids = hermon_nics,
  2075. .id_count = ( sizeof ( hermon_nics ) / sizeof ( hermon_nics[0] ) ),
  2076. .probe = hermon_probe,
  2077. .remove = hermon_remove,
  2078. };