Some BIOSes set the PCI cacheline size to zero for the card; the ath5k
driver fixes it to a reasonable in PCI config space, but failed to
correct the internal value it had already read. This resulted in
divide-by-zero errors when cacheline-aligning various data structures.

Fix by setting the internal cachelsz to a sane value at the same time
as we write that value to PCI config space.

Signed-off-by: Marty Connor <mdc@etherboot.org>

This adds basic rfkill support for enabling the wireless card on certain
laptops, and changes miscellaneous other details that may help in obscure
cases.

Also change the error handling to not report CRC errors, which due to the
basic facts of wireless may happen even more frequently than valid packets.

Signed-off-by: Marty Connor <mdc@etherboot.org>

Signed-off-by: Marty Connor <mdc@etherboot.org>

Signed-off-by: Michael Brown <mcb30@etherboot.org>