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[Drivers-r8169] Add support for newer rtl8169 variants from Hilko Bengen

03-19-2008, Hilko Bengen, Cleanups and fixes for newer cards
(successfully tested with 8110SC-d onboard NIC)
tags/v0.9.4
Marty Connor 16 年之前
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fbb6a3fd65
共有 2 個文件被更改,包括 363 次插入221 次删除
  1. 360
    221
      src/drivers/net/r8169.c
  2. 3
    0
      src/include/gpxe/pci.h

+ 360
- 221
src/drivers/net/r8169.c 查看文件

@@ -40,6 +40,9 @@
40 40
 *    v1.5	01-17-2004	timlegge	Initial driver output cleanup
41 41
 *    v1.6	03-27-2004	timlegge	Additional Cleanup
42 42
 *    v1.7	11-22-2005	timlegge	Update to RealTek Driver Version 2.2
43
+*
44
+*		03-19-2008	Hilko Bengen	Cleanups and fixes for newer cards
45
+*				(successfully tested with 8110SC-d onboard NIC)
43 46
 *    
44 47
 *    Indent Options: indent -kr -i8
45 48
 ***************************************************************************/
@@ -50,8 +53,8 @@
50 53
 #include <gpxe/ethernet.h>
51 54
 #include <gpxe/malloc.h>
52 55
 
53
-#define drv_version "v1.6"
54
-#define drv_date "03-27-2004"
56
+#define drv_version "v1.7+"
57
+#define drv_date "03-19-2008"
55 58
 
56 59
 #define HZ 1000
57 60
 
@@ -72,16 +75,6 @@ static u32 ioaddr;
72 75
 #undef RTL8169_DYNAMIC_CONTROL
73 76
 #define RTL8169_USE_IO
74 77
 
75
-
76
-/* media options 
77
-        _10_Half = 0x01,
78
-        _10_Full = 0x02,
79
-        _100_Half = 0x04,
80
-        _100_Full = 0x08,
81
-        _1000_Full = 0x10,
82
-*/
83
-static int media = -1;
84
-
85 78
 #if 0
86 79
 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
87 80
 static int max_interrupt_work = 20;
@@ -148,29 +141,59 @@ static int multicast_filter_limit = 32;
148 141
 #define RTL_R32(reg)		((unsigned long) readl (ioaddr + (reg)))
149 142
 #endif
150 143
 
151
-#define MCFG_METHOD_1		0x01
152
-#define MCFG_METHOD_2		0x02
153
-#define MCFG_METHOD_3		0x03
154
-#define MCFG_METHOD_4		0x04
144
+enum mac_version {
145
+	RTL_GIGA_MAC_VER_01 = 0x01, // 8169
146
+	RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
147
+	RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
148
+	RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
149
+	RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
150
+	RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
151
+	RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
152
+	RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
153
+	RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
154
+	RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
155
+	RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
156
+	RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
157
+	RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
158
+	RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
159
+	RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
160
+	RTL_GIGA_MAC_VER_20 = 0x14  // 8168C
161
+};
155 162
 
156
-#define PCFG_METHOD_1		0x01	//PHY Reg 0x03 bit0-3 == 0x0000
157
-#define PCFG_METHOD_2		0x02	//PHY Reg 0x03 bit0-3 == 0x0001
158
-#define PCFG_METHOD_3		0x03	//PHY Reg 0x03 bit0-3 == 0x0002
163
+enum cfg_version {
164
+	RTL_CFG_0 = 0x00,
165
+	RTL_CFG_1,
166
+	RTL_CFG_2
167
+};
159 168
 
160 169
 static struct {
161 170
 	const char *name;
162
-	u8 mcfg;		/* depend on RTL8169 docs */
171
+	u8 mac_version;		/* depend on RTL8169 docs */
163 172
 	u32 RxConfigMask;	/* should clear the bits supported by this chip */
164 173
 } rtl_chip_info[] = {
165
-	{
166
-	"RTL-8169", MCFG_METHOD_1, 0xff7e1880,}, {
167
-	"RTL8169s/8110s", MCFG_METHOD_2, 0xff7e1880}, {
168
-"RTL8169s/8110s", MCFG_METHOD_3, 0xff7e1880},};
174
+        {"RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880}, // 8169
175
+        {"RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880}, // 8169S
176
+        {"RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880}, // 8110S
177
+        {"RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880}, // 8169SB
178
+        {"RTL8169sc/8110sc-d",RTL_GIGA_MAC_VER_05, 0xff7e1880}, // 8110SCd
179
+        {"RTL8169sc/8110sc-e",RTL_GIGA_MAC_VER_06, 0xff7e1880}, // 8110SCe
180
+        {"RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880}, // PCI-E
181
+        {"RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880}, // PCI-E
182
+        {"RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880}, // PCI-E 8139
183
+        {"RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880}, // PCI-E 8139
184
+        {"RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880}, // PCI-E 8139
185
+        {"RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, 0xff7e1880}, // PCI-E
186
+        {"RTL8101e",          RTL_GIGA_MAC_VER_16, 0xff7e1880}, // PCI-E
187
+        {"RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, 0xff7e1880}, // PCI-E
188
+        {"RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, 0xff7e1880}, // PCI-E
189
+        {"RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, 0xff7e1880}, // PCI-E
190
+};
169 191
 
170 192
 enum RTL8169_registers {
171 193
 	MAC0 = 0x0,		/* Ethernet hardware address. */
172 194
 	MAR0 = 0x8,		/* Multicast filter. */
173
-	TxDescStartAddr = 0x20,
195
+	TxDescAddrLow = 0x20,
196
+	TxDescAddrHigh	= 0x24,
174 197
 	TxHDescStartAddr = 0x28,
175 198
 	FLASH = 0x30,
176 199
 	ERSR = 0x36,
@@ -194,9 +217,11 @@ enum RTL8169_registers {
194 217
 	TBI_ANAR = 0x68,
195 218
 	TBI_LPAR = 0x6A,
196 219
 	PHYstatus = 0x6C,
197
-	RxMaxSize = 0xDA,
198
-	CPlusCmd = 0xE0,
199
-	RxDescStartAddr = 0xE4,
220
+	RxMaxSize = 0xda,
221
+	CPlusCmd = 0xe0,
222
+        IntrMitigate = 0xe2,
223
+	RxDescAddrLow = 0xe4,
224
+	RxDescAddrHigh	= 0xe8,
200 225
 	ETThReg = 0xEC,
201 226
 	FuncEvent = 0xF0,
202 227
 	FuncEventMask = 0xF4,
@@ -345,7 +370,7 @@ static struct rtl8169_private {
345 370
 	void *mmio_addr;	/* memory map physical address */
346 371
 	int chipset;
347 372
 	int pcfg;
348
-	int mcfg;
373
+	int mac_version;
349 374
 	unsigned long cur_rx;	/* Index into the Rx descriptor buffer of next Rx pkt. */
350 375
 	unsigned long cur_tx;	/* Index into the Tx descriptor buffer of next Rx pkt. */
351 376
 	struct TxDesc *TxDescArray;	/* Index of 256-alignment Tx Descriptor buffer */
@@ -354,16 +379,14 @@ static struct rtl8169_private {
354 379
 	unsigned char *Tx_skbuff[NUM_TX_DESC];
355 380
 } tpx;
356 381
 
357
-static struct rtl8169_private *tpc;
358
-
359 382
 static const u16 rtl8169_intr_mask =
360 383
     LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
361 384
 static const unsigned int rtl8169_rx_config =
362 385
     (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift) |
363 386
     0x0000000E;
364 387
 
365
-static void rtl8169_hw_PHY_config(struct nic *nic __unused);
366
-//static void rtl8169_hw_PHY_reset(struct net_device *dev);
388
+static void rtl8169_hw_phy_config(struct nic *nic __unused);
389
+//static void rtl8169_hw_phy_reset(struct net_device *dev);
367 390
 
368 391
 #define RTL8169_WRITE_GMII_REG_BIT( ioaddr, reg, bitnum, bitval )\
369 392
 { \
@@ -457,6 +480,65 @@ static int mdio_read(int RegAddr)
457 480
 }
458 481
 #endif
459 482
 
483
+static void rtl8169_get_mac_version( struct rtl8169_private *tp,
484
+                                     u32 ioaddr )
485
+{
486
+	/*
487
+	 * The driver currently handles the 8168Bf and the 8168Be identically
488
+	 * but they can be identified more specifically through the test below
489
+	 * if needed:
490
+	 *
491
+	 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
492
+	 *
493
+	 * Same thing for the 8101Eb and the 8101Ec:
494
+	 *
495
+	 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
496
+	 */
497
+	const struct {
498
+		u32 mask;
499
+		u32 val;
500
+		int mac_version;
501
+	} mac_info[] = {
502
+		/* 8168B family. */
503
+		{ 0x7c800000, 0x3c800000,	RTL_GIGA_MAC_VER_18 },
504
+		{ 0x7cf00000, 0x3c000000,	RTL_GIGA_MAC_VER_19 },
505
+		{ 0x7cf00000, 0x3c200000,	RTL_GIGA_MAC_VER_20 },
506
+		{ 0x7c800000, 0x3c000000,	RTL_GIGA_MAC_VER_20 },
507
+		/* 8168B family. */
508
+		{ 0x7cf00000, 0x38000000,	RTL_GIGA_MAC_VER_12 },
509
+		{ 0x7cf00000, 0x38500000,	RTL_GIGA_MAC_VER_17 },
510
+		{ 0x7c800000, 0x38000000,	RTL_GIGA_MAC_VER_17 },
511
+		{ 0x7c800000, 0x30000000,	RTL_GIGA_MAC_VER_11 },
512
+		/* 8101 family. */
513
+		{ 0x7cf00000, 0x34000000,	RTL_GIGA_MAC_VER_13 },
514
+		{ 0x7cf00000, 0x34200000,	RTL_GIGA_MAC_VER_16 },
515
+		{ 0x7c800000, 0x34000000,	RTL_GIGA_MAC_VER_16 },
516
+		/* FIXME: where did these entries come from ? -- FR */
517
+		{ 0xfc800000, 0x38800000,	RTL_GIGA_MAC_VER_15 },
518
+		{ 0xfc800000, 0x30800000,	RTL_GIGA_MAC_VER_14 },
519
+		/* 8110 family. */
520
+		{ 0xfc800000, 0x98000000,	RTL_GIGA_MAC_VER_06 },
521
+		{ 0xfc800000, 0x18000000,	RTL_GIGA_MAC_VER_05 },
522
+		{ 0xfc800000, 0x10000000,	RTL_GIGA_MAC_VER_04 },
523
+		{ 0xfc800000, 0x04000000,	RTL_GIGA_MAC_VER_03 },
524
+		{ 0xfc800000, 0x00800000,	RTL_GIGA_MAC_VER_02 },
525
+		{ 0xfc800000, 0x00000000,	RTL_GIGA_MAC_VER_01 },
526
+		{ 0x00000000, 0x00000000,	RTL_GIGA_MAC_VER_01 }	/* Catch-all */
527
+	}, *p = mac_info;
528
+
529
+	unsigned long rv;
530
+
531
+        rv = (RTL_R32(TxConfig));
532
+
533
+	while ((rv & p->mask) != p->val)
534
+		p++;
535
+	tp->mac_version = p->mac_version;
536
+
537
+	if (p->mask == 0x00000000) {
538
+                DBG("unknown MAC (%08lx)\n", rv);
539
+	}
540
+}
541
+
460 542
 #define IORESOURCE_MEM 0x00000200
461 543
 
462 544
 static int rtl8169_init_board(struct pci_device *pdev)
@@ -464,6 +546,7 @@ static int rtl8169_init_board(struct pci_device *pdev)
464 546
 	int i;
465 547
 //	unsigned long mmio_end, mmio_flags
466 548
         unsigned long mmio_start, mmio_len;
549
+	struct rtl8169_private *tp = &tpx;
467 550
 
468 551
 	adjust_pci_device(pdev);
469 552
 
@@ -494,7 +577,7 @@ static int rtl8169_init_board(struct pci_device *pdev)
494 577
 	}
495 578
 #endif
496 579
 
497
-	tpc->mmio_addr = &ioaddr;
580
+	tp->mmio_addr = (void*)ioaddr;
498 581
 	/* Soft reset the chip. */
499 582
 	RTL_W8(ChipCmd, CmdReset);
500 583
 
@@ -504,48 +587,39 @@ static int rtl8169_init_board(struct pci_device *pdev)
504 587
 			break;
505 588
 		else
506 589
 			udelay(10);
507
-	// identify config method
508
-	{
509
-		unsigned long val32 = (RTL_R32(TxConfig) & 0x7c800000);
510
-		if (val32 == (0x1 << 28)) {
511
-			tpc->mcfg = MCFG_METHOD_4;
512
-		} else if (val32 == (0x1 << 26)) {
513
-			tpc->mcfg = MCFG_METHOD_3;
514
-		} else if (val32 == (0x1 << 23)) {
515
-			tpc->mcfg = MCFG_METHOD_2;
516
-		} else if (val32 == 0x00000000) {
517
-			tpc->mcfg = MCFG_METHOD_1;
518
-		} else {
519
-			tpc->mcfg = MCFG_METHOD_1;
520
-		}
521
-	}
590
+
591
+	/* Identify chip attached to board */
592
+        rtl8169_get_mac_version( tp, ioaddr );
593
+
594
+	// rtl8169_print_mac_version(tp);
595
+
522 596
 	{
523 597
 		unsigned char val8 =
524 598
 		    (unsigned char) (RTL8169_READ_GMII_REG(ioaddr, 3) &
525 599
 				     0x000f);
526 600
 		if (val8 == 0x00) {
527
-			tpc->pcfg = PCFG_METHOD_1;
601
+			tp->pcfg = RTL_CFG_0;
528 602
 		} else if (val8 == 0x01) {
529
-			tpc->pcfg = PCFG_METHOD_2;
603
+			tp->pcfg = RTL_CFG_1;
530 604
 		} else if (val8 == 0x02) {
531
-			tpc->pcfg = PCFG_METHOD_3;
605
+			tp->pcfg = RTL_CFG_2;
532 606
 		} else {
533
-			tpc->pcfg = PCFG_METHOD_3;
607
+			tp->pcfg = RTL_CFG_2;
534 608
 		}
535 609
 	}
536 610
 
537 611
 	/* identify chip attached to board */
538 612
 
539 613
 	for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--)
540
-		if (tpc->mcfg == rtl_chip_info[i].mcfg) {
541
-			tpc->chipset = i;
614
+		if (tp->mac_version == rtl_chip_info[i].mac_version) {
615
+			tp->chipset = i;
542 616
 			goto match;
543 617
 		}
544 618
 	/* if unknown chip, assume array element #0, original RTL-8169 in this case */
545 619
 	DBG ( "PCI device: unknown chip version, assuming RTL-8169\n" );
546 620
 	DBG ( "PCI device: TxConfig = %#lX\n", ( unsigned long ) RTL_R32 ( TxConfig ) );
547 621
 
548
-	tpc->chipset = 0;
622
+	tp->chipset = 0;
549 623
 	return 1;
550 624
 
551 625
       match:
@@ -584,51 +658,57 @@ static void r8169_irq(struct nic *nic __unused, irq_action_t action)
584 658
 /**************************************************************************
585 659
 POLL - Wait for a frame
586 660
 ***************************************************************************/
587
-static int r8169_poll(struct nic *nic, int retreive)
661
+static int r8169_poll(struct nic *nic, int retrieve)
588 662
 {
589 663
 	/* return true if there's an ethernet packet ready to read */
590 664
 	/* nic->packet should contain data on return */
591 665
 	/* nic->packetlen should contain length of data */
592 666
 	int cur_rx;
593 667
 	unsigned int intr_status = 0;
594
-	cur_rx = tpc->cur_rx;
595
-	if ((tpc->RxDescArray[cur_rx].status & OWNbit) == 0) {
668
+	struct rtl8169_private *tp = &tpx;
669
+
670
+	cur_rx = tp->cur_rx;
671
+	if ((tp->RxDescArray[cur_rx].status & OWNbit) == 0) {
596 672
 		/* There is a packet ready */
597
-		if (!retreive)
673
+                DBG("r8169_poll(): packet ready\n");
674
+		if (!retrieve)
598 675
 			return 1;
599 676
 		intr_status = RTL_R16(IntrStatus);
600 677
 		/* h/w no longer present (hotplug?) or major error,
601 678
 		   bail */
602
-		if (intr_status == 0xFFFF)
679
+		if (intr_status == 0xFFFF) {
680
+                        DBG("r8169_poll(): unknown error\n");
603 681
 			return 0;
682
+                }
604 683
 		RTL_W16(IntrStatus, intr_status &
605 684
 			~(RxFIFOOver | RxOverflow | RxOK));
606 685
 
607
-		if (!(tpc->RxDescArray[cur_rx].status & RxRES)) {
608
-			nic->packetlen = (int) (tpc->RxDescArray[cur_rx].
686
+		if (!(tp->RxDescArray[cur_rx].status & RxRES)) {
687
+			nic->packetlen = (int) (tp->RxDescArray[cur_rx].
609 688
 						status & 0x00001FFF) - 4;
610
-			memcpy(nic->packet, tpc->RxBufferRing[cur_rx],
689
+			memcpy(nic->packet, tp->RxBufferRing[cur_rx],
611 690
 			       nic->packetlen);
612 691
 			if (cur_rx == NUM_RX_DESC - 1)
613
-				tpc->RxDescArray[cur_rx].status =
692
+				tp->RxDescArray[cur_rx].status =
614 693
 				    (OWNbit | EORbit) + RX_BUF_SIZE;
615 694
 			else
616
-				tpc->RxDescArray[cur_rx].status =
695
+				tp->RxDescArray[cur_rx].status =
617 696
 				    OWNbit + RX_BUF_SIZE;
618
-			tpc->RxDescArray[cur_rx].buf_addr =
619
-			    virt_to_bus(tpc->RxBufferRing[cur_rx]);
697
+			tp->RxDescArray[cur_rx].buf_addr =
698
+			    virt_to_bus(tp->RxBufferRing[cur_rx]);
699
+			tp->RxDescArray[cur_rx].buf_Haddr = 0;
620 700
 		} else
621 701
 			printf("Error Rx");
622 702
 		/* FIXME: shouldn't I reset the status on an error */
623 703
 		cur_rx = (cur_rx + 1) % NUM_RX_DESC;
624
-		tpc->cur_rx = cur_rx;
704
+		tp->cur_rx = cur_rx;
625 705
 		RTL_W16(IntrStatus, intr_status &
626 706
 			(RxFIFOOver | RxOverflow | RxOK));
627 707
 
628 708
 		return 1;
629 709
 
630 710
 	}
631
-	tpc->cur_rx = cur_rx;
711
+	tp->cur_rx = cur_rx;
632 712
 	/* FIXME: There is no reason to do this as cur_rx did not change */
633 713
 
634 714
 	return (0);		/* initially as this is called to flush the input */
@@ -648,10 +728,11 @@ static void r8169_transmit(struct nic *nic, const char *d,	/* Destination */
648 728
 	u16 nstype;
649 729
 	u32 to;
650 730
 	u8 *ptxb;
651
-	int entry = tpc->cur_tx % NUM_TX_DESC;
731
+	struct rtl8169_private *tp = &tpx;
732
+	int entry = tp->cur_tx % NUM_TX_DESC;
652 733
 
653 734
 	/* point to the current txb incase multiple tx_rings are used */
654
-	ptxb = tpc->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
735
+	ptxb = tp->Tx_skbuff[entry * MAX_ETH_FRAME_SIZE];
655 736
 	memcpy(ptxb, d, ETH_ALEN);
656 737
 	memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN);
657 738
 	nstype = htons((u16) t);
@@ -662,20 +743,21 @@ static void r8169_transmit(struct nic *nic, const char *d,	/* Destination */
662 743
 	while (s < ETH_ZLEN)
663 744
 		ptxb[s++] = '\0';
664 745
 
665
-	tpc->TxDescArray[entry].buf_addr = virt_to_bus(ptxb);
746
+	tp->TxDescArray[entry].buf_addr = virt_to_bus(ptxb);
747
+	tp->TxDescArray[entry].buf_Haddr = 0;
666 748
 	if (entry != (NUM_TX_DESC - 1))
667
-		tpc->TxDescArray[entry].status =
749
+		tp->TxDescArray[entry].status =
668 750
 		    (OWNbit | FSbit | LSbit) | ((s > ETH_ZLEN) ? s :
669 751
 						ETH_ZLEN);
670 752
 	else
671
-		tpc->TxDescArray[entry].status =
753
+		tp->TxDescArray[entry].status =
672 754
 		    (OWNbit | EORbit | FSbit | LSbit) | ((s > ETH_ZLEN) ? s
673 755
 							 : ETH_ZLEN);
674 756
 	RTL_W8(TxPoll, 0x40);	/* set polling bit */
675 757
 
676
-	tpc->cur_tx++;
758
+	tp->cur_tx++;
677 759
 	to = currticks() + TX_TIMEOUT;
678
-	while ((tpc->TxDescArray[entry].status & OWNbit) && (currticks() < to));	/* wait */
760
+	while ((tp->TxDescArray[entry].status & OWNbit) && (currticks() < to));	/* wait */
679 761
 
680 762
 	if (currticks() >= to) {
681 763
 		printf("TX Time Out");
@@ -687,6 +769,7 @@ static void rtl8169_set_rx_mode(struct nic *nic __unused)
687 769
 	u32 mc_filter[2];	/* Multicast hash filter */
688 770
 	int rx_mode;
689 771
 	u32 tmp = 0;
772
+	struct rtl8169_private *tp = &tpx;
690 773
 
691 774
 	/* IFF_ALLMULTI */
692 775
 	/* Too many to filter perfectly -- accept all multicasts. */
@@ -695,7 +778,7 @@ static void rtl8169_set_rx_mode(struct nic *nic __unused)
695 778
 
696 779
 	tmp =
697 780
 	    rtl8169_rx_config | rx_mode | (RTL_R32(RxConfig) &
698
-					   rtl_chip_info[tpc->chipset].
781
+					   rtl_chip_info[tp->chipset].
699 782
 					   RxConfigMask);
700 783
 
701 784
 	RTL_W32(RxConfig, tmp);
@@ -705,6 +788,7 @@ static void rtl8169_set_rx_mode(struct nic *nic __unused)
705 788
 static void rtl8169_hw_start(struct nic *nic)
706 789
 {
707 790
 	u32 i;
791
+	struct rtl8169_private *tp = &tpx;
708 792
 
709 793
 	/* Soft reset the chip. */
710 794
 	RTL_W8(ChipCmd, CmdReset);
@@ -726,7 +810,7 @@ static void rtl8169_hw_start(struct nic *nic)
726 810
 
727 811
 	/* Set Rx Config register */
728 812
 	i = rtl8169_rx_config | (RTL_R32(RxConfig) &
729
-				 rtl_chip_info[tpc->chipset].RxConfigMask);
813
+				 rtl_chip_info[tp->chipset].RxConfigMask);
730 814
 	RTL_W32(RxConfig, i);
731 815
 
732 816
 	/* Set DMA burst size and Interframe Gap Time */
@@ -737,7 +821,7 @@ static void rtl8169_hw_start(struct nic *nic)
737 821
 
738 822
 	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd));
739 823
 
740
-	if (tpc->mcfg == MCFG_METHOD_2 || tpc->mcfg == MCFG_METHOD_3) {
824
+	if (tp->mac_version == RTL_GIGA_MAC_VER_02 || tp->mac_version == RTL_GIGA_MAC_VER_03) {
741 825
 		RTL_W16(CPlusCmd,
742 826
 			(RTL_R16(CPlusCmd) | (1 << 14) | (1 << 3)));
743 827
 		DBG
@@ -748,18 +832,18 @@ static void rtl8169_hw_start(struct nic *nic)
748 832
 	}
749 833
 
750 834
 	{
751
-		//RTL_W16(0xE2, 0x1517);
752
-		//RTL_W16(0xE2, 0x152a);
753
-		//RTL_W16(0xE2, 0x282a);
754
-		RTL_W16(0xE2, 0x0000);
835
+		//RTL_W16(IntrMitigate, 0x1517);
836
+		//RTL_W16(IntrMitigate, 0x152a);
837
+		//RTL_W16(IntrMitigate, 0x282a);
838
+		RTL_W16(IntrMitigate, 0x0000);
755 839
 	}
756 840
 
841
+	tp->cur_rx = 0;
757 842
 
758
-
759
-	tpc->cur_rx = 0;
760
-
761
-	RTL_W32(TxDescStartAddr, virt_to_le32desc(tpc->TxDescArray));
762
-	RTL_W32(RxDescStartAddr, virt_to_le32desc(tpc->RxDescArray));
843
+	RTL_W32(TxDescAddrLow, virt_to_le32desc(tp->TxDescArray));
844
+	RTL_W32(TxDescAddrHigh, virt_to_le32desc(NULL));
845
+	RTL_W32(RxDescAddrLow, virt_to_le32desc(tp->RxDescArray));
846
+	RTL_W32(RxDescAddrHigh, virt_to_le32desc(NULL));
763 847
 	RTL_W8(Cfg9346, Cfg9346_Lock);
764 848
 	udelay(10);
765 849
 
@@ -777,26 +861,28 @@ static void rtl8169_hw_start(struct nic *nic)
777 861
 static void rtl8169_init_ring(struct nic *nic __unused)
778 862
 {
779 863
 	int i;
864
+	struct rtl8169_private *tp = &tpx;
780 865
 
781
-	tpc->cur_rx = 0;
782
-	tpc->cur_tx = 0;
783
-	memset(tpc->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
784
-	memset(tpc->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
866
+	tp->cur_rx = 0;
867
+	tp->cur_tx = 0;
868
+	memset(tp->TxDescArray, 0x0, NUM_TX_DESC * sizeof(struct TxDesc));
869
+	memset(tp->RxDescArray, 0x0, NUM_RX_DESC * sizeof(struct RxDesc));
785 870
 
786 871
 	for (i = 0; i < NUM_TX_DESC; i++) {
787
-		tpc->Tx_skbuff[i] = &txb[i];
872
+		tp->Tx_skbuff[i] = &txb[i];
788 873
 	}
789 874
 
790 875
 	for (i = 0; i < NUM_RX_DESC; i++) {
791 876
 		if (i == (NUM_RX_DESC - 1))
792
-			tpc->RxDescArray[i].status =
877
+			tp->RxDescArray[i].status =
793 878
 			    (OWNbit | EORbit) | RX_BUF_SIZE;
794 879
 		else
795
-			tpc->RxDescArray[i].status = OWNbit | RX_BUF_SIZE;
880
+			tp->RxDescArray[i].status = OWNbit | RX_BUF_SIZE;
796 881
 
797
-		tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
798
-		tpc->RxDescArray[i].buf_addr =
799
-		    virt_to_bus(tpc->RxBufferRing[i]);
882
+		tp->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
883
+		tp->RxDescArray[i].buf_addr =
884
+		    virt_to_bus(tp->RxBufferRing[i]);
885
+		tp->RxDescArray[i].buf_Haddr = 0;
800 886
 	}
801 887
 }
802 888
 
@@ -806,9 +892,10 @@ RESET - Finish setting up the ethernet interface
806 892
 static void r8169_reset(struct nic *nic)
807 893
 {
808 894
 	int i;
895
+	struct rtl8169_private *tp = &tpx;
809 896
 
810
-	tpc->TxDescArray = tx_ring;
811
-	tpc->RxDescArray = rx_ring;
897
+	tp->TxDescArray = tx_ring;
898
+	tp->RxDescArray = rx_ring;
812 899
 
813 900
 	rtl8169_init_ring(nic);
814 901
 	rtl8169_hw_start(nic);
@@ -830,6 +917,8 @@ DISABLE - Turn off ethernet interface
830 917
 ***************************************************************************/
831 918
 static void r8169_disable ( struct nic *nic __unused ) {
832 919
 	int i;
920
+	struct rtl8169_private *tp = &tpx;
921
+
833 922
 	/* Stop the chip's Tx and Rx DMA processes. */
834 923
 	RTL_W8(ChipCmd, 0x00);
835 924
 
@@ -838,10 +927,10 @@ static void r8169_disable ( struct nic *nic __unused ) {
838 927
 
839 928
 	RTL_W32(RxMissed, 0);
840 929
 
841
-	tpc->TxDescArray = NULL;
842
-	tpc->RxDescArray = NULL;
930
+	tp->TxDescArray = NULL;
931
+	tp->RxDescArray = NULL;
843 932
 	for (i = 0; i < NUM_RX_DESC; i++) {
844
-		tpc->RxBufferRing[i] = NULL;
933
+		tp->RxBufferRing[i] = NULL;
845 934
 	}
846 935
 }
847 936
 
@@ -858,6 +947,10 @@ static struct pci_device_id r8169_nics[] = {
858 947
         PCI_ROM(0x16ec, 0x0116, "usr-r8169", "US Robotics RTL8169 Gigabit Ethernet"),
859 948
         PCI_ROM(0x1186, 0x4300, "dlink-r8169", "D-Link RTL8169 Gigabit Ethernet"),
860 949
 	PCI_ROM(0x1737, 0x1032, "linksys-r8169", "Linksys RTL8169 Gigabit Ethernet"),
950
+	PCI_ROM(0x10ec, 0x8129, "r8169-8129", "RealTek RT8129 Fast Ethernet Adapter"),
951
+	PCI_ROM(0x10ec, 0x8136, "r8169-8101e", "RealTek RTL8101E PCI Express Fast Ethernet controller"),
952
+	PCI_ROM(0x10ec, 0x8167, "r8169-8110sc/8169sc", "RealTek RTL-8110SC/8169SC Gigabit Ethernet"),
953
+	PCI_ROM(0x10ec, 0x8168, "r8169-8168b", "RealTek RTL8111/8168B PCI Express Gigabit Ethernet controller"),
861 954
 };
862 955
 
863 956
 PCI_DRIVER ( r8169_driver, r8169_nics, PCI_NO_CLASS );
@@ -872,6 +965,7 @@ static int r8169_probe ( struct nic *nic, struct pci_device *pci ) {
872 965
 
873 966
 	static int board_idx = -1;
874 967
 	static int printed_version = 0;
968
+	struct rtl8169_private *tp = &tpx;
875 969
 	int i, rc;
876 970
 	int option = -1, Cap10_100 = 0, Cap1000 = 0;
877 971
 
@@ -891,9 +985,6 @@ static int r8169_probe ( struct nic *nic, struct pci_device *pci ) {
891 985
 		return 0;
892 986
 	memset ( r8169_bufs, 0, sizeof ( *r8169_bufs ) );
893 987
 
894
-	/* point to private storage */
895
-	tpc = &tpx;
896
-
897 988
 	rc = rtl8169_init_board(pci);	/* Return code is meaningless */
898 989
 
899 990
 	/* Get MAC address.  FIXME: read EEPROM */
@@ -901,30 +992,32 @@ static int r8169_probe ( struct nic *nic, struct pci_device *pci ) {
901 992
 		nic->node_addr[i] = RTL_R8(MAC0 + i);
902 993
 
903 994
 	DBG ( "%s: Identified chip type is '%s'.\n", pci->driver_name,
904
-		 rtl_chip_info[tpc->chipset].name );
995
+		 rtl_chip_info[tp->chipset].name );
905 996
 
906 997
 	/* Print out some hardware info */
907
-	DBG ( "%s: %s at IOAddr %#hX, ", pci->driver_name, eth_ntoa ( nic->node_addr ),
998
+	DBG ( "%s: %s at ioaddr %#hx, ", pci->driver_name, eth_ntoa ( nic->node_addr ),
908 999
 	      (unsigned int) ioaddr );
909 1000
 
910 1001
 	/* Config PHY */
911
-	rtl8169_hw_PHY_config(nic);
912
-
1002
+	rtl8169_hw_phy_config(nic);
1003
+ 
913 1004
 	DBG("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
914 1005
 	RTL_W8(0x82, 0x01);
915 1006
 
916
-	if (tpc->mcfg < MCFG_METHOD_3) {
917
-		DBG("Set PCI Latency=0x40\n");
918
-		pci_write_config_byte(pci, PCI_LATENCY_TIMER, 0x40);
919
-	}
1007
+	pci_write_config_byte(pci, PCI_LATENCY_TIMER, 0x40);
1008
+
1009
+	if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1010
+		pci_write_config_byte(pci, PCI_CACHE_LINE_SIZE, 0x08);
920 1011
 
921
-	if (tpc->mcfg == MCFG_METHOD_2) {
1012
+	if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
922 1013
 		DBG("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
923 1014
 		RTL_W8(0x82, 0x01);
924 1015
 		DBG("Set PHY Reg 0x0bh = 0x00h\n");
925
-		RTL8169_WRITE_GMII_REG(ioaddr, 0x0b, 0x0000);	//w 0x0b 15 0 0
1016
+		RTL8169_WRITE_GMII_REG(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
926 1017
 	}
927 1018
 
1019
+	r8169_reset(nic);
1020
+
928 1021
 	/* if TBI is not endbled */
929 1022
 	if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
930 1023
 		int val = RTL8169_READ_GMII_REG(ioaddr, PHY_AUTO_NEGO_REG);
@@ -933,7 +1026,6 @@ static int r8169_probe ( struct nic *nic, struct pci_device *pci ) {
933 1026
 		val |= PHY_Cap_PAUSE | PHY_Cap_ASYM_PAUSE;
934 1027
 #endif				//end #define RTL8169_HW_FLOW_CONTROL_SUPPORT
935 1028
 
936
-		option = media;
937 1029
 		/* Force RTL8169 in 10/100/1000 Full/Half mode. */
938 1030
 		if (option > 0) {
939 1031
 			printf(" Force-mode Enabled.\n");
@@ -1062,113 +1154,160 @@ static void rtl8169_hw_PHY_reset(struct nic *nic __unused)
1062 1154
 
1063 1155
 */
1064 1156
 
1065
-//======================================================================================================
1066
-static void rtl8169_hw_PHY_config(struct nic *nic __unused)
1157
+struct phy_reg {
1158
+	u16 reg;
1159
+	u16 val;
1160
+};
1161
+
1162
+static void rtl_phy_write(void *ioaddr, struct phy_reg *regs, int len)
1067 1163
 {
1164
+	while (len-- > 0) {
1165
+		RTL8169_WRITE_GMII_REG((u32)ioaddr, regs->reg, regs->val);
1166
+		regs++;
1167
+	}
1168
+}
1068 1169
 
1069
-	DBG("priv->mcfg=%d, priv->pcfg=%d\n", tpc->mcfg, tpc->pcfg);
1170
+static void rtl8169s_hw_phy_config(void *ioaddr)
1171
+{
1172
+	struct {
1173
+		u16 regs[5]; /* Beware of bit-sign propagation */
1174
+	} phy_magic[5] = { {
1175
+		{ 0x0000,	//w 4 15 12 0
1176
+		  0x00a1,	//w 3 15 0 00a1
1177
+		  0x0008,	//w 2 15 0 0008
1178
+		  0x1020,	//w 1 15 0 1020
1179
+		  0x1000 } },{	//w 0 15 0 1000
1180
+		{ 0x7000,	//w 4 15 12 7
1181
+		  0xff41,	//w 3 15 0 ff41
1182
+		  0xde60,	//w 2 15 0 de60
1183
+		  0x0140,	//w 1 15 0 0140
1184
+		  0x0077 } },{	//w 0 15 0 0077
1185
+		{ 0xa000,	//w 4 15 12 a
1186
+		  0xdf01,	//w 3 15 0 df01
1187
+		  0xdf20,	//w 2 15 0 df20
1188
+		  0xff95,	//w 1 15 0 ff95
1189
+		  0xfa00 } },{	//w 0 15 0 fa00
1190
+		{ 0xb000,	//w 4 15 12 b
1191
+		  0xff41,	//w 3 15 0 ff41
1192
+		  0xde20,	//w 2 15 0 de20
1193
+		  0x0140,	//w 1 15 0 0140
1194
+		  0x00bb } },{	//w 0 15 0 00bb
1195
+		{ 0xf000,	//w 4 15 12 f
1196
+		  0xdf01,	//w 3 15 0 df01
1197
+		  0xdf20,	//w 2 15 0 df20
1198
+		  0xff95,	//w 1 15 0 ff95
1199
+		  0xbf00 }	//w 0 15 0 bf00
1200
+		}
1201
+	}, *p = phy_magic;
1202
+	unsigned int i;
1203
+
1204
+	RTL8169_WRITE_GMII_REG((u32)ioaddr, 0x1f, 0x0001);		//w 31 2 0 1
1205
+	RTL8169_WRITE_GMII_REG((u32)ioaddr, 0x15, 0x1000);		//w 21 15 0 1000
1206
+	RTL8169_WRITE_GMII_REG((u32)ioaddr, 0x18, 0x65c7);		//w 24 15 0 65c7
1207
+	RTL8169_WRITE_GMII_REG_BIT((u32)ioaddr, 4, 11, 0);	//w 4 11 11 0
1208
+
1209
+	for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1210
+		int val, pos = 4;
1211
+
1212
+		val = (RTL8169_READ_GMII_REG((u32)ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1213
+		RTL8169_WRITE_GMII_REG((u32)ioaddr, pos, val);
1214
+		while (--pos >= 0)
1215
+			RTL8169_WRITE_GMII_REG((u32)ioaddr, pos, p->regs[4 - pos] & 0xffff);
1216
+		RTL8169_WRITE_GMII_REG_BIT((u32)ioaddr, 4, 11, 1); //w 4 11 11 1
1217
+		RTL8169_WRITE_GMII_REG_BIT((u32)ioaddr, 4, 11, 0); //w 4 11 11 0
1218
+	}
1219
+	RTL8169_WRITE_GMII_REG((u32)ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1220
+}
1070 1221
 
1071
-	if (tpc->mcfg == MCFG_METHOD_4) {
1072
-/*
1073
-                RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x1F, 0x0001 );
1074
-                RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x1b, 0x841e );
1075
-                RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x0e, 0x7bfb );
1076
-                RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x09, 0x273a );
1077
-*/
1222
+static void rtl8169sb_hw_phy_config(void *ioaddr)
1223
+{
1224
+	struct phy_reg phy_reg_init[] = {
1225
+		{ 0x1f, 0x0002 },
1226
+		{ 0x01, 0x90d0 },
1227
+		{ 0x1f, 0x0000 }
1228
+	};
1078 1229
 
1079
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1080
-				       0x0002);
1081
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1082
-				       0x90D0);
1083
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1084
-				       0x0000);
1085
-	} else if ((tpc->mcfg == MCFG_METHOD_2)
1086
-		   || (tpc->mcfg == MCFG_METHOD_3)) {
1087
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1088
-				       0x0001);
1089
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x15,
1090
-				       0x1000);
1091
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x18,
1092
-				       0x65C7);
1093
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1094
-				       0x0000);
1095
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1096
-				       0x00A1);
1097
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1098
-				       0x0008);
1099
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1100
-				       0x1020);
1101
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1102
-				       0x1000);
1103
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1104
-				       0x0800);
1105
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1106
-				       0x0000);
1107
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1108
-				       0x7000);
1109
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1110
-				       0xFF41);
1111
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1112
-				       0xDE60);
1113
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1114
-				       0x0140);
1115
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1116
-				       0x0077);
1117
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1118
-				       0x7800);
1119
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1120
-				       0x7000);
1121
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1122
-				       0xA000);
1123
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1124
-				       0xDF01);
1125
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1126
-				       0xDF20);
1127
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1128
-				       0xFF95);
1129
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1130
-				       0xFA00);
1131
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1132
-				       0xA800);
1133
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1134
-				       0xA000);
1135
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1136
-				       0xB000);
1137
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1138
-				       0xFF41);
1139
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1140
-				       0xDE20);
1141
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1142
-				       0x0140);
1143
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1144
-				       0x00BB);
1145
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1146
-				       0xB800);
1147
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1148
-				       0xB000);
1149
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1150
-				       0xF000);
1151
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1152
-				       0xDF01);
1153
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1154
-				       0xDF20);
1155
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1156
-				       0xFF95);
1157
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1158
-				       0xBF00);
1159
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1160
-				       0xF800);
1161
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1162
-				       0xF000);
1163
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1164
-				       0x0000);
1165
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1166
-				       0x0000);
1167
-		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x0B,
1168
-				       0x0000);
1169
-	} else {
1170
-		DBG("tpc->mcfg=%d. Discard hw PHY config.\n",
1171
-			  tpc->mcfg);
1230
+	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1231
+}
1232
+
1233
+static void rtl8168cp_hw_phy_config(void *ioaddr)
1234
+{
1235
+	struct phy_reg phy_reg_init[] = {
1236
+		{ 0x1f, 0x0000 },
1237
+		{ 0x1d, 0x0f00 },
1238
+		{ 0x1f, 0x0002 },
1239
+		{ 0x0c, 0x1ec8 },
1240
+		{ 0x1f, 0x0000 }
1241
+	};
1242
+
1243
+	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1244
+}
1245
+
1246
+static void rtl8168c_hw_phy_config(void *ioaddr)
1247
+{
1248
+	struct phy_reg phy_reg_init[] = {
1249
+		{ 0x1f, 0x0001 },
1250
+		{ 0x12, 0x2300 },
1251
+		{ 0x1f, 0x0002 },
1252
+		{ 0x00, 0x88d4 },
1253
+		{ 0x01, 0x82b1 },
1254
+		{ 0x03, 0x7002 },
1255
+		{ 0x08, 0x9e30 },
1256
+		{ 0x09, 0x01f0 },
1257
+		{ 0x0a, 0x5500 },
1258
+		{ 0x0c, 0x00c8 },
1259
+		{ 0x1f, 0x0003 },
1260
+		{ 0x12, 0xc096 },
1261
+		{ 0x16, 0x000a },
1262
+		{ 0x1f, 0x0000 }
1263
+	};
1264
+
1265
+	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1266
+}
1267
+
1268
+static void rtl8168cx_hw_phy_config(void *ioaddr)
1269
+{
1270
+	struct phy_reg phy_reg_init[] = {
1271
+		{ 0x1f, 0x0000 },
1272
+		{ 0x12, 0x2300 },
1273
+		{ 0x1f, 0x0003 },
1274
+		{ 0x16, 0x0f0a },
1275
+		{ 0x1f, 0x0000 },
1276
+		{ 0x1f, 0x0002 },
1277
+		{ 0x0c, 0x7eb8 },
1278
+		{ 0x1f, 0x0000 }
1279
+	};
1280
+
1281
+	rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1282
+}
1283
+
1284
+static void rtl8169_hw_phy_config(struct nic *nic __unused)
1285
+{
1286
+	struct rtl8169_private *tp = &tpx;
1287
+	void *ioaddr = tp->mmio_addr;
1288
+	DBG("rtl8169_hw_phy_config(): card at addr=0x%lx: priv->mac_version=%d, priv->pcfg=%d\n", (unsigned long) ioaddr, tp->mac_version, tp->pcfg);
1289
+
1290
+	switch (tp->mac_version) {
1291
+	case RTL_GIGA_MAC_VER_01:
1292
+		break;
1293
+	case RTL_GIGA_MAC_VER_02:
1294
+	case RTL_GIGA_MAC_VER_03:
1295
+		rtl8169s_hw_phy_config(ioaddr);
1296
+		break;
1297
+	case RTL_GIGA_MAC_VER_04:
1298
+		rtl8169sb_hw_phy_config(ioaddr);
1299
+		break;
1300
+	case RTL_GIGA_MAC_VER_18:
1301
+		rtl8168cp_hw_phy_config(ioaddr);
1302
+		break;
1303
+	case RTL_GIGA_MAC_VER_19:
1304
+		rtl8168c_hw_phy_config(ioaddr);
1305
+		break;
1306
+	case RTL_GIGA_MAC_VER_20:
1307
+		rtl8168cx_hw_phy_config(ioaddr);
1308
+		break;
1309
+	default:
1310
+		break;
1172 1311
 	}
1173 1312
 }
1174 1313
 

+ 3
- 0
src/include/gpxe/pci.h 查看文件

@@ -30,7 +30,10 @@
30 30
 #define PCI_COMMAND_IO			0x1	/* Enable response in I/O space */
31 31
 #define PCI_COMMAND_MEM			0x2	/* Enable response in mem space */
32 32
 #define PCI_COMMAND_MASTER		0x4	/* Enable bus mastering */
33
+
34
+#define PCI_CACHE_LINE_SIZE		0x0c	/* 8 bits */
33 35
 #define PCI_LATENCY_TIMER		0x0d	/* 8 bits */
36
+
34 37
 #define PCI_COMMAND_SPECIAL		0x8	/* Enable response to special cycles */
35 38
 #define PCI_COMMAND_INVALIDATE		0x10	/* Use memory write and invalidate */
36 39
 #define  PCI_COMMAND_VGA_PALETTE 0x20	/* Enable palette snooping */

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