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[intel] Show original CTRL and STATUS values in debugging output

In situations where iPXE fails to reach link-up as expected, it is
useful to know the original values of the CTRL and STATUS registers
prior to our reset attempt.

Signed-off-by: Michael Brown <mcb30@ipxe.org>
tags/v1.20.1
Michael Brown 7 anos atrás
pai
commit
e6616da8b8
1 arquivos alterados com 12 adições e 4 exclusões
  1. 12
    4
      src/drivers/net/intel.c

+ 12
- 4
src/drivers/net/intel.c Ver arquivo

@@ -268,6 +268,12 @@ static int intel_reset ( struct intel_nic *intel ) {
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 	uint32_t pba;
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 	uint32_t ctrl;
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 	uint32_t status;
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+	uint32_t orig_ctrl;
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+	uint32_t orig_status;
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+
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+	/* Record initial control and status register values */
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+	orig_ctrl = ctrl = readl ( intel->regs + INTEL_CTRL );
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+	orig_status = readl ( intel->regs + INTEL_STATUS );
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272 278
 	/* Force RX and TX packet buffer allocation, to work around an
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 	 * errata in ICH devices.
@@ -285,7 +291,6 @@ static int intel_reset ( struct intel_nic *intel ) {
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 	}
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 	/* Always reset MAC.  Required to reset the TX and RX rings. */
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-	ctrl = readl ( intel->regs + INTEL_CTRL );
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 	writel ( ( ctrl | INTEL_CTRL_RST ), intel->regs + INTEL_CTRL );
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 	mdelay ( INTEL_RESET_DELAY_MS );
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@@ -309,9 +314,10 @@ static int intel_reset ( struct intel_nic *intel ) {
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 	status = readl ( intel->regs + INTEL_STATUS );
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 	if ( ( intel->flags & INTEL_NO_PHY_RST ) ||
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 	     ( status & INTEL_STATUS_LU ) ) {
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-		DBGC ( intel, "INTEL %p %sMAC reset (ctrl %08x)\n", intel,
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+		DBGC ( intel, "INTEL %p %sMAC reset (%08x/%08x was "
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+		       "%08x/%08x)\n", intel,
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 		       ( ( intel->flags & INTEL_NO_PHY_RST ) ? "forced " : "" ),
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-		       ctrl );
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+		       ctrl, status, orig_ctrl, orig_status );
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 		return 0;
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 	}
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@@ -323,8 +329,10 @@ static int intel_reset ( struct intel_nic *intel ) {
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 	/* PHY reset is not self-clearing on all models */
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 	writel ( ctrl, intel->regs + INTEL_CTRL );
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 	mdelay ( INTEL_RESET_DELAY_MS );
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+	status = readl ( intel->regs + INTEL_STATUS );
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-	DBGC ( intel, "INTEL %p MAC+PHY reset (ctrl %08x)\n", intel, ctrl );
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+	DBGC ( intel, "INTEL %p MAC+PHY reset (%08x/%08x was %08x/%08x)\n",
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+	       intel, ctrl, status, orig_ctrl, orig_status );
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 	return 0;
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 }
330 338
 

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