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[pci] Rewrite unrelicensable portions of pci.h

Signed-off-by: Michael Brown <mcb30@ipxe.org>
tags/v1.20.1
Michael Brown 9 年之前
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e399fc0d21

+ 8
- 8
src/drivers/bus/pci.c 查看文件

@@ -62,8 +62,8 @@ static unsigned long pci_bar ( struct pci_device *pci, unsigned int reg ) {
62 62
 	uint32_t high;
63 63
 
64 64
 	pci_read_config_dword ( pci, reg, &low );
65
-	if ( ( low & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK) )
66
-	     == (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64) ){
65
+	if ( ( low & (PCI_BASE_ADDRESS_SPACE_IO|PCI_BASE_ADDRESS_MEM_TYPE_MASK))
66
+	     == PCI_BASE_ADDRESS_MEM_TYPE_64 ) {
67 67
 		pci_read_config_dword ( pci, reg + 4, &high );
68 68
 		if ( high ) {
69 69
 			if ( sizeof ( unsigned long ) > sizeof ( uint32_t ) ) {
@@ -97,10 +97,10 @@ unsigned long pci_bar_start ( struct pci_device *pci, unsigned int reg ) {
97 97
 	unsigned long bar;
98 98
 
99 99
 	bar = pci_bar ( pci, reg );
100
-	if ( (bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY ){
101
-		return ( bar & PCI_BASE_ADDRESS_MEM_MASK );
100
+	if ( bar & PCI_BASE_ADDRESS_SPACE_IO ) {
101
+		return ( bar & ~PCI_BASE_ADDRESS_IO_MASK );
102 102
 	} else {
103
-		return ( bar & PCI_BASE_ADDRESS_IO_MASK );
103
+		return ( bar & ~PCI_BASE_ADDRESS_MEM_MASK );
104 104
 	}
105 105
 }
106 106
 
@@ -126,11 +126,11 @@ static void pci_read_bases ( struct pci_device *pci ) {
126 126
 		if ( bar & PCI_BASE_ADDRESS_SPACE_IO ) {
127 127
 			if ( ! pci->ioaddr )
128 128
 				pci->ioaddr = 
129
-					( bar & PCI_BASE_ADDRESS_IO_MASK );
129
+					( bar & ~PCI_BASE_ADDRESS_IO_MASK );
130 130
 		} else {
131 131
 			if ( ! pci->membase )
132 132
 				pci->membase =
133
-					( bar & PCI_BASE_ADDRESS_MEM_MASK );
133
+					( bar & ~PCI_BASE_ADDRESS_MEM_MASK );
134 134
 			/* Skip next BAR if 64-bit */
135 135
 			if ( bar & PCI_BASE_ADDRESS_MEM_TYPE_64 )
136 136
 				reg += 4;
@@ -185,7 +185,7 @@ int pci_read_config ( struct pci_device *pci ) {
185 185
 		pci->busdevfn = PCI_FIRST_FUNC ( pci->busdevfn );
186 186
 		pci_read_config_byte ( pci, PCI_HEADER_TYPE, &hdrtype );
187 187
 		pci->busdevfn = busdevfn;
188
-		if ( ! ( hdrtype & 0x80 ) )
188
+		if ( ! ( hdrtype & PCI_HEADER_TYPE_MULTI ) )
189 189
 			return -ENODEV;
190 190
 	}
191 191
 

+ 5
- 5
src/drivers/bus/pciextra.c 查看文件

@@ -26,7 +26,7 @@ int pci_find_capability ( struct pci_device *pci, int cap ) {
26 26
 		return 0;
27 27
 
28 28
 	pci_read_config_byte ( pci, PCI_HEADER_TYPE, &hdr_type );
29
-	switch ( hdr_type & 0x7F ) {
29
+	switch ( hdr_type & PCI_HEADER_TYPE_MASK ) {
30 30
 	case PCI_HEADER_TYPE_NORMAL:
31 31
 	case PCI_HEADER_TYPE_BRIDGE:
32 32
 	default:
@@ -38,13 +38,13 @@ int pci_find_capability ( struct pci_device *pci, int cap ) {
38 38
 	}
39 39
 	while ( ttl-- && pos >= 0x40 ) {
40 40
 		pos &= ~3;
41
-		pci_read_config_byte ( pci, pos + PCI_CAP_LIST_ID, &id );
41
+		pci_read_config_byte ( pci, pos + PCI_CAP_ID, &id );
42 42
 		DBG ( "PCI Capability: %d\n", id );
43 43
 		if ( id == 0xff )
44 44
 			break;
45 45
 		if ( id == cap )
46 46
 			return pos;
47
-		pci_read_config_byte ( pci, pos + PCI_CAP_LIST_NEXT, &pos );
47
+		pci_read_config_byte ( pci, pos + PCI_CAP_NEXT, &pos );
48 48
 	}
49 49
 	return 0;
50 50
 }
@@ -76,9 +76,9 @@ unsigned long pci_bar_size ( struct pci_device *pci, unsigned int reg ) {
76 76
 	/* Restore the original command register. This reenables decoding. */
77 77
 	pci_write_config_word ( pci, PCI_COMMAND, cmd );
78 78
 	if ( start & PCI_BASE_ADDRESS_SPACE_IO ) {
79
-		size &= PCI_BASE_ADDRESS_IO_MASK;
79
+		size &= ~PCI_BASE_ADDRESS_IO_MASK;
80 80
 	} else {
81
-		size &= PCI_BASE_ADDRESS_MEM_MASK;
81
+		size &= ~PCI_BASE_ADDRESS_MEM_MASK;
82 82
 	}
83 83
 	/* Find the lowest bit set */
84 84
 	size = size & ~( size - 1 );

+ 1
- 1
src/drivers/net/atl1e.c 查看文件

@@ -224,7 +224,7 @@ static int atl1e_sw_init(struct atl1e_adapter *adapter)
224 224
 	adapter->link_duplex = FULL_DUPLEX;
225 225
 
226 226
 	/* PCI config space info */
227
-	pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
227
+	pci_read_config_byte(pdev, PCI_REVISION, &rev_id);
228 228
 
229 229
 	phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
230 230
 	/* nic type */

+ 1
- 1
src/drivers/net/dmfe.c 查看文件

@@ -462,7 +462,7 @@ static int dmfe_probe ( struct nic *nic, struct pci_device *pci ) {
462 462
 	       pci->id->name, pci->vendor, pci->device);
463 463
 
464 464
 	/* Read Chip revision */
465
-	pci_read_config_dword(pci, PCI_REVISION_ID, &dev_rev);
465
+	pci_read_config_dword(pci, PCI_REVISION, &dev_rev);
466 466
 	dprintf(("Revision %lX\n", dev_rev));
467 467
 
468 468
 	/* point to private storage */

+ 1
- 1
src/drivers/net/etherfabric.c 查看文件

@@ -3176,7 +3176,7 @@ falcon_probe_nic_variant ( struct efab_nic *efab, struct pci_device *pci )
3176 3176
 	uint8_t revision;
3177 3177
 
3178 3178
 	/* PCI revision */
3179
-	pci_read_config_byte ( pci, PCI_CLASS_REVISION, &revision );
3179
+	pci_read_config_byte ( pci, PCI_REVISION, &revision );
3180 3180
 	efab->pci_revision = revision;
3181 3181
 
3182 3182
 	/* Asic vs FPGA */

+ 2
- 4
src/drivers/net/forcedeth.c 查看文件

@@ -1749,10 +1749,8 @@ forcedeth_map_regs ( struct forcedeth_private *priv )
1749 1749
 	for ( reg = PCI_BASE_ADDRESS_0; reg <= PCI_BASE_ADDRESS_5; reg += 4 ) {
1750 1750
 		pci_read_config_dword ( priv->pci_dev, reg, &bar );
1751 1751
 
1752
-		if ( ( ( bar & PCI_BASE_ADDRESS_SPACE ) ==
1753
-			 PCI_BASE_ADDRESS_SPACE_MEMORY ) &&
1754
-		       ( pci_bar_size ( priv->pci_dev, reg ) >=
1755
-			 register_size ) ) {
1752
+		if ( ( ! ( bar & PCI_BASE_ADDRESS_SPACE_IO ) ) &&
1753
+		     ( pci_bar_size ( priv->pci_dev, reg ) >= register_size ) ){
1756 1754
 			addr = pci_bar_start ( priv->pci_dev, reg );
1757 1755
 			break;
1758 1756
 		}

+ 1
- 1
src/drivers/net/igbvf/igbvf_main.c 查看文件

@@ -461,7 +461,7 @@ static int __devinit igbvf_sw_init ( struct igbvf_adapter *adapter )
461 461
         hw->vendor_id = pdev->vendor;
462 462
         hw->device_id = pdev->device;
463 463
 
464
-        pci_read_config_byte ( pdev, PCI_REVISION_ID, &hw->revision_id );
464
+        pci_read_config_byte ( pdev, PCI_REVISION, &hw->revision_id );
465 465
 
466 466
         pci_read_config_word ( pdev, PCI_COMMAND, &hw->bus.pci_cmd_word );
467 467
 

+ 2
- 2
src/drivers/net/prism2_plx.c 查看文件

@@ -54,10 +54,10 @@ static int prism2_find_plx ( hfa384x_t *hw, struct pci_device *p )
54 54
   
55 55
   /* Obtain all memory and IO base addresses */
56 56
   pci_read_config_dword( p, PLX_LOCAL_CONFIG_REGISTER_BASE, &plx_lcr);
57
-  plx_lcr &= PCI_BASE_ADDRESS_IO_MASK;
57
+  plx_lcr &= ~PCI_BASE_ADDRESS_IO_MASK;
58 58
   pci_read_config_dword( p, PRISM2_PLX_ATTR_MEM_BASE, &attr_mem);
59 59
   pci_read_config_dword( p, PRISM2_PLX_IO_BASE, &iobase);
60
-  iobase &= PCI_BASE_ADDRESS_IO_MASK;
60
+  iobase &= ~PCI_BASE_ADDRESS_IO_MASK;
61 61
 
62 62
   /* Fill out hw structure */
63 63
   hw->iobase = iobase;

+ 1
- 1
src/drivers/net/sundance.c 查看文件

@@ -601,7 +601,7 @@ static int sundance_probe ( struct nic *nic, struct pci_device *pci ) {
601 601
 	sdc->nic_name = pci->id->name;
602 602
 	sdc->mtu = mtu;
603 603
 
604
-	pci_read_config_byte(pci, PCI_REVISION_ID, &sdc->pci_rev_id);
604
+	pci_read_config_byte(pci, PCI_REVISION, &sdc->pci_rev_id);
605 605
 
606 606
 	DBG ( "Device revision id: %hx\n", sdc->pci_rev_id );
607 607
 

+ 1
- 1
src/drivers/net/vxge/vxge_main.c 查看文件

@@ -509,7 +509,7 @@ vxge_probe(struct pci_device *pdev)
509 509
 	vxge_debug(VXGE_INFO, "vxge_probe for device " PCI_FMT "\n",
510 510
 			PCI_ARGS(pdev));
511 511
 
512
-	pci_read_config_byte(pdev, PCI_REVISION_ID, &revision);
512
+	pci_read_config_byte(pdev, PCI_REVISION, &revision);
513 513
 	titan1 = is_titan1(pdev->device, revision);
514 514
 
515 515
 	mmio_start = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);

+ 101
- 296
src/include/ipxe/pci.h 查看文件

@@ -1,317 +1,122 @@
1 1
 #ifndef	_IPXE_PCI_H
2 2
 #define _IPXE_PCI_H
3 3
 
4
-/*
5
- * Support for NE2000 PCI clones added David Monro June 1997
6
- * Generalised for other PCI NICs by Ken Yap July 1997
7
- * PCI support rewritten by Michael Brown 2006
4
+/** @file
5
+ *
6
+ * PCI bus
8 7
  *
9
- * Most of this is taken from /usr/src/linux/include/linux/pci.h.
10
- */
11
-
12
-/*
13
- * This program is free software; you can redistribute it and/or
14
- * modify it under the terms of the GNU General Public License as
15
- * published by the Free Software Foundation; either version 2, or (at
16
- * your option) any later version.
17 8
  */
18 9
 
19
-FILE_LICENCE ( GPL2_ONLY );
10
+FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
20 11
 
21 12
 #include <stdint.h>
22 13
 #include <ipxe/device.h>
23 14
 #include <ipxe/tables.h>
24 15
 #include <ipxe/pci_io.h>
25 16
 
26
-/*
27
- * PCI constants
28
- *
29
- */
30
-
31
-#define PCI_COMMAND_IO			0x1	/* Enable response in I/O space */
32
-#define PCI_COMMAND_MEM			0x2	/* Enable response in mem space */
33
-#define PCI_COMMAND_MASTER		0x4	/* Enable bus mastering */
34
-
35
-#define PCI_CACHE_LINE_SIZE		0x0c	/* 8 bits */
36
-#define PCI_LATENCY_TIMER		0x0d	/* 8 bits */
37
-
38
-#define PCI_COMMAND_SPECIAL		0x8	/* Enable response to special cycles */
39
-#define PCI_COMMAND_INVALIDATE		0x10	/* Use memory write and invalidate */
40
-#define  PCI_COMMAND_VGA_PALETTE 0x20	/* Enable palette snooping */
41
-#define  PCI_COMMAND_PARITY	0x40	/* Enable parity checking */
42
-#define  PCI_COMMAND_WAIT 	0x80	/* Enable address/data stepping */
43
-#define  PCI_COMMAND_SERR	0x100	/* Enable SERR */
44
-#define  PCI_COMMAND_FAST_BACK	0x200	/* Enable back-to-back writes */
45
-#define  PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
46
-
47
-
48
-#define PCI_VENDOR_ID           0x00    /* 16 bits */
49
-#define PCI_DEVICE_ID           0x02    /* 16 bits */
50
-#define PCI_COMMAND             0x04    /* 16 bits */
51
-
52
-#define PCI_STATUS		0x06	/* 16 bits */
53
-#define  PCI_STATUS_CAP_LIST	0x10	/* Support Capability List */
54
-#define  PCI_STATUS_66MHZ	0x20	/* Support 66 Mhz PCI 2.1 bus */
55
-#define  PCI_STATUS_UDF		0x40	/* Support User Definable Features [obsolete] */
56
-#define  PCI_STATUS_FAST_BACK	0x80	/* Accept fast-back to back */
57
-#define  PCI_STATUS_PARITY	0x100	/* Detected parity error */
58
-#define  PCI_STATUS_DEVSEL_MASK	0x600	/* DEVSEL timing */
59
-#define  PCI_STATUS_DEVSEL_FAST	0x000	
60
-#define  PCI_STATUS_DEVSEL_MEDIUM 0x200
61
-#define  PCI_STATUS_DEVSEL_SLOW 0x400
62
-#define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
63
-#define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
64
-#define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
65
-#define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
66
-#define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
67
-
68
-#define PCI_REVISION            0x08    /* 8 bits  */
69
-#define PCI_REVISION_ID         0x08    /* 8 bits  */
70
-#define PCI_CLASS_REVISION      0x08    /* 32 bits  */
71
-#define PCI_CLASS_CODE          0x0b    /* 8 bits */
72
-#define PCI_SUBCLASS_CODE       0x0a    /* 8 bits */
73
-#define PCI_HEADER_TYPE         0x0e    /* 8 bits */
74
-#define  PCI_HEADER_TYPE_NORMAL	0
75
-#define  PCI_HEADER_TYPE_BRIDGE 1
76
-#define  PCI_HEADER_TYPE_CARDBUS 2
77
-
78
-
79
-/* Header type 0 (normal devices) */
80
-#define PCI_CARDBUS_CIS		0x28
17
+/** PCI vendor ID */
18
+#define PCI_VENDOR_ID		0x00
19
+
20
+/** PCI device ID */
21
+#define PCI_DEVICE_ID		0x02
22
+
23
+/** PCI command */
24
+#define PCI_COMMAND		0x04
25
+#define PCI_COMMAND_IO			0x0001	/**< I/O space */
26
+#define PCI_COMMAND_MEM			0x0002	/**< Memory space */
27
+#define PCI_COMMAND_MASTER		0x0004	/**< Bus master */
28
+#define PCI_COMMAND_INVALIDATE		0x0010	/**< Mem. write & invalidate */
29
+#define PCI_COMMAND_PARITY		0x0040	/**< Parity error response */
30
+#define PCI_COMMAND_SERR		0x0100	/**< SERR# enable */
31
+#define PCI_COMMAND_INTX_DISABLE	0x0400	/**< Interrupt disable */
32
+
33
+/** PCI status */
34
+#define PCI_STATUS		0x06
35
+#define PCI_STATUS_CAP_LIST		0x0010	/**< Capabilities list */
36
+#define PCI_STATUS_PARITY		0x0100	/**< Master data parity error */
37
+#define PCI_STATUS_REC_TARGET_ABORT	0x1000	/**< Received target abort */
38
+#define PCI_STATUS_REC_MASTER_ABORT	0x2000	/**< Received master abort */
39
+#define PCI_STATUS_SIG_SYSTEM_ERROR	0x4000	/**< Signalled system error */
40
+#define PCI_STATUS_DETECTED_PARITY	0x8000	/**< Detected parity error */
41
+
42
+/** PCI revision */
43
+#define PCI_REVISION		0x08
44
+
45
+/** PCI cache line size */
46
+#define PCI_CACHE_LINE_SIZE	0x0c
47
+
48
+/** PCI latency timer */
49
+#define PCI_LATENCY_TIMER	0x0d
50
+
51
+/** PCI header type */
52
+#define PCI_HEADER_TYPE         0x0e
53
+#define PCI_HEADER_TYPE_NORMAL		0x00	/**< Normal header */
54
+#define PCI_HEADER_TYPE_BRIDGE		0x01	/**< PCI-to-PCI bridge header */
55
+#define PCI_HEADER_TYPE_CARDBUS		0x02	/**< CardBus header */
56
+#define PCI_HEADER_TYPE_MASK		0x7f	/**< Header type mask */
57
+#define PCI_HEADER_TYPE_MULTI		0x80	/**< Multi-function device */
58
+
59
+/** PCI base address registers */
60
+#define PCI_BASE_ADDRESS(n)	( 0x10 + ( 4 * (n) ) )
61
+#define PCI_BASE_ADDRESS_0	PCI_BASE_ADDRESS ( 0 )
62
+#define PCI_BASE_ADDRESS_1	PCI_BASE_ADDRESS ( 1 )
63
+#define PCI_BASE_ADDRESS_2	PCI_BASE_ADDRESS ( 2 )
64
+#define PCI_BASE_ADDRESS_3	PCI_BASE_ADDRESS ( 3 )
65
+#define PCI_BASE_ADDRESS_4	PCI_BASE_ADDRESS ( 4 )
66
+#define PCI_BASE_ADDRESS_5	PCI_BASE_ADDRESS ( 5 )
67
+#define PCI_BASE_ADDRESS_SPACE_IO	0x00000001UL	/**< I/O BAR */
68
+#define	PCI_BASE_ADDRESS_IO_MASK	0x00000003UL	/**< I/O BAR mask */
69
+#define PCI_BASE_ADDRESS_MEM_TYPE_64	0x00000004UL	/**< 64-bit memory */
70
+#define PCI_BASE_ADDRESS_MEM_TYPE_MASK	0x00000006UL	/**< Memory type mask */
71
+#define	PCI_BASE_ADDRESS_MEM_MASK	0x0000000fUL	/**< Memory BAR mask */
72
+
73
+/** PCI subsystem vendor ID */
81 74
 #define PCI_SUBSYSTEM_VENDOR_ID	0x2c
75
+
76
+/** PCI subsystem ID */
82 77
 #define PCI_SUBSYSTEM_ID	0x2e  
83 78
 
84
-#define PCI_BASE_ADDRESS_0      0x10    /* 32 bits */
85
-#define PCI_BASE_ADDRESS_1      0x14    /* 32 bits */
86
-#define PCI_BASE_ADDRESS_2      0x18    /* 32 bits */
87
-#define PCI_BASE_ADDRESS_3      0x1c    /* 32 bits */
88
-#define PCI_BASE_ADDRESS_4      0x20    /* 32 bits */
89
-#define PCI_BASE_ADDRESS_5      0x24    /* 32 bits */
90
-
91
-#define PCI_BASE_ADDRESS_SPACE		0x01    /* 0 = memory, 1 = I/O */
92
-#define PCI_BASE_ADDRESS_SPACE_IO	0x01
93
-#define PCI_BASE_ADDRESS_SPACE_MEMORY	0x00
94
-
95
-#define PCI_BASE_ADDRESS_MEM_TYPE_MASK	0x06
96
-#define PCI_BASE_ADDRESS_MEM_TYPE_32	0x00	/* 32 bit address */
97
-#define PCI_BASE_ADDRESS_MEM_TYPE_1M	0x02	/* Below 1M [obsolete] */
98
-#define PCI_BASE_ADDRESS_MEM_TYPE_64	0x04	/* 64 bit address */
99
-#define	PCI_BASE_ADDRESS_MEM_MASK	(~0x0f)
100
-#define	PCI_BASE_ADDRESS_IO_MASK	(~0x03)
101
-#define	PCI_ROM_ADDRESS		0x30	/* 32 bits */
102
-#define	PCI_ROM_ADDRESS_ENABLE	0x01	/* Write 1 to enable ROM,
103
-					   bits 31..11 are address,
104
-					   10..2 are reserved */
105
-
106
-#define PCI_CAPABILITY_LIST	0x34	/* Offset of first capability list entry */
107
-
108
-#define PCI_INTERRUPT_LINE	0x3c	/* IRQ number (0-15) */
109
-#define PCI_INTERRUPT_PIN	0x3d	/* IRQ pin on PCI bus (A-D) */
110
-
111
-/* Header type 1 (PCI-to-PCI bridges) */
112
-#define PCI_PRIMARY_BUS		0x18	/* Primary bus number */
113
-#define PCI_SECONDARY_BUS	0x19	/* Secondary bus number */
114
-#define PCI_SUBORDINATE_BUS	0x1a	/* Highest bus number behind the bridge */
115
-#define PCI_SEC_LATENCY_TIMER	0x1b	/* Latency timer for secondary interface */
116
-#define PCI_IO_BASE		0x1c	/* I/O range behind the bridge */
117
-#define PCI_IO_LIMIT		0x1d
118
-#define  PCI_IO_RANGE_TYPE_MASK	0x0f	/* I/O bridging type */
119
-#define  PCI_IO_RANGE_TYPE_16	0x00
120
-#define  PCI_IO_RANGE_TYPE_32	0x01
121
-#define  PCI_IO_RANGE_MASK	~0x0f
122
-#define PCI_SEC_STATUS		0x1e	/* Secondary status register, only bit 14 used */
123
-#define PCI_MEMORY_BASE		0x20	/* Memory range behind */
124
-#define PCI_MEMORY_LIMIT	0x22
125
-#define  PCI_MEMORY_RANGE_TYPE_MASK 0x0f
126
-#define  PCI_MEMORY_RANGE_MASK	~0x0f
127
-#define PCI_PREF_MEMORY_BASE	0x24	/* Prefetchable memory range behind */
128
-#define PCI_PREF_MEMORY_LIMIT	0x26
129
-#define  PCI_PREF_RANGE_TYPE_MASK 0x0f
130
-#define  PCI_PREF_RANGE_TYPE_32	0x00
131
-#define  PCI_PREF_RANGE_TYPE_64	0x01
132
-#define  PCI_PREF_RANGE_MASK	~0x0f
133
-#define PCI_PREF_BASE_UPPER32	0x28	/* Upper half of prefetchable memory range */
134
-#define PCI_PREF_LIMIT_UPPER32	0x2c
135
-#define PCI_IO_BASE_UPPER16	0x30	/* Upper half of I/O addresses */
136
-#define PCI_IO_LIMIT_UPPER16	0x32
137
-/* 0x34 same as for htype 0 */
138
-/* 0x35-0x3b is reserved */
139
-#define PCI_ROM_ADDRESS1	0x38	/* Same as PCI_ROM_ADDRESS, but for htype 1 */
140
-/* 0x3c-0x3d are same as for htype 0 */
141
-#define PCI_BRIDGE_CONTROL	0x3e
142
-#define  PCI_BRIDGE_CTL_PARITY	0x01	/* Enable parity detection on secondary interface */
143
-#define  PCI_BRIDGE_CTL_SERR	0x02	/* The same for SERR forwarding */
144
-#define  PCI_BRIDGE_CTL_NO_ISA	0x04	/* Disable bridging of ISA ports */
145
-#define  PCI_BRIDGE_CTL_VGA	0x08	/* Forward VGA addresses */
146
-#define  PCI_BRIDGE_CTL_MASTER_ABORT 0x20  /* Report master aborts */
147
-#define  PCI_BRIDGE_CTL_BUS_RESET 0x40	/* Secondary bus reset */
148
-#define  PCI_BRIDGE_CTL_FAST_BACK 0x80	/* Fast Back2Back enabled on secondary interface */
79
+/** PCI expansion ROM base address */
80
+#define	PCI_ROM_ADDRESS		0x30
149 81
 
150
-#define PCI_CB_CAPABILITY_LIST	0x14
82
+/** PCI capabilities pointer */
83
+#define PCI_CAPABILITY_LIST	0x34
151 84
 
152
-/* Capability lists */
153
-
154
-#define PCI_CAP_LIST_ID		0	/* Capability ID */
155
-#define  PCI_CAP_ID_PM		0x01	/* Power Management */
156
-#define  PCI_CAP_ID_AGP		0x02	/* Accelerated Graphics Port */
157
-#define  PCI_CAP_ID_VPD		0x03	/* Vital Product Data */
158
-#define  PCI_CAP_ID_SLOTID	0x04	/* Slot Identification */
159
-#define  PCI_CAP_ID_MSI		0x05	/* Message Signalled Interrupts */
160
-#define  PCI_CAP_ID_CHSWP	0x06	/* CompactPCI HotSwap */
161
-#define  PCI_CAP_ID_VNDR	0x09	/* Vendor specific */
162
-#define  PCI_CAP_ID_EXP		0x10	/* PCI Express */
163
-#define PCI_CAP_LIST_NEXT	1	/* Next capability in the list */
164
-#define PCI_CAP_FLAGS		2	/* Capability defined flags (16 bits) */
165
-#define PCI_CAP_SIZEOF		4
166
-
167
-/* Power Management Registers */
168
-
169
-#define PCI_PM_PMC              2       /* PM Capabilities Register */
170
-#define  PCI_PM_CAP_VER_MASK	0x0007	/* Version */
171
-#define  PCI_PM_CAP_PME_CLOCK	0x0008	/* PME clock required */
172
-#define  PCI_PM_CAP_RESERVED    0x0010  /* Reserved field */
173
-#define  PCI_PM_CAP_DSI		0x0020	/* Device specific initialization */
174
-#define  PCI_PM_CAP_AUX_POWER	0x01C0	/* Auxiliary power support mask */
175
-#define  PCI_PM_CAP_D1		0x0200	/* D1 power state support */
176
-#define  PCI_PM_CAP_D2		0x0400	/* D2 power state support */
177
-#define  PCI_PM_CAP_PME		0x0800	/* PME pin supported */
178
-#define  PCI_PM_CAP_PME_MASK    0xF800  /* PME Mask of all supported states */
179
-#define  PCI_PM_CAP_PME_D0      0x0800  /* PME# from D0 */
180
-#define  PCI_PM_CAP_PME_D1      0x1000  /* PME# from D1 */
181
-#define  PCI_PM_CAP_PME_D2      0x2000  /* PME# from D2 */
182
-#define  PCI_PM_CAP_PME_D3      0x4000  /* PME# from D3 (hot) */
183
-#define  PCI_PM_CAP_PME_D3cold  0x8000  /* PME# from D3 (cold) */
184
-#define PCI_PM_CTRL		4	/* PM control and status register */
185
-#define  PCI_PM_CTRL_STATE_MASK	0x0003	/* Current power state (D0 to D3) */
186
-#define  PCI_PM_CTRL_PME_ENABLE	0x0100	/* PME pin enable */
187
-#define  PCI_PM_CTRL_DATA_SEL_MASK	0x1e00	/* Data select (??) */
188
-#define  PCI_PM_CTRL_DATA_SCALE_MASK	0x6000	/* Data scale (??) */
189
-#define  PCI_PM_CTRL_PME_STATUS	0x8000	/* PME pin status */
190
-#define PCI_PM_PPB_EXTENSIONS	6	/* PPB support extensions (??) */
191
-#define  PCI_PM_PPB_B2_B3	0x40	/* Stop clock when in D3hot (??) */
192
-#define  PCI_PM_BPCC_ENABLE	0x80	/* Bus power/clock control enable (??) */
193
-#define PCI_PM_DATA_REGISTER	7	/* (??) */
194
-#define PCI_PM_SIZEOF		8
195
-
196
-/* AGP registers */
197
-
198
-#define PCI_AGP_VERSION		2	/* BCD version number */
199
-#define PCI_AGP_RFU		3	/* Rest of capability flags */
200
-#define PCI_AGP_STATUS		4	/* Status register */
201
-#define  PCI_AGP_STATUS_RQ_MASK	0xff000000	/* Maximum number of requests - 1 */
202
-#define  PCI_AGP_STATUS_SBA	0x0200	/* Sideband addressing supported */
203
-#define  PCI_AGP_STATUS_64BIT	0x0020	/* 64-bit addressing supported */
204
-#define  PCI_AGP_STATUS_FW	0x0010	/* FW transfers supported */
205
-#define  PCI_AGP_STATUS_RATE4	0x0004	/* 4x transfer rate supported */
206
-#define  PCI_AGP_STATUS_RATE2	0x0002	/* 2x transfer rate supported */
207
-#define  PCI_AGP_STATUS_RATE1	0x0001	/* 1x transfer rate supported */
208
-#define PCI_AGP_COMMAND		8	/* Control register */
209
-#define  PCI_AGP_COMMAND_RQ_MASK 0xff000000  /* Master: Maximum number of requests */
210
-#define  PCI_AGP_COMMAND_SBA	0x0200	/* Sideband addressing enabled */
211
-#define  PCI_AGP_COMMAND_AGP	0x0100	/* Allow processing of AGP transactions */
212
-#define  PCI_AGP_COMMAND_64BIT	0x0020 	/* Allow processing of 64-bit addresses */
213
-#define  PCI_AGP_COMMAND_FW	0x0010 	/* Force FW transfers */
214
-#define  PCI_AGP_COMMAND_RATE4	0x0004	/* Use 4x rate */
215
-#define  PCI_AGP_COMMAND_RATE2	0x0002	/* Use 2x rate */
216
-#define  PCI_AGP_COMMAND_RATE1	0x0001	/* Use 1x rate */
217
-#define PCI_AGP_SIZEOF		12
218
-
219
-/* Slot Identification */
220
-
221
-#define PCI_SID_ESR		2	/* Expansion Slot Register */
222
-#define  PCI_SID_ESR_NSLOTS	0x1f	/* Number of expansion slots available */
223
-#define  PCI_SID_ESR_FIC	0x20	/* First In Chassis Flag */
224
-#define PCI_SID_CHASSIS_NR	3	/* Chassis Number */
225
-
226
-/* Message Signalled Interrupts registers */
227
-
228
-#define PCI_MSI_FLAGS		2	/* Various flags */
229
-#define  PCI_MSI_FLAGS_64BIT	0x80	/* 64-bit addresses allowed */
230
-#define  PCI_MSI_FLAGS_QSIZE	0x70	/* Message queue size configured */
231
-#define  PCI_MSI_FLAGS_QMASK	0x0e	/* Maximum queue size available */
232
-#define  PCI_MSI_FLAGS_ENABLE	0x01	/* MSI feature enabled */
233
-#define PCI_MSI_RFU		3	/* Rest of capability flags */
234
-#define PCI_MSI_ADDRESS_LO	4	/* Lower 32 bits */
235
-#define PCI_MSI_ADDRESS_HI	8	/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
236
-#define PCI_MSI_DATA_32		8	/* 16 bits of data for 32-bit devices */
237
-#define PCI_MSI_DATA_64		12	/* 16 bits of data for 64-bit devices */
238
-
239
-/* Advanced Error Reporting */
240
-
241
-#define PCI_ERR_UNCOR_STATUS	4	/* Uncorrectable Error Status */
242
-#define  PCI_ERR_UNC_TRAIN	0x00000001	/* Training */
243
-#define  PCI_ERR_UNC_DLP	0x00000010	/* Data Link Protocol */
244
-#define  PCI_ERR_UNC_POISON_TLP	0x00001000	/* Poisoned TLP */
245
-#define  PCI_ERR_UNC_FCP	0x00002000	/* Flow Control Protocol */
246
-#define  PCI_ERR_UNC_COMP_TIME	0x00004000	/* Completion Timeout */
247
-#define  PCI_ERR_UNC_COMP_ABORT	0x00008000	/* Completer Abort */
248
-#define  PCI_ERR_UNC_UNX_COMP	0x00010000	/* Unexpected Completion */
249
-#define  PCI_ERR_UNC_RX_OVER	0x00020000	/* Receiver Overflow */
250
-#define  PCI_ERR_UNC_MALF_TLP	0x00040000	/* Malformed TLP */
251
-#define  PCI_ERR_UNC_ECRC	0x00080000	/* ECRC Error Status */
252
-#define  PCI_ERR_UNC_UNSUP	0x00100000	/* Unsupported Request */
253
-#define PCI_ERR_UNCOR_MASK	8	/* Uncorrectable Error Mask */
254
-	/* Same bits as above */
255
-#define PCI_ERR_UNCOR_SEVER	12	/* Uncorrectable Error Severity */
256
-	/* Same bits as above */
257
-#define PCI_ERR_COR_STATUS	16	/* Correctable Error Status */
258
-#define  PCI_ERR_COR_RCVR	0x00000001	/* Receiver Error Status */
259
-#define  PCI_ERR_COR_BAD_TLP	0x00000040	/* Bad TLP Status */
260
-#define  PCI_ERR_COR_BAD_DLLP	0x00000080	/* Bad DLLP Status */
261
-#define  PCI_ERR_COR_REP_ROLL	0x00000100	/* REPLAY_NUM Rollover */
262
-#define  PCI_ERR_COR_REP_TIMER	0x00001000	/* Replay Timer Timeout */
263
-#define PCI_ERR_COR_MASK	20	/* Correctable Error Mask */
264
-	/* Same bits as above */
265
-
266
-/* Device classes and subclasses */
267
-
268
-#define PCI_CLASS_NONE			0x00
269
-
270
-#define PCI_CLASS_STORAGE		0x01
271
-
272
-#define PCI_CLASS_NETWORK		0x02
273
-#define PCI_CLASS_NETWORK_ETHERNET	0x00
274
-#define PCI_CLASS_NETWORK_TOKENRING	0x01
275
-#define PCI_CLASS_NETWORK_FDDI		0x02
276
-#define PCI_CLASS_NETWORK_ATM		0x03
277
-#define PCI_CLASS_NETWORK_ISDN		0x04
278
-#define PCI_CLASS_NETWORK_WORLDFIP	0x05
279
-#define PCI_CLASS_NETWORK_PICMG		0x06
280
-
281
-#define PCI_CLASS_DISPLAY		0x03
282
-
283
-#define PCI_CLASS_MEDIA			0x04
284
-
285
-#define PCI_CLASS_MEMORY		0x05
286
-
287
-#define PCI_CLASS_BRIDGE		0x06
288
-
289
-#define PCI_CLASS_COMMS			0x07
290
-
291
-#define PCI_CLASS_GENERIC		0x08
292
-
293
-#define PCI_CLASS_INPUT			0x09
294
-
295
-#define PCI_CLASS_DOCK			0x0a
296
-
297
-#define PCI_CLASS_CPU			0x0b
298
-
299
-#define PCI_CLASS_SERIAL		0x0c
300
-#define PCI_CLASS_SERIAL_USB		0x03
301
-#define PCI_CLASS_SERIAL_USB_UHCI	0x00
302
-#define PCI_CLASS_SERIAL_USB_OHCI	0x10
303
-#define PCI_CLASS_SERIAL_USB_EHCI	0x20
304
-#define PCI_CLASS_SERIAL_USB_XHCI	0x30
305
-
306
-#define PCI_CLASS_WIFI			0x0d
307
-
308
-#define PCI_CLASS_IO			0x0e
309
-
310
-#define PCI_CLASS_SATELLITE		0x0f
311
-
312
-#define PCI_CLASS_CRYPTO		0x10
85
+/** CardBus capabilities pointer */
86
+#define PCI_CB_CAPABILITY_LIST	0x14
313 87
 
314
-#define PCI_CLASS_DATA			0x11
88
+/** PCI interrupt line */
89
+#define PCI_INTERRUPT_LINE	0x3c
90
+
91
+/** Capability ID */
92
+#define PCI_CAP_ID		0x00
93
+#define PCI_CAP_ID_PM			0x01	/**< Power management */
94
+#define PCI_CAP_ID_VPD			0x03	/**< Vital product data */
95
+#define PCI_CAP_ID_VNDR			0x09	/**< Vendor-specific */
96
+#define PCI_CAP_ID_EXP			0x10	/**< PCI Express */
97
+
98
+/** Next capability */
99
+#define PCI_CAP_NEXT		0x01
100
+
101
+/** Power management control and status */
102
+#define PCI_PM_CTRL		0x04
103
+#define PCI_PM_CTRL_STATE_MASK		0x0003	/**< Current power state */
104
+#define PCI_PM_CTRL_PME_ENABLE		0x0100	/**< PME pin enable */
105
+#define PCI_PM_CTRL_PME_STATUS		0x8000	/**< PME pin status */
106
+
107
+/** Uncorrectable error status */
108
+#define PCI_ERR_UNCOR_STATUS	0x04
109
+
110
+/** Network controller */
111
+#define PCI_CLASS_NETWORK	0x02
112
+
113
+/** Serial bus controller */
114
+#define PCI_CLASS_SERIAL	0x0c
115
+#define PCI_CLASS_SERIAL_USB		0x03	/**< USB controller */
116
+#define PCI_CLASS_SERIAL_USB_UHCI	 0x00	/**< UHCI USB controller */
117
+#define PCI_CLASS_SERIAL_USB_OHCI	 0x10	/**< OHCI USB controller */
118
+#define PCI_CLASS_SERIAL_USB_EHCI	 0x20	/**< ECHI USB controller */
119
+#define PCI_CLASS_SERIAL_USB_XHCI	 0x30	/**< xHCI USB controller */
315 120
 
316 121
 /** A PCI device ID list entry */
317 122
 struct pci_device_id {

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