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@@ -322,7 +322,7 @@ static void tg3_get_eeprom_hw_cfg(struct tg3 *tp)
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322
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322
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}
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323
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323
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324
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324
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if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
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325
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- tg3_flag(tp, 5750_PLUS))
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325
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+ tg3_flag(tp, ENABLE_ASF))
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326
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326
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tg3_flag_set(tp, ENABLE_APE);
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327
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327
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328
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328
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if (cfg2 & (1 << 17))
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@@ -466,6 +466,7 @@ int tg3_get_invariants(struct tg3 *tp)
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466
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466
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tg3_flag_set(tp, 5717_PLUS);
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467
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467
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468
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468
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 ||
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469
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+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57766 ||
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469
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470
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tg3_flag(tp, 5717_PLUS))
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470
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471
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tg3_flag_set(tp, 57765_PLUS);
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471
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472
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@@ -1465,6 +1466,13 @@ static int tg3_chip_reset(struct tg3 *tp)
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1465
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1466
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tw32(TG3_CPMU_CLCK_ORIDE, val & ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
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1466
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1467
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}
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1467
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1468
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1469
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+ if (tg3_flag(tp, CPMU_PRESENT)) {
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1470
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+ tw32(TG3_CPMU_D0_CLCK_POLICY, 0);
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1471
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+ val = tr32(TG3_CPMU_CLCK_ORIDE_EN);
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1472
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+ tw32(TG3_CPMU_CLCK_ORIDE_EN,
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1473
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+ val | CPMU_CLCK_ORIDE_MAC_CLCK_ORIDE_EN);
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1474
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+ }
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1475
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+
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1468
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1476
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return 0;
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1469
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1477
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}
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1470
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1478
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