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+/**************************************************************************
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+ ETHERBOOT - BOOTP/TFTP Bootstrap Program
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+
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+ Author: Martin Renters
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+ Date: May/94
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+
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+ This code is based heavily on David Greenman's if_ed.c driver
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+
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+ Copyright (C) 1993-1994, David Greenman, Martin Renters.
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+ This software may be used, modified, copied, distributed, and sold, in
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+ both source and binary form provided that the above copyright and these
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+ terms are retained. Under no circumstances are the authors responsible for
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+ the proper functioning of this software, nor do the authors assume any
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+ responsibility for damages incurred with its use.
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+
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+ Multicast support added by Timothy Legge (timlegge@users.sourceforge.net) 09/28/2003
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+ Relocation support added by Ken Yap (ken_yap@users.sourceforge.net) 28/12/02
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+ Card Detect support adapted from the eCos driver (Christian Plessl <cplessl@ee.ethz.ch>)
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+ Extracted from ns8390.c and adapted by Pantelis Koukousoulas <pktoss@gmail.com>
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+ **************************************************************************/
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+
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+#include "ns8390.h"
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+#include "etherboot.h"
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+#include "nic.h"
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+#include <gpxe/ethernet.h>
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+#include <gpxe/isa.h>
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+#include <errno.h>
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+
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+#define ASIC_PIO NE_DATA
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+
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+static unsigned char eth_vendor, eth_flags;
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+static unsigned short eth_nic_base, eth_asic_base;
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+static unsigned char eth_memsize, eth_rx_start, eth_tx_start;
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+static Address eth_bmem, eth_rmem;
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+static unsigned char eth_drain_receiver;
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+
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+static struct nic_operations ne_operations;
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+static void ne_reset(struct nic *nic, struct isa_device *isa);
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+
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+static isa_probe_addr_t ne_probe_addrs[] = { 0x300, 0x280, 0x320, 0x340, 0x380, 0x220, };
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+
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+/**************************************************************************
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+ ETH_PIO_READ - Read a frame via Programmed I/O
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+ **************************************************************************/
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+static void eth_pio_read(unsigned int src, unsigned char *dst, unsigned int cnt) {
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+ outb(D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND);
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+ outb(cnt, eth_nic_base + D8390_P0_RBCR0);
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+ outb(cnt >> 8, eth_nic_base + D8390_P0_RBCR1);
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+ outb(src, eth_nic_base + D8390_P0_RSAR0);
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+ outb(src >> 8, eth_nic_base + D8390_P0_RSAR1);
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+ outb(D8390_COMMAND_RD0 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND);
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+ if (eth_flags & FLAG_16BIT)
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+ cnt = (cnt + 1) >> 1;
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+
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+ while (cnt--) {
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+ if (eth_flags & FLAG_16BIT) {
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+ *((unsigned short *) dst) = inw(eth_asic_base + ASIC_PIO);
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+ dst += 2;
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+ } else
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+ *(dst++) = inb(eth_asic_base + ASIC_PIO);
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+ }
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+}
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+
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+/**************************************************************************
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+ ETH_PIO_WRITE - Write a frame via Programmed I/O
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+ **************************************************************************/
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+static void eth_pio_write(const unsigned char *src, unsigned int dst,
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+ unsigned int cnt) {
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+ outb(D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND);
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+ outb(D8390_ISR_RDC, eth_nic_base + D8390_P0_ISR);
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+ outb(cnt, eth_nic_base + D8390_P0_RBCR0);
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+ outb(cnt >> 8, eth_nic_base + D8390_P0_RBCR1);
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+ outb(dst, eth_nic_base + D8390_P0_RSAR0);
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+ outb(dst >> 8, eth_nic_base + D8390_P0_RSAR1);
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+ outb(D8390_COMMAND_RD1 | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND);
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+ if (eth_flags & FLAG_16BIT)
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+ cnt = (cnt + 1) >> 1;
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+
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+ while (cnt--) {
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+
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+ if (eth_flags & FLAG_16BIT) {
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+ outw(*((unsigned short *) src), eth_asic_base + ASIC_PIO);
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+ src += 2;
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+ } else
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+ outb(*(src++), eth_asic_base + ASIC_PIO);
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+ }
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+}
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+
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+/**************************************************************************
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+ enable_multicast - Enable Multicast
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+ **************************************************************************/
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+static void enable_multicast(unsigned short eth_nic_base) {
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+ unsigned char mcfilter[8];
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+ int i;
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+
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+ memset(mcfilter, 0xFF, 8);
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+ outb(4, eth_nic_base + D8390_P0_RCR);
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+ outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS1, eth_nic_base + D8390_P0_COMMAND);
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+ for (i = 0; i < 8; i++) {
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+ outb(mcfilter[i], eth_nic_base + 8 + i);
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+ if (inb(eth_nic_base + 8 + i) != mcfilter[i])
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+ DBG("Error SMC 83C690 Multicast filter read/write mishap %d\n",
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+ i);
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+ }
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+ outb(D8390_COMMAND_RD2 + D8390_COMMAND_PS0, eth_nic_base + D8390_P0_COMMAND);
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+ outb(4 | 0x08, eth_nic_base + D8390_P0_RCR);
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+}
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+
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+/**************************************************************************
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+ NE_PROBE1 - Look for an adapter on the ISA bus
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+ **************************************************************************/
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+static int ne_probe1(isa_probe_addr_t ioaddr) {
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113
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+ //From the eCos driver
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+ unsigned int regd;
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+ unsigned int state;
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+
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+ state = inb(ioaddr);
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+ outb(ioaddr, D8390_COMMAND_RD2 | D8390_COMMAND_PS1 | D8390_COMMAND_STP);
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+ regd = inb(ioaddr + D8390_P0_TCR);
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+
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+ if (inb(ioaddr + D8390_P0_TCR)) {
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+ outb(ioaddr, state);
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+ outb(ioaddr + 0x0d, regd);
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+ return 0;
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+ }
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+
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+ return 1;
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+}
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+
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+/**************************************************************************
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+ NE_PROBE - Initialize an adapter ???
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+ **************************************************************************/
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+static int ne_probe(struct nic *nic, struct isa_device *isa) {
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+ int i;
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+ unsigned char c;
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+ unsigned char romdata[16];
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+ unsigned char testbuf[32];
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+
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+ eth_vendor = VENDOR_NONE;
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+ eth_drain_receiver = 0;
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+
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+ nic->irqno = 0;
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+ nic->ioaddr = isa->ioaddr;
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+ eth_nic_base = isa->ioaddr;
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+
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+ /******************************************************************
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+ Search for NE1000/2000 if no WD/SMC or 3com cards
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+ ******************************************************************/
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+ if (eth_vendor == VENDOR_NONE) {
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+
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+ static unsigned char test[] = "NE*000 memory";
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+
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+ eth_bmem = 0; /* No shared memory */
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+
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+ eth_flags = FLAG_PIO;
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+ eth_asic_base = eth_nic_base + NE_ASIC_OFFSET;
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+ eth_memsize = MEM_16384;
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+ eth_tx_start = 32;
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+ eth_rx_start = 32 + D8390_TXBUF_SIZE;
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+ c = inb(eth_asic_base + NE_RESET);
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+ outb(c, eth_asic_base + NE_RESET);
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+ (void) inb(0x84);
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+ outb(D8390_COMMAND_STP | D8390_COMMAND_RD2, eth_nic_base
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+ + D8390_P0_COMMAND);
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+ outb(D8390_RCR_MON, eth_nic_base + D8390_P0_RCR);
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+ outb(D8390_DCR_FT1 | D8390_DCR_LS, eth_nic_base + D8390_P0_DCR);
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+ outb(MEM_8192, eth_nic_base + D8390_P0_PSTART);
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+ outb(MEM_16384, eth_nic_base + D8390_P0_PSTOP);
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+ eth_pio_write((unsigned char *) test, 8192, sizeof(test));
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+ eth_pio_read(8192, testbuf, sizeof(test));
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+ if (!memcmp(test, testbuf, sizeof(test)))
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+ goto out;
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+ eth_flags |= FLAG_16BIT;
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+ eth_memsize = MEM_32768;
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+ eth_tx_start = 64;
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+ eth_rx_start = 64 + D8390_TXBUF_SIZE;
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+ outb(D8390_DCR_WTS | D8390_DCR_FT1 | D8390_DCR_LS, eth_nic_base
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+ + D8390_P0_DCR);
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+ outb(MEM_16384, eth_nic_base + D8390_P0_PSTART);
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+ outb(MEM_32768, eth_nic_base + D8390_P0_PSTOP);
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+ eth_pio_write((unsigned char *) test, 16384, sizeof(test));
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+ eth_pio_read(16384, testbuf, sizeof(test));
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+ if (!memcmp(testbuf, test, sizeof(test)))
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+ goto out;
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+
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+
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+out:
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+ if (eth_nic_base == 0)
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+ return (0);
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+ if (eth_nic_base > ISA_MAX_ADDR) /* PCI probably */
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+ eth_flags |= FLAG_16BIT;
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+ eth_vendor = VENDOR_NOVELL;
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+ eth_pio_read(0, romdata, sizeof(romdata));
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+ for (i = 0; i < ETH_ALEN; i++) {
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+ nic->node_addr[i] = romdata[i + ((eth_flags & FLAG_16BIT) ? i : 0)];
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+ }
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+ nic->ioaddr = eth_nic_base;
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+ DBG("\nNE%c000 base %4.4x, MAC Addr %s\n",
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+ (eth_flags & FLAG_16BIT) ? '2' : '1', eth_nic_base, eth_ntoa(
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+ nic->node_addr));
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+ }
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+
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+ if (eth_vendor == VENDOR_NONE)
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+ return (0);
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+
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+ if (eth_vendor != VENDOR_3COM)
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+ eth_rmem = eth_bmem;
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+
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+ ne_reset(nic, isa);
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+ nic->nic_op = &ne_operations;
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+ return 1;
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+}
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+
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+
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215
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+/**************************************************************************
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216
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+ NE_DISABLE - Turn off adapter
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217
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+ **************************************************************************/
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218
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+static void ne_disable(struct nic *nic, struct isa_device *isa) {
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219
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+ ne_reset(nic, isa);
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+}
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+
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222
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+
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+/**************************************************************************
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224
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+ NE_RESET - Reset adapter
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+ **************************************************************************/
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226
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+static void ne_reset(struct nic *nic, struct isa_device *isa __unused)
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+{
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+ int i;
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+
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230
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+ eth_drain_receiver = 0;
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231
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+ outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 |
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232
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+ D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND);
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233
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+ if (eth_flags & FLAG_16BIT)
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234
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+ outb(0x49, eth_nic_base+D8390_P0_DCR);
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+ else
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+ outb(0x48, eth_nic_base+D8390_P0_DCR);
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+ outb(0, eth_nic_base+D8390_P0_RBCR0);
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+ outb(0, eth_nic_base+D8390_P0_RBCR1);
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+ outb(0x20, eth_nic_base+D8390_P0_RCR); /* monitor mode */
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+ outb(2, eth_nic_base+D8390_P0_TCR);
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+ outb(eth_tx_start, eth_nic_base+D8390_P0_TPSR);
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+ outb(eth_rx_start, eth_nic_base+D8390_P0_PSTART);
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243
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+
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244
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+ outb(eth_memsize, eth_nic_base+D8390_P0_PSTOP);
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245
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+ outb(eth_memsize - 1, eth_nic_base+D8390_P0_BOUND);
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246
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+ outb(0xFF, eth_nic_base+D8390_P0_ISR);
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247
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+ outb(0, eth_nic_base+D8390_P0_IMR);
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248
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+ outb(D8390_COMMAND_PS1 |
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249
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+ D8390_COMMAND_RD2 | D8390_COMMAND_STP, eth_nic_base+D8390_P0_COMMAND);
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250
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+
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251
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+ for (i=0; i<ETH_ALEN; i++)
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252
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+ outb(nic->node_addr[i], eth_nic_base+D8390_P1_PAR0+i);
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253
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+ for (i=0; i<ETH_ALEN; i++)
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254
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+ outb(0xFF, eth_nic_base+D8390_P1_MAR0+i);
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255
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+ outb(eth_rx_start, eth_nic_base+D8390_P1_CURR);
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256
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+ outb(D8390_COMMAND_PS0 |
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257
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+ D8390_COMMAND_RD2 | D8390_COMMAND_STA, eth_nic_base+D8390_P0_COMMAND);
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258
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+ outb(0xFF, eth_nic_base+D8390_P0_ISR);
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259
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+ outb(0, eth_nic_base+D8390_P0_TCR); /* transmitter on */
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260
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+ outb(4, eth_nic_base+D8390_P0_RCR); /* allow rx broadcast frames */
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261
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+
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262
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+ enable_multicast(eth_nic_base);
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263
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+}
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264
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+
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265
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+
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266
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+/**************************************************************************
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267
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+ NE_POLL - Wait for a frame
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268
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+ **************************************************************************/
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269
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+static int ne_poll(struct nic *nic __unused, int retrieve __unused)
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270
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+{
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271
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+ int ret = 0;
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272
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+ unsigned char rstat, curr, next;
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273
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+ unsigned short len, frag;
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274
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+ unsigned short pktoff;
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275
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+ unsigned char *p;
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276
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+ struct ringbuffer pkthdr;
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277
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+
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278
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+ rstat = inb(eth_nic_base+D8390_P0_RSR);
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279
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+ if (!(rstat & D8390_RSTAT_PRX)) return(0);
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280
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+ next = inb(eth_nic_base+D8390_P0_BOUND)+1;
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281
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+ if (next >= eth_memsize) next = eth_rx_start;
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282
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+ outb(D8390_COMMAND_PS1, eth_nic_base+D8390_P0_COMMAND);
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283
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+ curr = inb(eth_nic_base+D8390_P1_CURR);
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284
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+ outb(D8390_COMMAND_PS0, eth_nic_base+D8390_P0_COMMAND);
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285
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+ if (curr >= eth_memsize) curr=eth_rx_start;
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286
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+ if (curr == next) return(0);
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287
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+
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288
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+ if ( ! retrieve ) return 1;
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289
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+
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290
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+ pktoff = next << 8;
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291
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+ if (eth_flags & FLAG_PIO)
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292
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+ eth_pio_read(pktoff, (unsigned char *)&pkthdr, 4);
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293
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+ else
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294
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+ memcpy(&pkthdr, bus_to_virt(eth_rmem + pktoff), 4);
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295
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+ pktoff += sizeof(pkthdr);
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296
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+ /* incoming length includes FCS so must sub 4 */
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297
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+ len = pkthdr.len - 4;
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298
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+ if ((pkthdr.status & D8390_RSTAT_PRX) == 0 || len < ETH_ZLEN
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299
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+ || len> ETH_FRAME_LEN) {
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300
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+ DBG("Bogus packet, ignoring\n");
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301
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+ return (0);
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302
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+ }
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303
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+ else {
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304
|
+ p = nic->packet;
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305
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+ nic->packetlen = len; /* available to caller */
|
|
306
|
+ frag = (eth_memsize << 8) - pktoff;
|
|
307
|
+ if (len> frag) { /* We have a wrap-around */
|
|
308
|
+ /* read first part */
|
|
309
|
+ if (eth_flags & FLAG_PIO)
|
|
310
|
+ eth_pio_read(pktoff, p, frag);
|
|
311
|
+ else
|
|
312
|
+ memcpy(p, bus_to_virt(eth_rmem + pktoff), frag);
|
|
313
|
+ pktoff = eth_rx_start << 8;
|
|
314
|
+ p += frag;
|
|
315
|
+ len -= frag;
|
|
316
|
+ }
|
|
317
|
+ /* read second part */
|
|
318
|
+ if (eth_flags & FLAG_PIO)
|
|
319
|
+ eth_pio_read(pktoff, p, len);
|
|
320
|
+ else
|
|
321
|
+ memcpy(p, bus_to_virt(eth_rmem + pktoff), len);
|
|
322
|
+ ret = 1;
|
|
323
|
+ }
|
|
324
|
+ next = pkthdr.next; /* frame number of next packet */
|
|
325
|
+ if (next == eth_rx_start)
|
|
326
|
+ next = eth_memsize;
|
|
327
|
+ outb(next-1, eth_nic_base+D8390_P0_BOUND);
|
|
328
|
+ return(ret);
|
|
329
|
+}
|
|
330
|
+
|
|
331
|
+
|
|
332
|
+/**************************************************************************
|
|
333
|
+ NE_TRANSMIT - Transmit a frame
|
|
334
|
+ **************************************************************************/
|
|
335
|
+static void ne_transmit(struct nic *nic, const char *d, /* Destination */
|
|
336
|
+unsigned int t, /* Type */
|
|
337
|
+unsigned int s, /* size */
|
|
338
|
+const char *p) { /* Packet */
|
|
339
|
+
|
|
340
|
+ /* Programmed I/O */
|
|
341
|
+ unsigned short type;
|
|
342
|
+ type = (t >> 8) | (t << 8);
|
|
343
|
+ eth_pio_write((unsigned char *) d, eth_tx_start << 8, ETH_ALEN);
|
|
344
|
+ eth_pio_write(nic->node_addr, (eth_tx_start << 8) + ETH_ALEN, ETH_ALEN);
|
|
345
|
+ /* bcc generates worse code without (const+const) below */
|
|
346
|
+ eth_pio_write((unsigned char *) &type, (eth_tx_start << 8) + (ETH_ALEN
|
|
347
|
+ + ETH_ALEN), 2);
|
|
348
|
+ eth_pio_write((unsigned char *) p, (eth_tx_start << 8) + ETH_HLEN, s);
|
|
349
|
+ s += ETH_HLEN;
|
|
350
|
+ if (s < ETH_ZLEN)
|
|
351
|
+ s = ETH_ZLEN;
|
|
352
|
+
|
|
353
|
+ outb(D8390_COMMAND_PS0 | D8390_COMMAND_RD2 | D8390_COMMAND_STA,
|
|
354
|
+ eth_nic_base + D8390_P0_COMMAND);
|
|
355
|
+ outb(eth_tx_start, eth_nic_base + D8390_P0_TPSR);
|
|
356
|
+ outb(s, eth_nic_base + D8390_P0_TBCR0);
|
|
357
|
+ outb(s >> 8, eth_nic_base + D8390_P0_TBCR1);
|
|
358
|
+
|
|
359
|
+ outb(D8390_COMMAND_PS0 | D8390_COMMAND_TXP | D8390_COMMAND_RD2
|
|
360
|
+ | D8390_COMMAND_STA, eth_nic_base + D8390_P0_COMMAND);
|
|
361
|
+}
|
|
362
|
+
|
|
363
|
+static struct nic_operations ne_operations = { .connect = dummy_connect,
|
|
364
|
+ .poll = ne_poll, .transmit = ne_transmit, .irq = dummy_irq,
|
|
365
|
+};
|
|
366
|
+
|
|
367
|
+ISA_DRIVER ( ne_driver, ne_probe_addrs, ne_probe1,
|
|
368
|
+ GENERIC_ISAPNP_VENDOR, 0x0600 );
|
|
369
|
+
|
|
370
|
+DRIVER ( "ne", nic_driver, isapnp_driver, ne_driver,
|
|
371
|
+ ne_probe, ne_disable );
|
|
372
|
+
|
|
373
|
+ISA_ROM("ne","NE1000/2000 and clones");
|