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@@ -22,7 +22,7 @@
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22
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22
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#include <gpxe/pci.h>
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23
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23
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#include <gpxe/bitbash.h>
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24
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24
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#include <gpxe/i2c.h>
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25
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-#include <gpxe/nvs.h>
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25
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+#include <gpxe/spi.h>
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26
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26
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#include "timer.h"
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27
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27
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#define dma_addr_t unsigned long
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28
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28
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#include "etherfabric.h"
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@@ -208,13 +208,15 @@ struct efab_nic {
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208
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208
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/** INT_REG_KER for Falcon */
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209
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209
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efab_oword_t int_ker __attribute__ (( aligned ( 16 ) ));
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210
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210
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211
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- /** EEPROM access */
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211
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+ /** I2C access */
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212
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212
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struct i2c_bit_basher ef1002_i2c;
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213
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213
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unsigned long ef1002_i2c_outputs;
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214
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214
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struct i2c_device ef1002_eeprom;
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215
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215
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216
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- /** NVS access */
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217
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- struct nvs_device nvs;
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216
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+ /** SPI access */
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217
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+ struct spi_bus spi;
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218
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+ struct spi_device falcon_flash;
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219
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+ struct spi_device falcon_eeprom;
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220
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};
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219
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221
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220
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222
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/**************************************************************************
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@@ -2209,19 +2211,6 @@ static int falcon_reset ( struct efab_nic *efab ) {
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2209
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2211
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return 1;
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2210
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2212
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}
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2211
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2213
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2212
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-/** SPI device */
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2213
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-struct efab_spi_device {
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2214
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- /** Device ID */
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2215
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- unsigned int device_id;
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2216
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- /** Address length (in bytes) */
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2217
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- unsigned int addr_len;
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2218
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- /** Device size */
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2219
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- unsigned int len;
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2220
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-};
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2221
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-
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2222
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-#define SPI_WRITE_CMD 0x02
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2223
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-#define SPI_READ_CMD 0x03
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2224
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-
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2225
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2214
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/**
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2226
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2215
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* Wait for SPI command completion
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2227
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2216
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*
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@@ -2242,97 +2231,76 @@ static int falcon_spi_wait ( struct efab_nic *efab ) {
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2242
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2231
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}
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2243
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2232
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2244
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2233
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/**
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2245
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- * Perform SPI read
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2234
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+ * Perform SPI read/write
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2246
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2235
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*
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2247
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2236
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*/
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2248
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-static int falcon_spi_read ( struct efab_nic *efab,
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2249
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- struct efab_spi_device *spi, int address,
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2250
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- void *data, unsigned int len ) {
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2237
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+static int falcon_spi_rw ( struct spi_bus *bus, struct spi_device *device,
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2238
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+ unsigned int command, int address,
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2239
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+ const void *data_out, void *data_in, size_t len ) {
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2240
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+ struct efab_nic *efab = container_of ( bus, struct efab_nic, spi );
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2251
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2241
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efab_oword_t reg;
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2252
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2242
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2253
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2243
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/* Program address register */
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2254
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2244
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EFAB_POPULATE_OWORD_1 ( reg, FCN_EE_SPI_HADR_ADR, address );
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2255
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2245
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falcon_write ( efab, ®, FCN_EE_SPI_HADR_REG_KER );
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2256
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2246
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2257
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- /* Issue read command */
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2247
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+ /* Program data register, if applicable */
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2248
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+ if ( data_out ) {
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2249
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+ memcpy ( ®, data_out, len );
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2250
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+ falcon_write ( efab, ®, FCN_EE_SPI_HDATA_REG_KER );
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2251
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+ }
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2252
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+
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2253
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+ /* Issue command */
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2258
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2254
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EFAB_POPULATE_OWORD_7 ( reg,
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2259
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2255
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FCN_EE_SPI_HCMD_CMD_EN, 1,
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2260
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- FCN_EE_SPI_HCMD_SF_SEL, spi->device_id,
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2256
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+ FCN_EE_SPI_HCMD_SF_SEL, device->slave,
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2261
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2257
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FCN_EE_SPI_HCMD_DABCNT, len,
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2262
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- FCN_EE_SPI_HCMD_READ, FCN_EE_SPI_READ,
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2258
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+ FCN_EE_SPI_HCMD_READ, ( data_out ?
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2259
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+ FCN_EE_SPI_WRITE : FCN_EE_SPI_READ ),
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2263
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2260
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FCN_EE_SPI_HCMD_DUBCNT, 0,
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2264
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- FCN_EE_SPI_HCMD_ADBCNT, spi->addr_len,
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2265
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- FCN_EE_SPI_HCMD_ENC, SPI_READ_CMD );
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2261
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+ FCN_EE_SPI_HCMD_ADBCNT,
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2262
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+ ( device->address_len / 8 ),
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2263
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+ FCN_EE_SPI_HCMD_ENC, command );
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2266
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2264
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falcon_write ( efab, ®, FCN_EE_SPI_HCMD_REG_KER );
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2267
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2265
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2268
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- /* Wait for read to complete */
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2266
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+ /* Wait for operation to complete */
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2269
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2267
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if ( ! falcon_spi_wait ( efab ) )
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2270
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2268
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return 0;
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2271
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-
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2272
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- /* Read data */
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2273
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- falcon_read ( efab, ®, FCN_EE_SPI_HDATA_REG_KER );
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2274
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- memcpy ( data, ®, len );
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2275
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2269
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2270
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+ /* Read data, if applicable */
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2271
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+ if ( data_in ) {
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2272
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+ falcon_read ( efab, ®, FCN_EE_SPI_HDATA_REG_KER );
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2273
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+ memcpy ( data_in, ®, len );
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2274
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+ }
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2275
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+
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2276
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2276
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return 1;
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2277
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2277
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}
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2278
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2278
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2279
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2279
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/**
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2280
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- * Perform SPI write
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2280
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+ * Initialise SPI bus and devices
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2281
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2281
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*
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2282
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2282
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*/
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2283
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-static int falcon_spi_write ( struct efab_nic *efab,
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2284
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- struct efab_spi_device *spi, int address,
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2285
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- const void *data, unsigned int len ) {
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2286
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- efab_oword_t reg;
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2287
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-
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- /* Program address register */
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- EFAB_POPULATE_OWORD_1 ( reg, FCN_EE_SPI_HADR_ADR, address );
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2290
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- falcon_write ( efab, ®, FCN_EE_SPI_HADR_REG_KER );
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2291
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-
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2292
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- /* Program data register */
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2293
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- memcpy ( ®, data, len );
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2294
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- falcon_write ( efab, ®, FCN_EE_SPI_HDATA_REG_KER );
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2283
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+static void falcon_init_spi ( struct efab_nic *efab ) {
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2284
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+ /* Initialise SPI bus */
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2285
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+ efab->spi.rw = falcon_spi_rw;
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2286
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+ efab->falcon_eeprom.bus = &efab->spi;
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2287
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+ efab->falcon_eeprom.slave = FCN_EE_SPI_EEPROM;
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2288
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+ efab->falcon_flash.bus = &efab->spi;
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2289
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+ efab->falcon_flash.slave = FCN_EE_SPI_FLASH;
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2295
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2290
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2296
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- /* Issue write command */
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2297
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- EFAB_POPULATE_OWORD_7 ( reg,
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2298
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- FCN_EE_SPI_HCMD_CMD_EN, 1,
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2299
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- FCN_EE_SPI_HCMD_SF_SEL, spi->device_id,
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2300
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- FCN_EE_SPI_HCMD_DABCNT, len,
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2301
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- FCN_EE_SPI_HCMD_READ, FCN_EE_SPI_WRITE,
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2302
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- FCN_EE_SPI_HCMD_DUBCNT, 0,
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2303
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- FCN_EE_SPI_HCMD_ADBCNT, spi->addr_len,
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2304
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- FCN_EE_SPI_HCMD_ENC, SPI_WRITE_CMD );
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2305
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- falcon_write ( efab, ®, FCN_EE_SPI_HCMD_REG_KER );
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2306
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-
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2307
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- /* Wait for read to complete */
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2308
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- if ( ! falcon_spi_wait ( efab ) )
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2309
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- return 0;
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2310
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-
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2311
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- return 1;
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2291
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+ /* Initialise EEPROM, if present */
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2292
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+ if ( efab->has_flash ) {
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2293
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+ init_at25f1024 ( &efab->falcon_flash );
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2294
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+ init_at25040 ( &efab->falcon_eeprom );
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2295
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+ } else {
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2296
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+ init_mc25xx640 ( &efab->falcon_eeprom );
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2297
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+ /* Falcon's SPI interface cannot support a block size
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2298
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+ * larger than 16, so forcibly reduce it
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2299
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+ */
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2300
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+ efab->falcon_eeprom.nvs.block_size = 16;
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2301
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+ }
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2312
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2302
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}
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2313
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2303
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2314
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-#define AT25F1024_ADDR_LEN 3
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2315
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-#define AT25040_ADDR_LEN 1
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2316
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-#define MC25XX640_ADDR_LEN 2
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2317
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-
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2318
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-/** Falcon Flash SPI device */
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2319
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-static struct efab_spi_device falcon_spi_flash = {
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2320
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- .device_id = FCN_EE_SPI_FLASH,
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2321
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- .addr_len = AT25F1024_ADDR_LEN,
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2322
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-};
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2323
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-
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2324
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-/** Falcon EEPROM SPI device */
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2325
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-static struct efab_spi_device falcon_spi_large_eeprom = {
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2326
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- .device_id = FCN_EE_SPI_EEPROM,
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2327
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- .addr_len = MC25XX640_ADDR_LEN,
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2328
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-};
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2329
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-
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2330
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-/** Falcon EEPROM SPI device */
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2331
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-static struct efab_spi_device falcon_spi_small_eeprom = {
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2332
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- .device_id = FCN_EE_SPI_EEPROM,
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2333
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- .addr_len = AT25040_ADDR_LEN,
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2334
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-};
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2335
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-
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2336
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2304
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/** Offset of MAC address within EEPROM or Flash */
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2337
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2305
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#define FALCON_MAC_ADDRESS_OFFSET(port) ( 0x310 + 0x08 * (port) )
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2338
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2306
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@@ -2341,51 +2309,14 @@ static struct efab_spi_device falcon_spi_small_eeprom = {
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2341
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2309
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*
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2342
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2310
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*/
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2343
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2311
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static int falcon_read_eeprom ( struct efab_nic *efab ) {
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2344
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- struct efab_spi_device *spi;
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2345
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-
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2346
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- /* Determine the SPI device containing the MAC address */
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2347
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- spi = efab->has_flash ? &falcon_spi_flash : &falcon_spi_large_eeprom;
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2348
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- return falcon_spi_read ( efab, spi,
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2349
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- FALCON_MAC_ADDRESS_OFFSET ( efab->port ),
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2350
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- efab->mac_addr, sizeof ( efab->mac_addr ) );
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2351
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-}
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2352
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-
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2353
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-#define FALCON_NVS_OFFSET 0x000
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2354
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-
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2355
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-static int falcon_read_nvs ( struct nvs_device *nvs, unsigned int offset,
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2356
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- void *data, size_t len ) {
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2357
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- struct efab_nic *efab = container_of ( nvs, struct efab_nic, nvs );
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2358
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- struct efab_spi_device *spi = &falcon_spi_small_eeprom;
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2359
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-
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2360
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- while ( len ) {
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2361
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- if ( ! falcon_spi_read ( efab, spi,
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2362
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- ( offset + FALCON_NVS_OFFSET ),
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2363
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- data, 16 ) ) {
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2364
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- return -EIO;
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2365
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- }
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2366
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- data += 16;
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2367
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- offset += 16;
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2368
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- len -=16;
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2369
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- }
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2370
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- return 0;
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2371
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-}
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2312
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+ struct nvs_device *nvs;
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2372
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2313
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2373
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-static int falcon_write_nvs ( struct nvs_device *nvs, unsigned int offset,
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2374
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- const void *data, size_t len ) {
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2375
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- struct efab_nic *efab = container_of ( nvs, struct efab_nic, nvs );
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2376
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- struct efab_spi_device *spi = &falcon_spi_large_eeprom;
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2314
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+ /* Determine the NVS device containing the MAC address */
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2315
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+ nvs = ( efab->has_flash ?
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2316
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+ &efab->falcon_flash.nvs : &efab->falcon_eeprom.nvs );
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2377
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2317
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2378
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- while ( len ) {
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2379
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- if ( ! falcon_spi_write ( efab, spi,
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2380
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- ( offset + FALCON_NVS_OFFSET ),
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2381
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- data, 16 ) ) {
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2382
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- return -EIO;
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2383
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- }
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2384
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- data += 16;
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2385
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- offset += 16;
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2386
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- len -=16;
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2387
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- }
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2388
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- return 0;
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2318
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+ return nvs_read ( nvs, FALCON_MAC_ADDRESS_OFFSET ( efab->port ),
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2319
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+ efab->mac_addr, sizeof ( efab->mac_addr ) );
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2389
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2320
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}
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2390
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2321
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2391
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2322
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/** RX descriptor */
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@@ -2962,12 +2893,12 @@ static int falcon_init_nic ( struct efab_nic *efab ) {
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2962
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2893
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} else {
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2963
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2894
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falcon_read ( efab, ®, FCN_GPIO_CTL_REG_KER );
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2964
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2895
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efab->has_flash = EFAB_OWORD_FIELD ( reg, FCN_FLASH_PRESENT );
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2965
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- efab->has_eeprom = EFAB_OWORD_FIELD ( reg, FCN_EEPROM_PRESENT );
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2896
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+ efab->has_eeprom = EFAB_OWORD_FIELD ( reg, FCN_EEPROM_PRESENT);
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2966
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2897
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}
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2967
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-
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2968
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2898
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EFAB_LOG ( "flash is %s, EEPROM is %s\n",
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2969
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2899
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( efab->has_flash ? "present" : "absent" ),
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2970
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2900
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( efab->has_eeprom ? "present" : "absent" ) );
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2901
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+ falcon_init_spi ( efab );
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2971
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2902
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|
2972
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2903
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/* Set up TX and RX descriptor caches in SRAM */
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2973
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2904
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EFAB_POPULATE_OWORD_1 ( reg, FCN_SRM_TX_DC_BASE_ADR,
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