Ver código fonte

[intel] Add intelx driver for Intel 10 Gigabit Ethernet NICs

Signed-off-by: Michael Brown <mcb30@ipxe.org>
tags/v1.20.1
Michael Brown 11 anos atrás
pai
commit
cdca99f068
3 arquivos alterados com 580 adições e 0 exclusões
  1. 465
    0
      src/drivers/net/intelx.c
  2. 114
    0
      src/drivers/net/intelx.h
  3. 1
    0
      src/include/ipxe/errfile.h

+ 465
- 0
src/drivers/net/intelx.c Ver arquivo

@@ -0,0 +1,465 @@
1
+/*
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+ * Copyright (C) 2013 Michael Brown <mbrown@fensystems.co.uk>.
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of the
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+ * License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful, but
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+ * WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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+ * General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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+ * 02110-1301, USA.
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+ */
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+
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+FILE_LICENCE ( GPL2_OR_LATER );
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+
22
+#include <stdint.h>
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+#include <string.h>
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+#include <unistd.h>
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+#include <errno.h>
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+#include <byteswap.h>
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+#include <ipxe/netdevice.h>
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+#include <ipxe/ethernet.h>
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+#include <ipxe/if_ether.h>
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+#include <ipxe/iobuf.h>
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+#include <ipxe/malloc.h>
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+#include <ipxe/pci.h>
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+#include "intelx.h"
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+
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+/** @file
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+ *
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+ * Intel 10 Gigabit Ethernet network card driver
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+ *
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+ */
40
+
41
+/******************************************************************************
42
+ *
43
+ * MAC address
44
+ *
45
+ ******************************************************************************
46
+ */
47
+
48
+/**
49
+ * Try to fetch initial MAC address
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+ *
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+ * @v intel		Intel device
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+ * @v ral0		RAL0 register address
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+ * @v hw_addr		Hardware address to fill in
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+ * @ret rc		Return status code
55
+ */
56
+static int intelx_try_fetch_mac ( struct intel_nic *intel, unsigned int ral0,
57
+				  uint8_t *hw_addr ) {
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+	union intel_receive_address mac;
59
+
60
+	/* Read current address from RAL0/RAH0 */
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+	mac.reg.low = cpu_to_le32 ( readl ( intel->regs + ral0 ) );
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+	mac.reg.high = cpu_to_le32 ( readl ( intel->regs + ral0 +
63
+					     ( INTELX_RAH0 - INTELX_RAL0 ) ) );
64
+
65
+	/* Use current address if valid */
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+	if ( is_valid_ether_addr ( mac.raw ) ) {
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+		DBGC ( intel, "INTEL %p has autoloaded MAC address %s at "
68
+		       "%#05x\n", intel, eth_ntoa ( mac.raw ), ral0 );
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+		memcpy ( hw_addr, mac.raw, ETH_ALEN );
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+		return 0;
71
+	}
72
+
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+	return -ENOENT;
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+}
75
+
76
+/**
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+ * Fetch initial MAC address
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+ *
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+ * @v intel		Intel device
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+ * @v hw_addr		Hardware address to fill in
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+ * @ret rc		Return status code
82
+ */
83
+static int intelx_fetch_mac ( struct intel_nic *intel, uint8_t *hw_addr ) {
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+	int rc;
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+
86
+	/* Try to fetch address from INTELX_RAL0 */
87
+	if ( ( rc = intelx_try_fetch_mac ( intel, INTELX_RAL0,
88
+					   hw_addr ) ) == 0 ) {
89
+		return 0;
90
+	}
91
+
92
+	/* Try to fetch address from INTELX_RAL0_ALT */
93
+	if ( ( rc = intelx_try_fetch_mac ( intel, INTELX_RAL0_ALT,
94
+					   hw_addr ) ) == 0 ) {
95
+		return 0;
96
+	}
97
+
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+	DBGC ( intel, "INTEL %p has no MAC address to use\n", intel );
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+	return -ENOENT;
100
+}
101
+
102
+/******************************************************************************
103
+ *
104
+ * Device reset
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+ *
106
+ ******************************************************************************
107
+ */
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+
109
+/**
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+ * Reset hardware
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+ *
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+ * @v intel		Intel device
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+ * @ret rc		Return status code
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+ */
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+static int intelx_reset ( struct intel_nic *intel ) {
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+	uint32_t ctrl;
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+
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+	/* Perform a global software reset */
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+	ctrl = readl ( intel->regs + INTELX_CTRL );
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+	writel ( ( ctrl | INTELX_CTRL_RST | INTELX_CTRL_LRST ),
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+		 intel->regs + INTELX_CTRL );
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+	mdelay ( INTELX_RESET_DELAY_MS );
123
+
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+	DBGC ( intel, "INTEL %p reset (ctrl %08x)\n", intel, ctrl );
125
+	return 0;
126
+}
127
+
128
+/******************************************************************************
129
+ *
130
+ * Link state
131
+ *
132
+ ******************************************************************************
133
+ */
134
+
135
+/**
136
+ * Check link state
137
+ *
138
+ * @v netdev		Network device
139
+ */
140
+static void intelx_check_link ( struct net_device *netdev ) {
141
+	struct intel_nic *intel = netdev->priv;
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+	uint32_t links;
143
+
144
+	/* Read link status */
145
+	links = readl ( intel->regs + INTELX_LINKS );
146
+	DBGC ( intel, "INTEL %p link status is %08x\n", intel, links );
147
+
148
+	/* Update network device */
149
+	if ( links & INTELX_LINKS_UP ) {
150
+		netdev_link_up ( netdev );
151
+	} else {
152
+		netdev_link_down ( netdev );
153
+	}
154
+}
155
+
156
+/******************************************************************************
157
+ *
158
+ * Network device interface
159
+ *
160
+ ******************************************************************************
161
+ */
162
+
163
+/**
164
+ * Open network device
165
+ *
166
+ * @v netdev		Network device
167
+ * @ret rc		Return status code
168
+ */
169
+static int intelx_open ( struct net_device *netdev ) {
170
+	struct intel_nic *intel = netdev->priv;
171
+	union intel_receive_address mac;
172
+	uint32_t ral0;
173
+	uint32_t rah0;
174
+	uint32_t dmatxctl;
175
+	uint32_t fctrl;
176
+	uint32_t srrctl;
177
+	uint32_t hlreg0;
178
+	uint32_t maxfrs;
179
+	uint32_t rdrxctl;
180
+	uint32_t rxctrl;
181
+	uint32_t dca_rxctrl;
182
+	int rc;
183
+
184
+	/* Create transmit descriptor ring */
185
+	if ( ( rc = intel_create_ring ( intel, &intel->tx ) ) != 0 )
186
+		goto err_create_tx;
187
+
188
+	/* Create receive descriptor ring */
189
+	if ( ( rc = intel_create_ring ( intel, &intel->rx ) ) != 0 )
190
+		goto err_create_rx;
191
+
192
+	/* Program MAC address */
193
+	memset ( &mac, 0, sizeof ( mac ) );
194
+	memcpy ( mac.raw, netdev->ll_addr, sizeof ( mac.raw ) );
195
+	ral0 = le32_to_cpu ( mac.reg.low );
196
+	rah0 = ( le32_to_cpu ( mac.reg.high ) | INTELX_RAH0_AV );
197
+	writel ( ral0, intel->regs + INTELX_RAL0 );
198
+	writel ( rah0, intel->regs + INTELX_RAH0 );
199
+	writel ( ral0, intel->regs + INTELX_RAL0_ALT );
200
+	writel ( rah0, intel->regs + INTELX_RAH0_ALT );
201
+
202
+	/* Allocate interrupt vectors */
203
+	writel ( ( INTELX_IVAR_RX0_DEFAULT | INTELX_IVAR_RX0_VALID |
204
+		   INTELX_IVAR_TX0_DEFAULT | INTELX_IVAR_TX0_VALID ),
205
+		 intel->regs + INTELX_IVAR );
206
+
207
+	/* Enable transmitter  */
208
+	dmatxctl = readl ( intel->regs + INTELX_DMATXCTL );
209
+	dmatxctl |= INTELX_DMATXCTL_TE;
210
+	writel ( dmatxctl, intel->regs + INTELX_DMATXCTL );
211
+
212
+	/* Configure receive filter */
213
+	fctrl = readl ( intel->regs + INTELX_FCTRL );
214
+	fctrl |= ( INTELX_FCTRL_BAM | INTELX_FCTRL_UPE | INTELX_FCTRL_MPE );
215
+	writel ( fctrl, intel->regs + INTELX_FCTRL );
216
+
217
+	/* Configure receive buffer sizes */
218
+	srrctl = readl ( intel->regs + INTELX_SRRCTL );
219
+	srrctl &= ~INTELX_SRRCTL_BSIZE_MASK;
220
+	srrctl |= INTELX_SRRCTL_BSIZE_DEFAULT;
221
+	writel ( srrctl, intel->regs + INTELX_SRRCTL );
222
+
223
+	/* Configure jumbo frames.  Required to allow the extra 4-byte
224
+	 * headroom for VLANs, since we don't use the hardware's
225
+	 * native VLAN offload.
226
+	 */
227
+	hlreg0 = readl ( intel->regs + INTELX_HLREG0 );
228
+	hlreg0 |= INTELX_HLREG0_JUMBOEN;
229
+	writel ( hlreg0, intel->regs + INTELX_HLREG0 );
230
+
231
+	/* Configure frame size */
232
+	maxfrs = readl ( intel->regs + INTELX_MAXFRS );
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+	maxfrs &= ~INTELX_MAXFRS_MFS_MASK;
234
+	maxfrs |= INTELX_MAXFRS_MFS_DEFAULT;
235
+	writel ( maxfrs, intel->regs + INTELX_MAXFRS );
236
+
237
+	/* Configure receive DMA */
238
+	rdrxctl = readl ( intel->regs + INTELX_RDRXCTL );
239
+	rdrxctl |= INTELX_RDRXCTL_SECRC;
240
+	writel ( rdrxctl, intel->regs + INTELX_RDRXCTL );
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+
242
+	/* Clear "must-be-zero" bit for direct cache access (DCA).  We
243
+	 * leave DCA disabled anyway, but if we do not clear this bit
244
+	 * then the received packets contain garbage data.
245
+	 */
246
+	dca_rxctrl = readl ( intel->regs + INTELX_DCA_RXCTRL );
247
+	dca_rxctrl &= ~INTELX_DCA_RXCTRL_MUST_BE_ZERO;
248
+	writel ( dca_rxctrl, intel->regs + INTELX_DCA_RXCTRL );
249
+
250
+	/* Enable receiver */
251
+	rxctrl = readl ( intel->regs + INTELX_RXCTRL );
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+	rxctrl |= INTELX_RXCTRL_RXEN;
253
+	writel ( rxctrl, intel->regs + INTELX_RXCTRL );
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+
255
+	/* Fill receive ring */
256
+	intel_refill_rx ( intel );
257
+
258
+	/* Update link state */
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+	intelx_check_link ( netdev );
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+
261
+	return 0;
262
+
263
+	intel_destroy_ring ( intel, &intel->rx );
264
+ err_create_rx:
265
+	intel_destroy_ring ( intel, &intel->tx );
266
+ err_create_tx:
267
+	return rc;
268
+}
269
+
270
+/**
271
+ * Close network device
272
+ *
273
+ * @v netdev		Network device
274
+ */
275
+static void intelx_close ( struct net_device *netdev ) {
276
+	struct intel_nic *intel = netdev->priv;
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+	uint32_t rxctrl;
278
+	uint32_t dmatxctl;
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+
280
+	/* Disable receiver */
281
+	rxctrl = readl ( intel->regs + INTELX_RXCTRL );
282
+	rxctrl &= ~INTELX_RXCTRL_RXEN;
283
+	writel ( rxctrl, intel->regs + INTELX_RXCTRL );
284
+
285
+	/* Disable transmitter  */
286
+	dmatxctl = readl ( intel->regs + INTELX_DMATXCTL );
287
+	dmatxctl &= ~INTELX_DMATXCTL_TE;
288
+	writel ( dmatxctl, intel->regs + INTELX_DMATXCTL );
289
+
290
+	/* Destroy receive descriptor ring */
291
+	intel_destroy_ring ( intel, &intel->rx );
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+
293
+	/* Discard any unused receive buffers */
294
+	intel_empty_rx ( intel );
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+
296
+	/* Destroy transmit descriptor ring */
297
+	intel_destroy_ring ( intel, &intel->tx );
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+
299
+	/* Reset the NIC, to flush the transmit and receive FIFOs */
300
+	intelx_reset ( intel );
301
+}
302
+
303
+/**
304
+ * Poll for completed and received packets
305
+ *
306
+ * @v netdev		Network device
307
+ */
308
+static void intelx_poll ( struct net_device *netdev ) {
309
+	struct intel_nic *intel = netdev->priv;
310
+	uint32_t eicr;
311
+
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+	/* Check for and acknowledge interrupts */
313
+	eicr = readl ( intel->regs + INTELX_EICR );
314
+	if ( ! eicr )
315
+		return;
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+
317
+	/* Poll for TX completions, if applicable */
318
+	if ( eicr & INTELX_EIRQ_TX0 )
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+		intel_poll_tx ( netdev );
320
+
321
+	/* Poll for RX completions, if applicable */
322
+	if ( eicr & ( INTELX_EIRQ_RX0 | INTELX_EIRQ_RXO ) )
323
+		intel_poll_rx ( netdev );
324
+
325
+	/* Report receive overruns */
326
+	if ( eicr & INTELX_EIRQ_RXO )
327
+		netdev_rx_err ( netdev, NULL, -ENOBUFS );
328
+
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+	/* Check link state, if applicable */
330
+	if ( eicr & INTELX_EIRQ_LSC )
331
+		intelx_check_link ( netdev );
332
+
333
+	/* Refill RX ring */
334
+	intel_refill_rx ( intel );
335
+}
336
+
337
+/**
338
+ * Enable or disable interrupts
339
+ *
340
+ * @v netdev		Network device
341
+ * @v enable		Interrupts should be enabled
342
+ */
343
+static void intelx_irq ( struct net_device *netdev, int enable ) {
344
+	struct intel_nic *intel = netdev->priv;
345
+	uint32_t mask;
346
+
347
+	mask = ( INTELX_EIRQ_LSC | INTELX_EIRQ_RXO | INTELX_EIRQ_TX0 |
348
+		 INTELX_EIRQ_RX0 );
349
+	if ( enable ) {
350
+		writel ( mask, intel->regs + INTELX_EIMS );
351
+	} else {
352
+		writel ( mask, intel->regs + INTELX_EIMC );
353
+	}
354
+}
355
+
356
+/** Network device operations */
357
+static struct net_device_operations intelx_operations = {
358
+	.open		= intelx_open,
359
+	.close		= intelx_close,
360
+	.transmit	= intel_transmit,
361
+	.poll		= intelx_poll,
362
+	.irq		= intelx_irq,
363
+};
364
+
365
+/******************************************************************************
366
+ *
367
+ * PCI interface
368
+ *
369
+ ******************************************************************************
370
+ */
371
+
372
+/**
373
+ * Probe PCI device
374
+ *
375
+ * @v pci		PCI device
376
+ * @ret rc		Return status code
377
+ */
378
+static int intelx_probe ( struct pci_device *pci ) {
379
+	struct net_device *netdev;
380
+	struct intel_nic *intel;
381
+	int rc;
382
+
383
+	/* Allocate and initialise net device */
384
+	netdev = alloc_etherdev ( sizeof ( *intel ) );
385
+	if ( ! netdev ) {
386
+		rc = -ENOMEM;
387
+		goto err_alloc;
388
+	}
389
+	netdev_init ( netdev, &intelx_operations );
390
+	intel = netdev->priv;
391
+	pci_set_drvdata ( pci, netdev );
392
+	netdev->dev = &pci->dev;
393
+	memset ( intel, 0, sizeof ( *intel ) );
394
+	intel->port = PCI_FUNC ( pci->busdevfn );
395
+	intel_init_ring ( &intel->tx, INTEL_NUM_TX_DESC, INTELX_TD );
396
+	intel_init_ring ( &intel->rx, INTEL_NUM_RX_DESC, INTELX_RD );
397
+
398
+	/* Fix up PCI device */
399
+	adjust_pci_device ( pci );
400
+
401
+	/* Map registers */
402
+	intel->regs = ioremap ( pci->membase, INTEL_BAR_SIZE );
403
+
404
+	/* Reset the NIC */
405
+	if ( ( rc = intelx_reset ( intel ) ) != 0 )
406
+		goto err_reset;
407
+
408
+	/* Fetch MAC address */
409
+	if ( ( rc = intelx_fetch_mac ( intel, netdev->hw_addr ) ) != 0 )
410
+		goto err_fetch_mac;
411
+
412
+	/* Register network device */
413
+	if ( ( rc = register_netdev ( netdev ) ) != 0 )
414
+		goto err_register_netdev;
415
+
416
+	/* Set initial link state */
417
+	intelx_check_link ( netdev );
418
+
419
+	return 0;
420
+
421
+	unregister_netdev ( netdev );
422
+ err_register_netdev:
423
+ err_fetch_mac:
424
+	intelx_reset ( intel );
425
+ err_reset:
426
+	iounmap ( intel->regs );
427
+	netdev_nullify ( netdev );
428
+	netdev_put ( netdev );
429
+ err_alloc:
430
+	return rc;
431
+}
432
+
433
+/**
434
+ * Remove PCI device
435
+ *
436
+ * @v pci		PCI device
437
+ */
438
+static void intelx_remove ( struct pci_device *pci ) {
439
+	struct net_device *netdev = pci_get_drvdata ( pci );
440
+	struct intel_nic *intel = netdev->priv;
441
+
442
+	/* Unregister network device */
443
+	unregister_netdev ( netdev );
444
+
445
+	/* Reset the NIC */
446
+	intelx_reset ( intel );
447
+
448
+	/* Free network device */
449
+	iounmap ( intel->regs );
450
+	netdev_nullify ( netdev );
451
+	netdev_put ( netdev );
452
+}
453
+
454
+/** PCI device IDs */
455
+static struct pci_device_id intelx_nics[] = {
456
+	PCI_ROM ( 0x8086, 0x10fb, "82599", "82599", 0 ),
457
+};
458
+
459
+/** PCI driver */
460
+struct pci_driver intelx_driver __pci_driver = {
461
+	.ids = intelx_nics,
462
+	.id_count = ( sizeof ( intelx_nics ) / sizeof ( intelx_nics[0] ) ),
463
+	.probe = intelx_probe,
464
+	.remove = intelx_remove,
465
+};

+ 114
- 0
src/drivers/net/intelx.h Ver arquivo

@@ -0,0 +1,114 @@
1
+#ifndef _INTELX_H
2
+#define _INTELX_H
3
+
4
+/** @file
5
+ *
6
+ * Intel 10 Gigabit Ethernet network card driver
7
+ *
8
+ */
9
+
10
+FILE_LICENCE ( GPL2_OR_LATER );
11
+
12
+#include <stdint.h>
13
+#include <ipxe/if_ether.h>
14
+#include "intel.h"
15
+
16
+/** Device Control Register */
17
+#define INTELX_CTRL 0x00000UL
18
+#define INTELX_CTRL_LRST	0x00000008UL	/**< Link reset */
19
+#define INTELX_CTRL_RST		0x04000000UL	/**< Device reset */
20
+
21
+/** Time to delay for device reset, in milliseconds */
22
+#define INTELX_RESET_DELAY_MS 20
23
+
24
+/** Extended Interrupt Cause Read Register */
25
+#define INTELX_EICR 0x00800UL
26
+#define INTELX_EIRQ_RX0		0x00000001UL	/**< RX0 (via IVAR) */
27
+#define INTELX_EIRQ_TX0		0x00000002UL	/**< RX0 (via IVAR) */
28
+#define INTELX_EIRQ_RXO		0x00020000UL	/**< Receive overrun */
29
+#define INTELX_EIRQ_LSC		0x00100000UL	/**< Link status change */
30
+
31
+/** Interrupt Mask Set/Read Register */
32
+#define INTELX_EIMS 0x00880UL
33
+
34
+/** Interrupt Mask Clear Register */
35
+#define INTELX_EIMC 0x00888UL
36
+
37
+/** Interrupt Vector Allocation Register */
38
+#define INTELX_IVAR 0x00900UL
39
+#define INTELX_IVAR_RX0(bit)	( (bit) << 0 )	/**< RX queue 0 allocation */
40
+#define INTELX_IVAR_RX0_DEFAULT	INTELX_IVAR_RX0 ( 0x00 )
41
+#define INTELX_IVAR_RX0_MASK	INTELX_IVAR_RX0 ( 0x3f )
42
+#define INTELX_IVAR_RX0_VALID	0x00000080UL	/**< RX queue 0 valid */
43
+#define INTELX_IVAR_TX0(bit)	( (bit) << 8 )	/**< TX queue 0 allocation */
44
+#define INTELX_IVAR_TX0_DEFAULT	INTELX_IVAR_TX0 ( 0x01 )
45
+#define INTELX_IVAR_TX0_MASK	INTELX_IVAR_TX0 ( 0x3f )
46
+#define INTELX_IVAR_TX0_VALID	0x00008000UL	/**< TX queue 0 valid */
47
+
48
+/** Receive Filter Control Register */
49
+#define INTELX_FCTRL 0x05080UL
50
+#define INTELX_FCTRL_MPE	0x00000100UL	/**< Multicast promiscuous */
51
+#define INTELX_FCTRL_UPE	0x00000200UL	/**< Unicast promiscuous mode */
52
+#define INTELX_FCTRL_BAM	0x00000400UL	/**< Broadcast accept mode */
53
+
54
+/** Receive Address Low
55
+ *
56
+ * The MAC address registers RAL0/RAH0 exist at address 0x05400 for
57
+ * the 82598 and 0x0a200 for the 82599, according to the datasheet.
58
+ * In practice, the 82599 seems to also provide a copy of these
59
+ * registers at 0x05400.  To aim for maximum compatibility, we try
60
+ * both addresses when reading the initial MAC address, and set both
61
+ * addresses when setting the MAC address.
62
+ */
63
+#define INTELX_RAL0 0x05400UL
64
+#define INTELX_RAL0_ALT 0x0a200UL
65
+
66
+/** Receive Address High */
67
+#define INTELX_RAH0 0x05404UL
68
+#define INTELX_RAH0_ALT 0x0a204UL
69
+#define INTELX_RAH0_AV		0x80000000UL	/**< Address valid */
70
+
71
+/** Receive Descriptor register block */
72
+#define INTELX_RD 0x01000UL
73
+
74
+/** Split Receive Control Register */
75
+#define INTELX_SRRCTL 0x02100UL
76
+#define INTELX_SRRCTL_BSIZE(kb)	( (kb) << 0 )	/**< Receive buffer size */
77
+#define INTELX_SRRCTL_BSIZE_DEFAULT INTELX_SRRCTL_BSIZE ( 0x02 )
78
+#define INTELX_SRRCTL_BSIZE_MASK INTELX_SRRCTL_BSIZE ( 0x1f )
79
+
80
+/** Receive DMA Control Register */
81
+#define INTELX_RDRXCTL 0x02f00UL
82
+#define INTELX_RDRXCTL_SECRC	0x00000001UL	/**< Strip CRC */
83
+
84
+/** Receive Control Register */
85
+#define INTELX_RXCTRL 0x03000UL
86
+#define INTELX_RXCTRL_RXEN	0x00000001UL	/**< Receive enable */
87
+
88
+/** Transmit DMA Control Register */
89
+#define INTELX_DMATXCTL 0x04a80UL
90
+#define INTELX_DMATXCTL_TE	0x00000001UL	/**< Transmit enable */
91
+
92
+/** Transmit Descriptor register block */
93
+#define INTELX_TD 0x06000UL
94
+
95
+/** RX DCA Control Register */
96
+#define INTELX_DCA_RXCTRL 0x02200UL
97
+#define INTELX_DCA_RXCTRL_MUST_BE_ZERO 0x00001000UL /**< Must be zero */
98
+
99
+/** MAC Core Control 0 Register */
100
+#define INTELX_HLREG0 0x04240UL
101
+#define INTELX_HLREG0_JUMBOEN	0x00000004UL	/**< Jumbo frame enable */
102
+
103
+/** Maximum Frame Size Register */
104
+#define INTELX_MAXFRS 0x04268UL
105
+#define INTELX_MAXFRS_MFS(len)	( (len) << 16 )	/**< Maximum frame size */
106
+#define INTELX_MAXFRS_MFS_DEFAULT \
107
+	INTELX_MAXFRS_MFS ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ )
108
+#define INTELX_MAXFRS_MFS_MASK	INTELX_MAXFRS_MFS ( 0xffff )
109
+
110
+/** Link Status Register */
111
+#define INTELX_LINKS 0x042a4UL
112
+#define INTELX_LINKS_UP		0x40000000UL	/**< Link up */
113
+
114
+#endif /* _INTELX_H */

+ 1
- 0
src/include/ipxe/errfile.h Ver arquivo

@@ -148,6 +148,7 @@ FILE_LICENCE ( GPL2_OR_LATER );
148 148
 #define ERRFILE_skeleton	     ( ERRFILE_DRIVER | 0x00640000 )
149 149
 #define ERRFILE_intel		     ( ERRFILE_DRIVER | 0x00650000 )
150 150
 #define ERRFILE_myson		     ( ERRFILE_DRIVER | 0x00660000 )
151
+#define ERRFILE_intelx		     ( ERRFILE_DRIVER | 0x00670000 )
151 152
 
152 153
 #define ERRFILE_scsi		     ( ERRFILE_DRIVER | 0x00700000 )
153 154
 #define ERRFILE_arbel		     ( ERRFILE_DRIVER | 0x00710000 )

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