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+/*
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+ * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
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+ *
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+ * This software is available to you under a choice of one of two
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+ * licenses. You may choose to be licensed under the terms of the GNU
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+ * General Public License (GPL) Version 2, available from the file
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+ * COPYING in the main directory of this source tree, or the
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+ * OpenIB.org BSD license below:
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+ *
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+ * Redistribution and use in source and binary forms, with or
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+ * without modification, are permitted provided that the following
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+ * conditions are met:
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+ *
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+ * - Redistributions of source code must retain the above
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+ * copyright notice, this list of conditions and the following
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+ * disclaimer.
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+ *
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+ * - Redistributions in binary form must reproduce the above
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+ * copyright notice, this list of conditions and the following
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+ * disclaimer in the documentation and/or other materials
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+ * provided with the distribution.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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+ * SOFTWARE.
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+ *
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+ */
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+#ifndef H_MTNIC_IF_DEFS_H
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+#define H_MTNIC_IF_DEFS_H
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+
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+
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+
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+/*
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+* Device setup
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+*/
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+
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+/*
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+ Note port number can be changed under mtnic.c !
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+*/
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+#define MTNIC_MAX_PORTS 2
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+#define NUM_TX_RINGS 1
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+#define NUM_RX_RINGS 1
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+#define NUM_CQS (NUM_RX_RINGS + NUM_TX_RINGS)
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+#define GO_BIT_TIMEOUT 6000
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+#define TBIT_RETRIES 100
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+#define UNITS_BUFFER_SIZE 8 /* can be configured to 4/8/16 */
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+#define MAX_GAP_PROD_CONS (UNITS_BUFFER_SIZE/4)
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+#define DEF_MTU 1600
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+#define DEF_IOBUF_SIZE 1600
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+#define MAC_ADDRESS_SIZE 6
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+#define NUM_EQES 16
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+#define ROUND_TO_CHECK 0x400
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+
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+
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+/*
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+* Helper macros
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+*/
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+/* Print in case of an error */
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+#define eprintf(fmt, a...) \
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+ printf("%s:%d: " fmt "\n", __func__, __LINE__, ##a)
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+
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+#define XNOR(x,y) (!(x) == !(y))
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+#define dma_addr_t unsigned long
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+#define PAGE_SIZE 4096
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+#define PAGE_MASK (PAGE_SIZE - 1)
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+#define MTNIC_MAILBOX_SIZE PAGE_SIZE
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+#define MTNIC_ERROR 1
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+
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+
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+
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+
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+/* BITOPS */
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+#define MTNIC_BC_OFF(bc) ((bc) >> 8)
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+#define MTNIC_BC_SZ(bc) ((bc) & 0xff)
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+#define MTNIC_BC_ONES(size) (~((int)0x80000000 >> (31 - size)))
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+#define MTNIC_BC_MASK(bc) \
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+ (MTNIC_BC_ONES(MTNIC_BC_SZ(bc)) << MTNIC_BC_OFF(bc))
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+#define MTNIC_BC_VAL(val, bc) \
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+ (((val) & MTNIC_BC_ONES(MTNIC_BC_SZ(bc))) << MTNIC_BC_OFF(bc))
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+/*
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+ * Sub word fields - bit code base extraction/setting etc
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+ */
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+
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+/* Encode two values */
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+#define MTNIC_BC(off, size) ((off << 8) | (size & 0xff))
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+
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+/* Get value of field 'bc' from 'x' */
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+#define MTNIC_BC_GET(x, bc) \
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+ (((x) >> MTNIC_BC_OFF(bc)) & MTNIC_BC_ONES(MTNIC_BC_SZ(bc)))
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+
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+/* Set value of field 'bc' of 'x' to 'val' */
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+#define MTNIC_BC_SET(x, val, bc) \
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+ ((x) = ((x) & ~MTNIC_BC_MASK(bc)) | MTNIC_BC_VAL(val, bc))
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+
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+/* Like MTNIC_BC_SET, except the previous value is assumed to be 0 */
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+#define MTNIC_BC_PUT(x, val, bc) ((x) |= MTNIC_BC_VAL(val, bc))
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+
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+
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+
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+/*
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+ * Device constants
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+ */
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+typedef enum mtnic_if_cmd {
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+ /* NIC commands: */
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+ MTNIC_IF_CMD_QUERY_FW = 0x004, /* query FW (size, version, etc) */
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+ MTNIC_IF_CMD_MAP_FW = 0xfff, /* map pages for FW image */
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+ MTNIC_IF_CMD_RUN_FW = 0xff6, /* run the FW */
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+ MTNIC_IF_CMD_QUERY_CAP = 0x001, /* query MTNIC capabilities */
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+ MTNIC_IF_CMD_MAP_PAGES = 0x002, /* map physical pages to HW */
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+ MTNIC_IF_CMD_OPEN_NIC = 0x003, /* run the firmware */
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+ MTNIC_IF_CMD_CONFIG_RX = 0x005, /* general receive configuration */
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+ MTNIC_IF_CMD_CONFIG_TX = 0x006, /* general transmit configuration */
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+ MTNIC_IF_CMD_CONFIG_INT_FREQ = 0x007, /* interrupt timers freq limits */
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+ MTNIC_IF_CMD_HEART_BEAT = 0x008, /* NOP command testing liveliness */
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+ MTNIC_IF_CMD_CLOSE_NIC = 0x009, /* release memory and stop the NIC */
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+
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+ /* Port commands: */
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+ MTNIC_IF_CMD_CONFIG_PORT_RSS_STEER = 0x10, /* set RSS mode */
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+ MTNIC_IF_CMD_SET_PORT_RSS_INDIRECTION = 0x11, /* set RSS indirection tbl */
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+ MTNIC_IF_CMD_CONFIG_PORT_PRIO_STEERING = 0x12, /* set PRIORITY mode */
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+ MTNIC_IF_CMD_CONFIG_PORT_ADDR_STEER = 0x13, /* set Address steer mode */
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+ MTNIC_IF_CMD_CONFIG_PORT_VLAN_FILTER = 0x14, /* configure VLAN filter */
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+ MTNIC_IF_CMD_CONFIG_PORT_MCAST_FILTER = 0x15, /* configure mcast filter */
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+ MTNIC_IF_CMD_ENABLE_PORT_MCAST_FILTER = 0x16, /* enable/disable */
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+ MTNIC_IF_CMD_SET_PORT_MTU = 0x17, /* set port MTU */
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+ MTNIC_IF_CMD_SET_PORT_PROMISCUOUS_MODE = 0x18, /* enable/disable promisc */
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+ MTNIC_IF_CMD_SET_PORT_DEFAULT_RING = 0x19, /* set the default ring */
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+ MTNIC_IF_CMD_SET_PORT_STATE = 0x1a, /* set link up/down */
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+ MTNIC_IF_CMD_DUMP_STAT = 0x1b, /* dump statistics */
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+ MTNIC_IF_CMD_ARM_PORT_STATE_EVENT = 0x1c, /* arm the port state event */
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+
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+ /* Ring / Completion queue commands: */
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+ MTNIC_IF_CMD_CONFIG_CQ = 0x20, /* set up completion queue */
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+ MTNIC_IF_CMD_CONFIG_RX_RING = 0x21, /* setup Rx ring */
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+ MTNIC_IF_CMD_SET_RX_RING_ADDR = 0x22, /* set Rx ring filter by address */
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+ MTNIC_IF_CMD_SET_RX_RING_MCAST = 0x23, /* set Rx ring mcast filter */
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+ MTNIC_IF_CMD_ARM_RX_RING_WM = 0x24, /* one-time low-watermark INT */
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+ MTNIC_IF_CMD_CONFIG_TX_RING = 0x25, /* set up Tx ring */
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+ MTNIC_IF_CMD_ENFORCE_TX_RING_ADDR = 0x26, /* setup anti spoofing */
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+ MTNIC_IF_CMD_CONFIG_EQ = 0x27, /* config EQ ring */
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+ MTNIC_IF_CMD_RELEASE_RESOURCE = 0x28, /* release internal ref to resource */
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+}
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+mtnic_if_cmd_t;
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+
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+
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+/** selectors for MTNIC_IF_CMD_QUERY_CAP */
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+typedef enum mtnic_if_caps {
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+ MTNIC_IF_CAP_MAX_TX_RING_PER_PORT = 0x0,
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+ MTNIC_IF_CAP_MAX_RX_RING_PER_PORT = 0x1,
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+ MTNIC_IF_CAP_MAX_CQ_PER_PORT = 0x2,
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+ MTNIC_IF_CAP_NUM_PORTS = 0x3,
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+ MTNIC_IF_CAP_MAX_TX_DESC = 0x4,
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+ MTNIC_IF_CAP_MAX_RX_DESC = 0x5,
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+ MTNIC_IF_CAP_MAX_CQES = 0x6,
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+ MTNIC_IF_CAP_MAX_TX_SG_ENTRIES = 0x7,
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+ MTNIC_IF_CAP_MAX_RX_SG_ENTRIES = 0x8,
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+ MTNIC_IF_CAP_MEM_KEY = 0x9, /* key to mem (after map_pages) */
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+ MTNIC_IF_CAP_RSS_HASH_TYPE = 0xa, /* one of mtnic_if_rss_types_t */
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+ MTNIC_IF_CAP_MAX_PORT_UCAST_ADDR = 0xc,
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+ MTNIC_IF_CAP_MAX_RING_UCAST_ADDR = 0xd, /* only for ADDR steer */
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+ MTNIC_IF_CAP_MAX_PORT_MCAST_ADDR = 0xe,
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+ MTNIC_IF_CAP_MAX_RING_MCAST_ADDR = 0xf, /* only for ADDR steer */
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+ MTNIC_IF_CAP_INTA = 0x10,
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+ MTNIC_IF_CAP_BOARD_ID_LOW = 0x11,
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+ MTNIC_IF_CAP_BOARD_ID_HIGH = 0x12,
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+ MTNIC_IF_CAP_TX_CQ_DB_OFFSET = 0x13, /* offset in bytes for TX, CQ doorbell record */
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+ MTNIC_IF_CAP_EQ_DB_OFFSET = 0x14, /* offset in bytes for EQ doorbell record */
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+
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+ /* These are per port - using port number from cap modifier field */
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+ MTNIC_IF_CAP_SPEED = 0x20,
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+ MTNIC_IF_CAP_DEFAULT_MAC = 0x21,
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+ MTNIC_IF_CAP_EQ_OFFSET = 0x22,
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+ MTNIC_IF_CAP_CQ_OFFSET = 0x23,
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+ MTNIC_IF_CAP_TX_OFFSET = 0x24,
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+ MTNIC_IF_CAP_RX_OFFSET = 0x25,
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+
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+} mtnic_if_caps_t;
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+
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+typedef enum mtnic_if_steer_types {
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+ MTNIC_IF_STEER_NONE = 0,
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+ MTNIC_IF_STEER_PRIORITY = 1,
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+ MTNIC_IF_STEER_RSS = 2,
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+ MTNIC_IF_STEER_ADDRESS = 3,
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+} mtnic_if_steer_types_t;
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+
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+/** types of memory access modes */
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+typedef enum mtnic_if_memory_types {
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+ MTNIC_IF_MEM_TYPE_SNOOP = 1,
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+ MTNIC_IF_MEM_TYPE_NO_SNOOP = 2
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+} mtnic_if_memory_types_t;
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+
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+
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+enum {
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+ MTNIC_HCR_BASE = 0x1f000,
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+ MTNIC_HCR_SIZE = 0x0001c,
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+ MTNIC_CLR_INT_SIZE = 0x00008,
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+};
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+
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+#define MELLANOX_VENDOR_ID 0x15b3
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+#define MTNIC_DEVICE_ID 0x00a00190
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+#define MTNIC_RESET_OFFSET 0xF0010
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+#define MTNIC_DEVICE_ID_OFFSET 0xF0014
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+
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+
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+
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+
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+
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+
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+
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+/********************************************************************
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+* Device private data structures
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+*
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+* This section contains structures of all device private data:
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+* descriptors, rings, CQs, EQ ....
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+*
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+*
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+*********************************************************************/
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+/*
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+ * Descriptor format
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+ */
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+struct mtnic_ctrl_seg {
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+ u32 op_own;
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+#define MTNIC_BIT_DESC_OWN 0x80000000
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+#define MTNIC_OPCODE_SEND 0xa
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+ u32 size_vlan;
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+ u32 flags;
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+#define MTNIC_BIT_NO_ICRC 0x2
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+#define MTNIC_BIT_TX_COMP 0xc
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+ u32 reserved;
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+};
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+
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+struct mtnic_data_seg {
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+ u32 count;
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+#define MTNIC_INLINE 0x80000000
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+ u32 mem_type;
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+#define MTNIC_MEMTYPE_PAD 0x100
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+ u32 addr_h;
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+ u32 addr_l;
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+};
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+
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+struct mtnic_tx_desc {
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+ struct mtnic_ctrl_seg ctrl;
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+ struct mtnic_data_seg data; /* at least one data segment */
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+};
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+
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+struct mtnic_rx_desc {
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+ u16 reserved1;
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+ u16 next;
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+ u32 reserved2[3];
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+ struct mtnic_data_seg data; /* actual number of entries depends on
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+ * rx ring stride */
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+};
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+
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+/*
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+ * Rings
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+ */
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+struct mtnic_rx_db_record {
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+ u32 count;
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+};
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+
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+struct mtnic_ring {
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+ u32 size; /* REMOVE ____cacheline_aligned_in_smp; *//* number of Rx descs or TXBBs */
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+ u32 size_mask;
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+ u16 stride;
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+ u16 cq; /* index of port CQ associated with this ring */
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+ u32 prod;
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+ u32 cons; /* holds the last consumed index */
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+
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+ /* Buffers */
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+ u32 buf_size; /* ring buffer size in bytes */
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+ dma_addr_t dma;
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+ void *buf;
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+ struct io_buffer *iobuf[UNITS_BUFFER_SIZE];
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+
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+ /* Tx only */
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+ struct mtnic_txcq_db *txcq_db;
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+ u32 db_offset;
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+
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+ /* Rx ring only */
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+ dma_addr_t iobuf_dma;
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+ struct mtnic_rx_db_record *db;
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+ dma_addr_t db_dma;
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+};
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+
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+/*
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+ * CQ
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+ */
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+
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+struct mtnic_cqe {
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+ u8 vp; /* VLAN present */
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+ u8 reserved1[3];
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+ u32 rss_hash;
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+ u32 reserved2;
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+ u16 vlan_prio;
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+ u16 reserved3;
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+ u8 flags_h;
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+ u8 flags_l_rht;
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+ u8 ipv6_mask;
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+ u8 enc_bf;
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+#define MTNIC_BIT_BAD_FCS 0x10
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+#define MTNIC_OPCODE_ERROR 0x1e
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+ u32 byte_cnt;
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+ u16 index;
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+ u16 chksum;
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+ u8 reserved4[3];
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+ u8 op_tr_own;
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+#define MTNIC_BIT_CQ_OWN 0x80
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+};
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+
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+
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+struct mtnic_cq_db_record {
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+ u32 update_ci;
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+ u32 cmd_ci;
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+};
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|
320
|
+
|
|
321
|
+struct mtnic_cq {
|
|
322
|
+ int num; /* CQ number (on attached port) */
|
|
323
|
+ u32 size; /* number of CQEs in CQ */
|
|
324
|
+ u32 last; /* number of CQEs consumed */
|
|
325
|
+ struct mtnic_cq_db_record *db;
|
|
326
|
+ struct net_device *dev;
|
|
327
|
+
|
|
328
|
+ dma_addr_t db_dma;
|
|
329
|
+ u8 is_rx;
|
|
330
|
+ u16 ring; /* ring associated with this CQ */
|
|
331
|
+ u32 offset_ind;
|
|
332
|
+
|
|
333
|
+ /* CQE ring */
|
|
334
|
+ u32 buf_size; /* ring size in bytes */
|
|
335
|
+ struct mtnic_cqe *buf;
|
|
336
|
+ dma_addr_t dma;
|
|
337
|
+};
|
|
338
|
+
|
|
339
|
+/*
|
|
340
|
+ * EQ
|
|
341
|
+ */
|
|
342
|
+
|
|
343
|
+struct mtnic_eqe {
|
|
344
|
+ u8 reserved1;
|
|
345
|
+ u8 type;
|
|
346
|
+ u8 reserved2;
|
|
347
|
+ u8 subtype;
|
|
348
|
+ u8 reserved3[3];
|
|
349
|
+ u8 ring_cq;
|
|
350
|
+ u32 reserved4;
|
|
351
|
+ u8 port;
|
|
352
|
+#define MTNIC_MASK_EQE_PORT MTNIC_BC(4,2)
|
|
353
|
+ u8 reserved5[2];
|
|
354
|
+ u8 syndrome;
|
|
355
|
+ u8 reserved6[15];
|
|
356
|
+ u8 own;
|
|
357
|
+#define MTNIC_BIT_EQE_OWN 0x80
|
|
358
|
+};
|
|
359
|
+
|
|
360
|
+struct mtnic_eq {
|
|
361
|
+ u32 size; /* number of EQEs in ring */
|
|
362
|
+ u32 buf_size; /* EQ size in bytes */
|
|
363
|
+ void *buf;
|
|
364
|
+ dma_addr_t dma;
|
|
365
|
+};
|
|
366
|
+
|
|
367
|
+enum mtnic_state {
|
|
368
|
+ CARD_DOWN,
|
|
369
|
+ CARD_INITIALIZED,
|
|
370
|
+ CARD_UP
|
|
371
|
+};
|
|
372
|
+
|
|
373
|
+/* FW */
|
|
374
|
+struct mtnic_pages {
|
|
375
|
+ u32 num;
|
|
376
|
+ u32 *buf;
|
|
377
|
+};
|
|
378
|
+struct mtnic_err_buf {
|
|
379
|
+ u64 offset;
|
|
380
|
+ u32 size;
|
|
381
|
+};
|
|
382
|
+
|
|
383
|
+
|
|
384
|
+
|
|
385
|
+struct mtnic_cmd {
|
|
386
|
+ void *buf;
|
|
387
|
+ u32 mapping;
|
|
388
|
+ u32 tbit;
|
|
389
|
+};
|
|
390
|
+
|
|
391
|
+
|
|
392
|
+struct mtnic_txcq_db {
|
|
393
|
+ u32 reserved1[5];
|
|
394
|
+ u32 send_db;
|
|
395
|
+ u32 reserved2[2];
|
|
396
|
+ u32 cq_arm;
|
|
397
|
+ u32 cq_ci;
|
|
398
|
+};
|
|
399
|
+
|
|
400
|
+
|
|
401
|
+
|
|
402
|
+/*
|
|
403
|
+ * Device private data
|
|
404
|
+ *
|
|
405
|
+ */
|
|
406
|
+struct mtnic_priv {
|
|
407
|
+ struct net_device *dev;
|
|
408
|
+ struct pci_device *pdev;
|
|
409
|
+ u8 port;
|
|
410
|
+
|
|
411
|
+ enum mtnic_state state;
|
|
412
|
+ /* Firmware and board info */
|
|
413
|
+ u64 fw_ver;
|
|
414
|
+ struct {
|
|
415
|
+ struct mtnic_pages fw_pages;
|
|
416
|
+ struct mtnic_pages extra_pages;
|
|
417
|
+ struct mtnic_err_buf err_buf;
|
|
418
|
+ u16 ifc_rev;
|
|
419
|
+ u8 num_ports;
|
|
420
|
+ u64 mac[MTNIC_MAX_PORTS];
|
|
421
|
+ u16 cq_offset;
|
|
422
|
+ u16 tx_offset[MTNIC_MAX_PORTS];
|
|
423
|
+ u16 rx_offset[MTNIC_MAX_PORTS];
|
|
424
|
+ u32 mem_type_snoop_be;
|
|
425
|
+ u32 txcq_db_offset;
|
|
426
|
+ u32 eq_db_offset;
|
|
427
|
+ } fw;
|
|
428
|
+
|
|
429
|
+
|
|
430
|
+ struct mtnic_if_cmd_reg *hcr;
|
|
431
|
+ struct mtnic_cmd cmd;
|
|
432
|
+
|
|
433
|
+ /* TX, RX, CQs, EQ */
|
|
434
|
+ struct mtnic_ring tx_ring;
|
|
435
|
+ struct mtnic_ring rx_ring;
|
|
436
|
+ struct mtnic_cq cq[NUM_CQS];
|
|
437
|
+ struct mtnic_eq eq;
|
|
438
|
+ u32 *eq_db;
|
|
439
|
+ u32 poll_counter;
|
|
440
|
+};
|
|
441
|
+
|
|
442
|
+
|
|
443
|
+
|
|
444
|
+
|
|
445
|
+
|
|
446
|
+
|
|
447
|
+
|
|
448
|
+
|
|
449
|
+
|
|
450
|
+
|
|
451
|
+
|
|
452
|
+
|
|
453
|
+/***************************************************************************
|
|
454
|
+ * NIC COMMANDS
|
|
455
|
+ *
|
|
456
|
+ * The section below provides struct definition for commands parameters,
|
|
457
|
+ * and arguments values enumeration.
|
|
458
|
+ *
|
|
459
|
+ * The format used for the struct names is:
|
|
460
|
+ * mtnic_if_<cmd name>_<in|out>_<imm|mbox>
|
|
461
|
+ *
|
|
462
|
+ ***************************************************************************/
|
|
463
|
+/**
|
|
464
|
+ * Command Register (Command interface)
|
|
465
|
+ */
|
|
466
|
+struct mtnic_if_cmd_reg {
|
|
467
|
+ unsigned long in_param_h;
|
|
468
|
+ u32 in_param_l;
|
|
469
|
+ u32 input_modifier;
|
|
470
|
+ u32 out_param_h;
|
|
471
|
+ u32 out_param_l;
|
|
472
|
+ u32 token;
|
|
473
|
+#define MTNIC_MASK_CMD_REG_TOKEN MTNIC_BC(16,32)
|
|
474
|
+ u32 status_go_opcode;
|
|
475
|
+#define MTNIC_MASK_CMD_REG_OPCODE MTNIC_BC(0,16)
|
|
476
|
+#define MTNIC_MASK_CMD_REG_T_BIT MTNIC_BC(21,1)
|
|
477
|
+#define MTNIC_MASK_CMD_REG_GO_BIT MTNIC_BC(23,1)
|
|
478
|
+#define MTNIC_MASK_CMD_REG_STATUS MTNIC_BC(24,8)
|
|
479
|
+};
|
|
480
|
+
|
|
481
|
+
|
|
482
|
+
|
|
483
|
+/* CMD QUERY_FW */
|
|
484
|
+struct mtnic_if_query_fw_out_mbox {
|
|
485
|
+ u16 fw_pages; /* Total number of memory pages the device requires */
|
|
486
|
+ u16 rev_maj;
|
|
487
|
+ u16 rev_smin;
|
|
488
|
+ u16 rev_min;
|
|
489
|
+ u16 reserved1;
|
|
490
|
+ u16 ifc_rev; /* major revision of the command interface */
|
|
491
|
+ u8 ft;
|
|
492
|
+ u8 reserved2[3];
|
|
493
|
+ u32 reserved3[4];
|
|
494
|
+ u64 clr_int_base;
|
|
495
|
+ u32 reserved4[2];
|
|
496
|
+ u64 err_buf_start;
|
|
497
|
+ u32 err_buf_size;
|
|
498
|
+};
|
|
499
|
+
|
|
500
|
+/* CMD MTNIC_IF_CMD_QUERY_CAP */
|
|
501
|
+struct mtnic_if_query_cap_in_imm {
|
|
502
|
+ u16 reserved1;
|
|
503
|
+ u8 cap_modifier; /* a modifier for the particular capability */
|
|
504
|
+ u8 cap_index; /* the index of the capability queried */
|
|
505
|
+ u32 reserved2;
|
|
506
|
+};
|
|
507
|
+
|
|
508
|
+/* CMD OPEN_NIC */
|
|
509
|
+struct mtnic_if_open_nic_in_mbox {
|
|
510
|
+ u16 reserved1;
|
|
511
|
+ u16 mkey; /* number of mem keys for all chip*/
|
|
512
|
+ u32 mkey_entry; /* mem key entries for each key*/
|
|
513
|
+ u8 log_rx_p1; /* log2 rx rings for port1 */
|
|
514
|
+ u8 log_cq_p1; /* log2 cq for port1 */
|
|
515
|
+ u8 log_tx_p1; /* log2 tx rings for port1 */
|
|
516
|
+ u8 steer_p1; /* port 1 steering mode */
|
|
517
|
+ u16 reserved2;
|
|
518
|
+ u8 log_vlan_p1; /* log2 vlan per rx port1 */
|
|
519
|
+ u8 log_mac_p1; /* log2 mac per rx port1 */
|
|
520
|
+
|
|
521
|
+ u8 log_rx_p2; /* log2 rx rings for port1 */
|
|
522
|
+ u8 log_cq_p2; /* log2 cq for port1 */
|
|
523
|
+ u8 log_tx_p2; /* log2 tx rings for port1 */
|
|
524
|
+ u8 steer_p2; /* port 1 steering mode */
|
|
525
|
+ u16 reserved3;
|
|
526
|
+ u8 log_vlan_p2; /* log2 vlan per rx port1 */
|
|
527
|
+ u8 log_mac_p2; /* log2 mac per rx port1 */
|
|
528
|
+};
|
|
529
|
+
|
|
530
|
+/* CMD CONFIG_RX */
|
|
531
|
+struct mtnic_if_config_rx_in_imm {
|
|
532
|
+ u16 spkt_size; /* size of small packets interrupts enabled on CQ */
|
|
533
|
+ u16 resp_rcv_pause_frm_mcast_vlan_comp; /* Two flags see MASK below */
|
|
534
|
+ /* Enable response to receive pause frames */
|
|
535
|
+ /* Use VLAN in exact-match multicast checks (see SET_RX_RING_MCAST) */
|
|
536
|
+};
|
|
537
|
+
|
|
538
|
+/* CMD CONFIG_TX */
|
|
539
|
+struct mtnic_if_config_send_in_imm {
|
|
540
|
+ u32 enph_gpf; /* Enable PseudoHeader and GeneratePauseFrames flags */
|
|
541
|
+ u32 reserved;
|
|
542
|
+};
|
|
543
|
+
|
|
544
|
+/* CMD HEART_BEAT */
|
|
545
|
+struct mtnic_if_heart_beat_out_imm {
|
|
546
|
+ u32 flags; /* several flags */
|
|
547
|
+#define MTNIC_MASK_HEAR_BEAT_INT_ERROR MTNIC_BC(31,1)
|
|
548
|
+ u32 reserved;
|
|
549
|
+};
|
|
550
|
+
|
|
551
|
+
|
|
552
|
+/*
|
|
553
|
+ * PORT COMMANDS
|
|
554
|
+ */
|
|
555
|
+/* CMD CONFIG_PORT_VLAN_FILTER */
|
|
556
|
+/* in mbox is a 4K bits mask - bit per VLAN */
|
|
557
|
+struct mtnic_if_config_port_vlan_filter_in_mbox {
|
|
558
|
+ u64 filter[64]; /* vlans[63:0] sit in filter[0], vlans[127:64] sit in filter[1] .. */
|
|
559
|
+};
|
|
560
|
+
|
|
561
|
+
|
|
562
|
+/* CMD SET_PORT_MTU */
|
|
563
|
+struct mtnic_if_set_port_mtu_in_imm {
|
|
564
|
+ u16 reserved1;
|
|
565
|
+ u16 mtu; /* The MTU of the port in bytes */
|
|
566
|
+ u32 reserved2;
|
|
567
|
+};
|
|
568
|
+
|
|
569
|
+/* CMD SET_PORT_DEFAULT_RING */
|
|
570
|
+struct mtnic_if_set_port_default_ring_in_imm {
|
|
571
|
+ u8 reserved1[3];
|
|
572
|
+ u8 ring; /* Index of ring that collects promiscuous traffic */
|
|
573
|
+ u32 reserved2;
|
|
574
|
+};
|
|
575
|
+
|
|
576
|
+/* CMD SET_PORT_STATE */
|
|
577
|
+struct mtnic_if_set_port_state_in_imm {
|
|
578
|
+ u32 state; /* if 1 the port state should be up */
|
|
579
|
+#define MTNIC_MASK_CONFIG_PORT_STATE MTNIC_BC(0,1)
|
|
580
|
+ u32 reserved;
|
|
581
|
+};
|
|
582
|
+
|
|
583
|
+/* CMD CONFIG_CQ */
|
|
584
|
+struct mtnic_if_config_cq_in_mbox {
|
|
585
|
+ u8 reserved1;
|
|
586
|
+ u8 cq;
|
|
587
|
+ u8 size; /* Num CQs is 2^size (size <= 22) */
|
|
588
|
+ u8 offset; /* start address of CQE in first page (11:6) */
|
|
589
|
+ u16 tlast; /* interrupt moderation timer from last completion usec */
|
|
590
|
+ u8 flags; /* flags */
|
|
591
|
+ u8 int_vector; /* MSI index if MSI is enabled, otherwise reserved */
|
|
592
|
+ u16 reserved2;
|
|
593
|
+ u16 max_cnt; /* interrupt moderation counter */
|
|
594
|
+ u8 page_size; /* each mapped page is 2^(12+page_size) bytes */
|
|
595
|
+ u8 reserved4[3];
|
|
596
|
+ u32 db_record_addr_h; /*physical address of CQ doorbell record */
|
|
597
|
+ u32 db_record_addr_l; /*physical address of CQ doorbell record */
|
|
598
|
+ u32 page_address[0]; /* 64 bit page addresses of CQ buffer */
|
|
599
|
+};
|
|
600
|
+
|
|
601
|
+/* CMD CONFIG_RX_RING */
|
|
602
|
+struct mtnic_if_config_rx_ring_in_mbox {
|
|
603
|
+ u8 reserved1;
|
|
604
|
+ u8 ring; /* The ring index (with offset) */
|
|
605
|
+ u8 stride_size; /* stride and size */
|
|
606
|
+ /* Entry size = 16* (2^stride) bytes */
|
|
607
|
+#define MTNIC_MASK_CONFIG_RX_RING_STRIDE MTNIC_BC(4,3)
|
|
608
|
+ /* Rx ring size is 2^size entries */
|
|
609
|
+#define MTNIC_MASK_CONFIG_RX_RING_SIZE MTNIC_BC(0,4)
|
|
610
|
+ u8 flags; /* Bit0 - header separation */
|
|
611
|
+ u8 page_size; /* Each mapped page is 2^(12+page_size) bytes */
|
|
612
|
+ u8 reserved2[2];
|
|
613
|
+ u8 cq; /* CQ associated with this ring */
|
|
614
|
+ u32 db_record_addr_h;
|
|
615
|
+ u32 db_record_addr_l;
|
|
616
|
+ u32 page_address[0];/* Array of 2^size 64b page descriptor addresses */
|
|
617
|
+ /* Must hold all Rx descriptors + doorbell record. */
|
|
618
|
+};
|
|
619
|
+
|
|
620
|
+/* The modifier for SET_RX_RING_ADDR */
|
|
621
|
+struct mtnic_if_set_rx_ring_modifier {
|
|
622
|
+ u8 reserved;
|
|
623
|
+ u8 port_num;
|
|
624
|
+ u8 index;
|
|
625
|
+ u8 ring;
|
|
626
|
+};
|
|
627
|
+
|
|
628
|
+/* CMD SET_RX_RING_ADDR */
|
|
629
|
+struct mtnic_if_set_rx_ring_addr_in_imm {
|
|
630
|
+ u16 mac_47_32; /* UCAST MAC Address bits 47:32 */
|
|
631
|
+ u16 flags_vlan_id; /* MAC/VLAN flags and vlan id */
|
|
632
|
+#define MTNIC_MASK_SET_RX_RING_ADDR_VLAN_ID MTNIC_BC(0,12)
|
|
633
|
+#define MTNIC_MASK_SET_RX_RING_ADDR_BY_MAC MTNIC_BC(12,1)
|
|
634
|
+#define MTNIC_MASK_SET_RX_RING_ADDR_BY_VLAN MTNIC_BC(13,1)
|
|
635
|
+ u32 mac_31_0; /* UCAST MAC Address bits 31:0 */
|
|
636
|
+};
|
|
637
|
+
|
|
638
|
+/* CMD CONFIG_TX_RING */
|
|
639
|
+struct mtnic_if_config_send_ring_in_mbox {
|
|
640
|
+ u16 ring; /* The ring index (with offset) */
|
|
641
|
+#define MTNIC_MASK_CONFIG_TX_RING_INDEX MTNIC_BC(0,8)
|
|
642
|
+ u8 size; /* Tx ring size is 32*2^size bytes */
|
|
643
|
+#define MTNIC_MASK_CONFIG_TX_RING_SIZE MTNIC_BC(0,4)
|
|
644
|
+ u8 reserved;
|
|
645
|
+ u8 page_size; /* Each mapped page is 2^(12+page_size) bytes */
|
|
646
|
+ u8 qos_class; /* The COS used for this Tx */
|
|
647
|
+ u16 cq; /* CQ associated with this ring */
|
|
648
|
+#define MTNIC_MASK_CONFIG_TX_CQ_INDEX MTNIC_BC(0,8)
|
|
649
|
+ u32 page_address[0]; /* 64 bit page addresses of descriptor buffer. */
|
|
650
|
+ /* The buffer must accommodate all Tx descriptors */
|
|
651
|
+};
|
|
652
|
+
|
|
653
|
+/* CMD CONFIG_EQ */
|
|
654
|
+struct mtnic_if_config_eq_in_mbox {
|
|
655
|
+ u8 reserved1;
|
|
656
|
+ u8 int_vector; /* MSI index if MSI enabled; otherwise reserved */
|
|
657
|
+#define MTNIC_MASK_CONFIG_EQ_INT_VEC MTNIC_BC(0,6)
|
|
658
|
+ u8 size; /* Num CQs is 2^size entries (size <= 22) */
|
|
659
|
+#define MTNIC_MASK_CONFIG_EQ_SIZE MTNIC_BC(0,5)
|
|
660
|
+ u8 offset; /* Start address of CQE in first page (11:6) */
|
|
661
|
+#define MTNIC_MASK_CONFIG_EQ_OFFSET MTNIC_BC(0,6)
|
|
662
|
+ u8 page_size; /* Each mapped page is 2^(12+page_size) bytes*/
|
|
663
|
+ u8 reserved[3];
|
|
664
|
+ u32 page_address[0]; /* 64 bit page addresses of EQ buffer */
|
|
665
|
+};
|
|
666
|
+
|
|
667
|
+/* CMD RELEASE_RESOURCE */
|
|
668
|
+enum mtnic_if_resource_types {
|
|
669
|
+ MTNIC_IF_RESOURCE_TYPE_CQ = 0,
|
|
670
|
+ MTNIC_IF_RESOURCE_TYPE_RX_RING,
|
|
671
|
+ MTNIC_IF_RESOURCE_TYPE_TX_RING,
|
|
672
|
+ MTNIC_IF_RESOURCE_TYPE_EQ
|
|
673
|
+};
|
|
674
|
+
|
|
675
|
+struct mtnic_if_release_resource_in_imm {
|
|
676
|
+ u8 reserved1;
|
|
677
|
+ u8 index; /* must be 0 for TYPE_EQ */
|
|
678
|
+ u8 reserved2;
|
|
679
|
+ u8 type; /* see enum mtnic_if_resource_types */
|
|
680
|
+ u32 reserved3;
|
|
681
|
+};
|
|
682
|
+
|
|
683
|
+
|
|
684
|
+
|
|
685
|
+
|
|
686
|
+
|
|
687
|
+
|
|
688
|
+
|
|
689
|
+
|
|
690
|
+
|
|
691
|
+/*******************************************************************
|
|
692
|
+*
|
|
693
|
+* PCI addon structures
|
|
694
|
+*
|
|
695
|
+********************************************************************/
|
|
696
|
+
|
|
697
|
+struct pcidev {
|
|
698
|
+ unsigned long bar[6];
|
|
699
|
+ u32 dev_config_space[64];
|
|
700
|
+ struct pci_device *dev;
|
|
701
|
+ u8 bus;
|
|
702
|
+ u8 devfn;
|
|
703
|
+};
|
|
704
|
+
|
|
705
|
+struct dev_pci_struct {
|
|
706
|
+ struct pcidev dev;
|
|
707
|
+ struct pcidev br;
|
|
708
|
+};
|
|
709
|
+
|
|
710
|
+/* The only global var */
|
|
711
|
+struct dev_pci_struct mtnic_pci_dev;
|
|
712
|
+
|
|
713
|
+
|
|
714
|
+
|
|
715
|
+#endif /* H_MTNIC_IF_DEFS_H */
|
|
716
|
+
|