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[intel] Remove hardcoded offsets for descriptor ring registers

The Intel 10 Gigabit NICs use the same simplified (aka "legacy")
descriptor format and the same layout for descriptor register blocks
as the Intel 1 Gigabit NICs.  The offsets of the descriptor register
blocks are not the same.

Simplify reuse of the existing code by removing all hardcoded offsets
for registers within descriptor register blocks, and ensuring that all
offsets are calculated using the descriptor register block base
address provided via intel_init_ring().

Signed-off-by: Michael Brown <mcb30@ipxe.org>
tags/v1.20.1
Michael Brown 11 jaren geleden
bovenliggende
commit
c2ba57e517
2 gewijzigde bestanden met toevoegingen van 6 en 18 verwijderingen
  1. 6
    6
      src/drivers/net/intel.c
  2. 0
    12
      src/drivers/net/intel.h

+ 6
- 6
src/drivers/net/intel.c Bestand weergeven

@@ -248,10 +248,10 @@ static int intel_fetch_mac ( struct intel_nic *intel, uint8_t *hw_addr ) {
248 248
 static void __attribute__ (( unused )) intel_diag ( struct intel_nic *intel ) {
249 249
 
250 250
 	DBGC ( intel, "INTEL %p TDH=%04x TDT=%04x RDH=%04x RDT=%04x\n", intel,
251
-	       readl ( intel->regs + INTEL_TDH ),
252
-	       readl ( intel->regs + INTEL_TDT ),
253
-	       readl ( intel->regs + INTEL_RDH ),
254
-	       readl ( intel->regs + INTEL_RDT ) );
251
+	       readl ( intel->regs + intel->tx.reg + INTEL_xDH ),
252
+	       readl ( intel->regs + intel->tx.reg + INTEL_xDT ),
253
+	       readl ( intel->regs + intel->rx.reg + INTEL_xDH ),
254
+	       readl ( intel->regs + intel->rx.reg + INTEL_xDT ) );
255 255
 }
256 256
 
257 257
 /******************************************************************************
@@ -468,7 +468,7 @@ static void intel_refill_rx ( struct intel_nic *intel ) {
468 468
 		intel->rx_iobuf[rx_idx] = iobuf;
469 469
 
470 470
 		/* Push descriptor to card */
471
-		writel ( rx_tail, intel->regs + INTEL_RDT );
471
+		writel ( rx_tail, intel->regs + intel->rx.reg + INTEL_xDT );
472 472
 
473 473
 		DBGC2 ( intel, "INTEL %p RX %d is [%llx,%llx)\n", intel, rx_idx,
474 474
 			( ( unsigned long long ) address ),
@@ -599,7 +599,7 @@ static int intel_transmit ( struct net_device *netdev,
599 599
 	wmb();
600 600
 
601 601
 	/* Notify card that there are packets ready to transmit */
602
-	writel ( tx_tail, intel->regs + INTEL_TDT );
602
+	writel ( tx_tail, intel->regs + intel->tx.reg + INTEL_xDT );
603 603
 
604 604
 	DBGC2 ( intel, "INTEL %p TX %d is [%llx,%llx)\n", intel, tx_idx,
605 605
 		( ( unsigned long long ) address ),

+ 0
- 12
src/drivers/net/intel.h Bestand weergeven

@@ -175,18 +175,6 @@ enum intel_descriptor_status {
175 175
 #define INTEL_xDCTL 0x28
176 176
 #define INTEL_xDCTL_ENABLE	0x02000000UL	/**< Queue enable */
177 177
 
178
-/** Receive Descriptor Head */
179
-#define INTEL_RDH ( INTEL_RD + INTEL_xDH )
180
-
181
-/** Receive Descriptor Tail */
182
-#define INTEL_RDT ( INTEL_RD + INTEL_xDT )
183
-
184
-/** Transmit Descriptor Head */
185
-#define INTEL_TDH ( INTEL_TD + INTEL_xDH )
186
-
187
-/** Transmit Descriptor Tail */
188
-#define INTEL_TDT ( INTEL_TD + INTEL_xDT )
189
-
190 178
 /** Receive Address Low */
191 179
 #define INTEL_RAL0 0x05400UL
192 180
 

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