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[e1000e] Add e1000e driver

This commit adds an e1000e driver based on Intel source code
available at:

    http://sourceforge.net/projects/e1000/

which is upstream source for the Linux kernel e1000 drivers, and
should support many PCIe e1000 variants.

Signed-off-by: Marty Connor <mdc@etherboot.org>
tags/v1.20.1
Marty Connor vor 14 Jahren
Ursprung
Commit
be5392c93a

+ 1
- 0
src/Makefile Datei anzeigen

@@ -59,6 +59,7 @@ SRCDIRS		+= image
59 59
 SRCDIRS		+= drivers/bus
60 60
 SRCDIRS		+= drivers/net
61 61
 SRCDIRS		+= drivers/net/e1000
62
+SRCDIRS		+= drivers/net/e1000e
62 63
 SRCDIRS		+= drivers/net/phantom
63 64
 SRCDIRS		+= drivers/net/rtl818x
64 65
 SRCDIRS		+= drivers/net/ath5k

+ 34
- 0
src/drivers/net/e1000e/e1000e.c Datei anzeigen

@@ -0,0 +1,34 @@
1
+/*******************************************************************************
2
+
3
+  Intel PRO/1000 Linux driver
4
+  Copyright(c) 1999 - 2008 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  Linux NICS <linux.nics@intel.com>
24
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
+
27
+*******************************************************************************/
28
+
29
+FILE_LICENCE ( GPL2_ONLY );
30
+
31
+REQUIRE_OBJECT(e1000e_main);
32
+REQUIRE_OBJECT(e1000e_80003es2lan);
33
+REQUIRE_OBJECT(e1000e_82571);
34
+REQUIRE_OBJECT(e1000e_ich8lan);

+ 533
- 0
src/drivers/net/e1000e/e1000e.h Datei anzeigen

@@ -0,0 +1,533 @@
1
+/*******************************************************************************
2
+
3
+  Intel PRO/1000 Linux driver
4
+  Copyright(c) 1999 - 2009 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  Linux NICS <linux.nics@intel.com>
24
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
+
27
+*******************************************************************************/
28
+
29
+FILE_LICENCE ( GPL2_OR_LATER );
30
+
31
+/* Linux PRO/1000 Ethernet Driver main header file */
32
+
33
+#ifndef _E1000E_H_
34
+#define _E1000E_H_
35
+
36
+#include <stdint.h>
37
+#include <stdlib.h>
38
+#include <stdio.h>
39
+#include <string.h>
40
+#include <unistd.h>
41
+#include <gpxe/io.h>
42
+#include <errno.h>
43
+#include <byteswap.h>
44
+#include <gpxe/pci.h>
45
+#include <gpxe/malloc.h>
46
+#include <gpxe/if_ether.h>
47
+#include <gpxe/ethernet.h>
48
+#include <gpxe/iobuf.h>
49
+#include <gpxe/netdevice.h>
50
+
51
+/* Begin OS Dependencies */
52
+
53
+#define u8         unsigned char
54
+#define bool       boolean_t
55
+#define dma_addr_t unsigned long
56
+#define __le16     uint16_t
57
+#define __le32     uint32_t
58
+#define __le64     uint64_t
59
+
60
+#define __iomem
61
+
62
+#define msleep(x) mdelay(x)
63
+
64
+#define ETH_FCS_LEN 4
65
+
66
+typedef int spinlock_t;
67
+typedef enum {
68
+    false = 0,
69
+    true = 1
70
+} boolean_t;
71
+
72
+/* End OS Dependencies */
73
+
74
+#include "e1000e_hw.h"
75
+
76
+#define E1000_TX_FLAGS_CSUM		0x00000001
77
+#define E1000_TX_FLAGS_VLAN		0x00000002
78
+#define E1000_TX_FLAGS_TSO		0x00000004
79
+#define E1000_TX_FLAGS_IPV4		0x00000008
80
+#define E1000_TX_FLAGS_VLAN_MASK	0xffff0000
81
+#define E1000_TX_FLAGS_VLAN_SHIFT	16
82
+
83
+#define E1000_MAX_PER_TXD	8192
84
+#define E1000_MAX_TXD_PWR	12
85
+
86
+#define MINIMUM_DHCP_PACKET_SIZE 282
87
+
88
+struct e1000_info;
89
+
90
+#define e_dbg(arg...) if (0) { printf (arg); };
91
+
92
+#ifdef CONFIG_E1000E_MSIX
93
+/* Interrupt modes, as used by the IntMode paramter */
94
+#define E1000E_INT_MODE_LEGACY		0
95
+#define E1000E_INT_MODE_MSI		1
96
+#define E1000E_INT_MODE_MSIX		2
97
+
98
+#endif /* CONFIG_E1000E_MSIX */
99
+#ifndef CONFIG_E1000E_NAPI
100
+#define E1000_MAX_INTR 10
101
+
102
+#endif /* CONFIG_E1000E_NAPI */
103
+/* Tx/Rx descriptor defines */
104
+#define E1000_DEFAULT_TXD		256
105
+#define E1000_MAX_TXD			4096
106
+#define E1000_MIN_TXD			64
107
+
108
+#define E1000_DEFAULT_RXD		256
109
+#define E1000_MAX_RXD			4096
110
+#define E1000_MIN_RXD			64
111
+
112
+#define E1000_MIN_ITR_USECS		10 /* 100000 irq/sec */
113
+#define E1000_MAX_ITR_USECS		10000 /* 100    irq/sec */
114
+
115
+/* Early Receive defines */
116
+#define E1000_ERT_2048			0x100
117
+
118
+#define E1000_FC_PAUSE_TIME		0x0680 /* 858 usec */
119
+
120
+/* How many Tx Descriptors do we need to call netif_wake_queue ? */
121
+/* How many Rx Buffers do we bundle into one write to the hardware ? */
122
+#define E1000_RX_BUFFER_WRITE		16 /* Must be power of 2 */
123
+
124
+#define AUTO_ALL_MODES			0
125
+#define E1000_EEPROM_APME		0x0400
126
+
127
+#define E1000_MNG_VLAN_NONE		(-1)
128
+
129
+/* Number of packet split data buffers (not including the header buffer) */
130
+#define PS_PAGE_BUFFERS			(MAX_PS_BUFFERS - 1)
131
+
132
+#define MAXIMUM_ETHERNET_VLAN_SIZE 	1522
133
+
134
+#define DEFAULT_JUMBO			9234
135
+
136
+enum e1000_boards {
137
+	board_82571,
138
+	board_82572,
139
+	board_82573,
140
+	board_82574,
141
+	board_80003es2lan,
142
+	board_ich8lan,
143
+	board_ich9lan,
144
+	board_ich10lan,
145
+	board_pchlan,
146
+	board_82583,
147
+};
148
+
149
+/* board specific private data structure */
150
+struct e1000_adapter {
151
+	const struct e1000_info *ei;
152
+
153
+	/* OS defined structs */
154
+	struct net_device *netdev;
155
+	struct pci_device *pdev;
156
+	struct net_device_stats net_stats;
157
+
158
+	/* structs defined in e1000_hw.h */
159
+	struct e1000_hw hw;
160
+
161
+	struct e1000_phy_info phy_info;
162
+
163
+	u32 wol;
164
+	u32 pba;
165
+	u32 max_hw_frame_size;
166
+
167
+	bool fc_autoneg;
168
+
169
+	unsigned int flags;
170
+	unsigned int flags2;
171
+
172
+#define NUM_TX_DESC	8
173
+#define NUM_RX_DESC	8
174
+
175
+	struct io_buffer *tx_iobuf[NUM_TX_DESC];
176
+	struct io_buffer *rx_iobuf[NUM_RX_DESC];
177
+
178
+	struct e1000_tx_desc *tx_base;
179
+	struct e1000_rx_desc *rx_base;
180
+
181
+	uint32_t tx_ring_size;
182
+	uint32_t rx_ring_size;
183
+
184
+	uint32_t tx_head;
185
+	uint32_t tx_tail;
186
+	uint32_t tx_fill_ctr;
187
+
188
+	uint32_t rx_curr;
189
+
190
+	uint32_t ioaddr;
191
+	uint32_t irqno;
192
+
193
+        uint32_t tx_int_delay;
194
+        uint32_t tx_abs_int_delay;
195
+        uint32_t txd_cmd;
196
+};
197
+
198
+struct e1000_info {
199
+	enum e1000_mac_type	mac;
200
+	unsigned int		flags;
201
+	unsigned int		flags2;
202
+	u32			pba;
203
+	u32			max_hw_frame_size;
204
+	s32			(*get_variants)(struct e1000_adapter *);
205
+	void			(*init_ops)(struct e1000_hw *);
206
+};
207
+
208
+/* hardware capability, feature, and workaround flags */
209
+#define FLAG_HAS_AMT                      (1 << 0)
210
+#define FLAG_HAS_FLASH                    (1 << 1)
211
+#define FLAG_HAS_HW_VLAN_FILTER           (1 << 2)
212
+#define FLAG_HAS_WOL                      (1 << 3)
213
+#define FLAG_HAS_ERT                      (1 << 4)
214
+#define FLAG_HAS_CTRLEXT_ON_LOAD          (1 << 5)
215
+#define FLAG_HAS_SWSM_ON_LOAD             (1 << 6)
216
+#define FLAG_HAS_JUMBO_FRAMES             (1 << 7)
217
+#define FLAG_IS_ICH                       (1 << 9)
218
+#ifdef CONFIG_E1000E_MSIX
219
+#define FLAG_HAS_MSIX                     (1 << 10)
220
+#endif
221
+#define FLAG_HAS_SMART_POWER_DOWN         (1 << 11)
222
+#define FLAG_IS_QUAD_PORT_A               (1 << 12)
223
+#define FLAG_IS_QUAD_PORT                 (1 << 13)
224
+#define FLAG_TIPG_MEDIUM_FOR_80003ESLAN   (1 << 14)
225
+#define FLAG_APME_IN_WUC                  (1 << 15)
226
+#define FLAG_APME_IN_CTRL3                (1 << 16)
227
+#define FLAG_APME_CHECK_PORT_B            (1 << 17)
228
+#define FLAG_DISABLE_FC_PAUSE_TIME        (1 << 18)
229
+#define FLAG_NO_WAKE_UCAST                (1 << 19)
230
+#define FLAG_MNG_PT_ENABLED               (1 << 20)
231
+#define FLAG_RESET_OVERWRITES_LAA         (1 << 21)
232
+#define FLAG_TARC_SPEED_MODE_BIT          (1 << 22)
233
+#define FLAG_TARC_SET_BIT_ZERO            (1 << 23)
234
+#define FLAG_RX_NEEDS_RESTART             (1 << 24)
235
+#define FLAG_LSC_GIG_SPEED_DROP           (1 << 25)
236
+#define FLAG_SMART_POWER_DOWN             (1 << 26)
237
+#define FLAG_MSI_ENABLED                  (1 << 27)
238
+#define FLAG_RX_CSUM_ENABLED              (1 << 28)
239
+#define FLAG_TSO_FORCE                    (1 << 29)
240
+#define FLAG_RX_RESTART_NOW               (1 << 30)
241
+#define FLAG_MSI_TEST_FAILED              (1 << 31)
242
+
243
+/* CRC Stripping defines */
244
+#define FLAG2_CRC_STRIPPING               (1 << 0)
245
+#define FLAG2_HAS_PHY_WAKEUP              (1 << 1)
246
+
247
+#define E1000_RX_DESC_PS(R, i)	    \
248
+	(&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
249
+#define E1000_GET_DESC(R, i, type)	(&(((struct type *)((R).desc))[i]))
250
+#define E1000_RX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_rx_desc)
251
+#define E1000_TX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_tx_desc)
252
+#define E1000_CONTEXT_DESC(R, i)	E1000_GET_DESC(R, i, e1000_context_desc)
253
+
254
+enum e1000_state_t {
255
+	__E1000E_TESTING,
256
+	__E1000E_RESETTING,
257
+	__E1000E_DOWN
258
+};
259
+
260
+enum latency_range {
261
+	lowest_latency = 0,
262
+	low_latency = 1,
263
+	bulk_latency = 2,
264
+	latency_invalid = 255
265
+};
266
+
267
+extern void e1000e_check_options(struct e1000_adapter *adapter);
268
+
269
+extern void e1000e_reset(struct e1000_adapter *adapter);
270
+extern void e1000e_power_up_phy(struct e1000_adapter *adapter);
271
+
272
+extern void e1000e_init_function_pointers_82571(struct e1000_hw *hw)
273
+						__attribute__((weak));
274
+extern void e1000e_init_function_pointers_80003es2lan(struct e1000_hw *hw)
275
+						__attribute__((weak));
276
+extern void e1000e_init_function_pointers_ich8lan(struct e1000_hw *hw)
277
+						__attribute__((weak));
278
+
279
+extern int e1000e_probe(struct pci_device *pdev,
280
+		       const struct pci_device_id *id __unused);
281
+
282
+extern void e1000e_remove(struct pci_device *pdev);
283
+
284
+extern s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num);
285
+
286
+static inline s32 e1000e_commit_phy(struct e1000_hw *hw)
287
+{
288
+	if (hw->phy.ops.commit)
289
+		return hw->phy.ops.commit(hw);
290
+
291
+	return 0;
292
+}
293
+
294
+extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
295
+
296
+extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
297
+extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
298
+
299
+extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
300
+						 bool state);
301
+extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
302
+extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
303
+extern void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw);
304
+
305
+extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
306
+extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
307
+extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
308
+extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
309
+extern s32 e1000e_led_on_generic(struct e1000_hw *hw);
310
+extern s32 e1000e_led_off_generic(struct e1000_hw *hw);
311
+extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
312
+extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex);
313
+extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex);
314
+extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
315
+extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
316
+extern s32 e1000e_id_led_init(struct e1000_hw *hw);
317
+extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
318
+extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
319
+extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
320
+extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
321
+extern s32 e1000e_setup_link(struct e1000_hw *hw);
322
+static inline void e1000e_clear_vfta(struct e1000_hw *hw)
323
+{
324
+	hw->mac.ops.clear_vfta(hw);
325
+}
326
+extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
327
+extern void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
328
+					       u8 *mc_addr_list,
329
+					       u32 mc_addr_count);
330
+extern void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
331
+extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
332
+extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
333
+extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
334
+extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
335
+extern void e1000e_config_collision_dist(struct e1000_hw *hw);
336
+extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
337
+extern s32 e1000e_force_mac_fc(struct e1000_hw *hw);
338
+extern s32 e1000e_blink_led(struct e1000_hw *hw);
339
+extern void e1000e_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
340
+static inline void e1000e_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
341
+{
342
+	if (hw->mac.ops.write_vfta)
343
+		hw->mac.ops.write_vfta(hw, offset, value);
344
+}
345
+extern void e1000e_reset_adaptive(struct e1000_hw *hw);
346
+extern void e1000e_update_adaptive(struct e1000_hw *hw);
347
+
348
+extern s32 e1000e_setup_copper_link(struct e1000_hw *hw);
349
+extern void e1000e_put_hw_semaphore(struct e1000_hw *hw);
350
+extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
351
+#if 0
352
+extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
353
+#endif
354
+#if 0
355
+extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
356
+#endif
357
+extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
358
+extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
359
+extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
360
+extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
361
+extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
362
+extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
363
+#if 0
364
+extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
365
+#endif
366
+extern s32 e1000e_get_cfg_done(struct e1000_hw *hw);
367
+#if 0
368
+extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
369
+#endif
370
+extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
371
+extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
372
+extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
373
+extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
374
+extern s32 e1000e_determine_phy_address(struct e1000_hw *hw);
375
+extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
376
+extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
377
+#if 0
378
+extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
379
+#endif
380
+extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
381
+extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
382
+extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
383
+			       u32 usec_interval, bool *success);
384
+extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
385
+extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
386
+extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
387
+extern s32 e1000e_check_downshift(struct e1000_hw *hw);
388
+
389
+static inline s32 e1000e_phy_hw_reset(struct e1000_hw *hw)
390
+{
391
+	if (hw->phy.ops.reset)
392
+		return hw->phy.ops.reset(hw);
393
+
394
+	return 0;
395
+}
396
+
397
+static inline s32 e1000e_check_reset_block(struct e1000_hw *hw)
398
+{
399
+	if (hw->phy.ops.check_reset_block)
400
+		return hw->phy.ops.check_reset_block(hw);
401
+
402
+	return 0;
403
+}
404
+
405
+static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
406
+{
407
+	if (hw->phy.ops.read_reg)
408
+		return hw->phy.ops.read_reg(hw, offset, data);
409
+
410
+	return 0;
411
+}
412
+
413
+static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
414
+{
415
+	if (hw->phy.ops.write_reg)
416
+		return hw->phy.ops.write_reg(hw, offset, data);
417
+
418
+	return 0;
419
+}
420
+
421
+#if 0
422
+static inline s32 e1000e_get_cable_length(struct e1000_hw *hw)
423
+{
424
+	if (hw->phy.ops.get_cable_length)
425
+		return hw->phy.ops.get_cable_length(hw);
426
+
427
+	return 0;
428
+}
429
+#endif
430
+
431
+extern s32 e1000e_acquire_nvm(struct e1000_hw *hw);
432
+extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
433
+extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
434
+extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
435
+extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
436
+extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
437
+extern void e1000e_release_nvm(struct e1000_hw *hw);
438
+
439
+static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
440
+{
441
+       if (hw->mac.ops.read_mac_addr)
442
+               return hw->mac.ops.read_mac_addr(hw);
443
+
444
+       return e1000e_read_mac_addr_generic(hw);
445
+}
446
+
447
+static inline s32 e1000e_validate_nvm_checksum(struct e1000_hw *hw)
448
+{
449
+	return hw->nvm.ops.validate(hw);
450
+}
451
+
452
+static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
453
+{
454
+	return hw->nvm.ops.update(hw);
455
+}
456
+
457
+static inline s32 e1000e_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
458
+{
459
+	return hw->nvm.ops.read(hw, offset, words, data);
460
+}
461
+
462
+static inline s32 e1000e_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
463
+{
464
+	return hw->nvm.ops.write(hw, offset, words, data);
465
+}
466
+
467
+static inline s32 e1000e_get_phy_info(struct e1000_hw *hw)
468
+{
469
+	if (hw->phy.ops.get_info)
470
+		return hw->phy.ops.get_info(hw);
471
+
472
+	return 0;
473
+}
474
+
475
+extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
476
+#if 0
477
+extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
478
+#endif
479
+
480
+static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
481
+{
482
+	return readl(hw->hw_addr + reg);
483
+}
484
+
485
+static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
486
+{
487
+	writel(val, hw->hw_addr + reg);
488
+}
489
+
490
+#define er32(reg)	__er32(hw, E1000_##reg)
491
+#define ew32(reg, val)	__ew32(hw, E1000_##reg, (val))
492
+#define e1e_flush()	er32(STATUS)
493
+
494
+#define E1000_WRITE_REG(a, reg, value)  \
495
+    writel((value), ((a)->hw_addr + reg))
496
+
497
+#define E1000_READ_REG(a, reg) (readl((a)->hw_addr + reg))
498
+
499
+#define E1000_WRITE_REG_ARRAY(a, reg, offset, value)  \
500
+    writel((value), ((a)->hw_addr + reg + ((offset) << 2)))
501
+
502
+#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
503
+    readl((a)->hw_addr + reg + ((offset) << 2)))
504
+
505
+#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
506
+#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
507
+
508
+static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
509
+{
510
+	return readw(hw->flash_address + reg);
511
+}
512
+
513
+static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
514
+{
515
+	return readl(hw->flash_address + reg);
516
+}
517
+
518
+static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
519
+{
520
+	writew(val, hw->flash_address + reg);
521
+}
522
+
523
+static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
524
+{
525
+	writel(val, hw->flash_address + reg);
526
+}
527
+
528
+#define er16flash(reg)		__er16flash(hw, (reg))
529
+#define er32flash(reg)		__er32flash(hw, (reg))
530
+#define ew16flash(reg, val)	__ew16flash(hw, (reg), (val))
531
+#define ew32flash(reg, val)	__ew32flash(hw, (reg), (val))
532
+
533
+#endif /* _E1000E_H_ */

+ 1533
- 0
src/drivers/net/e1000e/e1000e_80003es2lan.c
Datei-Diff unterdrückt, da er zu groß ist
Datei anzeigen


+ 100
- 0
src/drivers/net/e1000e/e1000e_80003es2lan.h Datei anzeigen

@@ -0,0 +1,100 @@
1
+/*******************************************************************************
2
+
3
+  Intel PRO/1000 Linux driver
4
+  Copyright(c) 1999 - 2009 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  Linux NICS <linux.nics@intel.com>
24
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
+
27
+*******************************************************************************/
28
+
29
+FILE_LICENCE ( GPL2_OR_LATER );
30
+
31
+#ifndef _E1000E_80003ES2LAN_H_
32
+#define _E1000E_80003ES2LAN_H_
33
+
34
+#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL       0x00
35
+#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL        0x02
36
+#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL         0x10
37
+#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE  0x1F
38
+
39
+#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS    0x0008
40
+#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS    0x0800
41
+#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING   0x0010
42
+
43
+#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
44
+#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT   0x0000
45
+#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE          0x2000
46
+
47
+#define E1000_KMRNCTRLSTA_OPMODE_MASK            0x000C
48
+#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO     0x0004
49
+
50
+#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
51
+#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN        0x00010000
52
+
53
+#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN       0x8
54
+#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN     0x9
55
+
56
+/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
57
+#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE  0x0002 /* 1=Reversal Disabled */
58
+#define GG82563_PSCR_CROSSOVER_MODE_MASK        0x0060
59
+#define GG82563_PSCR_CROSSOVER_MODE_MDI         0x0000 /* 00=Manual MDI */
60
+#define GG82563_PSCR_CROSSOVER_MODE_MDIX        0x0020 /* 01=Manual MDIX */
61
+#define GG82563_PSCR_CROSSOVER_MODE_AUTO        0x0060 /* 11=Auto crossover */
62
+
63
+/* PHY Specific Control Register 2 (Page 0, Register 26) */
64
+#define GG82563_PSCR2_REVERSE_AUTO_NEG          0x2000
65
+                                               /* 1=Reverse Auto-Negotiation */
66
+
67
+/* MAC Specific Control Register (Page 2, Register 21) */
68
+/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
69
+#define GG82563_MSCR_TX_CLK_MASK                0x0007
70
+#define GG82563_MSCR_TX_CLK_10MBPS_2_5          0x0004
71
+#define GG82563_MSCR_TX_CLK_100MBPS_25          0x0005
72
+#define GG82563_MSCR_TX_CLK_1000MBPS_2_5        0x0006
73
+#define GG82563_MSCR_TX_CLK_1000MBPS_25         0x0007
74
+
75
+#define GG82563_MSCR_ASSERT_CRS_ON_TX           0x0010 /* 1=Assert */
76
+
77
+/* DSP Distance Register (Page 5, Register 26) */
78
+/*
79
+ * 0 = <50M
80
+ * 1 = 50-80M
81
+ * 2 = 80-100M
82
+ * 3 = 110-140M
83
+ * 4 = >140M
84
+ */
85
+#define GG82563_DSPD_CABLE_LENGTH               0x0007
86
+
87
+/* Kumeran Mode Control Register (Page 193, Register 16) */
88
+#define GG82563_KMCR_PASS_FALSE_CARRIER         0x0800
89
+
90
+/* Max number of times Kumeran read/write should be validated */
91
+#define GG82563_MAX_KMRN_RETRY                  0x5
92
+
93
+/* Power Management Control Register (Page 193, Register 20) */
94
+#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE     0x0001
95
+                                          /* 1=Enable SERDES Electrical Idle */
96
+
97
+/* In-Band Control Register (Page 194, Register 18) */
98
+#define GG82563_ICR_DIS_PADDING                 0x0010 /* Disable Padding */
99
+
100
+#endif

+ 1818
- 0
src/drivers/net/e1000e/e1000e_82571.c
Datei-Diff unterdrückt, da er zu groß ist
Datei anzeigen


+ 55
- 0
src/drivers/net/e1000e/e1000e_82571.h Datei anzeigen

@@ -0,0 +1,55 @@
1
+/*******************************************************************************
2
+
3
+  Intel PRO/1000 Linux driver
4
+  Copyright(c) 1999 - 2009 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  Linux NICS <linux.nics@intel.com>
24
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
+
27
+*******************************************************************************/
28
+
29
+FILE_LICENCE ( GPL2_OR_LATER );
30
+
31
+#ifndef _E1000E_82571_H_
32
+#define _E1000E_82571_H_
33
+
34
+#define ID_LED_RESERVED_F746 0xF746
35
+#define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
36
+                              (ID_LED_OFF1_ON2  <<  8) | \
37
+                              (ID_LED_DEF1_DEF2 <<  4) | \
38
+                              (ID_LED_DEF1_DEF2))
39
+
40
+#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
41
+
42
+/* Intr Throttling - RW */
43
+#define E1000_EITR_82574(_n)    (0x000E8 + (0x4 * (_n)))
44
+
45
+#define E1000_EIAC_82574        0x000DC /* Ext. Interrupt Auto Clear - RW */
46
+#define E1000_EIAC_MASK_82574   0x01F00000
47
+
48
+#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
49
+
50
+#define E1000_RXCFGL    0x0B634 /* TimeSync Rx EtherType & Msg Type Reg - RW */
51
+
52
+bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
53
+void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
54
+
55
+#endif

+ 1469
- 0
src/drivers/net/e1000e/e1000e_defines.h
Datei-Diff unterdrückt, da er zu groß ist
Datei anzeigen


+ 719
- 0
src/drivers/net/e1000e/e1000e_hw.h Datei anzeigen

@@ -0,0 +1,719 @@
1
+/*******************************************************************************
2
+
3
+  Intel PRO/1000 Linux driver
4
+  Copyright(c) 1999 - 2009 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  Linux NICS <linux.nics@intel.com>
24
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
+
27
+*******************************************************************************/
28
+
29
+FILE_LICENCE ( GPL2_OR_LATER );
30
+
31
+#ifndef _E1000E_HW_H_
32
+#define _E1000E_HW_H_
33
+
34
+#include "e1000e_regs.h"
35
+#include "e1000e_defines.h"
36
+
37
+struct e1000_hw;
38
+
39
+#define E1000_DEV_ID_82571EB_COPPER           0x105E
40
+#define E1000_DEV_ID_82571EB_FIBER            0x105F
41
+#define E1000_DEV_ID_82571EB_SERDES           0x1060
42
+#define E1000_DEV_ID_82571EB_SERDES_DUAL      0x10D9
43
+#define E1000_DEV_ID_82571EB_SERDES_QUAD      0x10DA
44
+#define E1000_DEV_ID_82571EB_QUAD_COPPER      0x10A4
45
+#define E1000_DEV_ID_82571PT_QUAD_COPPER      0x10D5
46
+#define E1000_DEV_ID_82571EB_QUAD_FIBER       0x10A5
47
+#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP   0x10BC
48
+#define E1000_DEV_ID_82572EI_COPPER           0x107D
49
+#define E1000_DEV_ID_82572EI_FIBER            0x107E
50
+#define E1000_DEV_ID_82572EI_SERDES           0x107F
51
+#define E1000_DEV_ID_82572EI                  0x10B9
52
+#define E1000_DEV_ID_82573E                   0x108B
53
+#define E1000_DEV_ID_82573E_IAMT              0x108C
54
+#define E1000_DEV_ID_82573L                   0x109A
55
+#define E1000_DEV_ID_82574L                   0x10D3
56
+#define E1000_DEV_ID_82574LA                  0x10F6
57
+#define E1000_DEV_ID_82583V                   0x150C
58
+#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT   0x1096
59
+#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT   0x1098
60
+#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT   0x10BA
61
+#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT   0x10BB
62
+#define E1000_DEV_ID_ICH8_82567V_3            0x1501
63
+#define E1000_DEV_ID_ICH8_IGP_M_AMT           0x1049
64
+#define E1000_DEV_ID_ICH8_IGP_AMT             0x104A
65
+#define E1000_DEV_ID_ICH8_IGP_C               0x104B
66
+#define E1000_DEV_ID_ICH8_IFE                 0x104C
67
+#define E1000_DEV_ID_ICH8_IFE_GT              0x10C4
68
+#define E1000_DEV_ID_ICH8_IFE_G               0x10C5
69
+#define E1000_DEV_ID_ICH8_IGP_M               0x104D
70
+#define E1000_DEV_ID_ICH9_IGP_M               0x10BF
71
+#define E1000_DEV_ID_ICH9_IGP_M_AMT           0x10F5
72
+#define E1000_DEV_ID_ICH9_IGP_M_V             0x10CB
73
+#define E1000_DEV_ID_ICH9_IGP_AMT             0x10BD
74
+#define E1000_DEV_ID_ICH9_BM                  0x10E5
75
+#define E1000_DEV_ID_ICH9_IGP_C               0x294C
76
+#define E1000_DEV_ID_ICH9_IFE                 0x10C0
77
+#define E1000_DEV_ID_ICH9_IFE_GT              0x10C3
78
+#define E1000_DEV_ID_ICH9_IFE_G               0x10C2
79
+#define E1000_DEV_ID_ICH10_R_BM_LM            0x10CC
80
+#define E1000_DEV_ID_ICH10_R_BM_LF            0x10CD
81
+#define E1000_DEV_ID_ICH10_R_BM_V             0x10CE
82
+#define E1000_DEV_ID_ICH10_D_BM_LM            0x10DE
83
+#define E1000_DEV_ID_ICH10_D_BM_LF            0x10DF
84
+#define E1000_DEV_ID_PCH_M_HV_LM              0x10EA
85
+#define E1000_DEV_ID_PCH_M_HV_LC              0x10EB
86
+#define E1000_DEV_ID_PCH_D_HV_DM              0x10EF
87
+#define E1000_DEV_ID_PCH_D_HV_DC              0x10F0
88
+#define E1000_REVISION_0 0
89
+#define E1000_REVISION_1 1
90
+#define E1000_REVISION_2 2
91
+#define E1000_REVISION_3 3
92
+#define E1000_REVISION_4 4
93
+
94
+#define E1000_FUNC_0     0
95
+#define E1000_FUNC_1     1
96
+
97
+#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
98
+#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
99
+
100
+enum e1000_mac_type {
101
+	e1000_undefined = 0,
102
+	e1000_82571,
103
+	e1000_82572,
104
+	e1000_82573,
105
+	e1000_82574,
106
+	e1000_82583,
107
+	e1000_80003es2lan,
108
+	e1000_ich8lan,
109
+	e1000_ich9lan,
110
+	e1000_ich10lan,
111
+	e1000_pchlan,
112
+	e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
113
+};
114
+
115
+enum e1000_media_type {
116
+	e1000_media_type_unknown = 0,
117
+	e1000_media_type_copper = 1,
118
+	e1000_media_type_fiber = 2,
119
+	e1000_media_type_internal_serdes = 3,
120
+	e1000_num_media_types
121
+};
122
+
123
+enum e1000_nvm_type {
124
+	e1000_nvm_unknown = 0,
125
+	e1000_nvm_none,
126
+	e1000_nvm_eeprom_spi,
127
+	e1000_nvm_flash_hw,
128
+	e1000_nvm_flash_sw
129
+};
130
+
131
+enum e1000_nvm_override {
132
+	e1000_nvm_override_none = 0,
133
+	e1000_nvm_override_spi_small,
134
+	e1000_nvm_override_spi_large,
135
+};
136
+
137
+enum e1000_phy_type {
138
+	e1000_phy_unknown = 0,
139
+	e1000_phy_none,
140
+	e1000_phy_m88,
141
+	e1000_phy_igp,
142
+	e1000_phy_igp_2,
143
+	e1000_phy_gg82563,
144
+	e1000_phy_igp_3,
145
+	e1000_phy_ife,
146
+	e1000_phy_bm,
147
+	e1000_phy_82578,
148
+	e1000_phy_82577,
149
+};
150
+
151
+enum e1000_bus_type {
152
+	e1000_bus_type_unknown = 0,
153
+	e1000_bus_type_pci,
154
+	e1000_bus_type_pcix,
155
+	e1000_bus_type_pci_express,
156
+	e1000_bus_type_reserved
157
+};
158
+
159
+enum e1000_bus_speed {
160
+	e1000_bus_speed_unknown = 0,
161
+	e1000_bus_speed_33,
162
+	e1000_bus_speed_66,
163
+	e1000_bus_speed_100,
164
+	e1000_bus_speed_120,
165
+	e1000_bus_speed_133,
166
+	e1000_bus_speed_2500,
167
+	e1000_bus_speed_5000,
168
+	e1000_bus_speed_reserved
169
+};
170
+
171
+enum e1000_bus_width {
172
+	e1000_bus_width_unknown = 0,
173
+	e1000_bus_width_pcie_x1,
174
+	e1000_bus_width_pcie_x2,
175
+	e1000_bus_width_pcie_x4 = 4,
176
+	e1000_bus_width_pcie_x8 = 8,
177
+	e1000_bus_width_32,
178
+	e1000_bus_width_64,
179
+	e1000_bus_width_reserved
180
+};
181
+
182
+enum e1000_1000t_rx_status {
183
+	e1000_1000t_rx_status_not_ok = 0,
184
+	e1000_1000t_rx_status_ok,
185
+	e1000_1000t_rx_status_undefined = 0xFF
186
+};
187
+
188
+enum e1000_rev_polarity {
189
+	e1000_rev_polarity_normal = 0,
190
+	e1000_rev_polarity_reversed,
191
+	e1000_rev_polarity_undefined = 0xFF
192
+};
193
+
194
+enum e1000_fc_mode {
195
+	e1000_fc_none = 0,
196
+	e1000_fc_rx_pause,
197
+	e1000_fc_tx_pause,
198
+	e1000_fc_full,
199
+	e1000_fc_default = 0xFF
200
+};
201
+
202
+enum e1000_ms_type {
203
+	e1000_ms_hw_default = 0,
204
+	e1000_ms_force_master,
205
+	e1000_ms_force_slave,
206
+	e1000_ms_auto
207
+};
208
+
209
+enum e1000_smart_speed {
210
+	e1000_smart_speed_default = 0,
211
+	e1000_smart_speed_on,
212
+	e1000_smart_speed_off
213
+};
214
+
215
+enum e1000_serdes_link_state {
216
+	e1000_serdes_link_down = 0,
217
+	e1000_serdes_link_autoneg_progress,
218
+	e1000_serdes_link_autoneg_complete,
219
+	e1000_serdes_link_forced_up
220
+};
221
+
222
+/* Receive Descriptor */
223
+struct e1000_rx_desc {
224
+	__le64 buffer_addr; /* Address of the descriptor's data buffer */
225
+	__le16 length;      /* Length of data DMAed into data buffer */
226
+	__le16 csum;        /* Packet checksum */
227
+	u8  status;         /* Descriptor status */
228
+	u8  errors;         /* Descriptor Errors */
229
+	__le16 special;
230
+};
231
+
232
+/* Receive Descriptor - Extended */
233
+union e1000_rx_desc_extended {
234
+	struct {
235
+		__le64 buffer_addr;
236
+		__le64 reserved;
237
+	} read;
238
+	struct {
239
+		struct {
240
+			__le32 mrq;           /* Multiple Rx Queues */
241
+			union {
242
+				__le32 rss;         /* RSS Hash */
243
+				struct {
244
+					__le16 ip_id;  /* IP id */
245
+					__le16 csum;   /* Packet Checksum */
246
+				} csum_ip;
247
+			} hi_dword;
248
+		} lower;
249
+		struct {
250
+			__le32 status_error;  /* ext status/error */
251
+			__le16 length;
252
+			__le16 vlan;          /* VLAN tag */
253
+		} upper;
254
+	} wb;  /* writeback */
255
+};
256
+
257
+#define MAX_PS_BUFFERS 4
258
+/* Receive Descriptor - Packet Split */
259
+union e1000_rx_desc_packet_split {
260
+	struct {
261
+		/* one buffer for protocol header(s), three data buffers */
262
+		__le64 buffer_addr[MAX_PS_BUFFERS];
263
+	} read;
264
+	struct {
265
+		struct {
266
+			__le32 mrq;           /* Multiple Rx Queues */
267
+			union {
268
+				__le32 rss;           /* RSS Hash */
269
+				struct {
270
+					__le16 ip_id;    /* IP id */
271
+					__le16 csum;     /* Packet Checksum */
272
+				} csum_ip;
273
+			} hi_dword;
274
+		} lower;
275
+		struct {
276
+			__le32 status_error;  /* ext status/error */
277
+			__le16 length0;       /* length of buffer 0 */
278
+			__le16 vlan;          /* VLAN tag */
279
+		} middle;
280
+		struct {
281
+			__le16 header_status;
282
+			__le16 length[3];     /* length of buffers 1-3 */
283
+		} upper;
284
+		__le64 reserved;
285
+	} wb; /* writeback */
286
+};
287
+
288
+/* Transmit Descriptor */
289
+struct e1000_tx_desc {
290
+	__le64 buffer_addr;   /* Address of the descriptor's data buffer */
291
+	union {
292
+		__le32 data;
293
+		struct {
294
+			__le16 length;    /* Data buffer length */
295
+			u8 cso;           /* Checksum offset */
296
+			u8 cmd;           /* Descriptor control */
297
+		} flags;
298
+	} lower;
299
+	union {
300
+		__le32 data;
301
+		struct {
302
+			u8 status;        /* Descriptor status */
303
+			u8 css;           /* Checksum start */
304
+			__le16 special;
305
+		} fields;
306
+	} upper;
307
+};
308
+
309
+/* Offload Context Descriptor */
310
+struct e1000_context_desc {
311
+	union {
312
+		__le32 ip_config;
313
+		struct {
314
+			u8 ipcss;         /* IP checksum start */
315
+			u8 ipcso;         /* IP checksum offset */
316
+			__le16 ipcse;     /* IP checksum end */
317
+		} ip_fields;
318
+	} lower_setup;
319
+	union {
320
+		__le32 tcp_config;
321
+		struct {
322
+			u8 tucss;         /* TCP checksum start */
323
+			u8 tucso;         /* TCP checksum offset */
324
+			__le16 tucse;     /* TCP checksum end */
325
+		} tcp_fields;
326
+	} upper_setup;
327
+	__le32 cmd_and_length;
328
+	union {
329
+		__le32 data;
330
+		struct {
331
+			u8 status;        /* Descriptor status */
332
+			u8 hdr_len;       /* Header length */
333
+			__le16 mss;       /* Maximum segment size */
334
+		} fields;
335
+	} tcp_seg_setup;
336
+};
337
+
338
+/* Offload data descriptor */
339
+struct e1000_data_desc {
340
+	__le64 buffer_addr;   /* Address of the descriptor's buffer address */
341
+	union {
342
+		__le32 data;
343
+		struct {
344
+			__le16 length;    /* Data buffer length */
345
+			u8 typ_len_ext;
346
+			u8 cmd;
347
+		} flags;
348
+	} lower;
349
+	union {
350
+		__le32 data;
351
+		struct {
352
+			u8 status;        /* Descriptor status */
353
+			u8 popts;         /* Packet Options */
354
+			__le16 special;
355
+		} fields;
356
+	} upper;
357
+};
358
+
359
+/* Statistics counters collected by the MAC */
360
+struct e1000_hw_stats {
361
+	u64 crcerrs;
362
+	u64 algnerrc;
363
+	u64 symerrs;
364
+	u64 rxerrc;
365
+	u64 mpc;
366
+	u64 scc;
367
+	u64 ecol;
368
+	u64 mcc;
369
+	u64 latecol;
370
+	u64 colc;
371
+	u64 dc;
372
+	u64 tncrs;
373
+	u64 sec;
374
+	u64 cexterr;
375
+	u64 rlec;
376
+	u64 xonrxc;
377
+	u64 xontxc;
378
+	u64 xoffrxc;
379
+	u64 xofftxc;
380
+	u64 fcruc;
381
+	u64 prc64;
382
+	u64 prc127;
383
+	u64 prc255;
384
+	u64 prc511;
385
+	u64 prc1023;
386
+	u64 prc1522;
387
+	u64 gprc;
388
+	u64 bprc;
389
+	u64 mprc;
390
+	u64 gptc;
391
+	u64 gorc;
392
+	u64 gotc;
393
+	u64 rnbc;
394
+	u64 ruc;
395
+	u64 rfc;
396
+	u64 roc;
397
+	u64 rjc;
398
+	u64 mgprc;
399
+	u64 mgpdc;
400
+	u64 mgptc;
401
+	u64 tor;
402
+	u64 tot;
403
+	u64 tpr;
404
+	u64 tpt;
405
+	u64 ptc64;
406
+	u64 ptc127;
407
+	u64 ptc255;
408
+	u64 ptc511;
409
+	u64 ptc1023;
410
+	u64 ptc1522;
411
+	u64 mptc;
412
+	u64 bptc;
413
+	u64 tsctc;
414
+	u64 tsctfc;
415
+	u64 iac;
416
+	u64 icrxptc;
417
+	u64 icrxatc;
418
+	u64 ictxptc;
419
+	u64 ictxatc;
420
+	u64 ictxqec;
421
+	u64 ictxqmtc;
422
+	u64 icrxdmtc;
423
+	u64 icrxoc;
424
+	u64 doosync;
425
+};
426
+
427
+
428
+struct e1000_phy_stats {
429
+	u32 idle_errors;
430
+	u32 receive_errors;
431
+};
432
+
433
+struct e1000_host_mng_dhcp_cookie {
434
+	u32 signature;
435
+	u8  status;
436
+	u8  reserved0;
437
+	u16 vlan_id;
438
+	u32 reserved1;
439
+	u16 reserved2;
440
+	u8  reserved3;
441
+	u8  checksum;
442
+};
443
+
444
+/* Host Interface "Rev 1" */
445
+struct e1000_host_command_header {
446
+	u8 command_id;
447
+	u8 command_length;
448
+	u8 command_options;
449
+	u8 checksum;
450
+};
451
+
452
+#define E1000_HI_MAX_DATA_LENGTH     252
453
+struct e1000_host_command_info {
454
+	struct e1000_host_command_header command_header;
455
+	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
456
+};
457
+
458
+/* Host Interface "Rev 2" */
459
+struct e1000_host_mng_command_header {
460
+	u8  command_id;
461
+	u8  checksum;
462
+	u16 reserved1;
463
+	u16 reserved2;
464
+	u16 command_length;
465
+};
466
+
467
+#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
468
+struct e1000_host_mng_command_info {
469
+	struct e1000_host_mng_command_header command_header;
470
+	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
471
+};
472
+
473
+#include "e1000e_mac.h"
474
+#include "e1000e_phy.h"
475
+#include "e1000e_nvm.h"
476
+#include "e1000e_manage.h"
477
+
478
+struct e1000_mac_operations {
479
+	/* Function pointers for the MAC. */
480
+	s32  (*init_params)(struct e1000_hw *);
481
+	s32  (*id_led_init)(struct e1000_hw *);
482
+	s32  (*blink_led)(struct e1000_hw *);
483
+	s32  (*check_for_link)(struct e1000_hw *);
484
+	bool (*check_mng_mode)(struct e1000_hw *hw);
485
+	s32  (*cleanup_led)(struct e1000_hw *);
486
+	void (*clear_hw_cntrs)(struct e1000_hw *);
487
+	void (*clear_vfta)(struct e1000_hw *);
488
+	s32  (*get_bus_info)(struct e1000_hw *);
489
+	void (*set_lan_id)(struct e1000_hw *);
490
+	s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
491
+	s32  (*led_on)(struct e1000_hw *);
492
+	s32  (*led_off)(struct e1000_hw *);
493
+	void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
494
+	s32  (*reset_hw)(struct e1000_hw *);
495
+	s32  (*init_hw)(struct e1000_hw *);
496
+	s32  (*setup_link)(struct e1000_hw *);
497
+	s32  (*setup_physical_interface)(struct e1000_hw *);
498
+	s32  (*setup_led)(struct e1000_hw *);
499
+	void (*write_vfta)(struct e1000_hw *, u32, u32);
500
+	void (*mta_set)(struct e1000_hw *, u32);
501
+	void (*config_collision_dist)(struct e1000_hw *);
502
+	void (*rar_set)(struct e1000_hw *, u8*, u32);
503
+	s32  (*read_mac_addr)(struct e1000_hw *);
504
+	s32  (*validate_mdi_setting)(struct e1000_hw *);
505
+	s32  (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
506
+	s32  (*mng_write_cmd_header)(struct e1000_hw *hw,
507
+                      struct e1000_host_mng_command_header*);
508
+	s32  (*mng_enable_host_if)(struct e1000_hw *);
509
+	s32  (*wait_autoneg)(struct e1000_hw *);
510
+};
511
+
512
+struct e1000_phy_operations {
513
+	s32  (*init_params)(struct e1000_hw *);
514
+	s32  (*acquire)(struct e1000_hw *);
515
+	s32  (*cfg_on_link_up)(struct e1000_hw *);
516
+	s32  (*check_polarity)(struct e1000_hw *);
517
+	s32  (*check_reset_block)(struct e1000_hw *);
518
+	s32  (*commit)(struct e1000_hw *);
519
+#if 0
520
+	s32  (*force_speed_duplex)(struct e1000_hw *);
521
+#endif
522
+	s32  (*get_cfg_done)(struct e1000_hw *hw);
523
+#if 0
524
+	s32  (*get_cable_length)(struct e1000_hw *);
525
+#endif
526
+	s32  (*get_info)(struct e1000_hw *);
527
+	s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
528
+	s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
529
+	void (*release)(struct e1000_hw *);
530
+	s32  (*reset)(struct e1000_hw *);
531
+	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
532
+	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
533
+	s32  (*write_reg)(struct e1000_hw *, u32, u16);
534
+	s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
535
+	void (*power_up)(struct e1000_hw *);
536
+	void (*power_down)(struct e1000_hw *);
537
+};
538
+
539
+struct e1000_nvm_operations {
540
+	s32  (*init_params)(struct e1000_hw *);
541
+	s32  (*acquire)(struct e1000_hw *);
542
+	s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
543
+	void (*release)(struct e1000_hw *);
544
+	void (*reload)(struct e1000_hw *);
545
+	s32  (*update)(struct e1000_hw *);
546
+	s32  (*valid_led_default)(struct e1000_hw *, u16 *);
547
+	s32  (*validate)(struct e1000_hw *);
548
+	s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
549
+};
550
+
551
+struct e1000_mac_info {
552
+	struct e1000_mac_operations ops;
553
+	u8 addr[6];
554
+	u8 perm_addr[6];
555
+
556
+	enum e1000_mac_type type;
557
+
558
+	u32 collision_delta;
559
+	u32 ledctl_default;
560
+	u32 ledctl_mode1;
561
+	u32 ledctl_mode2;
562
+	u32 mc_filter_type;
563
+	u32 tx_packet_delta;
564
+	u32 txcw;
565
+
566
+	u16 current_ifs_val;
567
+	u16 ifs_max_val;
568
+	u16 ifs_min_val;
569
+	u16 ifs_ratio;
570
+	u16 ifs_step_size;
571
+	u16 mta_reg_count;
572
+
573
+	/* Maximum size of the MTA register table in all supported adapters */
574
+	#define MAX_MTA_REG 128
575
+	u32 mta_shadow[MAX_MTA_REG];
576
+	u16 rar_entry_count;
577
+
578
+	u8  forced_speed_duplex;
579
+
580
+	bool adaptive_ifs;
581
+	bool arc_subsystem_valid;
582
+	bool asf_firmware_present;
583
+	bool autoneg;
584
+	bool autoneg_failed;
585
+	bool get_link_status;
586
+	bool in_ifs_mode;
587
+	enum e1000_serdes_link_state serdes_link_state;
588
+	bool serdes_has_link;
589
+	bool tx_pkt_filtering;
590
+};
591
+
592
+struct e1000_phy_info {
593
+	struct e1000_phy_operations ops;
594
+	enum e1000_phy_type type;
595
+
596
+	enum e1000_1000t_rx_status local_rx;
597
+	enum e1000_1000t_rx_status remote_rx;
598
+	enum e1000_ms_type ms_type;
599
+	enum e1000_ms_type original_ms_type;
600
+	enum e1000_rev_polarity cable_polarity;
601
+	enum e1000_smart_speed smart_speed;
602
+
603
+	u32 addr;
604
+	u32 id;
605
+	u32 reset_delay_us; /* in usec */
606
+	u32 revision;
607
+
608
+	enum e1000_media_type media_type;
609
+
610
+	u16 autoneg_advertised;
611
+	u16 autoneg_mask;
612
+	u16 cable_length;
613
+	u16 max_cable_length;
614
+	u16 min_cable_length;
615
+
616
+	u8 mdix;
617
+
618
+	bool disable_polarity_correction;
619
+	bool is_mdix;
620
+	bool polarity_correction;
621
+	bool reset_disable;
622
+	bool speed_downgraded;
623
+	bool autoneg_wait_to_complete;
624
+};
625
+
626
+struct e1000_nvm_info {
627
+	struct e1000_nvm_operations ops;
628
+	enum e1000_nvm_type type;
629
+	enum e1000_nvm_override override;
630
+
631
+	u32 flash_bank_size;
632
+	u32 flash_base_addr;
633
+
634
+	u16 word_size;
635
+	u16 delay_usec;
636
+	u16 address_bits;
637
+	u16 opcode_bits;
638
+	u16 page_size;
639
+};
640
+
641
+struct e1000_bus_info {
642
+	enum e1000_bus_type type;
643
+	enum e1000_bus_speed speed;
644
+	enum e1000_bus_width width;
645
+
646
+	u16 func;
647
+	u16 pci_cmd_word;
648
+};
649
+
650
+struct e1000_fc_info {
651
+	u32 high_water;          /* Flow control high-water mark */
652
+	u32 low_water;           /* Flow control low-water mark */
653
+	u16 pause_time;          /* Flow control pause timer */
654
+	bool send_xon;           /* Flow control send XON */
655
+	bool strict_ieee;        /* Strict IEEE mode */
656
+	enum e1000_fc_mode current_mode; /* FC mode in effect */
657
+	enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
658
+};
659
+
660
+struct e1000_dev_spec_82571 {
661
+	bool laa_is_present;
662
+	u32 smb_counter;
663
+};
664
+
665
+struct e1000_dev_spec_80003es2lan {
666
+	bool  mdic_wa_enable;
667
+};
668
+
669
+struct e1000_shadow_ram {
670
+	u16  value;
671
+	bool modified;
672
+};
673
+
674
+#define E1000_ICH8_SHADOW_RAM_WORDS		2048
675
+
676
+struct e1000_dev_spec_ich8lan {
677
+	bool kmrn_lock_loss_workaround_enabled;
678
+	struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
679
+	bool nvm_k1_enabled;
680
+};
681
+
682
+struct e1000_hw {
683
+	struct e1000_adapter *adapter;
684
+
685
+	u8 __iomem *hw_addr;
686
+	u8 __iomem *flash_address;
687
+
688
+	void *back;
689
+	unsigned long io_base;
690
+
691
+	struct e1000_mac_info  mac;
692
+	struct e1000_fc_info   fc;
693
+	struct e1000_phy_info  phy;
694
+	struct e1000_nvm_info  nvm;
695
+	struct e1000_bus_info  bus;
696
+	struct e1000_host_mng_dhcp_cookie mng_cookie;
697
+
698
+	union {
699
+		struct e1000_dev_spec_82571	_82571;
700
+		struct e1000_dev_spec_80003es2lan _80003es2lan;
701
+		struct e1000_dev_spec_ich8lan	ich8lan;
702
+	} dev_spec;
703
+
704
+	u16 device_id;
705
+	u16 subsystem_vendor_id;
706
+	u16 subsystem_device_id;
707
+	u16 vendor_id;
708
+
709
+	u8  revision_id;
710
+};
711
+
712
+#include "e1000e_82571.h"
713
+#include "e1000e_80003es2lan.h"
714
+#include "e1000e_ich8lan.h"
715
+
716
+/* These functions must be implemented by drivers */
717
+s32  e1000e_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
718
+
719
+#endif

+ 3444
- 0
src/drivers/net/e1000e/e1000e_ich8lan.c
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- 0
src/drivers/net/e1000e/e1000e_ich8lan.h Datei anzeigen

@@ -0,0 +1,196 @@
1
+/*******************************************************************************
2
+
3
+  Intel PRO/1000 Linux driver
4
+  Copyright(c) 1999 - 2009 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  Linux NICS <linux.nics@intel.com>
24
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
+
27
+*******************************************************************************/
28
+
29
+FILE_LICENCE ( GPL2_OR_LATER );
30
+
31
+#ifndef _E1000E_ICH8LAN_H_
32
+#define _E1000E_ICH8LAN_H_
33
+
34
+#define ICH_FLASH_GFPREG                 0x0000
35
+#define ICH_FLASH_HSFSTS                 0x0004
36
+#define ICH_FLASH_HSFCTL                 0x0006
37
+#define ICH_FLASH_FADDR                  0x0008
38
+#define ICH_FLASH_FDATA0                 0x0010
39
+
40
+/* Requires up to 10 seconds when MNG might be accessing part. */
41
+#define ICH_FLASH_READ_COMMAND_TIMEOUT   10000000
42
+#define ICH_FLASH_WRITE_COMMAND_TIMEOUT  10000000
43
+#define ICH_FLASH_ERASE_COMMAND_TIMEOUT  10000000
44
+#define ICH_FLASH_LINEAR_ADDR_MASK       0x00FFFFFF
45
+#define ICH_FLASH_CYCLE_REPEAT_COUNT     10
46
+
47
+#define ICH_CYCLE_READ                   0
48
+#define ICH_CYCLE_WRITE                  2
49
+#define ICH_CYCLE_ERASE                  3
50
+
51
+#define FLASH_GFPREG_BASE_MASK           0x1FFF
52
+#define FLASH_SECTOR_ADDR_SHIFT          12
53
+
54
+#define ICH_FLASH_SEG_SIZE_256           256
55
+#define ICH_FLASH_SEG_SIZE_4K            4096
56
+#define ICH_FLASH_SEG_SIZE_8K            8192
57
+#define ICH_FLASH_SEG_SIZE_64K           65536
58
+#define ICH_FLASH_SECTOR_SIZE            4096
59
+
60
+#define ICH_FLASH_REG_MAPSIZE            0x00A0
61
+
62
+#define E1000_ICH_FWSM_RSPCIPHY          0x00000040 /* Reset PHY on PCI Reset */
63
+#define E1000_ICH_FWSM_DISSW             0x10000000 /* FW Disables SW Writes */
64
+/* FW established a valid mode */
65
+#define E1000_ICH_FWSM_FW_VALID          0x00008000
66
+
67
+#define E1000_ICH_MNG_IAMT_MODE          0x2
68
+
69
+#define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
70
+                                 (ID_LED_OFF1_OFF2 <<  8) | \
71
+                                 (ID_LED_OFF1_ON2  <<  4) | \
72
+                                 (ID_LED_DEF1_DEF2))
73
+
74
+#define E1000_ICH_NVM_SIG_WORD           0x13
75
+#define E1000_ICH_NVM_SIG_MASK           0xC000
76
+#define E1000_ICH_NVM_VALID_SIG_MASK     0xC0
77
+#define E1000_ICH_NVM_SIG_VALUE          0x80
78
+
79
+#define E1000_ICH8_LAN_INIT_TIMEOUT      1500
80
+
81
+#define E1000_FEXTNVM_SW_CONFIG        1
82
+#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */
83
+
84
+#define PCIE_ICH8_SNOOP_ALL   PCIE_NO_SNOOP_ALL
85
+
86
+#define E1000_ICH_RAR_ENTRIES            7
87
+
88
+#define PHY_PAGE_SHIFT 5
89
+#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
90
+                           ((reg) & MAX_PHY_REG_ADDRESS))
91
+#define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
92
+#define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
93
+#define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */
94
+#define IGP3_PM_CTRL    PHY_REG(769, 20) /* Power Management Control */
95
+
96
+#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS         0x0002
97
+#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
98
+#define IGP3_VR_CTRL_MODE_SHUTDOWN           0x0200
99
+#define IGP3_PM_CTRL_FORCE_PWR_DOWN          0x0020
100
+
101
+/* PHY Wakeup Registers and defines */
102
+#define BM_RCTL         PHY_REG(BM_WUC_PAGE, 0)
103
+#define BM_WUC          PHY_REG(BM_WUC_PAGE, 1)
104
+#define BM_WUFC         PHY_REG(BM_WUC_PAGE, 2)
105
+#define BM_WUS          PHY_REG(BM_WUC_PAGE, 3)
106
+#define BM_RAR_L(_i)    (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
107
+#define BM_RAR_M(_i)    (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
108
+#define BM_RAR_H(_i)    (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
109
+#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
110
+#define BM_MTA(_i)      (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
111
+
112
+#define BM_RCTL_UPE           0x0001          /* Unicast Promiscuous Mode */
113
+#define BM_RCTL_MPE           0x0002          /* Multicast Promiscuous Mode */
114
+#define BM_RCTL_MO_SHIFT      3               /* Multicast Offset Shift */
115
+#define BM_RCTL_MO_MASK       (3 << 3)        /* Multicast Offset Mask */
116
+#define BM_RCTL_BAM           0x0020          /* Broadcast Accept Mode */
117
+#define BM_RCTL_PMCF          0x0040          /* Pass MAC Control Frames */
118
+#define BM_RCTL_RFCE          0x0080          /* Rx Flow Control Enable */
119
+
120
+#define HV_LED_CONFIG		PHY_REG(768, 30) /* LED Configuration */
121
+#define HV_MUX_DATA_CTRL               PHY_REG(776, 16)
122
+#define HV_MUX_DATA_CTRL_GEN_TO_MAC    0x0400
123
+#define HV_MUX_DATA_CTRL_FORCE_SPEED   0x0004
124
+#define HV_SCC_UPPER		PHY_REG(778, 16) /* Single Collision Count */
125
+#define HV_SCC_LOWER		PHY_REG(778, 17)
126
+#define HV_ECOL_UPPER		PHY_REG(778, 18) /* Excessive Collision Count */
127
+#define HV_ECOL_LOWER		PHY_REG(778, 19)
128
+#define HV_MCC_UPPER		PHY_REG(778, 20) /* Multiple Collision Count */
129
+#define HV_MCC_LOWER		PHY_REG(778, 21)
130
+#define HV_LATECOL_UPPER	PHY_REG(778, 23) /* Late Collision Count */
131
+#define HV_LATECOL_LOWER	PHY_REG(778, 24)
132
+#define HV_COLC_UPPER		PHY_REG(778, 25) /* Collision Count */
133
+#define HV_COLC_LOWER		PHY_REG(778, 26)
134
+#define HV_DC_UPPER		PHY_REG(778, 27) /* Defer Count */
135
+#define HV_DC_LOWER		PHY_REG(778, 28)
136
+#define HV_TNCRS_UPPER		PHY_REG(778, 29) /* Transmit with no CRS */
137
+#define HV_TNCRS_LOWER		PHY_REG(778, 30)
138
+
139
+#define E1000_FCRTV_PCH     0x05F40 /* PCH Flow Control Refresh Timer Value */
140
+
141
+#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
142
+#define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
143
+
144
+/* SMBus Address Phy Register */
145
+#define HV_SMB_ADDR            PHY_REG(768, 26)
146
+#define HV_SMB_ADDR_PEC_EN     0x0200
147
+#define HV_SMB_ADDR_VALID      0x0080
148
+
149
+/* Strapping Option Register - RO */
150
+#define E1000_STRAP                     0x0000C
151
+#define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
152
+#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
153
+
154
+/* OEM Bits Phy Register */
155
+#define HV_OEM_BITS            PHY_REG(768, 25)
156
+#define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
157
+#define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
158
+#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
159
+
160
+#define LCD_CFG_PHY_ADDR_BIT   0x0020 /* Phy address bit from LCD Config word */
161
+
162
+#define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
163
+
164
+/*
165
+ * Additional interrupts need to be handled for ICH family:
166
+ *  DSW = The FW changed the status of the DISSW bit in FWSM
167
+ *  PHYINT = The LAN connected device generates an interrupt
168
+ *  EPRST = Manageability reset event
169
+ */
170
+#define IMS_ICH_ENABLE_MASK (\
171
+    E1000_IMS_DSW   | \
172
+    E1000_IMS_PHYINT | \
173
+    E1000_IMS_EPRST)
174
+
175
+/* Additional interrupt register bit definitions */
176
+#define E1000_ICR_LSECPNC       0x00004000          /* PN threshold - client */
177
+#define E1000_IMS_LSECPNC       E1000_ICR_LSECPNC   /* PN threshold - client */
178
+#define E1000_ICS_LSECPNC       E1000_ICR_LSECPNC   /* PN threshold - client */
179
+
180
+/* Security Processing bit Indication */
181
+#define E1000_RXDEXT_LINKSEC_STATUS_LSECH       0x01000000
182
+#define E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK     0x60000000
183
+#define E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH  0x20000000
184
+#define E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR 0x40000000
185
+#define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG      0x60000000
186
+
187
+
188
+void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
189
+                                                 bool state);
190
+void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
191
+void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
192
+void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw);
193
+s32 e1000e_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
194
+s32 e1000e_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_config);
195
+
196
+#endif

+ 1883
- 0
src/drivers/net/e1000e/e1000e_mac.c
Datei-Diff unterdrückt, da er zu groß ist
Datei anzeigen


+ 79
- 0
src/drivers/net/e1000e/e1000e_mac.h Datei anzeigen

@@ -0,0 +1,79 @@
1
+/*******************************************************************************
2
+
3
+  Intel PRO/1000 Linux driver
4
+  Copyright(c) 1999 - 2009 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  Linux NICS <linux.nics@intel.com>
24
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
+
27
+*******************************************************************************/
28
+
29
+FILE_LICENCE ( GPL2_OR_LATER );
30
+
31
+#ifndef _E1000E_MAC_H_
32
+#define _E1000E_MAC_H_
33
+
34
+/*
35
+ * Functions that should not be called directly from drivers but can be used
36
+ * by other files in this 'shared code'
37
+ */
38
+void e1000e_init_mac_ops_generic(struct e1000_hw *hw);
39
+s32  e1000e_blink_led(struct e1000_hw *hw);
40
+s32  e1000e_check_for_copper_link(struct e1000_hw *hw);
41
+s32  e1000e_check_for_fiber_link(struct e1000_hw *hw);
42
+s32  e1000e_check_for_serdes_link(struct e1000_hw *hw);
43
+s32  e1000e_cleanup_led_generic(struct e1000_hw *hw);
44
+s32  e1000e_config_fc_after_link_up(struct e1000_hw *hw);
45
+s32  e1000e_disable_pcie_master(struct e1000_hw *hw);
46
+s32  e1000e_force_mac_fc(struct e1000_hw *hw);
47
+s32  e1000e_get_auto_rd_done(struct e1000_hw *hw);
48
+s32  e1000e_get_bus_info_pcie(struct e1000_hw *hw);
49
+void e1000e_set_lan_id_single_port(struct e1000_hw *hw);
50
+s32  e1000e_get_hw_semaphore(struct e1000_hw *hw);
51
+s32  e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
52
+                                               u16 *duplex);
53
+s32  e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw,
54
+                                                     u16 *speed, u16 *duplex);
55
+s32  e1000e_id_led_init(struct e1000_hw *hw);
56
+s32  e1000e_led_on_generic(struct e1000_hw *hw);
57
+s32  e1000e_led_off_generic(struct e1000_hw *hw);
58
+void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
59
+	                               u8 *mc_addr_list, u32 mc_addr_count);
60
+s32  e1000e_set_fc_watermarks(struct e1000_hw *hw);
61
+s32  e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
62
+s32  e1000e_setup_led_generic(struct e1000_hw *hw);
63
+s32  e1000e_setup_link(struct e1000_hw *hw);
64
+
65
+void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
66
+void e1000e_clear_vfta_generic(struct e1000_hw *hw);
67
+void e1000e_config_collision_dist(struct e1000_hw *hw);
68
+void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
69
+void e1000e_mta_set_generic(struct e1000_hw *hw, u32 hash_value);
70
+void e1000e_pcix_mmrbc_workaround_generic(struct e1000_hw *hw);
71
+void e1000e_put_hw_semaphore(struct e1000_hw *hw);
72
+void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
73
+s32  e1000e_check_alt_mac_addr_generic(struct e1000_hw *hw);
74
+void e1000e_reset_adaptive(struct e1000_hw *hw);
75
+void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
76
+void e1000e_update_adaptive(struct e1000_hw *hw);
77
+void e1000e_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
78
+
79
+#endif

+ 1268
- 0
src/drivers/net/e1000e/e1000e_main.c
Datei-Diff unterdrückt, da er zu groß ist
Datei anzeigen


+ 372
- 0
src/drivers/net/e1000e/e1000e_manage.c Datei anzeigen

@@ -0,0 +1,372 @@
1
+/*******************************************************************************
2
+
3
+  Intel PRO/1000 Linux driver
4
+  Copyright(c) 1999 - 2009 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  Linux NICS <linux.nics@intel.com>
24
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
+
27
+*******************************************************************************/
28
+
29
+FILE_LICENCE ( GPL2_OR_LATER );
30
+
31
+#if 0
32
+
33
+#include "e1000e.h"
34
+
35
+static u8 e1000e_calculate_checksum(u8 *buffer, u32 length);
36
+
37
+/**
38
+ *  e1000e_calculate_checksum - Calculate checksum for buffer
39
+ *  @buffer: pointer to EEPROM
40
+ *  @length: size of EEPROM to calculate a checksum for
41
+ *
42
+ *  Calculates the checksum for some buffer on a specified length.  The
43
+ *  checksum calculated is returned.
44
+ **/
45
+static u8 e1000e_calculate_checksum(u8 *buffer, u32 length)
46
+{
47
+	u32 i;
48
+	u8  sum = 0;
49
+
50
+	if (!buffer)
51
+		return 0;
52
+	for (i = 0; i < length; i++)
53
+		sum += buffer[i];
54
+
55
+	return (u8) (0 - sum);
56
+}
57
+
58
+/**
59
+ *  e1000e_mng_enable_host_if_generic - Checks host interface is enabled
60
+ *  @hw: pointer to the HW structure
61
+ *
62
+ *  Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
63
+ *
64
+ *  This function checks whether the HOST IF is enabled for command operation
65
+ *  and also checks whether the previous command is completed.  It busy waits
66
+ *  in case of previous command is not completed.
67
+ **/
68
+s32 e1000e_mng_enable_host_if_generic(struct e1000_hw *hw)
69
+{
70
+	u32 hicr;
71
+	s32 ret_val = E1000_SUCCESS;
72
+	u8  i;
73
+
74
+	/* Check that the host interface is enabled. */
75
+	hicr = er32(HICR);
76
+	if ((hicr & E1000_HICR_EN) == 0) {
77
+		e_dbg("E1000_HOST_EN bit disabled.\n");
78
+		ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
79
+		goto out;
80
+	}
81
+	/* check the previous command is completed */
82
+	for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
83
+		hicr = er32(HICR);
84
+		if (!(hicr & E1000_HICR_C))
85
+			break;
86
+		mdelay(1);
87
+	}
88
+
89
+	if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
90
+		e_dbg("Previous command timeout failed .\n");
91
+		ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
92
+		goto out;
93
+	}
94
+
95
+out:
96
+	return ret_val;
97
+}
98
+
99
+/**
100
+ *  e1000e_check_mng_mode_generic - Generic check management mode
101
+ *  @hw: pointer to the HW structure
102
+ *
103
+ *  Reads the firmware semaphore register and returns true (>0) if
104
+ *  manageability is enabled, else false (0).
105
+ **/
106
+bool e1000e_check_mng_mode_generic(struct e1000_hw *hw)
107
+{
108
+	u32 fwsm;
109
+
110
+	fwsm = er32(FWSM);
111
+	return (fwsm & E1000_FWSM_MODE_MASK) ==
112
+	        (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
113
+}
114
+
115
+/**
116
+ *  e1000e_enable_tx_pkt_filtering - Enable packet filtering on TX
117
+ *  @hw: pointer to the HW structure
118
+ *
119
+ *  Enables packet filtering on transmit packets if manageability is enabled
120
+ *  and host interface is enabled.
121
+ **/
122
+bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
123
+{
124
+	struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
125
+	u32 *buffer = (u32 *)&hw->mng_cookie;
126
+	u32 offset;
127
+	s32 ret_val, hdr_csum, csum;
128
+	u8 i, len;
129
+	bool tx_filter = true;
130
+
131
+	/* No manageability, no filtering */
132
+	if (!hw->mac.ops.check_mng_mode(hw)) {
133
+		tx_filter = false;
134
+		goto out;
135
+	}
136
+
137
+	/*
138
+	 * If we can't read from the host interface for whatever
139
+	 * reason, disable filtering.
140
+	 */
141
+	ret_val = hw->mac.ops.mng_enable_host_if(hw);
142
+	if (ret_val != E1000_SUCCESS) {
143
+		tx_filter = false;
144
+		goto out;
145
+	}
146
+
147
+	/* Read in the header.  Length and offset are in dwords. */
148
+	len    = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
149
+	offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
150
+	for (i = 0; i < len; i++) {
151
+		*(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw,
152
+		                                           E1000_HOST_IF,
153
+		                                           offset + i);
154
+	}
155
+	hdr_csum = hdr->checksum;
156
+	hdr->checksum = 0;
157
+	csum = e1000e_calculate_checksum((u8 *)hdr,
158
+	                                E1000_MNG_DHCP_COOKIE_LENGTH);
159
+	/*
160
+	 * If either the checksums or signature don't match, then
161
+	 * the cookie area isn't considered valid, in which case we
162
+	 * take the safe route of assuming Tx filtering is enabled.
163
+	 */
164
+	if (hdr_csum != csum)
165
+		goto out;
166
+	if (hdr->signature != E1000_IAMT_SIGNATURE)
167
+		goto out;
168
+
169
+	/* Cookie area is valid, make the final check for filtering. */
170
+	if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))
171
+		tx_filter = false;
172
+
173
+out:
174
+	hw->mac.tx_pkt_filtering = tx_filter;
175
+	return tx_filter;
176
+}
177
+
178
+/**
179
+ *  e1000e_mng_write_dhcp_info - Writes DHCP info to host interface
180
+ *  @hw: pointer to the HW structure
181
+ *  @buffer: pointer to the host interface
182
+ *  @length: size of the buffer
183
+ *
184
+ *  Writes the DHCP information to the host interface.
185
+ **/
186
+s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer,
187
+                                      u16 length)
188
+{
189
+	struct e1000_host_mng_command_header hdr;
190
+	s32 ret_val;
191
+	u32 hicr;
192
+
193
+	hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
194
+	hdr.command_length = length;
195
+	hdr.reserved1 = 0;
196
+	hdr.reserved2 = 0;
197
+	hdr.checksum = 0;
198
+
199
+	/* Enable the host interface */
200
+	ret_val = hw->mac.ops.mng_enable_host_if(hw);
201
+	if (ret_val)
202
+		goto out;
203
+
204
+	/* Populate the host interface with the contents of "buffer". */
205
+	ret_val = hw->mac.ops.mng_host_if_write(hw, buffer, length,
206
+	                                  sizeof(hdr), &(hdr.checksum));
207
+	if (ret_val)
208
+		goto out;
209
+
210
+	/* Write the manageability command header */
211
+	ret_val = hw->mac.ops.mng_write_cmd_header(hw, &hdr);
212
+	if (ret_val)
213
+		goto out;
214
+
215
+	/* Tell the ARC a new command is pending. */
216
+	hicr = er32(HICR);
217
+	ew32(HICR, hicr | E1000_HICR_C);
218
+
219
+out:
220
+	return ret_val;
221
+}
222
+
223
+/**
224
+ *  e1000e_mng_write_cmd_header_generic - Writes manageability command header
225
+ *  @hw: pointer to the HW structure
226
+ *  @hdr: pointer to the host interface command header
227
+ *
228
+ *  Writes the command header after does the checksum calculation.
229
+ **/
230
+s32 e1000e_mng_write_cmd_header_generic(struct e1000_hw *hw,
231
+                                    struct e1000_host_mng_command_header *hdr)
232
+{
233
+	u16 i, length = sizeof(struct e1000_host_mng_command_header);
234
+
235
+	/* Write the whole command header structure with new checksum. */
236
+
237
+	hdr->checksum = e1000e_calculate_checksum((u8 *)hdr, length);
238
+
239
+	length >>= 2;
240
+	/* Write the relevant command block into the ram area. */
241
+	for (i = 0; i < length; i++) {
242
+		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
243
+		                            *((u32 *) hdr + i));
244
+		e1e_flush();
245
+	}
246
+
247
+	return E1000_SUCCESS;
248
+}
249
+
250
+/**
251
+ *  e1000e_mng_host_if_write_generic - Write to the manageability host interface
252
+ *  @hw: pointer to the HW structure
253
+ *  @buffer: pointer to the host interface buffer
254
+ *  @length: size of the buffer
255
+ *  @offset: location in the buffer to write to
256
+ *  @sum: sum of the data (not checksum)
257
+ *
258
+ *  This function writes the buffer content at the offset given on the host if.
259
+ *  It also does alignment considerations to do the writes in most efficient
260
+ *  way.  Also fills up the sum of the buffer in *buffer parameter.
261
+ **/
262
+s32 e1000e_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
263
+                                    u16 length, u16 offset, u8 *sum)
264
+{
265
+	u8 *tmp;
266
+	u8 *bufptr = buffer;
267
+	u32 data = 0;
268
+	s32 ret_val = E1000_SUCCESS;
269
+	u16 remaining, i, j, prev_bytes;
270
+
271
+	/* sum = only sum of the data and it is not checksum */
272
+
273
+	if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
274
+		ret_val = -E1000_ERR_PARAM;
275
+		goto out;
276
+	}
277
+
278
+	tmp = (u8 *)&data;
279
+	prev_bytes = offset & 0x3;
280
+	offset >>= 2;
281
+
282
+	if (prev_bytes) {
283
+		data = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset);
284
+		for (j = prev_bytes; j < sizeof(u32); j++) {
285
+			*(tmp + j) = *bufptr++;
286
+			*sum += *(tmp + j);
287
+		}
288
+		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset, data);
289
+		length -= j - prev_bytes;
290
+		offset++;
291
+	}
292
+
293
+	remaining = length & 0x3;
294
+	length -= remaining;
295
+
296
+	/* Calculate length in DWORDs */
297
+	length >>= 2;
298
+
299
+	/*
300
+	 * The device driver writes the relevant command block into the
301
+	 * ram area.
302
+	 */
303
+	for (i = 0; i < length; i++) {
304
+		for (j = 0; j < sizeof(u32); j++) {
305
+			*(tmp + j) = *bufptr++;
306
+			*sum += *(tmp + j);
307
+		}
308
+
309
+		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
310
+		                            data);
311
+	}
312
+	if (remaining) {
313
+		for (j = 0; j < sizeof(u32); j++) {
314
+			if (j < remaining)
315
+				*(tmp + j) = *bufptr++;
316
+			else
317
+				*(tmp + j) = 0;
318
+
319
+			*sum += *(tmp + j);
320
+		}
321
+		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i, data);
322
+	}
323
+
324
+out:
325
+	return ret_val;
326
+}
327
+
328
+/**
329
+ *  e1000e_enable_mng_pass_thru - Enable processing of ARP's
330
+ *  @hw: pointer to the HW structure
331
+ *
332
+ *  Verifies the hardware needs to allow ARPs to be processed by the host.
333
+ **/
334
+bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw)
335
+{
336
+	u32 manc;
337
+	u32 fwsm, factps;
338
+	bool ret_val = false;
339
+
340
+	if (!hw->mac.asf_firmware_present)
341
+		goto out;
342
+
343
+	manc = er32(MANC);
344
+
345
+	if (!(manc & E1000_MANC_RCV_TCO_EN) ||
346
+	    !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
347
+		goto out;
348
+
349
+	if (hw->mac.arc_subsystem_valid) {
350
+		fwsm = er32(FWSM);
351
+		factps = er32(FACTPS);
352
+
353
+		if (!(factps & E1000_FACTPS_MNGCG) &&
354
+		    ((fwsm & E1000_FWSM_MODE_MASK) ==
355
+		     (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
356
+			ret_val = true;
357
+			goto out;
358
+		}
359
+	} else {
360
+		if ((manc & E1000_MANC_SMBUS_EN) &&
361
+		    !(manc & E1000_MANC_ASF_EN)) {
362
+			ret_val = true;
363
+			goto out;
364
+		}
365
+	}
366
+
367
+out:
368
+	return ret_val;
369
+}
370
+
371
+#endif
372
+

+ 86
- 0
src/drivers/net/e1000e/e1000e_manage.h Datei anzeigen

@@ -0,0 +1,86 @@
1
+/*******************************************************************************
2
+
3
+  Intel PRO/1000 Linux driver
4
+  Copyright(c) 1999 - 2009 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  Linux NICS <linux.nics@intel.com>
24
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
+
27
+*******************************************************************************/
28
+
29
+FILE_LICENCE ( GPL2_OR_LATER );
30
+
31
+#ifndef _E1000E_MANAGE_H_
32
+#define _E1000E_MANAGE_H_
33
+
34
+bool e1000e_check_mng_mode_generic(struct e1000_hw *hw);
35
+bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
36
+s32  e1000e_mng_enable_host_if_generic(struct e1000_hw *hw);
37
+s32  e1000e_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
38
+                                     u16 length, u16 offset, u8 *sum);
39
+s32  e1000e_mng_write_cmd_header_generic(struct e1000_hw *hw,
40
+                                    struct e1000_host_mng_command_header *hdr);
41
+#if 0
42
+s32  e1000e_mng_write_dhcp_info(struct e1000_hw *hw,
43
+                                       u8 *buffer, u16 length);
44
+#endif
45
+bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
46
+
47
+enum e1000_mng_mode {
48
+	e1000_mng_mode_none = 0,
49
+	e1000_mng_mode_asf,
50
+	e1000_mng_mode_pt,
51
+	e1000_mng_mode_ipmi,
52
+	e1000_mng_mode_host_if_only
53
+};
54
+
55
+#define E1000_FACTPS_MNGCG    0x20000000
56
+
57
+#define E1000_FWSM_MODE_MASK  0xE
58
+#define E1000_FWSM_MODE_SHIFT 1
59
+
60
+#define E1000_MNG_IAMT_MODE                  0x3
61
+#define E1000_MNG_DHCP_COOKIE_LENGTH         0x10
62
+#define E1000_MNG_DHCP_COOKIE_OFFSET         0x6F0
63
+#define E1000_MNG_DHCP_COMMAND_TIMEOUT       10
64
+#define E1000_MNG_DHCP_TX_PAYLOAD_CMD        64
65
+#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
66
+#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN    0x2
67
+
68
+#define E1000_VFTA_ENTRY_SHIFT               5
69
+#define E1000_VFTA_ENTRY_MASK                0x7F
70
+#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK      0x1F
71
+
72
+#define E1000_HI_MAX_BLOCK_BYTE_LENGTH       1792 /* Num of bytes in range */
73
+#define E1000_HI_MAX_BLOCK_DWORD_LENGTH      448 /* Num of dwords in range */
74
+#define E1000_HI_COMMAND_TIMEOUT             500 /* Process HI command limit */
75
+
76
+#define E1000_HICR_EN              0x01  /* Enable bit - RO */
77
+/* Driver sets this bit when done to put command in RAM */
78
+#define E1000_HICR_C               0x02
79
+#define E1000_HICR_SV              0x04  /* Status Validity */
80
+#define E1000_HICR_FW_RESET_ENABLE 0x40
81
+#define E1000_HICR_FW_RESET        0x80
82
+
83
+/* Intel(R) Active Management Technology signature */
84
+#define E1000_IAMT_SIGNATURE  0x544D4149
85
+
86
+#endif

+ 596
- 0
src/drivers/net/e1000e/e1000e_nvm.c Datei anzeigen

@@ -0,0 +1,596 @@
1
+/*******************************************************************************
2
+
3
+  Intel PRO/1000 Linux driver
4
+  Copyright(c) 1999 - 2009 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  Linux NICS <linux.nics@intel.com>
24
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
+
27
+*******************************************************************************/
28
+
29
+FILE_LICENCE ( GPL2_OR_LATER );
30
+
31
+#include "e1000e.h"
32
+
33
+static void e1000e_stop_nvm(struct e1000_hw *hw);
34
+static void e1000e_reload_nvm(struct e1000_hw *hw);
35
+
36
+/**
37
+ *  e1000e_init_nvm_ops_generic - Initialize NVM function pointers
38
+ *  @hw: pointer to the HW structure
39
+ *
40
+ *  Setups up the function pointers to no-op functions
41
+ **/
42
+void e1000e_init_nvm_ops_generic(struct e1000_hw *hw)
43
+{
44
+	struct e1000_nvm_info *nvm = &hw->nvm;
45
+	/* Initialize function pointers */
46
+	nvm->ops.reload = e1000e_reload_nvm;
47
+}
48
+
49
+/**
50
+ *  e1000e_raise_eec_clk - Raise EEPROM clock
51
+ *  @hw: pointer to the HW structure
52
+ *  @eecd: pointer to the EEPROM
53
+ *
54
+ *  Enable/Raise the EEPROM clock bit.
55
+ **/
56
+static void e1000e_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
57
+{
58
+	*eecd = *eecd | E1000_EECD_SK;
59
+	ew32(EECD, *eecd);
60
+	e1e_flush();
61
+	udelay(hw->nvm.delay_usec);
62
+}
63
+
64
+/**
65
+ *  e1000e_lower_eec_clk - Lower EEPROM clock
66
+ *  @hw: pointer to the HW structure
67
+ *  @eecd: pointer to the EEPROM
68
+ *
69
+ *  Clear/Lower the EEPROM clock bit.
70
+ **/
71
+static void e1000e_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
72
+{
73
+	*eecd = *eecd & ~E1000_EECD_SK;
74
+	ew32(EECD, *eecd);
75
+	e1e_flush();
76
+	udelay(hw->nvm.delay_usec);
77
+}
78
+
79
+/**
80
+ *  e1000e_shift_out_eec_bits - Shift data bits our to the EEPROM
81
+ *  @hw: pointer to the HW structure
82
+ *  @data: data to send to the EEPROM
83
+ *  @count: number of bits to shift out
84
+ *
85
+ *  We need to shift 'count' bits out to the EEPROM.  So, the value in the
86
+ *  "data" parameter will be shifted out to the EEPROM one bit at a time.
87
+ *  In order to do this, "data" must be broken down into bits.
88
+ **/
89
+static void e1000e_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
90
+{
91
+	struct e1000_nvm_info *nvm = &hw->nvm;
92
+	u32 eecd = er32(EECD);
93
+	u32 mask;
94
+
95
+	mask = 0x01 << (count - 1);
96
+	if (nvm->type == e1000_nvm_eeprom_spi)
97
+		eecd |= E1000_EECD_DO;
98
+
99
+	do {
100
+		eecd &= ~E1000_EECD_DI;
101
+
102
+		if (data & mask)
103
+			eecd |= E1000_EECD_DI;
104
+
105
+		ew32(EECD, eecd);
106
+		e1e_flush();
107
+
108
+		udelay(nvm->delay_usec);
109
+
110
+		e1000e_raise_eec_clk(hw, &eecd);
111
+		e1000e_lower_eec_clk(hw, &eecd);
112
+
113
+		mask >>= 1;
114
+	} while (mask);
115
+
116
+	eecd &= ~E1000_EECD_DI;
117
+	ew32(EECD, eecd);
118
+}
119
+
120
+/**
121
+ *  e1000e_shift_in_eec_bits - Shift data bits in from the EEPROM
122
+ *  @hw: pointer to the HW structure
123
+ *  @count: number of bits to shift in
124
+ *
125
+ *  In order to read a register from the EEPROM, we need to shift 'count' bits
126
+ *  in from the EEPROM.  Bits are "shifted in" by raising the clock input to
127
+ *  the EEPROM (setting the SK bit), and then reading the value of the data out
128
+ *  "DO" bit.  During this "shifting in" process the data in "DI" bit should
129
+ *  always be clear.
130
+ **/
131
+static u16 e1000e_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
132
+{
133
+	u32 eecd;
134
+	u32 i;
135
+	u16 data;
136
+
137
+	eecd = er32(EECD);
138
+	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
139
+	data = 0;
140
+
141
+	for (i = 0; i < count; i++) {
142
+		data <<= 1;
143
+		e1000e_raise_eec_clk(hw, &eecd);
144
+
145
+		eecd = er32(EECD);
146
+
147
+		eecd &= ~E1000_EECD_DI;
148
+		if (eecd & E1000_EECD_DO)
149
+			data |= 1;
150
+
151
+		e1000e_lower_eec_clk(hw, &eecd);
152
+	}
153
+
154
+	return data;
155
+}
156
+
157
+/**
158
+ *  e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
159
+ *  @hw: pointer to the HW structure
160
+ *  @ee_reg: EEPROM flag for polling
161
+ *
162
+ *  Polls the EEPROM status bit for either read or write completion based
163
+ *  upon the value of 'ee_reg'.
164
+ **/
165
+s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
166
+{
167
+	u32 attempts = 100000;
168
+	u32 i, reg = 0;
169
+	s32 ret_val = -E1000_ERR_NVM;
170
+
171
+	for (i = 0; i < attempts; i++) {
172
+		if (ee_reg == E1000_NVM_POLL_READ)
173
+			reg = er32(EERD);
174
+		else
175
+			reg = er32(EEWR);
176
+
177
+		if (reg & E1000_NVM_RW_REG_DONE) {
178
+			ret_val = E1000_SUCCESS;
179
+			break;
180
+		}
181
+
182
+		udelay(5);
183
+	}
184
+
185
+	return ret_val;
186
+}
187
+
188
+/**
189
+ *  e1000e_acquire_nvm - Generic request for access to EEPROM
190
+ *  @hw: pointer to the HW structure
191
+ *
192
+ *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
193
+ *  Return successful if access grant bit set, else clear the request for
194
+ *  EEPROM access and return -E1000_ERR_NVM (-1).
195
+ **/
196
+s32 e1000e_acquire_nvm(struct e1000_hw *hw)
197
+{
198
+	u32 eecd = er32(EECD);
199
+	s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
200
+	s32 ret_val = E1000_SUCCESS;
201
+
202
+	ew32(EECD, eecd | E1000_EECD_REQ);
203
+	eecd = er32(EECD);
204
+	while (timeout) {
205
+		if (eecd & E1000_EECD_GNT)
206
+			break;
207
+		udelay(5);
208
+		eecd = er32(EECD);
209
+		timeout--;
210
+	}
211
+
212
+	if (!timeout) {
213
+		eecd &= ~E1000_EECD_REQ;
214
+		ew32(EECD, eecd);
215
+		e_dbg("Could not acquire NVM grant\n");
216
+		ret_val = -E1000_ERR_NVM;
217
+	}
218
+
219
+	return ret_val;
220
+}
221
+
222
+/**
223
+ *  e1000e_standby_nvm - Return EEPROM to standby state
224
+ *  @hw: pointer to the HW structure
225
+ *
226
+ *  Return the EEPROM to a standby state.
227
+ **/
228
+static void e1000e_standby_nvm(struct e1000_hw *hw)
229
+{
230
+	struct e1000_nvm_info *nvm = &hw->nvm;
231
+	u32 eecd = er32(EECD);
232
+
233
+	if (nvm->type == e1000_nvm_eeprom_spi) {
234
+		/* Toggle CS to flush commands */
235
+		eecd |= E1000_EECD_CS;
236
+		ew32(EECD, eecd);
237
+		e1e_flush();
238
+		udelay(nvm->delay_usec);
239
+		eecd &= ~E1000_EECD_CS;
240
+		ew32(EECD, eecd);
241
+		e1e_flush();
242
+		udelay(nvm->delay_usec);
243
+	}
244
+}
245
+
246
+/**
247
+ *  e1000e_stop_nvm - Terminate EEPROM command
248
+ *  @hw: pointer to the HW structure
249
+ *
250
+ *  Terminates the current command by inverting the EEPROM's chip select pin.
251
+ **/
252
+static void e1000e_stop_nvm(struct e1000_hw *hw)
253
+{
254
+	u32 eecd;
255
+
256
+	eecd = er32(EECD);
257
+	if (hw->nvm.type == e1000_nvm_eeprom_spi) {
258
+		/* Pull CS high */
259
+		eecd |= E1000_EECD_CS;
260
+		e1000e_lower_eec_clk(hw, &eecd);
261
+	}
262
+}
263
+
264
+/**
265
+ *  e1000e_release_nvm - Release exclusive access to EEPROM
266
+ *  @hw: pointer to the HW structure
267
+ *
268
+ *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
269
+ **/
270
+void e1000e_release_nvm(struct e1000_hw *hw)
271
+{
272
+	u32 eecd;
273
+
274
+	e1000e_stop_nvm(hw);
275
+
276
+	eecd = er32(EECD);
277
+	eecd &= ~E1000_EECD_REQ;
278
+	ew32(EECD, eecd);
279
+}
280
+
281
+/**
282
+ *  e1000e_ready_nvm_eeprom - Prepares EEPROM for read/write
283
+ *  @hw: pointer to the HW structure
284
+ *
285
+ *  Setups the EEPROM for reading and writing.
286
+ **/
287
+static s32 e1000e_ready_nvm_eeprom(struct e1000_hw *hw)
288
+{
289
+	struct e1000_nvm_info *nvm = &hw->nvm;
290
+	u32 eecd = er32(EECD);
291
+	s32 ret_val = E1000_SUCCESS;
292
+	u16 timeout = 0;
293
+	u8 spi_stat_reg;
294
+
295
+	if (nvm->type == e1000_nvm_eeprom_spi) {
296
+		/* Clear SK and CS */
297
+		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
298
+		ew32(EECD, eecd);
299
+		udelay(1);
300
+		timeout = NVM_MAX_RETRY_SPI;
301
+
302
+		/*
303
+		 * Read "Status Register" repeatedly until the LSB is cleared.
304
+		 * The EEPROM will signal that the command has been completed
305
+		 * by clearing bit 0 of the internal status register.  If it's
306
+		 * not cleared within 'timeout', then error out.
307
+		 */
308
+		while (timeout) {
309
+			e1000e_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
310
+			                         hw->nvm.opcode_bits);
311
+			spi_stat_reg = (u8)e1000e_shift_in_eec_bits(hw, 8);
312
+			if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
313
+				break;
314
+
315
+			udelay(5);
316
+			e1000e_standby_nvm(hw);
317
+			timeout--;
318
+		}
319
+
320
+		if (!timeout) {
321
+			e_dbg("SPI NVM Status error\n");
322
+			ret_val = -E1000_ERR_NVM;
323
+			goto out;
324
+		}
325
+	}
326
+
327
+out:
328
+	return ret_val;
329
+}
330
+
331
+/**
332
+ *  e1000e_read_nvm_eerd - Reads EEPROM using EERD register
333
+ *  @hw: pointer to the HW structure
334
+ *  @offset: offset of word in the EEPROM to read
335
+ *  @words: number of words to read
336
+ *  @data: word read from the EEPROM
337
+ *
338
+ *  Reads a 16 bit word from the EEPROM using the EERD register.
339
+ **/
340
+s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
341
+{
342
+	struct e1000_nvm_info *nvm = &hw->nvm;
343
+	u32 i, eerd = 0;
344
+	s32 ret_val = E1000_SUCCESS;
345
+
346
+	/*
347
+	 * A check for invalid values:  offset too large, too many words,
348
+	 * too many words for the offset, and not enough words.
349
+	 */
350
+	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
351
+	    (words == 0)) {
352
+		e_dbg("nvm parameter(s) out of bounds\n");
353
+		ret_val = -E1000_ERR_NVM;
354
+		goto out;
355
+	}
356
+
357
+	for (i = 0; i < words; i++) {
358
+		eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
359
+		       E1000_NVM_RW_REG_START;
360
+
361
+		ew32(EERD, eerd);
362
+		ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
363
+		if (ret_val)
364
+			break;
365
+
366
+		data[i] = (er32(EERD) >>
367
+		           E1000_NVM_RW_REG_DATA);
368
+	}
369
+
370
+out:
371
+	return ret_val;
372
+}
373
+
374
+/**
375
+ *  e1000e_write_nvm_spi - Write to EEPROM using SPI
376
+ *  @hw: pointer to the HW structure
377
+ *  @offset: offset within the EEPROM to be written to
378
+ *  @words: number of words to write
379
+ *  @data: 16 bit word(s) to be written to the EEPROM
380
+ *
381
+ *  Writes data to EEPROM at offset using SPI interface.
382
+ *
383
+ *  If e1000e_update_nvm_checksum is not called after this function , the
384
+ *  EEPROM will most likely contain an invalid checksum.
385
+ **/
386
+s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
387
+{
388
+	struct e1000_nvm_info *nvm = &hw->nvm;
389
+	s32 ret_val;
390
+	u16 widx = 0;
391
+
392
+	/*
393
+	 * A check for invalid values:  offset too large, too many words,
394
+	 * and not enough words.
395
+	 */
396
+	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
397
+	    (words == 0)) {
398
+		e_dbg("nvm parameter(s) out of bounds\n");
399
+		ret_val = -E1000_ERR_NVM;
400
+		goto out;
401
+	}
402
+
403
+	ret_val = nvm->ops.acquire(hw);
404
+	if (ret_val)
405
+		goto out;
406
+
407
+	while (widx < words) {
408
+		u8 write_opcode = NVM_WRITE_OPCODE_SPI;
409
+
410
+		ret_val = e1000e_ready_nvm_eeprom(hw);
411
+		if (ret_val)
412
+			goto release;
413
+
414
+		e1000e_standby_nvm(hw);
415
+
416
+		/* Send the WRITE ENABLE command (8 bit opcode) */
417
+		e1000e_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
418
+		                         nvm->opcode_bits);
419
+
420
+		e1000e_standby_nvm(hw);
421
+
422
+		/*
423
+		 * Some SPI eeproms use the 8th address bit embedded in the
424
+		 * opcode
425
+		 */
426
+		if ((nvm->address_bits == 8) && (offset >= 128))
427
+			write_opcode |= NVM_A8_OPCODE_SPI;
428
+
429
+		/* Send the Write command (8-bit opcode + addr) */
430
+		e1000e_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
431
+		e1000e_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
432
+		                         nvm->address_bits);
433
+
434
+		/* Loop to allow for up to whole page write of eeprom */
435
+		while (widx < words) {
436
+			u16 word_out = data[widx];
437
+			word_out = (word_out >> 8) | (word_out << 8);
438
+			e1000e_shift_out_eec_bits(hw, word_out, 16);
439
+			widx++;
440
+
441
+			if ((((offset + widx) * 2) % nvm->page_size) == 0) {
442
+				e1000e_standby_nvm(hw);
443
+				break;
444
+			}
445
+		}
446
+	}
447
+
448
+	msleep(10);
449
+release:
450
+	nvm->ops.release(hw);
451
+
452
+out:
453
+	return ret_val;
454
+}
455
+
456
+/**
457
+ *  e1000e_read_pba_num - Read device part number
458
+ *  @hw: pointer to the HW structure
459
+ *  @pba_num: pointer to device part number
460
+ *
461
+ *  Reads the product board assembly (PBA) number from the EEPROM and stores
462
+ *  the value in pba_num.
463
+ **/
464
+s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num)
465
+{
466
+	s32  ret_val;
467
+	u16 nvm_data;
468
+
469
+	ret_val = e1000e_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
470
+	if (ret_val) {
471
+		e_dbg("NVM Read Error\n");
472
+		goto out;
473
+	}
474
+	*pba_num = (u32)(nvm_data << 16);
475
+
476
+	ret_val = e1000e_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
477
+	if (ret_val) {
478
+		e_dbg("NVM Read Error\n");
479
+		goto out;
480
+	}
481
+	*pba_num |= nvm_data;
482
+
483
+out:
484
+	return ret_val;
485
+}
486
+
487
+/**
488
+ *  e1000e_read_mac_addr_generic - Read device MAC address
489
+ *  @hw: pointer to the HW structure
490
+ *
491
+ *  Reads the device MAC address from the EEPROM and stores the value.
492
+ *  Since devices with two ports use the same EEPROM, we increment the
493
+ *  last bit in the MAC address for the second port.
494
+ **/
495
+s32 e1000e_read_mac_addr_generic(struct e1000_hw *hw)
496
+{
497
+	u32 rar_high;
498
+	u32 rar_low;
499
+	u16 i;
500
+
501
+	rar_high = er32(RAH(0));
502
+	rar_low = er32(RAL(0));
503
+
504
+	for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
505
+		hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
506
+
507
+	for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
508
+		hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
509
+
510
+	for (i = 0; i < ETH_ADDR_LEN; i++)
511
+		hw->mac.addr[i] = hw->mac.perm_addr[i];
512
+
513
+	return E1000_SUCCESS;
514
+}
515
+
516
+/**
517
+ *  e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
518
+ *  @hw: pointer to the HW structure
519
+ *
520
+ *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
521
+ *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
522
+ **/
523
+s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
524
+{
525
+	s32 ret_val = E1000_SUCCESS;
526
+	u16 checksum = 0;
527
+	u16 i, nvm_data;
528
+
529
+	for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
530
+		ret_val = e1000e_read_nvm(hw, i, 1, &nvm_data);
531
+		if (ret_val) {
532
+			e_dbg("NVM Read Error\n");
533
+			goto out;
534
+		}
535
+		checksum += nvm_data;
536
+	}
537
+
538
+	if (checksum != (u16) NVM_SUM) {
539
+		e_dbg("NVM Checksum Invalid\n");
540
+		ret_val = -E1000_ERR_NVM;
541
+		goto out;
542
+	}
543
+
544
+out:
545
+	return ret_val;
546
+}
547
+
548
+/**
549
+ *  e1000e_update_nvm_checksum_generic - Update EEPROM checksum
550
+ *  @hw: pointer to the HW structure
551
+ *
552
+ *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
553
+ *  up to the checksum.  Then calculates the EEPROM checksum and writes the
554
+ *  value to the EEPROM.
555
+ **/
556
+s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
557
+{
558
+	s32  ret_val;
559
+	u16 checksum = 0;
560
+	u16 i, nvm_data;
561
+
562
+	for (i = 0; i < NVM_CHECKSUM_REG; i++) {
563
+		ret_val = e1000e_read_nvm(hw, i, 1, &nvm_data);
564
+		if (ret_val) {
565
+			e_dbg("NVM Read Error while updating checksum.\n");
566
+			goto out;
567
+		}
568
+		checksum += nvm_data;
569
+	}
570
+	checksum = (u16) NVM_SUM - checksum;
571
+	ret_val = e1000e_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
572
+	if (ret_val)
573
+		e_dbg("NVM Write Error while updating checksum.\n");
574
+
575
+out:
576
+	return ret_val;
577
+}
578
+
579
+/**
580
+ *  e1000e_reload_nvm - Reloads EEPROM
581
+ *  @hw: pointer to the HW structure
582
+ *
583
+ *  Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
584
+ *  extended control register.
585
+ **/
586
+static void e1000e_reload_nvm(struct e1000_hw *hw)
587
+{
588
+	u32 ctrl_ext;
589
+
590
+	udelay(10);
591
+	ctrl_ext = er32(CTRL_EXT);
592
+	ctrl_ext |= E1000_CTRL_EXT_EE_RST;
593
+	ew32(CTRL_EXT, ctrl_ext);
594
+	e1e_flush();
595
+}
596
+

+ 53
- 0
src/drivers/net/e1000e/e1000e_nvm.h Datei anzeigen

@@ -0,0 +1,53 @@
1
+/*******************************************************************************
2
+
3
+  Intel PRO/1000 Linux driver
4
+  Copyright(c) 1999 - 2009 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  Linux NICS <linux.nics@intel.com>
24
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
+
27
+*******************************************************************************/
28
+
29
+FILE_LICENCE ( GPL2_OR_LATER );
30
+
31
+#ifndef _E1000E_NVM_H_
32
+#define _E1000E_NVM_H_
33
+
34
+void e1000e_init_nvm_ops_generic(struct e1000_hw *hw);
35
+s32  e1000e_acquire_nvm(struct e1000_hw *hw);
36
+
37
+s32  e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
38
+s32  e1000e_read_mac_addr_generic(struct e1000_hw *hw);
39
+s32  e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num);
40
+s32  e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words,
41
+                         u16 *data);
42
+s32  e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
43
+s32  e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
44
+s32  e1000e_write_nvm_eewr(struct e1000_hw *hw, u16 offset,
45
+                          u16 words, u16 *data);
46
+s32  e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words,
47
+                         u16 *data);
48
+s32  e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
49
+void e1000e_release_nvm(struct e1000_hw *hw);
50
+
51
+#define E1000_STM_OPCODE  0xDB00
52
+
53
+#endif

+ 3323
- 0
src/drivers/net/e1000e/e1000e_phy.c
Datei-Diff unterdrückt, da er zu groß ist
Datei anzeigen


+ 261
- 0
src/drivers/net/e1000e/e1000e_phy.h Datei anzeigen

@@ -0,0 +1,261 @@
1
+/*******************************************************************************
2
+
3
+  Intel PRO/1000 Linux driver
4
+  Copyright(c) 1999 - 2009 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  Linux NICS <linux.nics@intel.com>
24
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
+
27
+*******************************************************************************/
28
+
29
+FILE_LICENCE ( GPL2_OR_LATER );
30
+
31
+#ifndef _E1000E_PHY_H_
32
+#define _E1000E_PHY_H_
33
+
34
+void e1000e_init_phy_ops_generic(struct e1000_hw *hw);
35
+s32  e1000e_check_downshift(struct e1000_hw *hw);
36
+s32  e1000e_check_polarity_m88(struct e1000_hw *hw);
37
+s32  e1000e_check_polarity_igp(struct e1000_hw *hw);
38
+s32  e1000e_check_polarity_ife(struct e1000_hw *hw);
39
+s32  e1000e_check_reset_block_generic(struct e1000_hw *hw);
40
+s32  e1000e_copper_link_setup_igp(struct e1000_hw *hw);
41
+s32  e1000e_copper_link_setup_m88(struct e1000_hw *hw);
42
+#if 0
43
+s32  e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
44
+s32  e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
45
+s32  e1000e_phy_force_speed_duplex_ife(struct e1000_hw *hw);
46
+#endif
47
+#if 0
48
+s32  e1000e_get_cable_length_m88(struct e1000_hw *hw);
49
+s32  e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
50
+#endif
51
+s32  e1000e_get_cfg_done(struct e1000_hw *hw);
52
+s32  e1000e_get_phy_id(struct e1000_hw *hw);
53
+s32  e1000e_get_phy_info_igp(struct e1000_hw *hw);
54
+s32  e1000e_get_phy_info_m88(struct e1000_hw *hw);
55
+s32  e1000e_phy_sw_reset(struct e1000_hw *hw);
56
+#if 0
57
+void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
58
+#endif
59
+s32  e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
60
+s32  e1000e_phy_reset_dsp(struct e1000_hw *hw);
61
+s32  e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
62
+s32  e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);
63
+s32  e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
64
+s32  e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);
65
+s32  e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
66
+s32  e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
67
+s32  e1000e_setup_copper_link(struct e1000_hw *hw);
68
+s32  e1000e_wait_autoneg(struct e1000_hw *hw);
69
+s32  e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
70
+s32  e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data);
71
+s32  e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
72
+s32  e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);
73
+s32  e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
74
+s32  e1000e_phy_reset_dsp(struct e1000_hw *hw);
75
+s32  e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
76
+                                u32 usec_interval, bool *success);
77
+s32  e1000e_phy_init_script_igp3(struct e1000_hw *hw);
78
+enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
79
+s32  e1000e_determine_phy_address(struct e1000_hw *hw);
80
+s32  e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
81
+s32  e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
82
+s32  e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
83
+s32  e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
84
+void e1000e_power_up_phy_copper(struct e1000_hw *hw);
85
+void e1000e_power_down_phy_copper(struct e1000_hw *hw);
86
+s32  e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
87
+s32  e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
88
+s32  e1000e_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
89
+s32  e1000e_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data);
90
+s32  e1000e_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
91
+s32  e1000e_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data);
92
+s32  e1000e_set_mdio_slow_mode_hv(struct e1000_hw *hw, bool slow);
93
+s32  e1000e_link_stall_workaround_hv(struct e1000_hw *hw);
94
+s32  e1000e_copper_link_setup_82577(struct e1000_hw *hw);
95
+s32  e1000e_check_polarity_82577(struct e1000_hw *hw);
96
+s32  e1000e_get_phy_info_82577(struct e1000_hw *hw);
97
+#if 0
98
+s32  e1000e_phy_force_speed_duplex_82577(struct e1000_hw *hw);
99
+#endif
100
+#if 0
101
+s32  e1000e_get_cable_length_82577(struct e1000_hw *hw);
102
+#endif
103
+
104
+#define E1000_MAX_PHY_ADDR                4
105
+
106
+/* IGP01E1000 Specific Registers */
107
+#define IGP01E1000_PHY_PORT_CONFIG        0x10 /* Port Config */
108
+#define IGP01E1000_PHY_PORT_STATUS        0x11 /* Status */
109
+#define IGP01E1000_PHY_PORT_CTRL          0x12 /* Control */
110
+#define IGP01E1000_PHY_LINK_HEALTH        0x13 /* PHY Link Health */
111
+#define IGP01E1000_GMII_FIFO              0x14 /* GMII FIFO */
112
+#define IGP01E1000_PHY_CHANNEL_QUALITY    0x15 /* PHY Channel Quality */
113
+#define IGP02E1000_PHY_POWER_MGMT         0x19 /* Power Management */
114
+#define IGP01E1000_PHY_PAGE_SELECT        0x1F /* Page Select */
115
+#define BM_PHY_PAGE_SELECT                22   /* Page Select for BM */
116
+#define IGP_PAGE_SHIFT                    5
117
+#define PHY_REG_MASK                      0x1F
118
+
119
+/* BM/HV Specific Registers */
120
+#define BM_PORT_CTRL_PAGE                 769
121
+#define BM_PCIE_PAGE                      770
122
+#define BM_WUC_PAGE                       800
123
+#define BM_WUC_ADDRESS_OPCODE             0x11
124
+#define BM_WUC_DATA_OPCODE                0x12
125
+#define BM_WUC_ENABLE_PAGE                BM_PORT_CTRL_PAGE
126
+#define BM_WUC_ENABLE_REG                 17
127
+#define BM_WUC_ENABLE_BIT                 (1 << 2)
128
+#define BM_WUC_HOST_WU_BIT                (1 << 4)
129
+
130
+#define PHY_UPPER_SHIFT                   21
131
+#define BM_PHY_REG(page, reg) \
132
+	(((reg) & MAX_PHY_REG_ADDRESS) |\
133
+	 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
134
+	 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
135
+#define BM_PHY_REG_PAGE(offset) \
136
+	((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
137
+#define BM_PHY_REG_NUM(offset) \
138
+	((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
139
+	 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
140
+		~MAX_PHY_REG_ADDRESS)))
141
+
142
+#define HV_INTC_FC_PAGE_START             768
143
+#define I82578_ADDR_REG                   29
144
+#define I82577_ADDR_REG                   16
145
+#define I82577_CFG_REG                    22
146
+#define I82577_CFG_ASSERT_CRS_ON_TX       (1 << 15)
147
+#define I82577_CFG_ENABLE_DOWNSHIFT       (3 << 10) /* auto downshift 100/10 */
148
+#define I82577_CTRL_REG                   23
149
+
150
+/* 82577 specific PHY registers */
151
+#define I82577_PHY_CTRL_2            18
152
+#define I82577_PHY_LBK_CTRL          19
153
+#define I82577_PHY_STATUS_2          26
154
+#define I82577_PHY_DIAG_STATUS       31
155
+
156
+/* I82577 PHY Status 2 */
157
+#define I82577_PHY_STATUS2_REV_POLARITY   0x0400
158
+#define I82577_PHY_STATUS2_MDIX           0x0800
159
+#define I82577_PHY_STATUS2_SPEED_MASK     0x0300
160
+#define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
161
+#define I82577_PHY_STATUS2_SPEED_100MBPS  0x0100
162
+
163
+/* I82577 PHY Control 2 */
164
+#define I82577_PHY_CTRL2_AUTO_MDIX        0x0400
165
+#define I82577_PHY_CTRL2_FORCE_MDI_MDIX   0x0200
166
+
167
+/* I82577 PHY Diagnostics Status */
168
+#define I82577_DSTATUS_CABLE_LENGTH       0x03FC
169
+#define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
170
+
171
+/* BM PHY Copper Specific Control 1 */
172
+#define BM_CS_CTRL1                       16
173
+#define BM_CS_CTRL1_ENERGY_DETECT         0x0300 /* Enable Energy Detect */
174
+
175
+/* BM PHY Copper Specific Status */
176
+#define BM_CS_STATUS                      17
177
+#define BM_CS_STATUS_ENERGY_DETECT        0x0010 /* Energy Detect Status */
178
+#define BM_CS_STATUS_LINK_UP              0x0400
179
+#define BM_CS_STATUS_RESOLVED             0x0800
180
+#define BM_CS_STATUS_SPEED_MASK           0xC000
181
+#define BM_CS_STATUS_SPEED_1000           0x8000
182
+
183
+/* 82577 Mobile Phy Status Register */
184
+#define HV_M_STATUS                       26
185
+#define HV_M_STATUS_AUTONEG_COMPLETE      0x1000
186
+#define HV_M_STATUS_SPEED_MASK            0x0300
187
+#define HV_M_STATUS_SPEED_1000            0x0200
188
+#define HV_M_STATUS_LINK_UP               0x0040
189
+
190
+#define IGP01E1000_PHY_PCS_INIT_REG       0x00B4
191
+#define IGP01E1000_PHY_POLARITY_MASK      0x0078
192
+
193
+#define IGP01E1000_PSCR_AUTO_MDIX         0x1000
194
+#define IGP01E1000_PSCR_FORCE_MDI_MDIX    0x2000 /* 0=MDI, 1=MDIX */
195
+
196
+#define IGP01E1000_PSCFR_SMART_SPEED      0x0080
197
+
198
+/* Enable flexible speed on link-up */
199
+#define IGP01E1000_GMII_FLEX_SPD          0x0010
200
+#define IGP01E1000_GMII_SPD               0x0020 /* Enable SPD */
201
+
202
+#define IGP02E1000_PM_SPD                 0x0001 /* Smart Power Down */
203
+#define IGP02E1000_PM_D0_LPLU             0x0002 /* For D0a states */
204
+#define IGP02E1000_PM_D3_LPLU             0x0004 /* For all other states */
205
+
206
+#define IGP01E1000_PLHR_SS_DOWNGRADE      0x8000
207
+
208
+#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
209
+#define IGP01E1000_PSSR_MDIX              0x0800
210
+#define IGP01E1000_PSSR_SPEED_MASK        0xC000
211
+#define IGP01E1000_PSSR_SPEED_1000MBPS    0xC000
212
+
213
+#define IGP02E1000_PHY_CHANNEL_NUM        4
214
+#define IGP02E1000_PHY_AGC_A              0x11B1
215
+#define IGP02E1000_PHY_AGC_B              0x12B1
216
+#define IGP02E1000_PHY_AGC_C              0x14B1
217
+#define IGP02E1000_PHY_AGC_D              0x18B1
218
+
219
+#define IGP02E1000_AGC_LENGTH_SHIFT       9   /* Course - 15:13, Fine - 12:9 */
220
+#define IGP02E1000_AGC_LENGTH_MASK        0x7F
221
+#define IGP02E1000_AGC_RANGE              15
222
+
223
+#define IGP03E1000_PHY_MISC_CTRL          0x1B
224
+#define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET  0x1000 /* Manually Set Duplex */
225
+
226
+#define E1000_CABLE_LENGTH_UNDEFINED      0xFF
227
+
228
+#define E1000_KMRNCTRLSTA_OFFSET          0x001F0000
229
+#define E1000_KMRNCTRLSTA_OFFSET_SHIFT    16
230
+#define E1000_KMRNCTRLSTA_REN             0x00200000
231
+#define E1000_KMRNCTRLSTA_DIAG_OFFSET     0x3    /* Kumeran Diagnostic */
232
+#define E1000_KMRNCTRLSTA_TIMEOUTS        0x4    /* Kumeran Timeouts */
233
+#define E1000_KMRNCTRLSTA_INBAND_PARAM    0x9    /* Kumeran InBand Parameters */
234
+#define E1000_KMRNCTRLSTA_DIAG_NELPBK     0x1000 /* Nearend Loopback mode */
235
+#define E1000_KMRNCTRLSTA_K1_CONFIG        0x7
236
+#define E1000_KMRNCTRLSTA_K1_ENABLE        0x0002
237
+
238
+#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
239
+#define IFE_PHY_SPECIAL_CONTROL     0x11 /* 100BaseTx PHY Special Control */
240
+#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
241
+#define IFE_PHY_MDIX_CONTROL        0x1C /* MDI/MDI-X Control */
242
+
243
+/* IFE PHY Extended Status Control */
244
+#define IFE_PESC_POLARITY_REVERSED    0x0100
245
+
246
+/* IFE PHY Special Control */
247
+#define IFE_PSC_AUTO_POLARITY_DISABLE      0x0010
248
+#define IFE_PSC_FORCE_POLARITY             0x0020
249
+#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
250
+
251
+/* IFE PHY Special Control and LED Control */
252
+#define IFE_PSCL_PROBE_MODE            0x0020
253
+#define IFE_PSCL_PROBE_LEDS_OFF        0x0006 /* Force LEDs 0 and 2 off */
254
+#define IFE_PSCL_PROBE_LEDS_ON         0x0007 /* Force LEDs 0 and 2 on */
255
+
256
+/* IFE PHY MDIX Control */
257
+#define IFE_PMC_MDIX_STATUS      0x0020 /* 1=MDI-X, 0=MDI */
258
+#define IFE_PMC_FORCE_MDIX       0x0040 /* 1=force MDI-X, 0=force MDI */
259
+#define IFE_PMC_AUTO_MDIX        0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
260
+
261
+#endif

+ 340
- 0
src/drivers/net/e1000e/e1000e_regs.h Datei anzeigen

@@ -0,0 +1,340 @@
1
+/*******************************************************************************
2
+
3
+  Intel PRO/1000 Linux driver
4
+  Copyright(c) 1999 - 2009 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  Linux NICS <linux.nics@intel.com>
24
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
+
27
+*******************************************************************************/
28
+
29
+FILE_LICENCE ( GPL2_OR_LATER );
30
+
31
+#ifndef _E1000E_REGS_H_
32
+#define _E1000E_REGS_H_
33
+
34
+#define E1000_CTRL     0x00000  /* Device Control - RW */
35
+#define E1000_CTRL_DUP 0x00004  /* Device Control Duplicate (Shadow) - RW */
36
+#define E1000_STATUS   0x00008  /* Device Status - RO */
37
+#define E1000_EECD     0x00010  /* EEPROM/Flash Control - RW */
38
+#define E1000_EERD     0x00014  /* EEPROM Read - RW */
39
+#define E1000_CTRL_EXT 0x00018  /* Extended Device Control - RW */
40
+#define E1000_FLA      0x0001C  /* Flash Access - RW */
41
+#define E1000_MDIC     0x00020  /* MDI Control - RW */
42
+#define E1000_SCTL     0x00024  /* SerDes Control - RW */
43
+#define E1000_FCAL     0x00028  /* Flow Control Address Low - RW */
44
+#define E1000_FCAH     0x0002C  /* Flow Control Address High -RW */
45
+#define E1000_FEXT     0x0002C  /* Future Extended - RW */
46
+#define E1000_FEXTNVM  0x00028  /* Future Extended NVM - RW */
47
+#define E1000_FCT      0x00030  /* Flow Control Type - RW */
48
+#define E1000_CONNSW   0x00034  /* Copper/Fiber switch control - RW */
49
+#define E1000_VET      0x00038  /* VLAN Ether Type - RW */
50
+#define E1000_ICR      0x000C0  /* Interrupt Cause Read - R/clr */
51
+#define E1000_ITR      0x000C4  /* Interrupt Throttling Rate - RW */
52
+#define E1000_ICS      0x000C8  /* Interrupt Cause Set - WO */
53
+#define E1000_IMS      0x000D0  /* Interrupt Mask Set - RW */
54
+#define E1000_IMC      0x000D8  /* Interrupt Mask Clear - WO */
55
+#define E1000_IAM      0x000E0  /* Interrupt Acknowledge Auto Mask */
56
+#define E1000_IVAR     0x000E4  /* Interrupt Vector Allocation Register - RW */
57
+#define E1000_SVCR     0x000F0
58
+#define E1000_SVT       0x000F4
59
+#define E1000_RCTL     0x00100  /* Rx Control - RW */
60
+#define E1000_FCTTV    0x00170  /* Flow Control Transmit Timer Value - RW */
61
+#define E1000_TXCW     0x00178  /* Tx Configuration Word - RW */
62
+#define E1000_RXCW     0x00180  /* Rx Configuration Word - RO */
63
+#define E1000_PBA_ECC  0x01100  /* PBA ECC Register */
64
+#define E1000_TCTL     0x00400  /* Tx Control - RW */
65
+#define E1000_TCTL_EXT 0x00404  /* Extended Tx Control - RW */
66
+#define E1000_TIPG     0x00410  /* Tx Inter-packet gap -RW */
67
+#define E1000_TBT      0x00448  /* Tx Burst Timer - RW */
68
+#define E1000_AIT      0x00458  /* Adaptive Interframe Spacing Throttle - RW */
69
+#define E1000_LEDCTL   0x00E00  /* LED Control - RW */
70
+#define E1000_EXTCNF_CTRL  0x00F00  /* Extended Configuration Control */
71
+#define E1000_EXTCNF_SIZE  0x00F08  /* Extended Configuration Size */
72
+#define E1000_PHY_CTRL     0x00F10  /* PHY Control Register in CSR */
73
+#define E1000_PBA      0x01000  /* Packet Buffer Allocation - RW */
74
+#define E1000_PBS      0x01008  /* Packet Buffer Size */
75
+#define E1000_EEMNGCTL 0x01010  /* MNG EEprom Control */
76
+#define E1000_EEARBC   0x01024  /* EEPROM Auto Read Bus Control */
77
+#define E1000_FLASHT   0x01028  /* FLASH Timer Register */
78
+#define E1000_EEWR     0x0102C  /* EEPROM Write Register - RW */
79
+#define E1000_FLSWCTL  0x01030  /* FLASH control register */
80
+#define E1000_FLSWDATA 0x01034  /* FLASH data register */
81
+#define E1000_FLSWCNT  0x01038  /* FLASH Access Counter */
82
+#define E1000_FLOP     0x0103C  /* FLASH Opcode Register */
83
+#define E1000_I2CCMD   0x01028  /* SFPI2C Command Register - RW */
84
+#define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */
85
+#define E1000_WDSTP    0x01040  /* Watchdog Setup - RW */
86
+#define E1000_SWDSTS   0x01044  /* SW Device Status - RW */
87
+#define E1000_FRTIMER  0x01048  /* Free Running Timer - RW */
88
+#define E1000_ERT      0x02008  /* Early Rx Threshold - RW */
89
+#define E1000_FCRTL    0x02160  /* Flow Control Receive Threshold Low - RW */
90
+#define E1000_FCRTH    0x02168  /* Flow Control Receive Threshold High - RW */
91
+#define E1000_PSRCTL   0x02170  /* Packet Split Receive Control - RW */
92
+#define E1000_RDFPCQ(_n)  (0x02430 + (0x4 * (_n)))
93
+#define E1000_PBRTH    0x02458  /* PB Rx Arbitration Threshold - RW */
94
+#define E1000_FCRTV    0x02460  /* Flow Control Refresh Timer Value - RW */
95
+/* Split and Replication Rx Control - RW */
96
+#define E1000_RDPUMB   0x025CC  /* DMA Rx Descriptor uC Mailbox - RW */
97
+#define E1000_RDPUAD   0x025D0  /* DMA Rx Descriptor uC Addr Command - RW */
98
+#define E1000_RDPUWD   0x025D4  /* DMA Rx Descriptor uC Data Write - RW */
99
+#define E1000_RDPURD   0x025D8  /* DMA Rx Descriptor uC Data Read - RW */
100
+#define E1000_RDPUCTL  0x025DC  /* DMA Rx Descriptor uC Control - RW */
101
+#define E1000_RDTR     0x02820  /* Rx Delay Timer - RW */
102
+#define E1000_RADV     0x0282C  /* Rx Interrupt Absolute Delay Timer - RW */
103
+/*
104
+ * Convenience macros
105
+ *
106
+ * Note: "_n" is the queue number of the register to be written to.
107
+ *
108
+ * Example usage:
109
+ * E1000_RDBAL_REG(current_rx_queue)
110
+ */
111
+#define E1000_RDBAL(_n)      ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \
112
+                                         (0x0C000 + ((_n) * 0x40)))
113
+#define E1000_RDBAH(_n)      ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \
114
+                                         (0x0C004 + ((_n) * 0x40)))
115
+#define E1000_RDLEN(_n)      ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \
116
+                                         (0x0C008 + ((_n) * 0x40)))
117
+#define E1000_SRRCTL(_n)     ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
118
+                                         (0x0C00C + ((_n) * 0x40)))
119
+#define E1000_RDH(_n)        ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \
120
+                                         (0x0C010 + ((_n) * 0x40)))
121
+#define E1000_RXCTL(_n)      ((_n) < 4 ? (0x02814 + ((_n) * 0x100)) : \
122
+                                         (0x0C014 + ((_n) * 0x40)))
123
+#define E1000_DCA_RXCTRL(_n) E1000_RXCTL(_n)
124
+#define E1000_RDT(_n)        ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \
125
+                                         (0x0C018 + ((_n) * 0x40)))
126
+#define E1000_RXDCTL(_n)     ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \
127
+                                         (0x0C028 + ((_n) * 0x40)))
128
+#define E1000_RQDPC(_n)      ((_n) < 4 ? (0x02830 + ((_n) * 0x100)) : \
129
+                                         (0x0C030 + ((_n) * 0x40)))
130
+#define E1000_TDBAL(_n)      ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \
131
+                                         (0x0E000 + ((_n) * 0x40)))
132
+#define E1000_TDBAH(_n)      ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \
133
+                                         (0x0E004 + ((_n) * 0x40)))
134
+#define E1000_TDLEN(_n)      ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \
135
+                                         (0x0E008 + ((_n) * 0x40)))
136
+#define E1000_TDH(_n)        ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \
137
+                                         (0x0E010 + ((_n) * 0x40)))
138
+#define E1000_TXCTL(_n)      ((_n) < 4 ? (0x03814 + ((_n) * 0x100)) : \
139
+                                         (0x0E014 + ((_n) * 0x40)))
140
+#define E1000_DCA_TXCTRL(_n) E1000_TXCTL(_n)
141
+#define E1000_TDT(_n)        ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \
142
+                                         (0x0E018 + ((_n) * 0x40)))
143
+#define E1000_TXDCTL(_n)     ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \
144
+                                         (0x0E028 + ((_n) * 0x40)))
145
+#define E1000_TDWBAL(_n)     ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : \
146
+                                         (0x0E038 + ((_n) * 0x40)))
147
+#define E1000_TDWBAH(_n)     ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : \
148
+                                         (0x0E03C + ((_n) * 0x40)))
149
+#define E1000_TARC(_n)                   (0x03840 + ((_n) * 0x100))
150
+#define E1000_RSRPD    0x02C00  /* Rx Small Packet Detect - RW */
151
+#define E1000_RAID     0x02C08  /* Receive Ack Interrupt Delay - RW */
152
+#define E1000_TXDMAC   0x03000  /* Tx DMA Control - RW */
153
+#define E1000_KABGTXD  0x03004  /* AFE Band Gap Transmit Ref Data */
154
+#define E1000_PSRTYPE(_i)       (0x05480 + ((_i) * 4))
155
+#define E1000_RAL(_i)  (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
156
+                                       (0x054E0 + ((_i - 16) * 8)))
157
+#define E1000_RAH(_i)  (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
158
+                                       (0x054E4 + ((_i - 16) * 8)))
159
+#define E1000_IP4AT_REG(_i)     (0x05840 + ((_i) * 8))
160
+#define E1000_IP6AT_REG(_i)     (0x05880 + ((_i) * 4))
161
+#define E1000_WUPM_REG(_i)      (0x05A00 + ((_i) * 4))
162
+#define E1000_FFMT_REG(_i)      (0x09000 + ((_i) * 8))
163
+#define E1000_FFVT_REG(_i)      (0x09800 + ((_i) * 8))
164
+#define E1000_FFLT_REG(_i)      (0x05F00 + ((_i) * 8))
165
+#define E1000_TDFH     0x03410  /* Tx Data FIFO Head - RW */
166
+#define E1000_TDFT     0x03418  /* Tx Data FIFO Tail - RW */
167
+#define E1000_TDFHS    0x03420  /* Tx Data FIFO Head Saved - RW */
168
+#define E1000_TDFTS    0x03428  /* Tx Data FIFO Tail Saved - RW */
169
+#define E1000_TDFPC    0x03430  /* Tx Data FIFO Packet Count - RW */
170
+#define E1000_TDPUMB   0x0357C  /* DMA Tx Descriptor uC Mail Box - RW */
171
+#define E1000_TDPUAD   0x03580  /* DMA Tx Descriptor uC Addr Command - RW */
172
+#define E1000_TDPUWD   0x03584  /* DMA Tx Descriptor uC Data Write - RW */
173
+#define E1000_TDPURD   0x03588  /* DMA Tx Descriptor uC Data  Read  - RW */
174
+#define E1000_TDPUCTL  0x0358C  /* DMA Tx Descriptor uC Control - RW */
175
+#define E1000_DTXCTL   0x03590  /* DMA Tx Control - RW */
176
+#define E1000_TIDV     0x03820  /* Tx Interrupt Delay Value - RW */
177
+#define E1000_TADV     0x0382C  /* Tx Interrupt Absolute Delay Val - RW */
178
+#define E1000_TSPMT    0x03830  /* TCP Segmentation PAD & Min Threshold - RW */
179
+#define E1000_CRCERRS  0x04000  /* CRC Error Count - R/clr */
180
+#define E1000_ALGNERRC 0x04004  /* Alignment Error Count - R/clr */
181
+#define E1000_SYMERRS  0x04008  /* Symbol Error Count - R/clr */
182
+#define E1000_RXERRC   0x0400C  /* Receive Error Count - R/clr */
183
+#define E1000_MPC      0x04010  /* Missed Packet Count - R/clr */
184
+#define E1000_SCC      0x04014  /* Single Collision Count - R/clr */
185
+#define E1000_ECOL     0x04018  /* Excessive Collision Count - R/clr */
186
+#define E1000_MCC      0x0401C  /* Multiple Collision Count - R/clr */
187
+#define E1000_LATECOL  0x04020  /* Late Collision Count - R/clr */
188
+#define E1000_COLC     0x04028  /* Collision Count - R/clr */
189
+#define E1000_DC       0x04030  /* Defer Count - R/clr */
190
+#define E1000_TNCRS    0x04034  /* Tx-No CRS - R/clr */
191
+#define E1000_SEC      0x04038  /* Sequence Error Count - R/clr */
192
+#define E1000_CEXTERR  0x0403C  /* Carrier Extension Error Count - R/clr */
193
+#define E1000_RLEC     0x04040  /* Receive Length Error Count - R/clr */
194
+#define E1000_XONRXC   0x04048  /* XON Rx Count - R/clr */
195
+#define E1000_XONTXC   0x0404C  /* XON Tx Count - R/clr */
196
+#define E1000_XOFFRXC  0x04050  /* XOFF Rx Count - R/clr */
197
+#define E1000_XOFFTXC  0x04054  /* XOFF Tx Count - R/clr */
198
+#define E1000_FCRUC    0x04058  /* Flow Control Rx Unsupported Count- R/clr */
199
+#define E1000_PRC64    0x0405C  /* Packets Rx (64 bytes) - R/clr */
200
+#define E1000_PRC127   0x04060  /* Packets Rx (65-127 bytes) - R/clr */
201
+#define E1000_PRC255   0x04064  /* Packets Rx (128-255 bytes) - R/clr */
202
+#define E1000_PRC511   0x04068  /* Packets Rx (255-511 bytes) - R/clr */
203
+#define E1000_PRC1023  0x0406C  /* Packets Rx (512-1023 bytes) - R/clr */
204
+#define E1000_PRC1522  0x04070  /* Packets Rx (1024-1522 bytes) - R/clr */
205
+#define E1000_GPRC     0x04074  /* Good Packets Rx Count - R/clr */
206
+#define E1000_BPRC     0x04078  /* Broadcast Packets Rx Count - R/clr */
207
+#define E1000_MPRC     0x0407C  /* Multicast Packets Rx Count - R/clr */
208
+#define E1000_GPTC     0x04080  /* Good Packets Tx Count - R/clr */
209
+#define E1000_GORCL    0x04088  /* Good Octets Rx Count Low - R/clr */
210
+#define E1000_GORCH    0x0408C  /* Good Octets Rx Count High - R/clr */
211
+#define E1000_GOTCL    0x04090  /* Good Octets Tx Count Low - R/clr */
212
+#define E1000_GOTCH    0x04094  /* Good Octets Tx Count High - R/clr */
213
+#define E1000_RNBC     0x040A0  /* Rx No Buffers Count - R/clr */
214
+#define E1000_RUC      0x040A4  /* Rx Undersize Count - R/clr */
215
+#define E1000_RFC      0x040A8  /* Rx Fragment Count - R/clr */
216
+#define E1000_ROC      0x040AC  /* Rx Oversize Count - R/clr */
217
+#define E1000_RJC      0x040B0  /* Rx Jabber Count - R/clr */
218
+#define E1000_MGTPRC   0x040B4  /* Management Packets Rx Count - R/clr */
219
+#define E1000_MGTPDC   0x040B8  /* Management Packets Dropped Count - R/clr */
220
+#define E1000_MGTPTC   0x040BC  /* Management Packets Tx Count - R/clr */
221
+#define E1000_TORL     0x040C0  /* Total Octets Rx Low - R/clr */
222
+#define E1000_TORH     0x040C4  /* Total Octets Rx High - R/clr */
223
+#define E1000_TOTL     0x040C8  /* Total Octets Tx Low - R/clr */
224
+#define E1000_TOTH     0x040CC  /* Total Octets Tx High - R/clr */
225
+#define E1000_TPR      0x040D0  /* Total Packets Rx - R/clr */
226
+#define E1000_TPT      0x040D4  /* Total Packets Tx - R/clr */
227
+#define E1000_PTC64    0x040D8  /* Packets Tx (64 bytes) - R/clr */
228
+#define E1000_PTC127   0x040DC  /* Packets Tx (65-127 bytes) - R/clr */
229
+#define E1000_PTC255   0x040E0  /* Packets Tx (128-255 bytes) - R/clr */
230
+#define E1000_PTC511   0x040E4  /* Packets Tx (256-511 bytes) - R/clr */
231
+#define E1000_PTC1023  0x040E8  /* Packets Tx (512-1023 bytes) - R/clr */
232
+#define E1000_PTC1522  0x040EC  /* Packets Tx (1024-1522 Bytes) - R/clr */
233
+#define E1000_MPTC     0x040F0  /* Multicast Packets Tx Count - R/clr */
234
+#define E1000_BPTC     0x040F4  /* Broadcast Packets Tx Count - R/clr */
235
+#define E1000_TSCTC    0x040F8  /* TCP Segmentation Context Tx - R/clr */
236
+#define E1000_TSCTFC   0x040FC  /* TCP Segmentation Context Tx Fail - R/clr */
237
+#define E1000_IAC      0x04100  /* Interrupt Assertion Count */
238
+#define E1000_ICRXPTC  0x04104  /* Interrupt Cause Rx Pkt Timer Expire Count */
239
+#define E1000_ICRXATC  0x04108  /* Interrupt Cause Rx Abs Timer Expire Count */
240
+#define E1000_ICTXPTC  0x0410C  /* Interrupt Cause Tx Pkt Timer Expire Count */
241
+#define E1000_ICTXATC  0x04110  /* Interrupt Cause Tx Abs Timer Expire Count */
242
+#define E1000_ICTXQEC  0x04118  /* Interrupt Cause Tx Queue Empty Count */
243
+#define E1000_ICTXQMTC 0x0411C  /* Interrupt Cause Tx Queue Min Thresh Count */
244
+#define E1000_ICRXDMTC 0x04120  /* Interrupt Cause Rx Desc Min Thresh Count */
245
+#define E1000_ICRXOC   0x04124  /* Interrupt Cause Receiver Overrun Count */
246
+#define E1000_CRC_OFFSET 0x05F50  /* CRC Offset register */
247
+
248
+#define E1000_PCS_CFG0    0x04200  /* PCS Configuration 0 - RW */
249
+#define E1000_PCS_LCTL    0x04208  /* PCS Link Control - RW */
250
+#define E1000_PCS_LSTAT   0x0420C  /* PCS Link Status - RO */
251
+#define E1000_CBTMPC      0x0402C  /* Circuit Breaker Tx Packet Count */
252
+#define E1000_HTDPMC      0x0403C  /* Host Transmit Discarded Packets */
253
+#define E1000_CBRDPC      0x04044  /* Circuit Breaker Rx Dropped Count */
254
+#define E1000_CBRMPC      0x040FC  /* Circuit Breaker Rx Packet Count */
255
+#define E1000_RPTHC       0x04104  /* Rx Packets To Host */
256
+#define E1000_HGPTC       0x04118  /* Host Good Packets Tx Count */
257
+#define E1000_HTCBDPC     0x04124  /* Host Tx Circuit Breaker Dropped Count */
258
+#define E1000_HGORCL      0x04128  /* Host Good Octets Received Count Low */
259
+#define E1000_HGORCH      0x0412C  /* Host Good Octets Received Count High */
260
+#define E1000_HGOTCL      0x04130  /* Host Good Octets Transmit Count Low */
261
+#define E1000_HGOTCH      0x04134  /* Host Good Octets Transmit Count High */
262
+#define E1000_LENERRS     0x04138  /* Length Errors Count */
263
+#define E1000_SCVPC       0x04228  /* SerDes/SGMII Code Violation Pkt Count */
264
+#define E1000_HRMPC       0x0A018  /* Header Redirection Missed Packet Count */
265
+#define E1000_PCS_ANADV   0x04218  /* AN advertisement - RW */
266
+#define E1000_PCS_LPAB    0x0421C  /* Link Partner Ability - RW */
267
+#define E1000_PCS_NPTX    0x04220  /* AN Next Page Transmit - RW */
268
+#define E1000_PCS_LPABNP  0x04224  /* Link Partner Ability Next Page - RW */
269
+#define E1000_1GSTAT_RCV  0x04228  /* 1GSTAT Code Violation Packet Count - RW */
270
+#define E1000_RXCSUM   0x05000  /* Rx Checksum Control - RW */
271
+#define E1000_RLPML    0x05004  /* Rx Long Packet Max Length */
272
+#define E1000_RFCTL    0x05008  /* Receive Filter Control*/
273
+#define E1000_MTA      0x05200  /* Multicast Table Array - RW Array */
274
+#define E1000_RA       0x05400  /* Receive Address - RW Array */
275
+#define E1000_VFTA     0x05600  /* VLAN Filter Table Array - RW Array */
276
+#define E1000_VT_CTL   0x0581C  /* VMDq Control - RW */
277
+#define E1000_VFQA0    0x0B000  /* VLAN Filter Queue Array 0 - RW Array */
278
+#define E1000_VFQA1    0x0B200  /* VLAN Filter Queue Array 1 - RW Array */
279
+#define E1000_WUC      0x05800  /* Wakeup Control - RW */
280
+#define E1000_WUFC     0x05808  /* Wakeup Filter Control - RW */
281
+#define E1000_WUS      0x05810  /* Wakeup Status - RO */
282
+#define E1000_MANC     0x05820  /* Management Control - RW */
283
+#define E1000_IPAV     0x05838  /* IP Address Valid - RW */
284
+#define E1000_IP4AT    0x05840  /* IPv4 Address Table - RW Array */
285
+#define E1000_IP6AT    0x05880  /* IPv6 Address Table - RW Array */
286
+#define E1000_WUPL     0x05900  /* Wakeup Packet Length - RW */
287
+#define E1000_WUPM     0x05A00  /* Wakeup Packet Memory - RO A */
288
+#define E1000_PBACL    0x05B68  /* MSIx PBA Clear - Read/Write 1's to clear */
289
+#define E1000_FFLT     0x05F00  /* Flexible Filter Length Table - RW Array */
290
+#define E1000_HOST_IF  0x08800  /* Host Interface */
291
+#define E1000_FFMT     0x09000  /* Flexible Filter Mask Table - RW Array */
292
+#define E1000_FFVT     0x09800  /* Flexible Filter Value Table - RW Array */
293
+
294
+#define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */
295
+#define E1000_MDPHYA      0x0003C /* PHY address - RW */
296
+#define E1000_MANC2H      0x05860 /* Management Control To Host - RW */
297
+#define E1000_SW_FW_SYNC  0x05B5C /* Software-Firmware Synchronization - RW */
298
+#define E1000_CCMCTL      0x05B48 /* CCM Control Register */
299
+#define E1000_GIOCTL      0x05B44 /* GIO Analog Control Register */
300
+#define E1000_SCCTL       0x05B4C /* PCIc PLL Configuration Register */
301
+#define E1000_GCR         0x05B00 /* PCI-Ex Control */
302
+#define E1000_GCR2        0x05B64 /* PCI-Ex Control #2 */
303
+#define E1000_GSCL_1    0x05B10 /* PCI-Ex Statistic Control #1 */
304
+#define E1000_GSCL_2    0x05B14 /* PCI-Ex Statistic Control #2 */
305
+#define E1000_GSCL_3    0x05B18 /* PCI-Ex Statistic Control #3 */
306
+#define E1000_GSCL_4    0x05B1C /* PCI-Ex Statistic Control #4 */
307
+#define E1000_FACTPS    0x05B30 /* Function Active and Power State to MNG */
308
+#define E1000_SWSM      0x05B50 /* SW Semaphore */
309
+#define E1000_FWSM      0x05B54 /* FW Semaphore */
310
+#define E1000_SWSM2     0x05B58 /* Driver-only SW semaphore (not used by BOOT agents) */
311
+#define E1000_DCA_ID    0x05B70 /* DCA Requester ID Information - RO */
312
+#define E1000_DCA_CTRL  0x05B74 /* DCA Control - RW */
313
+#define E1000_FFLT_DBG  0x05F04 /* Debug Register */
314
+#define E1000_HICR      0x08F00 /* Host Interface Control */
315
+
316
+/* RSS registers */
317
+#define E1000_CPUVEC    0x02C10 /* CPU Vector Register - RW */
318
+#define E1000_MRQC      0x05818 /* Multiple Receive Control - RW */
319
+#define E1000_IMIR(_i)      (0x05A80 + ((_i) * 4))  /* Immediate Interrupt */
320
+#define E1000_IMIREXT(_i)   (0x05AA0 + ((_i) * 4))  /* Immediate Interrupt Ext*/
321
+#define E1000_IMIRVP    0x05AC0 /* Immediate Interrupt Rx VLAN Priority - RW */
322
+#define E1000_MSIXBM(_i)    (0x01600 + ((_i) * 4)) /* MSI-X Allocation Register
323
+                                                    * (_i) - RW */
324
+#define E1000_MSIXTADD(_i)  (0x0C000 + ((_i) * 0x10)) /* MSI-X Table entry addr
325
+                                                       * low reg - RW */
326
+#define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10)) /* MSI-X Table entry addr
327
+                                                       * upper reg - RW */
328
+#define E1000_MSIXTMSG(_i)  (0x0C008 + ((_i) * 0x10)) /* MSI-X Table entry
329
+                                                       * message reg - RW */
330
+#define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10)) /* MSI-X Table entry
331
+                                                       * vector ctrl reg - RW */
332
+#define E1000_MSIXPBA    0x0E000 /* MSI-X Pending bit array */
333
+#define E1000_RETA(_i)  (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */
334
+#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */
335
+#define E1000_RSSIM     0x05864 /* RSS Interrupt Mask */
336
+#define E1000_RSSIR     0x05868 /* RSS Interrupt Request */
337
+#define E1000_RXMTRL     0x0B634 /* Time sync Rx EtherType and Msg Type - RW */
338
+#define E1000_RXUDP      0x0B638 /* Time Sync Rx UDP Port - RW */
339
+
340
+#endif

+ 1
- 0
src/include/gpxe/errfile.h Datei anzeigen

@@ -105,6 +105,7 @@ FILE_LICENCE ( GPL2_OR_LATER );
105 105
 #define ERRFILE_w89c840		     ( ERRFILE_DRIVER | 0x00460000 )
106 106
 #define ERRFILE_ipoib		     ( ERRFILE_DRIVER | 0x00470000 )
107 107
 #define ERRFILE_e1000_main	     ( ERRFILE_DRIVER | 0x00480000 )
108
+#define ERRFILE_e1000e_main	     ( ERRFILE_DRIVER | 0x00490000 )
108 109
 #define ERRFILE_mtnic		     ( ERRFILE_DRIVER | 0x004a0000 )
109 110
 #define ERRFILE_phantom		     ( ERRFILE_DRIVER | 0x004b0000 )
110 111
 #define ERRFILE_ne2k_isa	     ( ERRFILE_DRIVER | 0x004c0000 )

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