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@@ -1778,7 +1778,7 @@ static void tg3_rings_reset(struct tg3 *tp)
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1778
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1778
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{ DBGP("%s\n", __func__);
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1779
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1779
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1780
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1780
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int i;
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1781
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- u32 stblk, txrcb, rxrcb, limit;
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1781
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+ u32 txrcb, rxrcb, limit;
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1782
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1782
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1783
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1783
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/* Disable all transmit rings but the first. */
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1784
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1784
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if (!tg3_flag(tp, 5705_PLUS))
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@@ -1854,8 +1854,6 @@ static void tg3_rings_reset(struct tg3 *tp)
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1854
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1854
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BDINFO_FLAGS_MAXLEN_SHIFT, 0);
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1855
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1855
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rxrcb += TG3_BDINFO_SIZE;
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1856
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1856
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}
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1857
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-
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1858
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- stblk = HOSTCC_STATBLCK_RING1;
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1859
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1857
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}
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1860
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1858
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1861
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1859
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static void tg3_setup_rxbd_thresholds(struct tg3 *tp)
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@@ -2569,14 +2567,9 @@ void tg3_set_txd(struct tg3 *tp, int entry,
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2569
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2567
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u32 tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
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2570
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2568
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{ DBGP("%s\n", __func__);
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2571
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2569
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2572
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- int cacheline_size;
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2573
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2570
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u8 byte;
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2574
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2571
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2575
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2572
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pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
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2576
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- if (byte == 0)
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2577
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- cacheline_size = 1024;
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2578
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- else
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2579
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- cacheline_size = (int) byte * 4;
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2580
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2573
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2581
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2574
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/* On 5703 and later chips, the boundary bits have no
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2582
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2575
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* effect.
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