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[ehci] Support USB1 devices attached via transaction translators

Support low-speed and full-speed devices attached to a USB2 hub.  Such
devices use a transaction translator (TT) within the USB2 hub, which
asynchronously initiates transactions on the lower-speed bus and
returns the result via a split completion on the high-speed bus.

We make the simplifying assumption that there will never be more than
sixteen active interrupt endpoints behind a single transaction
translator; this assumption allows us to schedule all periodic start
splits in microframe 0 and all periodic split completions in
microframes 2 and 3.  (We do not handle isochronous endpoints.)

Signed-off-by: Michael Brown <mcb30@ipxe.org>
tags/v1.20.1
Michael Brown 9 years ago
parent
commit
b418af26d9
2 changed files with 53 additions and 11 deletions
  1. 19
    11
      src/drivers/usb/ehci.c
  2. 34
    0
      src/drivers/usb/ehci.h

+ 19
- 11
src/drivers/usb/ehci.c View File

@@ -545,7 +545,7 @@ static int ehci_enqueue ( struct ehci_device *ehci, struct ehci_ring *ring,
545 545
 		assert ( xfer->len <= EHCI_LEN_MASK );
546 546
 		assert ( EHCI_FL_TOGGLE == EHCI_LEN_TOGGLE );
547 547
 		desc->len = cpu_to_le16 ( xfer->len | toggle );
548
-		desc->flags = xfer->flags;
548
+		desc->flags = ( xfer->flags | EHCI_FL_CERR_MAX );
549 549
 
550 550
 		/* Copy data to immediate data buffer (if requested) */
551 551
 		data = xfer->data;
@@ -902,19 +902,16 @@ static uint32_t ehci_endpoint_characteristics ( struct usb_endpoint *ep ) {
902 902
 		chr |= EHCI_CHR_TOGGLE;
903 903
 
904 904
 	/* Determine endpoint speed */
905
-	switch ( usb->port->speed ) {
906
-	case USB_SPEED_HIGH :
905
+	if ( usb->port->speed == USB_SPEED_HIGH ) {
907 906
 		chr |= EHCI_CHR_EPS_HIGH;
908
-		break;
909
-	case USB_SPEED_FULL :
910
-		chr |= EHCI_CHR_EPS_FULL;
911
-		break;
912
-	default:
913
-		assert ( usb->port->speed == USB_SPEED_LOW );
914
-		chr |= EHCI_CHR_EPS_LOW;
907
+	} else {
908
+		if ( usb->port->speed == USB_SPEED_FULL ) {
909
+			chr |= EHCI_CHR_EPS_FULL;
910
+		} else {
911
+			chr |= EHCI_CHR_EPS_LOW;
912
+		}
915 913
 		if ( attr == USB_ENDPOINT_ATTR_CONTROL )
916 914
 			chr |= EHCI_CHR_CONTROL;
917
-		break;
918 915
 	}
919 916
 
920 917
 	return chr;
@@ -927,6 +924,8 @@ static uint32_t ehci_endpoint_characteristics ( struct usb_endpoint *ep ) {
927 924
  * @ret cap		Endpoint capabilities
928 925
  */
929 926
 static uint32_t ehci_endpoint_capabilities ( struct usb_endpoint *ep ) {
927
+	struct usb_device *usb = ep->usb;
928
+	struct usb_port *tt = usb_transaction_translator ( usb );
930 929
 	unsigned int attr = ( ep->attributes & USB_ENDPOINT_ATTR_TYPE_MASK );
931 930
 	uint32_t cap;
932 931
 	unsigned int i;
@@ -943,6 +942,15 @@ static uint32_t ehci_endpoint_capabilities ( struct usb_endpoint *ep ) {
943 942
 		}
944 943
 	}
945 944
 
945
+	/* Set transaction translator hub address and port, if applicable */
946
+	if ( tt ) {
947
+		assert ( tt->hub->usb );
948
+		cap |= ( EHCI_CAP_TT_HUB ( tt->hub->usb->address ) |
949
+			 EHCI_CAP_TT_PORT ( tt->address ) );
950
+		if ( attr == USB_ENDPOINT_ATTR_INTERRUPT )
951
+			cap |= EHCI_CAP_SPLIT_SCHED_DEFAULT;
952
+	}
953
+
946 954
 	return cap;
947 955
 }
948 956
 

+ 34
- 0
src/drivers/usb/ehci.h View File

@@ -285,6 +285,12 @@ struct ehci_transfer_descriptor {
285 285
 /** SETUP token */
286 286
 #define EHCI_FL_PID_SETUP EHCI_FL_PID ( 2 )
287 287
 
288
+/** Error counter */
289
+#define EHCI_FL_CERR( count ) ( (count) << 2 )
290
+
291
+/** Error counter maximum value */
292
+#define EHCI_FL_CERR_MAX EHCI_FL_CERR ( 3 )
293
+
288 294
 /** Interrupt on completion */
289 295
 #define EHCI_FL_IOC 0x80
290 296
 
@@ -341,6 +347,34 @@ struct ehci_queue_head {
341 347
 /** Interrupt schedule mask */
342 348
 #define EHCI_CAP_INTR_SCHED( uframe ) ( 1 << ( (uframe) + 0 ) )
343 349
 
350
+/** Split completion schedule mask */
351
+#define EHCI_CAP_SPLIT_SCHED( uframe ) ( 1 << ( (uframe) + 8 ) )
352
+
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+/** Default split completion schedule mask
354
+ *
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+ * We schedule all split starts in microframe 0, on the assumption
356
+ * that we will never have to deal with more than sixteen actively
357
+ * interrupting devices via the same transaction translator.  We
358
+ * schedule split completions for all remaining microframes after
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+ * microframe 1 (in which the low-speed or full-speed transaction is
360
+ * assumed to execute).  This is a very crude approximation designed
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+ * to avoid the need for calculating exactly when low-speed and
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+ * full-speed transactions will execute.  Since we only ever deal with
363
+ * interrupt endpoints (rather than isochronous endpoints), the volume
364
+ * of periodic traffic is extremely low, and this approximation should
365
+ * remain valid.
366
+ */
367
+#define EHCI_CAP_SPLIT_SCHED_DEFAULT					\
368
+	( EHCI_CAP_SPLIT_SCHED ( 2 ) | EHCI_CAP_SPLIT_SCHED ( 3 ) |	\
369
+	  EHCI_CAP_SPLIT_SCHED ( 4 ) | EHCI_CAP_SPLIT_SCHED ( 5 ) |	\
370
+	  EHCI_CAP_SPLIT_SCHED ( 6 ) | EHCI_CAP_SPLIT_SCHED ( 7 ) )
371
+
372
+/** Transaction translator hub address */
373
+#define EHCI_CAP_TT_HUB( address ) ( (address) << 16 )
374
+
375
+/** Transaction translator port number */
376
+#define EHCI_CAP_TT_PORT( port ) ( (port) << 23 )
377
+
344 378
 /** High-bandwidth pipe multiplier */
345 379
 #define EHCI_CAP_MULT( mult ) ( (mult) << 30 )
346 380
 

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