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[intel] Add intelxvf driver for Intel 10 GigE virtual function NICs

Signed-off-by: Michael Brown <mcb30@ipxe.org>
tags/v1.20.1
Michael Brown 9 anos atrás
pai
commit
a91b1f7339
3 arquivos alterados com 455 adições e 0 exclusões
  1. 377
    0
      src/drivers/net/intelxvf.c
  2. 77
    0
      src/drivers/net/intelxvf.h
  3. 1
    0
      src/include/ipxe/errfile.h

+ 377
- 0
src/drivers/net/intelxvf.c Ver arquivo

@@ -0,0 +1,377 @@
1
+/*
2
+ * Copyright (C) 2015 Michael Brown <mbrown@fensystems.co.uk>.
3
+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of the
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+ * License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful, but
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+ * WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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+ * General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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+ * 02110-1301, USA.
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+ *
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+ * You can also choose to distribute this program under the terms of
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+ * the Unmodified Binary Distribution Licence (as given in the file
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+ * COPYING.UBDL), provided that you have satisfied its requirements.
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+ */
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+
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+FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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+
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+#include <string.h>
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+#include <unistd.h>
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+#include <errno.h>
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+#include <ipxe/io.h>
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+#include <ipxe/pci.h>
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+#include <ipxe/netdevice.h>
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+#include <ipxe/ethernet.h>
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+#include "intelxvf.h"
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+
35
+/** @file
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+ *
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+ * Intel 10 Gigabit Ethernet virtual function network card driver
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+ *
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+ */
40
+
41
+/******************************************************************************
42
+ *
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+ * Device reset
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+ *
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+ ******************************************************************************
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+ */
47
+
48
+/**
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+ * Reset hardware
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+ *
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+ * @v intel		Intel device
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+ */
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+static void intelxvf_reset ( struct intel_nic *intel ) {
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+
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+	/* Perform a function-level reset */
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+	writel ( INTELXVF_CTRL_RST, intel->regs + INTELXVF_CTRL );
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+}
58
+
59
+/******************************************************************************
60
+ *
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+ * Link state
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+ *
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+ ******************************************************************************
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+ */
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+
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+/**
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+ * Check link state
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+ *
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+ * @v netdev		Network device
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+ */
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+static void intelxvf_check_link ( struct net_device *netdev ) {
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+	struct intel_nic *intel = netdev->priv;
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+	uint32_t links;
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+
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+	/* Read link status */
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+	links = readl ( intel->regs + INTELXVF_LINKS );
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+	DBGC ( intel, "INTEL %p link status is %08x\n", intel, links );
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+
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+	/* Update network device */
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+	if ( links & INTELXVF_LINKS_UP ) {
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+		netdev_link_up ( netdev );
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+	} else {
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+		netdev_link_down ( netdev );
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+	}
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+}
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+
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+/******************************************************************************
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+ *
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+ * Network device interface
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+ *
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+ ******************************************************************************
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+ */
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+
94
+/**
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+ * Open network device
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+ *
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+ * @v netdev		Network device
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+ * @ret rc		Return status code
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+ */
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+static int intelxvf_open ( struct net_device *netdev ) {
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+	struct intel_nic *intel = netdev->priv;
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+	uint32_t srrctl;
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+	uint32_t dca_rxctrl;
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+	int rc;
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+
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+	/* Reset the function */
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+	intelxvf_reset ( intel );
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+
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+	/* Notify PF that reset is complete */
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+	if ( ( rc = intelvf_mbox_reset ( intel, NULL ) ) != 0 ) {
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+		DBGC ( intel, "INTEL %p could not reset: %s\n",
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+		       intel, strerror ( rc ) );
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+		goto err_mbox_reset;
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+	}
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+
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+	/* Set MAC address */
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+	if ( ( rc = intelvf_mbox_set_mac ( intel, netdev->ll_addr ) ) != 0 ) {
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+		DBGC ( intel, "INTEL %p could not set MAC address: %s\n",
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+		       intel, strerror ( rc ) );
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+		goto err_mbox_set_mac;
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+	}
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+
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+	/* Create transmit descriptor ring */
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+	if ( ( rc = intel_create_ring ( intel, &intel->tx ) ) != 0 )
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+		goto err_create_tx;
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+
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+	/* Create receive descriptor ring */
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+	if ( ( rc = intel_create_ring ( intel, &intel->rx ) ) != 0 )
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+		goto err_create_rx;
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+
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+	/* Allocate interrupt vectors */
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+	writel ( ( INTELXVF_IVAR_RX0_DEFAULT | INTELXVF_IVAR_RX0_VALID |
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+		   INTELXVF_IVAR_TX0_DEFAULT | INTELXVF_IVAR_TX0_VALID ),
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+		 intel->regs + INTELXVF_IVAR );
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+	writel ( ( INTELXVF_IVARM_MBOX_DEFAULT | INTELXVF_IVARM_MBOX_VALID ),
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+		 intel->regs + INTELXVF_IVARM );
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+
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+	/* Configure receive buffer sizes and set receive descriptor type */
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+	srrctl = readl ( intel->regs + INTELXVF_SRRCTL );
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+	srrctl &= ~( INTELXVF_SRRCTL_BSIZE_MASK |
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+		     INTELXVF_SRRCTL_DESCTYPE_MASK );
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+	srrctl |= ( INTELXVF_SRRCTL_BSIZE_DEFAULT |
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+		    INTELXVF_SRRCTL_DESCTYPE_DEFAULT );
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+	writel ( srrctl, intel->regs + INTELXVF_SRRCTL );
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+
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+	/* Clear "must-be-zero" bit for direct cache access (DCA).  We
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+	 * leave DCA disabled anyway, but if we do not clear this bit
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+	 * then the received packets contain garbage data.
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+	 */
150
+	dca_rxctrl = readl ( intel->regs + INTELXVF_DCA_RXCTRL );
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+	dca_rxctrl &= ~INTELXVF_DCA_RXCTRL_MUST_BE_ZERO;
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+	writel ( dca_rxctrl, intel->regs + INTELXVF_DCA_RXCTRL );
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+
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+	/* Fill receive ring */
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+	intel_refill_rx ( intel );
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+
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+	/* Update link state */
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+	intelxvf_check_link ( netdev );
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+
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+	return 0;
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+
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+	intel_destroy_ring ( intel, &intel->rx );
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+ err_create_rx:
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+	intel_destroy_ring ( intel, &intel->tx );
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+ err_create_tx:
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+ err_mbox_set_mac:
167
+ err_mbox_reset:
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+	intelxvf_reset ( intel );
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+	return rc;
170
+}
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+
172
+/**
173
+ * Close network device
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+ *
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+ * @v netdev		Network device
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+ */
177
+static void intelxvf_close ( struct net_device *netdev ) {
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+	struct intel_nic *intel = netdev->priv;
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+
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+	/* Destroy receive descriptor ring */
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+	intel_destroy_ring ( intel, &intel->rx );
182
+
183
+	/* Discard any unused receive buffers */
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+	intel_empty_rx ( intel );
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+
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+	/* Destroy transmit descriptor ring */
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+	intel_destroy_ring ( intel, &intel->tx );
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+
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+	/* Reset the function */
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+	intelxvf_reset ( intel );
191
+}
192
+
193
+/**
194
+ * Poll for completed and received packets
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+ *
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+ * @v netdev		Network device
197
+ */
198
+static void intelxvf_poll ( struct net_device *netdev ) {
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+	struct intel_nic *intel = netdev->priv;
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+	uint32_t eicr;
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+	int rc;
202
+
203
+	/* Check for and acknowledge interrupts */
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+	eicr = readl ( intel->regs + INTELXVF_EICR );
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+	if ( ! eicr )
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+		return;
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+
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+	/* Poll for TX completions, if applicable */
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+	if ( eicr & INTELXVF_EIRQ_TX0 )
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+		intel_poll_tx ( netdev );
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+
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+	/* Poll for RX completions, if applicable */
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+	if ( eicr & INTELXVF_EIRQ_RX0 )
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+		intel_poll_rx ( netdev );
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+
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+	/* Poll for mailbox messages, if applicable */
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+	if ( eicr & INTELXVF_EIRQ_MBOX ) {
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+
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+		/* Poll mailbox */
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+		if ( ( rc = intelvf_mbox_poll ( intel ) ) != 0 ) {
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+			DBGC ( intel, "INTEL %p mailbox poll failed!\n",
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+			       intel );
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+			netdev_rx_err ( netdev, NULL, rc );
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+		}
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+
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+		/* Update link state */
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+		intelxvf_check_link ( netdev );
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+	}
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+
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+	/* Refill RX ring */
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+	intel_refill_rx ( intel );
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+}
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+
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+/**
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+ * Enable or disable interrupts
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+ *
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+ * @v netdev		Network device
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+ * @v enable		Interrupts should be enabled
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+ */
240
+static void intelxvf_irq ( struct net_device *netdev, int enable ) {
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+	struct intel_nic *intel = netdev->priv;
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+	uint32_t mask;
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+
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+	mask = ( INTELXVF_EIRQ_MBOX | INTELXVF_EIRQ_TX0 | INTELXVF_EIRQ_RX0 );
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+	if ( enable ) {
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+		writel ( mask, intel->regs + INTELXVF_EIMS );
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+	} else {
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+		writel ( mask, intel->regs + INTELXVF_EIMC );
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+	}
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+}
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+
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+/** Network device operations */
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+static struct net_device_operations intelxvf_operations = {
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+	.open		= intelxvf_open,
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+	.close		= intelxvf_close,
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+	.transmit	= intel_transmit,
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+	.poll		= intelxvf_poll,
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+	.irq		= intelxvf_irq,
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+};
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+
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+/******************************************************************************
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+ *
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+ * PCI interface
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+ *
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+ ******************************************************************************
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+ */
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+
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+/**
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+ * Probe PCI device
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+ *
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+ * @v pci		PCI device
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+ * @ret rc		Return status code
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+ */
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+static int intelxvf_probe ( struct pci_device *pci ) {
275
+	struct net_device *netdev;
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+	struct intel_nic *intel;
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+	int rc;
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+
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+	/* Allocate and initialise net device */
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+	netdev = alloc_etherdev ( sizeof ( *intel ) );
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+	if ( ! netdev ) {
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+		rc = -ENOMEM;
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+		goto err_alloc;
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+	}
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+	netdev_init ( netdev, &intelxvf_operations );
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+	intel = netdev->priv;
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+	pci_set_drvdata ( pci, netdev );
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+	netdev->dev = &pci->dev;
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+	memset ( intel, 0, sizeof ( *intel ) );
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+	intel_init_mbox ( &intel->mbox, INTELXVF_MBCTRL, INTELXVF_MBMEM );
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+	intel_init_ring ( &intel->tx, INTEL_NUM_TX_DESC, INTELXVF_TD,
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+			  intel_describe_tx_adv );
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+	intel_init_ring ( &intel->rx, INTEL_NUM_RX_DESC, INTELXVF_RD,
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+			  intel_describe_rx );
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+
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+	/* Fix up PCI device */
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+	adjust_pci_device ( pci );
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+
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+	/* Map registers */
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+	intel->regs = ioremap ( pci->membase, INTELVF_BAR_SIZE );
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+	if ( ! intel->regs ) {
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+		rc = -ENODEV;
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+		goto err_ioremap;
304
+	}
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+
306
+	/* Reset the function */
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+	intelxvf_reset ( intel );
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+
309
+	/* Send reset message and fetch MAC address */
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+	if ( ( rc = intelvf_mbox_reset ( intel, netdev->hw_addr ) ) != 0 ) {
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+		DBGC ( intel, "INTEL %p could not reset and fetch MAC: %s\n",
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+		       intel, strerror ( rc ) );
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+		goto err_mbox_reset;
314
+	}
315
+
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+	/* Reset the function (since we will not respond to Control
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+	 * ("ping") mailbox messages until the network device is opened.
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+	 */
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+	intelxvf_reset ( intel );
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+
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+	/* Register network device */
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+	if ( ( rc = register_netdev ( netdev ) ) != 0 )
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+		goto err_register_netdev;
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+
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+	/* Set initial link state */
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+	intelxvf_check_link ( netdev );
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+
328
+	return 0;
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+
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+	unregister_netdev ( netdev );
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+ err_register_netdev:
332
+ err_mbox_reset:
333
+	intelxvf_reset ( intel );
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+	iounmap ( intel->regs );
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+ err_ioremap:
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+	netdev_nullify ( netdev );
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+	netdev_put ( netdev );
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+ err_alloc:
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+	return rc;
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+}
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+
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+/**
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+ * Remove PCI device
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+ *
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+ * @v pci		PCI device
346
+ */
347
+static void intelxvf_remove ( struct pci_device *pci ) {
348
+	struct net_device *netdev = pci_get_drvdata ( pci );
349
+	struct intel_nic *intel = netdev->priv;
350
+
351
+	/* Unregister network device */
352
+	unregister_netdev ( netdev );
353
+
354
+	/* Reset the NIC */
355
+	intelxvf_reset ( intel );
356
+
357
+	/* Free network device */
358
+	iounmap ( intel->regs );
359
+	netdev_nullify ( netdev );
360
+	netdev_put ( netdev );
361
+}
362
+
363
+/** PCI device IDs */
364
+static struct pci_device_id intelxvf_nics[] = {
365
+	PCI_ROM ( 0x8086, 0x10ed, "82599-vf", "82599 VF", 0 ),
366
+	PCI_ROM ( 0x8086, 0x1515, "x540-vf", "X540 VF", 0 ),
367
+	PCI_ROM ( 0x8086, 0x1565, "x550-vf", "X550 VF", 0 ),
368
+	PCI_ROM ( 0x8086, 0x15a8, "x552-vf", "X552 VF", 0 ),
369
+};
370
+
371
+/** PCI driver */
372
+struct pci_driver intelxvf_driver __pci_driver = {
373
+	.ids = intelxvf_nics,
374
+	.id_count = ( sizeof ( intelxvf_nics ) / sizeof ( intelxvf_nics[0] ) ),
375
+	.probe = intelxvf_probe,
376
+	.remove = intelxvf_remove,
377
+};

+ 77
- 0
src/drivers/net/intelxvf.h Ver arquivo

@@ -0,0 +1,77 @@
1
+#ifndef _INTELXVF_H
2
+#define _INTELXVF_H
3
+
4
+/** @file
5
+ *
6
+ * Intel 10 Gigabit Ethernet virtual function network card driver
7
+ *
8
+ */
9
+
10
+FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
11
+
12
+#include "intelvf.h"
13
+
14
+/** Control Register */
15
+#define INTELXVF_CTRL 0x0000UL
16
+#define INTELXVF_CTRL_RST	0x04000000UL	/**< Function-level reset */
17
+
18
+/** Link Status Register */
19
+#define INTELXVF_LINKS 0x0010UL
20
+#define INTELXVF_LINKS_UP	0x40000000UL	/**< Link up */
21
+
22
+/** Extended Interrupt Cause Read Register */
23
+#define INTELXVF_EICR 0x0100UL
24
+#define INTELXVF_EIRQ_RX0	0x00000001UL	/**< RX queue 0 (via IVAR) */
25
+#define INTELXVF_EIRQ_TX0	0x00000002UL	/**< TX queue 0 (via IVAR) */
26
+#define INTELXVF_EIRQ_MBOX	0x00000004UL	/**< Mailbox (via IVARM) */
27
+
28
+/** Extended Interrupt Mask Set/Read Register */
29
+#define INTELXVF_EIMS 0x0108UL
30
+
31
+/** Extended Interrupt Mask Clear Register */
32
+#define INTELXVF_EIMC 0x010cUL
33
+
34
+/** Interrupt Vector Allocation Register */
35
+#define INTELXVF_IVAR 0x0120UL
36
+#define INTELXVF_IVAR_RX0(bit)	( (bit) << 0 )	/**< RX queue 0 allocation */
37
+#define INTELXVF_IVAR_RX0_DEFAULT INTELXVF_IVAR_RX0 ( 0x00 )
38
+#define INTELXVF_IVAR_RX0_MASK	INTELXVF_IVAR_RX0 ( 0x01 )
39
+#define INTELXVF_IVAR_RX0_VALID	0x00000080UL	/**< RX queue 0 valid */
40
+#define INTELXVF_IVAR_TX0(bit)	( (bit) << 8 )	/**< TX queue 0 allocation */
41
+#define INTELXVF_IVAR_TX0_DEFAULT INTELXVF_IVAR_TX0 ( 0x01 )
42
+#define INTELXVF_IVAR_TX0_MASK	INTELXVF_IVAR_TX0 ( 0x01 )
43
+#define INTELXVF_IVAR_TX0_VALID	0x00008000UL	/**< TX queue 0 valid */
44
+
45
+/** Interrupt Vector Allocation Miscellaneous Register */
46
+#define INTELXVF_IVARM 0x0140UL
47
+#define INTELXVF_IVARM_MBOX(bit) ( (bit) << 0 )	/**< Mailbox allocation */
48
+#define INTELXVF_IVARM_MBOX_DEFAULT INTELXVF_IVARM_MBOX ( 0x02 )
49
+#define INTELXVF_IVARM_MBOX_MASK INTELXVF_IVARM_MBOX ( 0x03 )
50
+#define INTELXVF_IVARM_MBOX_VALID 0x00000080UL	/**< Mailbox valid */
51
+
52
+/** Mailbox Memory Register Base */
53
+#define INTELXVF_MBMEM 0x0200UL
54
+
55
+/** Mailbox Control Register */
56
+#define INTELXVF_MBCTRL 0x02fcUL
57
+
58
+/** Receive Descriptor register block */
59
+#define INTELXVF_RD 0x1000UL
60
+
61
+/** RX DCA Control Register */
62
+#define INTELXVF_DCA_RXCTRL 0x100cUL
63
+#define INTELXVF_DCA_RXCTRL_MUST_BE_ZERO 0x00001000UL /**< Must be zero */
64
+
65
+/** Split Receive Control Register */
66
+#define INTELXVF_SRRCTL 0x1014UL
67
+#define INTELXVF_SRRCTL_BSIZE(kb) ( (kb) << 0 )	/**< Receive buffer size */
68
+#define INTELXVF_SRRCTL_BSIZE_DEFAULT INTELXVF_SRRCTL_BSIZE ( 0x02 )
69
+#define INTELXVF_SRRCTL_BSIZE_MASK INTELXVF_SRRCTL_BSIZE ( 0x1f )
70
+#define INTELXVF_SRRCTL_DESCTYPE(typ) ( (typ) << 25 ) /**< Descriptor type */
71
+#define INTELXVF_SRRCTL_DESCTYPE_DEFAULT INTELXVF_SRRCTL_DESCTYPE ( 0x00 )
72
+#define INTELXVF_SRRCTL_DESCTYPE_MASK INTELXVF_SRRCTL_DESCTYPE ( 0x07 )
73
+
74
+/** Transmit Descriptor register block */
75
+#define INTELXVF_TD 0x2000UL
76
+
77
+#endif /* _INTELXVF_H */

+ 1
- 0
src/include/ipxe/errfile.h Ver arquivo

@@ -178,6 +178,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
178 178
 #define ERRFILE_qib7322		     ( ERRFILE_DRIVER | 0x00760000 )
179 179
 #define ERRFILE_smsc75xx	     ( ERRFILE_DRIVER | 0x00770000 )
180 180
 #define ERRFILE_intelvf		     ( ERRFILE_DRIVER | 0x00780000 )
181
+#define ERRFILE_intelxvf	     ( ERRFILE_DRIVER | 0x00790000 )
181 182
 
182 183
 #define ERRFILE_aoe			( ERRFILE_NET | 0x00000000 )
183 184
 #define ERRFILE_arp			( ERRFILE_NET | 0x00010000 )

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