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[intelxl] Allow for arbitrary placement of ring tail registers

The virtual function transmit and receive ring tail register offsets
do not match those of the physical function.  Allow the tail register
offsets to be specified separately.

Signed-off-by: Michael Brown <mcb30@ipxe.org>
tags/v1.20.1
Michael Brown 5 years ago
parent
commit
9907fd54d3
2 changed files with 9 additions and 7 deletions
  1. 7
    7
      src/drivers/net/intelxl.c
  2. 2
    0
      src/drivers/net/intelxl.h

+ 7
- 7
src/drivers/net/intelxl.c View File

1096
  */
1096
  */
1097
 static int intelxl_create_ring ( struct intelxl_nic *intelxl,
1097
 static int intelxl_create_ring ( struct intelxl_nic *intelxl,
1098
 				 struct intelxl_ring *ring ) {
1098
 				 struct intelxl_ring *ring ) {
1099
-	void *ring_regs = ( intelxl->regs + ring->reg );
1100
 	physaddr_t address;
1099
 	physaddr_t address;
1101
 	int rc;
1100
 	int rc;
1102
 
1101
 
1111
 	memset ( ring->desc.raw, 0, ring->len );
1110
 	memset ( ring->desc.raw, 0, ring->len );
1112
 
1111
 
1113
 	/* Reset tail pointer */
1112
 	/* Reset tail pointer */
1114
-	writel ( 0, ( ring_regs + INTELXL_QXX_TAIL ) );
1113
+	writel ( 0, ( intelxl->regs + ring->tail ) );
1115
 
1114
 
1116
 	/* Program queue context */
1115
 	/* Program queue context */
1117
 	address = virt_to_bus ( ring->desc.raw );
1116
 	address = virt_to_bus ( ring->desc.raw );
1127
 	ring->cons = 0;
1126
 	ring->cons = 0;
1128
 
1127
 
1129
 	DBGC ( intelxl, "INTELXL %p ring %06x is at [%08llx,%08llx)\n",
1128
 	DBGC ( intelxl, "INTELXL %p ring %06x is at [%08llx,%08llx)\n",
1130
-	       intelxl, ring->reg, ( ( unsigned long long ) address ),
1129
+	       intelxl, ( ring->reg + ring->tail ),
1130
+	       ( ( unsigned long long ) address ),
1131
 	       ( ( unsigned long long ) address + ring->len ) );
1131
 	       ( ( unsigned long long ) address + ring->len ) );
1132
 
1132
 
1133
 	return 0;
1133
 	return 0;
1207
 	if ( refilled ) {
1207
 	if ( refilled ) {
1208
 		wmb();
1208
 		wmb();
1209
 		rx_tail = ( intelxl->rx.prod % INTELXL_RX_NUM_DESC );
1209
 		rx_tail = ( intelxl->rx.prod % INTELXL_RX_NUM_DESC );
1210
-		writel ( rx_tail,
1211
-			 ( intelxl->regs + intelxl->rx.reg + INTELXL_QXX_TAIL));
1210
+		writel ( rx_tail, ( intelxl->regs + intelxl->rx.tail ) );
1212
 	}
1211
 	}
1213
 }
1212
 }
1214
 
1213
 
1363
 	wmb();
1362
 	wmb();
1364
 
1363
 
1365
 	/* Notify card that there are packets ready to transmit */
1364
 	/* Notify card that there are packets ready to transmit */
1366
-	writel ( tx_tail,
1367
-		 ( intelxl->regs + intelxl->tx.reg + INTELXL_QXX_TAIL ) );
1365
+	writel ( tx_tail, ( intelxl->regs + intelxl->tx.tail ) );
1368
 
1366
 
1369
 	DBGC2 ( intelxl, "INTELXL %p TX %d is [%llx,%llx)\n", intelxl, tx_idx,
1367
 	DBGC2 ( intelxl, "INTELXL %p TX %d is [%llx,%llx)\n", intelxl, tx_idx,
1370
 		( ( unsigned long long ) address ),
1368
 		( ( unsigned long long ) address ),
1595
 
1593
 
1596
 	/* Configure queue register addresses */
1594
 	/* Configure queue register addresses */
1597
 	intelxl->tx.reg = INTELXL_QTX ( intelxl->queue );
1595
 	intelxl->tx.reg = INTELXL_QTX ( intelxl->queue );
1596
+	intelxl->tx.tail = ( intelxl->tx.reg + INTELXL_QXX_TAIL );
1598
 	intelxl->rx.reg = INTELXL_QRX ( intelxl->queue );
1597
 	intelxl->rx.reg = INTELXL_QRX ( intelxl->queue );
1598
+	intelxl->rx.tail = ( intelxl->rx.reg + INTELXL_QXX_TAIL );
1599
 
1599
 
1600
 	/* Configure interrupt causes */
1600
 	/* Configure interrupt causes */
1601
 	writel ( ( INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE |
1601
 	writel ( ( INTELXL_QINT_TQCTL_NEXTQ_INDX_NONE |

+ 2
- 0
src/drivers/net/intelxl.h View File

680
 
680
 
681
 	/** Register block */
681
 	/** Register block */
682
 	unsigned int reg;
682
 	unsigned int reg;
683
+	/** Tail register */
684
+	unsigned int tail;
683
 	/** Length (in bytes) */
685
 	/** Length (in bytes) */
684
 	size_t len;
686
 	size_t len;
685
 	/** Program queue context
687
 	/** Program queue context

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