Преглед изворни кода

[intel] Replace driver for Intel Gigabit NICs

Tested-by: Robin Smidsrød <robin@smidsrod.no>
Tested-by: Thomas Miletich <thomas.miletich@gmail.com>
Signed-off-by: Michael Brown <mcb30@ipxe.org>
tags/v1.20.1
Michael Brown пре 12 година
родитељ
комит
945e428137
65 измењених фајлова са 1199 додато и 47324 уклоњено
  1. 0
    35
      src/drivers/net/e1000/e1000.c
  2. 0
    326
      src/drivers/net/e1000/e1000.h
  3. 0
    754
      src/drivers/net/e1000/e1000_82540.c
  4. 0
    1314
      src/drivers/net/e1000/e1000_82541.c
  5. 0
    86
      src/drivers/net/e1000/e1000_82541.h
  6. 0
    571
      src/drivers/net/e1000/e1000_82542.c
  7. 0
    1635
      src/drivers/net/e1000/e1000_82543.c
  8. 0
    45
      src/drivers/net/e1000/e1000_82543.h
  9. 0
    1108
      src/drivers/net/e1000/e1000_api.c
  10. 0
    127
      src/drivers/net/e1000/e1000_api.h
  11. 0
    1416
      src/drivers/net/e1000/e1000_defines.h
  12. 0
    728
      src/drivers/net/e1000/e1000_hw.h
  13. 0
    2196
      src/drivers/net/e1000/e1000_mac.c
  14. 0
    94
      src/drivers/net/e1000/e1000_mac.h
  15. 0
    909
      src/drivers/net/e1000/e1000_main.c
  16. 0
    389
      src/drivers/net/e1000/e1000_manage.c
  17. 0
    84
      src/drivers/net/e1000/e1000_manage.h
  18. 0
    923
      src/drivers/net/e1000/e1000_nvm.c
  19. 0
    63
      src/drivers/net/e1000/e1000_nvm.h
  20. 0
    118
      src/drivers/net/e1000/e1000_osdep.h
  21. 0
    2308
      src/drivers/net/e1000/e1000_phy.c
  22. 0
    171
      src/drivers/net/e1000/e1000_phy.h
  23. 0
    329
      src/drivers/net/e1000/e1000_regs.h
  24. 0
    34
      src/drivers/net/e1000e/e1000e.c
  25. 0
    534
      src/drivers/net/e1000e/e1000e.h
  26. 0
    1533
      src/drivers/net/e1000e/e1000e_80003es2lan.c
  27. 0
    100
      src/drivers/net/e1000e/e1000e_80003es2lan.h
  28. 0
    1818
      src/drivers/net/e1000e/e1000e_82571.c
  29. 0
    55
      src/drivers/net/e1000e/e1000e_82571.h
  30. 0
    1471
      src/drivers/net/e1000e/e1000e_defines.h
  31. 0
    723
      src/drivers/net/e1000e/e1000e_hw.h
  32. 0
    3465
      src/drivers/net/e1000e/e1000e_ich8lan.c
  33. 0
    199
      src/drivers/net/e1000e/e1000e_ich8lan.h
  34. 0
    1883
      src/drivers/net/e1000e/e1000e_mac.c
  35. 0
    79
      src/drivers/net/e1000e/e1000e_mac.h
  36. 0
    1282
      src/drivers/net/e1000e/e1000e_main.c
  37. 0
    372
      src/drivers/net/e1000e/e1000e_manage.c
  38. 0
    86
      src/drivers/net/e1000e/e1000e_manage.h
  39. 0
    596
      src/drivers/net/e1000e/e1000e_nvm.c
  40. 0
    53
      src/drivers/net/e1000e/e1000e_nvm.h
  41. 0
    3326
      src/drivers/net/e1000e/e1000e_phy.c
  42. 0
    261
      src/drivers/net/e1000e/e1000e_phy.h
  43. 0
    340
      src/drivers/net/e1000e/e1000e_regs.h
  44. 0
    32
      src/drivers/net/igb/igb.c
  45. 0
    324
      src/drivers/net/igb/igb.h
  46. 0
    1617
      src/drivers/net/igb/igb_82575.c
  47. 0
    442
      src/drivers/net/igb/igb_82575.h
  48. 0
    1108
      src/drivers/net/igb/igb_api.c
  49. 0
    166
      src/drivers/net/igb/igb_api.h
  50. 0
    1515
      src/drivers/net/igb/igb_defines.h
  51. 0
    697
      src/drivers/net/igb/igb_hw.h
  52. 0
    1991
      src/drivers/net/igb/igb_mac.c
  53. 0
    82
      src/drivers/net/igb/igb_mac.h
  54. 0
    1010
      src/drivers/net/igb/igb_main.c
  55. 0
    388
      src/drivers/net/igb/igb_manage.c
  56. 0
    83
      src/drivers/net/igb/igb_manage.h
  57. 0
    627
      src/drivers/net/igb/igb_nvm.c
  58. 0
    52
      src/drivers/net/igb/igb_nvm.h
  59. 0
    124
      src/drivers/net/igb/igb_osdep.h
  60. 0
    2470
      src/drivers/net/igb/igb_phy.c
  61. 0
    171
      src/drivers/net/igb/igb_phy.h
  62. 0
    486
      src/drivers/net/igb/igb_regs.h
  63. 946
    0
      src/drivers/net/intel.c
  64. 252
    0
      src/drivers/net/intel.h
  65. 1
    0
      src/include/ipxe/errfile.h

+ 0
- 35
src/drivers/net/e1000/e1000.c Прегледај датотеку

@@ -1,35 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2008 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_ONLY );
30
-
31
-REQUIRE_OBJECT(e1000_main);
32
-REQUIRE_OBJECT(e1000_82540);
33
-REQUIRE_OBJECT(e1000_82541);
34
-REQUIRE_OBJECT(e1000_82542);
35
-REQUIRE_OBJECT(e1000_82543);

+ 0
- 326
src/drivers/net/e1000/e1000.h Прегледај датотеку

@@ -1,326 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2008 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_ONLY );
30
-
31
-/* Linux PRO/1000 Ethernet Driver main header file */
32
-
33
-#ifndef _E1000_H_
34
-#define _E1000_H_
35
-
36
-#include "e1000_api.h"
37
-
38
-#define BAR_0		0
39
-#define BAR_1		1
40
-#define BAR_5		5
41
-
42
-struct e1000_adapter;
43
-
44
-/* TX/RX descriptor defines */
45
-#define E1000_DEFAULT_TXD                  256
46
-#define E1000_MAX_TXD                      256
47
-#define E1000_MIN_TXD                       80
48
-#define E1000_MAX_82544_TXD               4096
49
-
50
-#define E1000_DEFAULT_TXD_PWR               12
51
-#define E1000_MAX_TXD_PWR                   12
52
-#define E1000_MIN_TXD_PWR                    7
53
-
54
-#define E1000_DEFAULT_RXD                  256
55
-#define E1000_MAX_RXD                      256
56
-
57
-#define E1000_MIN_RXD                       80
58
-#define E1000_MAX_82544_RXD               4096
59
-
60
-#define E1000_MIN_ITR_USECS                 10 /* 100000 irq/sec */
61
-#define E1000_MAX_ITR_USECS              10000 /* 100    irq/sec */
62
-
63
-
64
-/* this is the size past which hardware will drop packets when setting LPE=0 */
65
-#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
66
-
67
-/* Supported Rx Buffer Sizes */
68
-#define E1000_RXBUFFER_128   128
69
-#define E1000_RXBUFFER_256   256
70
-#define E1000_RXBUFFER_512   512
71
-#define E1000_RXBUFFER_1024  1024
72
-#define E1000_RXBUFFER_2048  2048
73
-#define E1000_RXBUFFER_4096  4096
74
-#define E1000_RXBUFFER_8192  8192
75
-#define E1000_RXBUFFER_16384 16384
76
-
77
-/* SmartSpeed delimiters */
78
-#define E1000_SMARTSPEED_DOWNSHIFT 3
79
-#define E1000_SMARTSPEED_MAX       15
80
-
81
-/* Packet Buffer allocations */
82
-#define E1000_PBA_BYTES_SHIFT 0xA
83
-#define E1000_TX_HEAD_ADDR_SHIFT 7
84
-#define E1000_PBA_TX_MASK 0xFFFF0000
85
-
86
-/* Early Receive defines */
87
-#define E1000_ERT_2048 0x100
88
-
89
-#define E1000_FC_PAUSE_TIME 0x0680 /* 858 usec */
90
-
91
-/* How many Tx Descriptors do we need to call netif_wake_queue ? */
92
-#define E1000_TX_QUEUE_WAKE	16
93
-/* How many Rx Buffers do we bundle into one write to the hardware ? */
94
-#define E1000_RX_BUFFER_WRITE	16	/* Must be power of 2 */
95
-
96
-#define AUTO_ALL_MODES            0
97
-#define E1000_EEPROM_82544_APM    0x0004
98
-#define E1000_EEPROM_APME         0x0400
99
-
100
-/* wrapper around a pointer to a socket buffer,
101
- * so a DMA handle can be stored along with the buffer */
102
-struct e1000_buffer {
103
-	struct sk_buff *skb;
104
-	dma_addr_t dma;
105
-	unsigned long time_stamp;
106
-	u16 length;
107
-	u16 next_to_watch;
108
-};
109
-
110
-struct e1000_rx_buffer {
111
-	struct sk_buff *skb;
112
-	dma_addr_t dma;
113
-	struct page *page;
114
-};
115
-
116
-
117
-
118
-struct e1000_tx_ring {
119
-	/* pointer to the descriptor ring memory */
120
-	void *desc;
121
-	/* physical address of the descriptor ring */
122
-	dma_addr_t dma;
123
-	/* length of descriptor ring in bytes */
124
-	unsigned int size;
125
-	/* number of descriptors in the ring */
126
-	unsigned int count;
127
-	/* next descriptor to associate a buffer with */
128
-	unsigned int next_to_use;
129
-	/* next descriptor to check for DD status bit */
130
-	unsigned int next_to_clean;
131
-	/* array of buffer information structs */
132
-	struct e1000_buffer *buffer_info;
133
-
134
-	spinlock_t tx_lock;
135
-	u16 tdh;
136
-	u16 tdt;
137
-
138
-	/* TXDdescriptor index increment to be used when advancing
139
-	* to the next descriptor. This is normally one, but on some
140
-	* architectures, but on some architectures there are cache
141
-	* coherency issues that require only the first descriptor in
142
-	* cache line can be used.
143
-	*/
144
-	unsigned int step;
145
-
146
-	bool last_tx_tso;
147
-};
148
-
149
-struct e1000_rx_ring {
150
-	struct e1000_adapter *adapter; /* back link */
151
-	/* pointer to the descriptor ring memory */
152
-	void *desc;
153
-	/* physical address of the descriptor ring */
154
-	dma_addr_t dma;
155
-	/* length of descriptor ring in bytes */
156
-	unsigned int size;
157
-	/* number of descriptors in the ring */
158
-	unsigned int count;
159
-	/* next descriptor to associate a buffer with */
160
-	unsigned int next_to_use;
161
-	/* next descriptor to check for DD status bit */
162
-	unsigned int next_to_clean;
163
-	/* array of buffer information structs */
164
-	struct e1000_rx_buffer *buffer_info;
165
-	struct sk_buff *rx_skb_top;
166
-
167
-	/* cpu for rx queue */
168
-	int cpu;
169
-
170
-	u16 rdh;
171
-	u16 rdt;
172
-};
173
-
174
-
175
-#define E1000_TX_DESC_INC(R,index) \
176
-	{index += (R)->step; if (index == (R)->count) index = 0; }
177
-
178
-#define E1000_TX_DESC_DEC(R,index) \
179
-	{ if (index == 0) index = (R)->count - (R)->step; \
180
-	else index -= (R)->step; }
181
-
182
-#define E1000_DESC_UNUSED(R) \
183
-	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
184
-	(R)->next_to_clean - (R)->next_to_use - 1)
185
-
186
-#define E1000_RX_DESC_EXT(R, i)	    \
187
-	(&(((union e1000_rx_desc_extended *)((R).desc))[i]))
188
-#define E1000_GET_DESC(R, i, type)	(&(((struct type *)((R).desc))[i]))
189
-#define E1000_RX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_rx_desc)
190
-#define E1000_TX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_tx_desc)
191
-#define E1000_CONTEXT_DESC(R, i)	E1000_GET_DESC(R, i, e1000_context_desc)
192
-
193
-/* board specific private data structure */
194
-
195
-struct e1000_adapter {
196
-	u32 bd_number;
197
-	u32 rx_buffer_len;
198
-	u32 wol;
199
-	u32 smartspeed;
200
-	u32 en_mng_pt;
201
-	u16 link_speed;
202
-	u16 link_duplex;
203
-	spinlock_t stats_lock;
204
-	unsigned int total_tx_bytes;
205
-	unsigned int total_tx_packets;
206
-	unsigned int total_rx_bytes;
207
-	unsigned int total_rx_packets;
208
-	/* Interrupt Throttle Rate */
209
-	u32 itr;
210
-	u32 itr_setting;
211
-	u16 tx_itr;
212
-	u16 rx_itr;
213
-
214
-	bool fc_autoneg;
215
-
216
-	/* TX */
217
-	struct e1000_tx_ring *tx_ring;
218
-	unsigned int restart_queue;
219
-	unsigned long tx_queue_len;
220
-	u32 txd_cmd;
221
-	u32 tx_int_delay;
222
-	u32 tx_abs_int_delay;
223
-	u32 gotc;
224
-	u64 gotc_old;
225
-	u64 tpt_old;
226
-	u64 colc_old;
227
-	u32 tx_timeout_count;
228
-	u32 tx_fifo_head;
229
-	u32 tx_head_addr;
230
-	u32 tx_fifo_size;
231
-	u8 tx_timeout_factor;
232
-	bool pcix_82544;
233
-	bool detect_tx_hung;
234
-
235
-	/* RX */
236
-	bool (*clean_rx) (struct e1000_adapter *adapter,
237
-			       struct e1000_rx_ring *rx_ring);
238
-	void (*alloc_rx_buf) (struct e1000_adapter *adapter,
239
-			      struct e1000_rx_ring *rx_ring,
240
-				int cleaned_count);
241
-	struct e1000_rx_ring *rx_ring;
242
-
243
-	u64 hw_csum_err;
244
-	u64 hw_csum_good;
245
-	u32 alloc_rx_buff_failed;
246
-	u32 rx_int_delay;
247
-	u32 rx_abs_int_delay;
248
-	bool rx_csum;
249
-	u32 gorc;
250
-	u64 gorc_old;
251
-	u32 max_frame_size;
252
-	u32 min_frame_size;
253
-
254
-
255
-	/* OS defined structs */
256
-	struct net_device *netdev;
257
-	struct pci_device *pdev;
258
-	struct net_device_stats net_stats;
259
-
260
-	/* structs defined in e1000_hw.h */
261
-	struct e1000_hw hw;
262
-	struct e1000_hw_stats stats;
263
-	struct e1000_phy_info phy_info;
264
-	struct e1000_phy_stats phy_stats;
265
-
266
-	int msg_enable;
267
-	/* to not mess up cache alignment, always add to the bottom */
268
-	unsigned long state;
269
-	u32 eeprom_wol;
270
-
271
-	u32 *config_space;
272
-
273
-	/* hardware capability, feature, and workaround flags */
274
-	unsigned int flags;
275
-
276
-	/* upper limit parameter for tx desc size */
277
-	u32 tx_desc_pwr;
278
-
279
-#define NUM_TX_DESC	8
280
-#define NUM_RX_DESC	8
281
-
282
-	struct io_buffer *tx_iobuf[NUM_TX_DESC];
283
-	struct io_buffer *rx_iobuf[NUM_RX_DESC];
284
-
285
-	struct e1000_tx_desc *tx_base;
286
-	struct e1000_rx_desc *rx_base;
287
-
288
-	uint32_t tx_ring_size;
289
-	uint32_t rx_ring_size;
290
-
291
-	uint32_t tx_head;
292
-	uint32_t tx_tail;
293
-	uint32_t tx_fill_ctr;
294
-
295
-	uint32_t rx_curr;
296
-
297
-	uint32_t ioaddr;
298
-	uint32_t irqno;
299
-};
300
-
301
-#define E1000_FLAG_HAS_SMBUS                (1 << 0)
302
-#define E1000_FLAG_HAS_INTR_MODERATION      (1 << 4)
303
-#define E1000_FLAG_BAD_TX_CARRIER_STATS_FD  (1 << 6)
304
-#define E1000_FLAG_QUAD_PORT_A              (1 << 8)
305
-#define E1000_FLAG_SMART_POWER_DOWN         (1 << 9)
306
-
307
-extern char e1000_driver_name[];
308
-extern const char e1000_driver_version[];
309
-
310
-extern void e1000_power_up_phy(struct e1000_hw *hw);
311
-
312
-extern void e1000_set_ethtool_ops(struct net_device *netdev);
313
-extern void e1000_check_options(struct e1000_adapter *adapter);
314
-
315
-extern int e1000_up(struct e1000_adapter *adapter);
316
-extern void e1000_down(struct e1000_adapter *adapter);
317
-extern void e1000_reinit_locked(struct e1000_adapter *adapter);
318
-extern void e1000_reset(struct e1000_adapter *adapter);
319
-extern int e1000_set_spd_dplx(struct e1000_adapter *adapter, u16 spddplx);
320
-extern int e1000_setup_all_rx_resources(struct e1000_adapter *adapter);
321
-extern int e1000_setup_all_tx_resources(struct e1000_adapter *adapter);
322
-extern void e1000_free_all_rx_resources(struct e1000_adapter *adapter);
323
-extern void e1000_free_all_tx_resources(struct e1000_adapter *adapter);
324
-extern void e1000_update_stats(struct e1000_adapter *adapter);
325
-
326
-#endif /* _E1000_H_ */

+ 0
- 754
src/drivers/net/e1000/e1000_82540.c Прегледај датотеку

@@ -1,754 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2008 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-/*
32
- * 82540EM Gigabit Ethernet Controller
33
- * 82540EP Gigabit Ethernet Controller
34
- * 82545EM Gigabit Ethernet Controller (Copper)
35
- * 82545EM Gigabit Ethernet Controller (Fiber)
36
- * 82545GM Gigabit Ethernet Controller
37
- * 82546EB Gigabit Ethernet Controller (Copper)
38
- * 82546EB Gigabit Ethernet Controller (Fiber)
39
- * 82546GB Gigabit Ethernet Controller
40
- */
41
-
42
-#include "e1000_api.h"
43
-
44
-static s32  e1000_init_phy_params_82540(struct e1000_hw *hw);
45
-static s32  e1000_init_nvm_params_82540(struct e1000_hw *hw);
46
-static s32  e1000_init_mac_params_82540(struct e1000_hw *hw);
47
-static s32  e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw);
48
-static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw);
49
-static s32  e1000_init_hw_82540(struct e1000_hw *hw);
50
-static s32  e1000_reset_hw_82540(struct e1000_hw *hw);
51
-static s32  e1000_set_phy_mode_82540(struct e1000_hw *hw);
52
-static s32  e1000_set_vco_speed_82540(struct e1000_hw *hw);
53
-static s32  e1000_setup_copper_link_82540(struct e1000_hw *hw);
54
-static s32  e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw);
55
-static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw);
56
-static s32  e1000_read_mac_addr_82540(struct e1000_hw *hw);
57
-
58
-/**
59
- * e1000_init_phy_params_82540 - Init PHY func ptrs.
60
- * @hw: pointer to the HW structure
61
- **/
62
-static s32 e1000_init_phy_params_82540(struct e1000_hw *hw)
63
-{
64
-	struct e1000_phy_info *phy = &hw->phy;
65
-	s32 ret_val = E1000_SUCCESS;
66
-
67
-	phy->addr                      = 1;
68
-	phy->autoneg_mask              = AUTONEG_ADVERTISE_SPEED_DEFAULT;
69
-	phy->reset_delay_us            = 10000;
70
-	phy->type                      = e1000_phy_m88;
71
-
72
-	/* Function Pointers */
73
-	phy->ops.check_polarity        = e1000_check_polarity_m88;
74
-	phy->ops.commit                = e1000_phy_sw_reset_generic;
75
-#if 0
76
-	phy->ops.force_speed_duplex    = e1000_phy_force_speed_duplex_m88;
77
-#endif
78
-#if 0
79
-	phy->ops.get_cable_length      = e1000_get_cable_length_m88;
80
-#endif
81
-	phy->ops.get_cfg_done          = e1000_get_cfg_done_generic;
82
-	phy->ops.read_reg              = e1000_read_phy_reg_m88;
83
-	phy->ops.reset                 = e1000_phy_hw_reset_generic;
84
-	phy->ops.write_reg             = e1000_write_phy_reg_m88;
85
-	phy->ops.get_info              = e1000_get_phy_info_m88;
86
-	phy->ops.power_up              = e1000_power_up_phy_copper;
87
-	phy->ops.power_down            = e1000_power_down_phy_copper_82540;
88
-
89
-	ret_val = e1000_get_phy_id(hw);
90
-	if (ret_val)
91
-		goto out;
92
-
93
-	/* Verify phy id */
94
-	switch (hw->mac.type) {
95
-	case e1000_82540:
96
-	case e1000_82545:
97
-	case e1000_82545_rev_3:
98
-	case e1000_82546:
99
-	case e1000_82546_rev_3:
100
-		if (phy->id == M88E1011_I_PHY_ID)
101
-			break;
102
-		/* Fall Through */
103
-	default:
104
-		ret_val = -E1000_ERR_PHY;
105
-		goto out;
106
-		break;
107
-	}
108
-
109
-out:
110
-	return ret_val;
111
-}
112
-
113
-/**
114
- * e1000_init_nvm_params_82540 - Init NVM func ptrs.
115
- * @hw: pointer to the HW structure
116
- **/
117
-static s32 e1000_init_nvm_params_82540(struct e1000_hw *hw)
118
-{
119
-	struct e1000_nvm_info *nvm = &hw->nvm;
120
-	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
121
-
122
-	DEBUGFUNC("e1000_init_nvm_params_82540");
123
-
124
-	nvm->type               = e1000_nvm_eeprom_microwire;
125
-	nvm->delay_usec         = 50;
126
-	nvm->opcode_bits        = 3;
127
-	switch (nvm->override) {
128
-	case e1000_nvm_override_microwire_large:
129
-		nvm->address_bits       = 8;
130
-		nvm->word_size          = 256;
131
-		break;
132
-	case e1000_nvm_override_microwire_small:
133
-		nvm->address_bits       = 6;
134
-		nvm->word_size          = 64;
135
-		break;
136
-	default:
137
-		nvm->address_bits       = eecd & E1000_EECD_SIZE ? 8 : 6;
138
-		nvm->word_size          = eecd & E1000_EECD_SIZE ? 256 : 64;
139
-		break;
140
-	}
141
-
142
-	/* Function Pointers */
143
-	nvm->ops.acquire            = e1000_acquire_nvm_generic;
144
-	nvm->ops.read               = e1000_read_nvm_microwire;
145
-	nvm->ops.release            = e1000_release_nvm_generic;
146
-	nvm->ops.update             = e1000_update_nvm_checksum_generic;
147
-	nvm->ops.valid_led_default  = e1000_valid_led_default_generic;
148
-	nvm->ops.validate           = e1000_validate_nvm_checksum_generic;
149
-	nvm->ops.write              = e1000_write_nvm_microwire;
150
-
151
-	return E1000_SUCCESS;
152
-}
153
-
154
-/**
155
- * e1000_init_mac_params_82540 - Init MAC func ptrs.
156
- * @hw: pointer to the HW structure
157
- **/
158
-static s32 e1000_init_mac_params_82540(struct e1000_hw *hw)
159
-{
160
-	struct e1000_mac_info *mac = &hw->mac;
161
-	s32 ret_val = E1000_SUCCESS;
162
-
163
-	DEBUGFUNC("e1000_init_mac_params_82540");
164
-
165
-	/* Set media type */
166
-	switch (hw->device_id) {
167
-	case E1000_DEV_ID_82545EM_FIBER:
168
-	case E1000_DEV_ID_82545GM_FIBER:
169
-	case E1000_DEV_ID_82546EB_FIBER:
170
-	case E1000_DEV_ID_82546GB_FIBER:
171
-		hw->phy.media_type = e1000_media_type_fiber;
172
-		break;
173
-	case E1000_DEV_ID_82545GM_SERDES:
174
-	case E1000_DEV_ID_82546GB_SERDES:
175
-		hw->phy.media_type = e1000_media_type_internal_serdes;
176
-		break;
177
-	default:
178
-		hw->phy.media_type = e1000_media_type_copper;
179
-		break;
180
-	}
181
-
182
-	/* Set mta register count */
183
-	mac->mta_reg_count = 128;
184
-	/* Set rar entry count */
185
-	mac->rar_entry_count = E1000_RAR_ENTRIES;
186
-
187
-	/* Function pointers */
188
-
189
-	/* bus type/speed/width */
190
-	mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
191
-	/* function id */
192
-	mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
193
-	/* reset */
194
-	mac->ops.reset_hw = e1000_reset_hw_82540;
195
-	/* hw initialization */
196
-	mac->ops.init_hw = e1000_init_hw_82540;
197
-	/* link setup */
198
-	mac->ops.setup_link = e1000_setup_link_generic;
199
-	/* physical interface setup */
200
-	mac->ops.setup_physical_interface =
201
-	        (hw->phy.media_type == e1000_media_type_copper)
202
-	                ? e1000_setup_copper_link_82540
203
-	                : e1000_setup_fiber_serdes_link_82540;
204
-	/* check for link */
205
-	switch (hw->phy.media_type) {
206
-	case e1000_media_type_copper:
207
-		mac->ops.check_for_link = e1000_check_for_copper_link_generic;
208
-		break;
209
-	case e1000_media_type_fiber:
210
-		mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
211
-		break;
212
-	case e1000_media_type_internal_serdes:
213
-		mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
214
-		break;
215
-	default:
216
-		ret_val = -E1000_ERR_CONFIG;
217
-		goto out;
218
-		break;
219
-	}
220
-	/* link info */
221
-	mac->ops.get_link_up_info =
222
-	        (hw->phy.media_type == e1000_media_type_copper)
223
-	                ? e1000_get_speed_and_duplex_copper_generic
224
-	                : e1000_get_speed_and_duplex_fiber_serdes_generic;
225
-	/* multicast address update */
226
-	mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
227
-	/* writing VFTA */
228
-	mac->ops.write_vfta = e1000_write_vfta_generic;
229
-	/* clearing VFTA */
230
-	mac->ops.clear_vfta = e1000_clear_vfta_generic;
231
-	/* setting MTA */
232
-	mac->ops.mta_set = e1000_mta_set_generic;
233
-	/* read mac address */
234
-	mac->ops.read_mac_addr = e1000_read_mac_addr_82540;
235
-	/* ID LED init */
236
-	mac->ops.id_led_init = e1000_id_led_init_generic;
237
-	/* setup LED */
238
-	mac->ops.setup_led = e1000_setup_led_generic;
239
-	/* cleanup LED */
240
-	mac->ops.cleanup_led = e1000_cleanup_led_generic;
241
-	/* turn on/off LED */
242
-	mac->ops.led_on = e1000_led_on_generic;
243
-	mac->ops.led_off = e1000_led_off_generic;
244
-	/* clear hardware counters */
245
-	mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82540;
246
-
247
-out:
248
-	return ret_val;
249
-}
250
-
251
-/**
252
- * e1000_init_function_pointers_82540 - Init func ptrs.
253
- * @hw: pointer to the HW structure
254
- *
255
- * Called to initialize all function pointers and parameters.
256
- **/
257
-void e1000_init_function_pointers_82540(struct e1000_hw *hw)
258
-{
259
-	DEBUGFUNC("e1000_init_function_pointers_82540");
260
-
261
-	hw->mac.ops.init_params = e1000_init_mac_params_82540;
262
-	hw->nvm.ops.init_params = e1000_init_nvm_params_82540;
263
-	hw->phy.ops.init_params = e1000_init_phy_params_82540;
264
-}
265
-
266
-/**
267
- *  e1000_reset_hw_82540 - Reset hardware
268
- *  @hw: pointer to the HW structure
269
- *
270
- *  This resets the hardware into a known state.
271
- **/
272
-static s32 e1000_reset_hw_82540(struct e1000_hw *hw)
273
-{
274
-	u32 ctrl, manc;
275
-	s32 ret_val = E1000_SUCCESS;
276
-
277
-	DEBUGFUNC("e1000_reset_hw_82540");
278
-
279
-	DEBUGOUT("Masking off all interrupts\n");
280
-	E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
281
-
282
-	E1000_WRITE_REG(hw, E1000_RCTL, 0);
283
-	E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
284
-	E1000_WRITE_FLUSH(hw);
285
-
286
-	/*
287
-	 * Delay to allow any outstanding PCI transactions to complete
288
-	 * before resetting the device.
289
-	 */
290
-	msec_delay(10);
291
-
292
-	ctrl = E1000_READ_REG(hw, E1000_CTRL);
293
-
294
-	DEBUGOUT("Issuing a global reset to 82540/82545/82546 MAC\n");
295
-	switch (hw->mac.type) {
296
-	case e1000_82545_rev_3:
297
-	case e1000_82546_rev_3:
298
-		E1000_WRITE_REG(hw, E1000_CTRL_DUP, ctrl | E1000_CTRL_RST);
299
-		break;
300
-	default:
301
-		/*
302
-		 * These controllers can't ack the 64-bit write when
303
-		 * issuing the reset, so we use IO-mapping as a
304
-		 * workaround to issue the reset.
305
-		 */
306
-		E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
307
-		break;
308
-	}
309
-
310
-	/* Wait for EEPROM reload */
311
-	msec_delay(5);
312
-
313
-	/* Disable HW ARPs on ASF enabled adapters */
314
-	manc = E1000_READ_REG(hw, E1000_MANC);
315
-	manc &= ~E1000_MANC_ARP_EN;
316
-	E1000_WRITE_REG(hw, E1000_MANC, manc);
317
-
318
-	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
319
-	E1000_READ_REG(hw, E1000_ICR);
320
-
321
-	return ret_val;
322
-}
323
-
324
-/**
325
- *  e1000_init_hw_82540 - Initialize hardware
326
- *  @hw: pointer to the HW structure
327
- *
328
- *  This inits the hardware readying it for operation.
329
- **/
330
-static s32 e1000_init_hw_82540(struct e1000_hw *hw)
331
-{
332
-	struct e1000_mac_info *mac = &hw->mac;
333
-	u32 txdctl, ctrl_ext;
334
-	s32 ret_val = E1000_SUCCESS;
335
-	u16 i;
336
-
337
-	DEBUGFUNC("e1000_init_hw_82540");
338
-
339
-	/* Initialize identification LED */
340
-	ret_val = mac->ops.id_led_init(hw);
341
-	if (ret_val) {
342
-		DEBUGOUT("Error initializing identification LED\n");
343
-		/* This is not fatal and we should not stop init due to this */
344
-	}
345
-
346
-	/* Disabling VLAN filtering */
347
-	DEBUGOUT("Initializing the IEEE VLAN\n");
348
-	if (mac->type < e1000_82545_rev_3)
349
-		E1000_WRITE_REG(hw, E1000_VET, 0);
350
-
351
-	mac->ops.clear_vfta(hw);
352
-
353
-	/* Setup the receive address. */
354
-	e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
355
-
356
-	/* Zero out the Multicast HASH table */
357
-	DEBUGOUT("Zeroing the MTA\n");
358
-	for (i = 0; i < mac->mta_reg_count; i++) {
359
-		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
360
-		/*
361
-		 * Avoid back to back register writes by adding the register
362
-		 * read (flush).  This is to protect against some strange
363
-		 * bridge configurations that may issue Memory Write Block
364
-		 * (MWB) to our register space.  The *_rev_3 hardware at
365
-		 * least doesn't respond correctly to every other dword in an
366
-		 * MWB to our register space.
367
-		 */
368
-		E1000_WRITE_FLUSH(hw);
369
-	}
370
-
371
-	if (mac->type < e1000_82545_rev_3)
372
-		e1000_pcix_mmrbc_workaround_generic(hw);
373
-
374
-	/* Setup link and flow control */
375
-	ret_val = mac->ops.setup_link(hw);
376
-
377
-	txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0));
378
-	txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) |
379
-	         E1000_TXDCTL_FULL_TX_DESC_WB;
380
-	E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl);
381
-
382
-	/*
383
-	 * Clear all of the statistics registers (clear on read).  It is
384
-	 * important that we do this after we have tried to establish link
385
-	 * because the symbol error count will increment wildly if there
386
-	 * is no link.
387
-	 */
388
-	e1000_clear_hw_cntrs_82540(hw);
389
-
390
-	if ((hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER) ||
391
-	    (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3)) {
392
-		ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
393
-		/*
394
-		 * Relaxed ordering must be disabled to avoid a parity
395
-		 * error crash in a PCI slot.
396
-		 */
397
-		ctrl_ext |= E1000_CTRL_EXT_RO_DIS;
398
-		E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
399
-	}
400
-
401
-	return ret_val;
402
-}
403
-
404
-/**
405
- *  e1000_setup_copper_link_82540 - Configure copper link settings
406
- *  @hw: pointer to the HW structure
407
- *
408
- *  Calls the appropriate function to configure the link for auto-neg or forced
409
- *  speed and duplex.  Then we check for link, once link is established calls
410
- *  to configure collision distance and flow control are called.  If link is
411
- *  not established, we return -E1000_ERR_PHY (-2).
412
- **/
413
-static s32 e1000_setup_copper_link_82540(struct e1000_hw *hw)
414
-{
415
-	u32 ctrl;
416
-	s32 ret_val = E1000_SUCCESS;
417
-	u16 data;
418
-
419
-	DEBUGFUNC("e1000_setup_copper_link_82540");
420
-
421
-	ctrl = E1000_READ_REG(hw, E1000_CTRL);
422
-	ctrl |= E1000_CTRL_SLU;
423
-	ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
424
-	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
425
-
426
-	ret_val = e1000_set_phy_mode_82540(hw);
427
-	if (ret_val)
428
-		goto out;
429
-
430
-	if (hw->mac.type == e1000_82545_rev_3 ||
431
-	    hw->mac.type == e1000_82546_rev_3) {
432
-		ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &data);
433
-		if (ret_val)
434
-			goto out;
435
-		data |= 0x00000008;
436
-		ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, data);
437
-		if (ret_val)
438
-			goto out;
439
-	}
440
-
441
-	ret_val = e1000_copper_link_setup_m88(hw);
442
-	if (ret_val)
443
-		goto out;
444
-
445
-	ret_val = e1000_setup_copper_link_generic(hw);
446
-
447
-out:
448
-	return ret_val;
449
-}
450
-
451
-/**
452
- *  e1000_setup_fiber_serdes_link_82540 - Setup link for fiber/serdes
453
- *  @hw: pointer to the HW structure
454
- *
455
- *  Set the output amplitude to the value in the EEPROM and adjust the VCO
456
- *  speed to improve Bit Error Rate (BER) performance.  Configures collision
457
- *  distance and flow control for fiber and serdes links.  Upon successful
458
- *  setup, poll for link.
459
- **/
460
-static s32 e1000_setup_fiber_serdes_link_82540(struct e1000_hw *hw)
461
-{
462
-	struct e1000_mac_info *mac = &hw->mac;
463
-	s32 ret_val = E1000_SUCCESS;
464
-
465
-	DEBUGFUNC("e1000_setup_fiber_serdes_link_82540");
466
-
467
-	switch (mac->type) {
468
-	case e1000_82545_rev_3:
469
-	case e1000_82546_rev_3:
470
-		if (hw->phy.media_type == e1000_media_type_internal_serdes) {
471
-			/*
472
-			 * If we're on serdes media, adjust the output
473
-			 * amplitude to value set in the EEPROM.
474
-			 */
475
-			ret_val = e1000_adjust_serdes_amplitude_82540(hw);
476
-			if (ret_val)
477
-				goto out;
478
-		}
479
-		/* Adjust VCO speed to improve BER performance */
480
-		ret_val = e1000_set_vco_speed_82540(hw);
481
-		if (ret_val)
482
-			goto out;
483
-	default:
484
-		break;
485
-	}
486
-
487
-	ret_val = e1000_setup_fiber_serdes_link_generic(hw);
488
-
489
-out:
490
-	return ret_val;
491
-}
492
-
493
-/**
494
- *  e1000_adjust_serdes_amplitude_82540 - Adjust amplitude based on EEPROM
495
- *  @hw: pointer to the HW structure
496
- *
497
- *  Adjust the SERDES output amplitude based on the EEPROM settings.
498
- **/
499
-static s32 e1000_adjust_serdes_amplitude_82540(struct e1000_hw *hw)
500
-{
501
-	s32 ret_val = E1000_SUCCESS;
502
-	u16 nvm_data;
503
-
504
-	DEBUGFUNC("e1000_adjust_serdes_amplitude_82540");
505
-
506
-	ret_val = hw->nvm.ops.read(hw, NVM_SERDES_AMPLITUDE, 1, &nvm_data);
507
-	if (ret_val)
508
-		goto out;
509
-
510
-	if (nvm_data != NVM_RESERVED_WORD) {
511
-		/* Adjust serdes output amplitude only. */
512
-		nvm_data &= NVM_SERDES_AMPLITUDE_MASK;
513
-		ret_val = hw->phy.ops.write_reg(hw,
514
-		                             M88E1000_PHY_EXT_CTRL,
515
-		                             nvm_data);
516
-		if (ret_val)
517
-			goto out;
518
-	}
519
-
520
-out:
521
-	return ret_val;
522
-}
523
-
524
-/**
525
- *  e1000_set_vco_speed_82540 - Set VCO speed for better performance
526
- *  @hw: pointer to the HW structure
527
- *
528
- *  Set the VCO speed to improve Bit Error Rate (BER) performance.
529
- **/
530
-static s32 e1000_set_vco_speed_82540(struct e1000_hw *hw)
531
-{
532
-	s32  ret_val = E1000_SUCCESS;
533
-	u16 default_page = 0;
534
-	u16 phy_data;
535
-
536
-	DEBUGFUNC("e1000_set_vco_speed_82540");
537
-
538
-	/* Set PHY register 30, page 5, bit 8 to 0 */
539
-
540
-	ret_val = hw->phy.ops.read_reg(hw,
541
-	                            M88E1000_PHY_PAGE_SELECT,
542
-	                            &default_page);
543
-	if (ret_val)
544
-		goto out;
545
-
546
-	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
547
-	if (ret_val)
548
-		goto out;
549
-
550
-	ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
551
-	if (ret_val)
552
-		goto out;
553
-
554
-	phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
555
-	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
556
-	if (ret_val)
557
-		goto out;
558
-
559
-	/* Set PHY register 30, page 4, bit 11 to 1 */
560
-
561
-	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
562
-	if (ret_val)
563
-		goto out;
564
-
565
-	ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
566
-	if (ret_val)
567
-		goto out;
568
-
569
-	phy_data |= M88E1000_PHY_VCO_REG_BIT11;
570
-	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
571
-	if (ret_val)
572
-		goto out;
573
-
574
-	ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
575
-	                              default_page);
576
-
577
-out:
578
-	return ret_val;
579
-}
580
-
581
-/**
582
- *  e1000_set_phy_mode_82540 - Set PHY to class A mode
583
- *  @hw: pointer to the HW structure
584
- *
585
- *  Sets the PHY to class A mode and assumes the following operations will
586
- *  follow to enable the new class mode:
587
- *    1.  Do a PHY soft reset.
588
- *    2.  Restart auto-negotiation or force link.
589
- **/
590
-static s32 e1000_set_phy_mode_82540(struct e1000_hw *hw)
591
-{
592
-	struct e1000_phy_info *phy = &hw->phy;
593
-	s32 ret_val = E1000_SUCCESS;
594
-	u16 nvm_data;
595
-
596
-	DEBUGFUNC("e1000_set_phy_mode_82540");
597
-
598
-	if (hw->mac.type != e1000_82545_rev_3)
599
-		goto out;
600
-
601
-	ret_val = hw->nvm.ops.read(hw, NVM_PHY_CLASS_WORD, 1, &nvm_data);
602
-	if (ret_val) {
603
-		ret_val = -E1000_ERR_PHY;
604
-		goto out;
605
-	}
606
-
607
-	if ((nvm_data != NVM_RESERVED_WORD) && (nvm_data & NVM_PHY_CLASS_A)) {
608
-		ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT,
609
-		                              0x000B);
610
-		if (ret_val) {
611
-			ret_val = -E1000_ERR_PHY;
612
-			goto out;
613
-		}
614
-		ret_val = hw->phy.ops.write_reg(hw,
615
-		                              M88E1000_PHY_GEN_CONTROL,
616
-		                              0x8104);
617
-		if (ret_val) {
618
-			ret_val = -E1000_ERR_PHY;
619
-			goto out;
620
-		}
621
-
622
-		phy->reset_disable = false;
623
-	}
624
-
625
-out:
626
-	return ret_val;
627
-}
628
-
629
-/**
630
- * e1000_power_down_phy_copper_82540 - Remove link in case of PHY power down
631
- * @hw: pointer to the HW structure
632
- *
633
- * In the case of a PHY power down to save power, or to turn off link during a
634
- * driver unload, or wake on lan is not enabled, remove the link.
635
- **/
636
-static void e1000_power_down_phy_copper_82540(struct e1000_hw *hw)
637
-{
638
-	/* If the management interface is not enabled, then power down */
639
-	if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN))
640
-		e1000_power_down_phy_copper(hw);
641
-
642
-	return;
643
-}
644
-
645
-/**
646
- *  e1000_clear_hw_cntrs_82540 - Clear device specific hardware counters
647
- *  @hw: pointer to the HW structure
648
- *
649
- *  Clears the hardware counters by reading the counter registers.
650
- **/
651
-static void e1000_clear_hw_cntrs_82540(struct e1000_hw *hw)
652
-{
653
-	DEBUGFUNC("e1000_clear_hw_cntrs_82540");
654
-
655
-	e1000_clear_hw_cntrs_base_generic(hw);
656
-
657
-#if 0
658
-	E1000_READ_REG(hw, E1000_PRC64);
659
-	E1000_READ_REG(hw, E1000_PRC127);
660
-	E1000_READ_REG(hw, E1000_PRC255);
661
-	E1000_READ_REG(hw, E1000_PRC511);
662
-	E1000_READ_REG(hw, E1000_PRC1023);
663
-	E1000_READ_REG(hw, E1000_PRC1522);
664
-	E1000_READ_REG(hw, E1000_PTC64);
665
-	E1000_READ_REG(hw, E1000_PTC127);
666
-	E1000_READ_REG(hw, E1000_PTC255);
667
-	E1000_READ_REG(hw, E1000_PTC511);
668
-	E1000_READ_REG(hw, E1000_PTC1023);
669
-	E1000_READ_REG(hw, E1000_PTC1522);
670
-
671
-	E1000_READ_REG(hw, E1000_ALGNERRC);
672
-	E1000_READ_REG(hw, E1000_RXERRC);
673
-	E1000_READ_REG(hw, E1000_TNCRS);
674
-	E1000_READ_REG(hw, E1000_CEXTERR);
675
-	E1000_READ_REG(hw, E1000_TSCTC);
676
-	E1000_READ_REG(hw, E1000_TSCTFC);
677
-
678
-	E1000_READ_REG(hw, E1000_MGTPRC);
679
-	E1000_READ_REG(hw, E1000_MGTPDC);
680
-	E1000_READ_REG(hw, E1000_MGTPTC);
681
-#endif
682
-}
683
-
684
-/**
685
- *  e1000_read_mac_addr_82540 - Read device MAC address
686
- *  @hw: pointer to the HW structure
687
- *
688
- *  Reads the device MAC address from the EEPROM and stores the value.
689
- *  Since devices with two ports use the same EEPROM, we increment the
690
- *  last bit in the MAC address for the second port.
691
- *
692
- *  This version is being used over generic because of customer issues
693
- *  with VmWare and Virtual Box when using generic. It seems in
694
- *  the emulated 82545, RAR[0] does NOT have a valid address after a
695
- *  reset, this older method works and using this breaks nothing for
696
- *  these legacy adapters.
697
- **/
698
-s32 e1000_read_mac_addr_82540(struct e1000_hw *hw)
699
-{
700
-	s32  ret_val = E1000_SUCCESS;
701
-	u16 offset, nvm_data, i;
702
-
703
-	DEBUGFUNC("e1000_read_mac_addr");
704
-
705
-	for (i = 0; i < ETH_ADDR_LEN; i += 2) {
706
-		offset = i >> 1;
707
-		ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
708
-		if (ret_val) {
709
-			DEBUGOUT("NVM Read Error\n");
710
-			goto out;
711
-		}
712
-		hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
713
-		hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
714
-	}
715
-
716
-	/* Flip last bit of mac address if we're on second port */
717
-	if (hw->bus.func == E1000_FUNC_1)
718
-		hw->mac.perm_addr[5] ^= 1;
719
-
720
-	for (i = 0; i < ETH_ADDR_LEN; i++)
721
-		hw->mac.addr[i] = hw->mac.perm_addr[i];
722
-
723
-out:
724
-	return ret_val;
725
-}
726
-
727
-static struct pci_device_id e1000_82540_nics[] = {
728
-     PCI_ROM(0x8086, 0x100E, "E1000_DEV_ID_82540EM", "E1000_DEV_ID_82540EM", e1000_82540),
729
-     PCI_ROM(0x8086, 0x1015, "E1000_DEV_ID_82540EM_LOM", "E1000_DEV_ID_82540EM_LOM", e1000_82540),
730
-     PCI_ROM(0x8086, 0x1016, "E1000_DEV_ID_82540EP_LOM", "E1000_DEV_ID_82540EP_LOM", e1000_82540),
731
-     PCI_ROM(0x8086, 0x1017, "E1000_DEV_ID_82540EP", "E1000_DEV_ID_82540EP", e1000_82540),
732
-     PCI_ROM(0x8086, 0x101E, "E1000_DEV_ID_82540EP_LP", "E1000_DEV_ID_82540EP_LP", e1000_82540),
733
-     PCI_ROM(0x8086, 0x100F, "E1000_DEV_ID_82545EM_COPPER", "E1000_DEV_ID_82545EM_COPPER", e1000_82545),
734
-     PCI_ROM(0x8086, 0x1011, "E1000_DEV_ID_82545EM_FIBER", "E1000_DEV_ID_82545EM_FIBER", e1000_82545),
735
-     PCI_ROM(0x8086, 0x1026, "E1000_DEV_ID_82545GM_COPPER", "E1000_DEV_ID_82545GM_COPPER", e1000_82545_rev_3),
736
-     PCI_ROM(0x8086, 0x1027, "E1000_DEV_ID_82545GM_FIBER", "E1000_DEV_ID_82545GM_FIBER", e1000_82545_rev_3),
737
-     PCI_ROM(0x8086, 0x1028, "E1000_DEV_ID_82545GM_SERDES", "E1000_DEV_ID_82545GM_SERDES", e1000_82545_rev_3),
738
-     PCI_ROM(0x8086, 0x1010, "E1000_DEV_ID_82546EB_COPPER", "E1000_DEV_ID_82546EB_COPPER", e1000_82546),
739
-     PCI_ROM(0x8086, 0x1012, "E1000_DEV_ID_82546EB_FIBER", "E1000_DEV_ID_82546EB_FIBER", e1000_82546),
740
-     PCI_ROM(0x8086, 0x101D, "E1000_DEV_ID_82546EB_QUAD_COPPER", "E1000_DEV_ID_82546EB_QUAD_COPPER", e1000_82546),
741
-     PCI_ROM(0x8086, 0x1079, "E1000_DEV_ID_82546GB_COPPER", "E1000_DEV_ID_82546GB_COPPER", e1000_82546_rev_3),
742
-     PCI_ROM(0x8086, 0x107A, "E1000_DEV_ID_82546GB_FIBER", "E1000_DEV_ID_82546GB_FIBER", e1000_82546_rev_3),
743
-     PCI_ROM(0x8086, 0x107B, "E1000_DEV_ID_82546GB_SERDES", "E1000_DEV_ID_82546GB_SERDES", e1000_82546_rev_3),
744
-     PCI_ROM(0x8086, 0x108A, "E1000_DEV_ID_82546GB_PCIE", "E1000_DEV_ID_82546GB_PCIE", e1000_82546_rev_3),
745
-     PCI_ROM(0x8086, 0x1099, "E1000_DEV_ID_82546GB_QUAD_COPPER", "E1000_DEV_ID_82546GB_QUAD_COPPER", e1000_82546_rev_3),
746
-     PCI_ROM(0x8086, 0x10B5, "E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3", "E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3", e1000_82546_rev_3),
747
-};
748
-
749
-struct pci_driver e1000_82540_driver __pci_driver = {
750
-	.ids = e1000_82540_nics,
751
-	.id_count = (sizeof (e1000_82540_nics) / sizeof (e1000_82540_nics[0])),
752
-	.probe = e1000_probe,
753
-	.remove = e1000_remove,
754
-};

+ 0
- 1314
src/drivers/net/e1000/e1000_82541.c
Разлика између датотеке није приказан због своје велике величине
Прегледај датотеку


+ 0
- 86
src/drivers/net/e1000/e1000_82541.h Прегледај датотеку

@@ -1,86 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2008 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-#ifndef _E1000_82541_H_
32
-#define _E1000_82541_H_
33
-
34
-#define NVM_WORD_SIZE_BASE_SHIFT_82541 (NVM_WORD_SIZE_BASE_SHIFT + 1)
35
-
36
-#define IGP01E1000_PHY_CHANNEL_NUM                    4
37
-
38
-#define IGP01E1000_PHY_AGC_A                     0x1172
39
-#define IGP01E1000_PHY_AGC_B                     0x1272
40
-#define IGP01E1000_PHY_AGC_C                     0x1472
41
-#define IGP01E1000_PHY_AGC_D                     0x1872
42
-
43
-#define IGP01E1000_PHY_AGC_PARAM_A               0x1171
44
-#define IGP01E1000_PHY_AGC_PARAM_B               0x1271
45
-#define IGP01E1000_PHY_AGC_PARAM_C               0x1471
46
-#define IGP01E1000_PHY_AGC_PARAM_D               0x1871
47
-
48
-#define IGP01E1000_PHY_EDAC_MU_INDEX             0xC000
49
-#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS      0x8000
50
-
51
-#define IGP01E1000_PHY_DSP_RESET                 0x1F33
52
-
53
-#define IGP01E1000_PHY_DSP_FFE                   0x1F35
54
-#define IGP01E1000_PHY_DSP_FFE_CM_CP             0x0069
55
-#define IGP01E1000_PHY_DSP_FFE_DEFAULT           0x002A
56
-
57
-#define IGP01E1000_IEEE_FORCE_GIG                0x0140
58
-#define IGP01E1000_IEEE_RESTART_AUTONEG          0x3300
59
-
60
-#define IGP01E1000_AGC_LENGTH_SHIFT                   7
61
-#define IGP01E1000_AGC_RANGE                         10
62
-
63
-#define FFE_IDLE_ERR_COUNT_TIMEOUT_20                20
64
-#define FFE_IDLE_ERR_COUNT_TIMEOUT_100              100
65
-
66
-#define IGP01E1000_ANALOG_FUSE_STATUS            0x20D0
67
-#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS      0x20D1
68
-#define IGP01E1000_ANALOG_FUSE_CONTROL           0x20DC
69
-#define IGP01E1000_ANALOG_FUSE_BYPASS            0x20DE
70
-
71
-#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED     0x0100
72
-#define IGP01E1000_ANALOG_FUSE_FINE_MASK         0x0F80
73
-#define IGP01E1000_ANALOG_FUSE_COARSE_MASK       0x0070
74
-#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH     0x0040
75
-#define IGP01E1000_ANALOG_FUSE_COARSE_10         0x0010
76
-#define IGP01E1000_ANALOG_FUSE_FINE_1            0x0080
77
-#define IGP01E1000_ANALOG_FUSE_FINE_10           0x0500
78
-#define IGP01E1000_ANALOG_FUSE_POLY_MASK         0xF000
79
-#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
80
-
81
-#define IGP01E1000_MSE_CHANNEL_D                 0x000F
82
-#define IGP01E1000_MSE_CHANNEL_C                 0x00F0
83
-#define IGP01E1000_MSE_CHANNEL_B                 0x0F00
84
-#define IGP01E1000_MSE_CHANNEL_A                 0xF000
85
-
86
-#endif

+ 0
- 571
src/drivers/net/e1000/e1000_82542.c Прегледај датотеку

@@ -1,571 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2008 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-/*
32
- * 82542 Gigabit Ethernet Controller
33
- */
34
-
35
-#include "e1000_api.h"
36
-
37
-static s32  e1000_init_phy_params_82542(struct e1000_hw *hw);
38
-static s32  e1000_init_nvm_params_82542(struct e1000_hw *hw);
39
-static s32  e1000_init_mac_params_82542(struct e1000_hw *hw);
40
-static s32  e1000_get_bus_info_82542(struct e1000_hw *hw);
41
-static s32  e1000_reset_hw_82542(struct e1000_hw *hw);
42
-static s32  e1000_init_hw_82542(struct e1000_hw *hw);
43
-static s32  e1000_setup_link_82542(struct e1000_hw *hw);
44
-static s32  e1000_led_on_82542(struct e1000_hw *hw);
45
-static s32  e1000_led_off_82542(struct e1000_hw *hw);
46
-static void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index);
47
-static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw);
48
-
49
-/**
50
- *  e1000_init_phy_params_82542 - Init PHY func ptrs.
51
- *  @hw: pointer to the HW structure
52
- **/
53
-static s32 e1000_init_phy_params_82542(struct e1000_hw *hw)
54
-{
55
-	struct e1000_phy_info *phy = &hw->phy;
56
-	s32 ret_val = E1000_SUCCESS;
57
-
58
-	DEBUGFUNC("e1000_init_phy_params_82542");
59
-
60
-	phy->type               = e1000_phy_none;
61
-
62
-	return ret_val;
63
-}
64
-
65
-/**
66
- *  e1000_init_nvm_params_82542 - Init NVM func ptrs.
67
- *  @hw: pointer to the HW structure
68
- **/
69
-static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw)
70
-{
71
-	struct e1000_nvm_info *nvm = &hw->nvm;
72
-
73
-	DEBUGFUNC("e1000_init_nvm_params_82542");
74
-
75
-	nvm->address_bits       =  6;
76
-	nvm->delay_usec         = 50;
77
-	nvm->opcode_bits        =  3;
78
-	nvm->type               = e1000_nvm_eeprom_microwire;
79
-	nvm->word_size          = 64;
80
-
81
-	/* Function Pointers */
82
-	nvm->ops.read           = e1000_read_nvm_microwire;
83
-	nvm->ops.release        = e1000_stop_nvm;
84
-	nvm->ops.write          = e1000_write_nvm_microwire;
85
-	nvm->ops.update         = e1000_update_nvm_checksum_generic;
86
-	nvm->ops.validate       = e1000_validate_nvm_checksum_generic;
87
-
88
-	return E1000_SUCCESS;
89
-}
90
-
91
-/**
92
- *  e1000_init_mac_params_82542 - Init MAC func ptrs.
93
- *  @hw: pointer to the HW structure
94
- **/
95
-static s32 e1000_init_mac_params_82542(struct e1000_hw *hw)
96
-{
97
-	struct e1000_mac_info *mac = &hw->mac;
98
-
99
-	DEBUGFUNC("e1000_init_mac_params_82542");
100
-
101
-	/* Set media type */
102
-	hw->phy.media_type = e1000_media_type_fiber;
103
-
104
-	/* Set mta register count */
105
-	mac->mta_reg_count = 128;
106
-	/* Set rar entry count */
107
-	mac->rar_entry_count = E1000_RAR_ENTRIES;
108
-
109
-	/* Function pointers */
110
-
111
-	/* bus type/speed/width */
112
-	mac->ops.get_bus_info = e1000_get_bus_info_82542;
113
-	/* function id */
114
-	mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
115
-	/* reset */
116
-	mac->ops.reset_hw = e1000_reset_hw_82542;
117
-	/* hw initialization */
118
-	mac->ops.init_hw = e1000_init_hw_82542;
119
-	/* link setup */
120
-	mac->ops.setup_link = e1000_setup_link_82542;
121
-	/* phy/fiber/serdes setup */
122
-	mac->ops.setup_physical_interface = e1000_setup_fiber_serdes_link_generic;
123
-	/* check for link */
124
-	mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
125
-	/* multicast address update */
126
-	mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
127
-	/* writing VFTA */
128
-	mac->ops.write_vfta = e1000_write_vfta_generic;
129
-	/* clearing VFTA */
130
-	mac->ops.clear_vfta = e1000_clear_vfta_generic;
131
-	/* setting MTA */
132
-	mac->ops.mta_set = e1000_mta_set_generic;
133
-	/* set RAR */
134
-	mac->ops.rar_set = e1000_rar_set_82542;
135
-	/* turn on/off LED */
136
-	mac->ops.led_on = e1000_led_on_82542;
137
-	mac->ops.led_off = e1000_led_off_82542;
138
-	/* clear hardware counters */
139
-	mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82542;
140
-	/* link info */
141
-	mac->ops.get_link_up_info = e1000_get_speed_and_duplex_fiber_serdes_generic;
142
-
143
-	return E1000_SUCCESS;
144
-}
145
-
146
-/**
147
- *  e1000_init_function_pointers_82542 - Init func ptrs.
148
- *  @hw: pointer to the HW structure
149
- *
150
- *  Called to initialize all function pointers and parameters.
151
- **/
152
-void e1000_init_function_pointers_82542(struct e1000_hw *hw)
153
-{
154
-	DEBUGFUNC("e1000_init_function_pointers_82542");
155
-
156
-	hw->mac.ops.init_params = e1000_init_mac_params_82542;
157
-	hw->nvm.ops.init_params = e1000_init_nvm_params_82542;
158
-	hw->phy.ops.init_params = e1000_init_phy_params_82542;
159
-}
160
-
161
-/**
162
- *  e1000_get_bus_info_82542 - Obtain bus information for adapter
163
- *  @hw: pointer to the HW structure
164
- *
165
- *  This will obtain information about the HW bus for which the
166
- *  adapter is attached and stores it in the hw structure.
167
- **/
168
-static s32 e1000_get_bus_info_82542(struct e1000_hw *hw)
169
-{
170
-	DEBUGFUNC("e1000_get_bus_info_82542");
171
-
172
-	hw->bus.type = e1000_bus_type_pci;
173
-	hw->bus.speed = e1000_bus_speed_unknown;
174
-	hw->bus.width = e1000_bus_width_unknown;
175
-
176
-	return E1000_SUCCESS;
177
-}
178
-
179
-/**
180
- *  e1000_reset_hw_82542 - Reset hardware
181
- *  @hw: pointer to the HW structure
182
- *
183
- *  This resets the hardware into a known state.
184
- **/
185
-static s32 e1000_reset_hw_82542(struct e1000_hw *hw)
186
-{
187
-	struct e1000_bus_info *bus = &hw->bus;
188
-	s32 ret_val = E1000_SUCCESS;
189
-	u32 ctrl;
190
-
191
-	DEBUGFUNC("e1000_reset_hw_82542");
192
-
193
-	if (hw->revision_id == E1000_REVISION_2) {
194
-		DEBUGOUT("Disabling MWI on 82542 rev 2\n");
195
-		e1000_pci_clear_mwi(hw);
196
-	}
197
-
198
-	DEBUGOUT("Masking off all interrupts\n");
199
-	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
200
-
201
-	E1000_WRITE_REG(hw, E1000_RCTL, 0);
202
-	E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
203
-	E1000_WRITE_FLUSH(hw);
204
-
205
-	/*
206
-	 * Delay to allow any outstanding PCI transactions to complete before
207
-	 * resetting the device
208
-	 */
209
-	msec_delay(10);
210
-
211
-	ctrl = E1000_READ_REG(hw, E1000_CTRL);
212
-
213
-	DEBUGOUT("Issuing a global reset to 82542/82543 MAC\n");
214
-	E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
215
-
216
-	hw->nvm.ops.reload(hw);
217
-	msec_delay(2);
218
-
219
-	E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
220
-	E1000_READ_REG(hw, E1000_ICR);
221
-
222
-	if (hw->revision_id == E1000_REVISION_2) {
223
-		if (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
224
-			e1000_pci_set_mwi(hw);
225
-	}
226
-
227
-	return ret_val;
228
-}
229
-
230
-/**
231
- *  e1000_init_hw_82542 - Initialize hardware
232
- *  @hw: pointer to the HW structure
233
- *
234
- *  This inits the hardware readying it for operation.
235
- **/
236
-static s32 e1000_init_hw_82542(struct e1000_hw *hw)
237
-{
238
-	struct e1000_mac_info *mac = &hw->mac;
239
-	struct e1000_dev_spec_82542 *dev_spec = &hw->dev_spec._82542;
240
-	s32 ret_val = E1000_SUCCESS;
241
-	u32 ctrl;
242
-	u16 i;
243
-
244
-	DEBUGFUNC("e1000_init_hw_82542");
245
-
246
-	/* Disabling VLAN filtering */
247
-	E1000_WRITE_REG(hw, E1000_VET, 0);
248
-	mac->ops.clear_vfta(hw);
249
-
250
-	/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
251
-	if (hw->revision_id == E1000_REVISION_2) {
252
-		DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
253
-		e1000_pci_clear_mwi(hw);
254
-		E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST);
255
-		E1000_WRITE_FLUSH(hw);
256
-		msec_delay(5);
257
-	}
258
-
259
-	/* Setup the receive address. */
260
-	e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
261
-
262
-	/* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
263
-	if (hw->revision_id == E1000_REVISION_2) {
264
-		E1000_WRITE_REG(hw, E1000_RCTL, 0);
265
-		E1000_WRITE_FLUSH(hw);
266
-		msec_delay(1);
267
-		if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
268
-			e1000_pci_set_mwi(hw);
269
-	}
270
-
271
-	/* Zero out the Multicast HASH table */
272
-	DEBUGOUT("Zeroing the MTA\n");
273
-	for (i = 0; i < mac->mta_reg_count; i++)
274
-		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
275
-
276
-	/*
277
-	 * Set the PCI priority bit correctly in the CTRL register.  This
278
-	 * determines if the adapter gives priority to receives, or if it
279
-	 * gives equal priority to transmits and receives.
280
-	 */
281
-	if (dev_spec->dma_fairness) {
282
-		ctrl = E1000_READ_REG(hw, E1000_CTRL);
283
-		E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
284
-	}
285
-
286
-	/* Setup link and flow control */
287
-	ret_val = e1000_setup_link_82542(hw);
288
-
289
-	/*
290
-	 * Clear all of the statistics registers (clear on read).  It is
291
-	 * important that we do this after we have tried to establish link
292
-	 * because the symbol error count will increment wildly if there
293
-	 * is no link.
294
-	 */
295
-	e1000_clear_hw_cntrs_82542(hw);
296
-
297
-	return ret_val;
298
-}
299
-
300
-/**
301
- *  e1000_setup_link_82542 - Setup flow control and link settings
302
- *  @hw: pointer to the HW structure
303
- *
304
- *  Determines which flow control settings to use, then configures flow
305
- *  control.  Calls the appropriate media-specific link configuration
306
- *  function.  Assuming the adapter has a valid link partner, a valid link
307
- *  should be established.  Assumes the hardware has previously been reset
308
- *  and the transmitter and receiver are not enabled.
309
- **/
310
-static s32 e1000_setup_link_82542(struct e1000_hw *hw)
311
-{
312
-	struct e1000_mac_info *mac = &hw->mac;
313
-	s32 ret_val = E1000_SUCCESS;
314
-
315
-	DEBUGFUNC("e1000_setup_link_82542");
316
-
317
-	ret_val = e1000_set_default_fc_generic(hw);
318
-	if (ret_val)
319
-		goto out;
320
-
321
-	hw->fc.requested_mode &= ~e1000_fc_tx_pause;
322
-
323
-	if (mac->report_tx_early == 1)
324
-		hw->fc.requested_mode &= ~e1000_fc_rx_pause;
325
-
326
-	/*
327
-	 * Save off the requested flow control mode for use later.  Depending
328
-	 * on the link partner's capabilities, we may or may not use this mode.
329
-	 */
330
-	hw->fc.current_mode = hw->fc.requested_mode;
331
-
332
-	DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
333
-	                                             hw->fc.current_mode);
334
-
335
-	/* Call the necessary subroutine to configure the link. */
336
-	ret_val = mac->ops.setup_physical_interface(hw);
337
-	if (ret_val)
338
-		goto out;
339
-
340
-	/*
341
-	 * Initialize the flow control address, type, and PAUSE timer
342
-	 * registers to their default values.  This is done even if flow
343
-	 * control is disabled, because it does not hurt anything to
344
-	 * initialize these registers.
345
-	 */
346
-	DEBUGOUT("Initializing Flow Control address, type and timer regs\n");
347
-
348
-	E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
349
-	E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
350
-	E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
351
-
352
-	E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
353
-
354
-	ret_val = e1000_set_fc_watermarks_generic(hw);
355
-
356
-out:
357
-	return ret_val;
358
-}
359
-
360
-/**
361
- *  e1000_led_on_82542 - Turn on SW controllable LED
362
- *  @hw: pointer to the HW structure
363
- *
364
- *  Turns the SW defined LED on.
365
- **/
366
-static s32 e1000_led_on_82542(struct e1000_hw *hw __unused)
367
-{
368
-#if 0
369
-	u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
370
-
371
-	DEBUGFUNC("e1000_led_on_82542");
372
-
373
-	ctrl |= E1000_CTRL_SWDPIN0;
374
-	ctrl |= E1000_CTRL_SWDPIO0;
375
-	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
376
-
377
-	return E1000_SUCCESS;
378
-#endif
379
-	return 0;
380
-}
381
-
382
-/**
383
- *  e1000_led_off_82542 - Turn off SW controllable LED
384
- *  @hw: pointer to the HW structure
385
- *
386
- *  Turns the SW defined LED off.
387
- **/
388
-static s32 e1000_led_off_82542(struct e1000_hw *hw __unused)
389
-{
390
-#if 0
391
-	u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
392
-
393
-	DEBUGFUNC("e1000_led_off_82542");
394
-
395
-	ctrl &= ~E1000_CTRL_SWDPIN0;
396
-	ctrl |= E1000_CTRL_SWDPIO0;
397
-	E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
398
-
399
-	return E1000_SUCCESS;
400
-#endif
401
-	return 0;
402
-}
403
-
404
-/**
405
- *  e1000_rar_set_82542 - Set receive address register
406
- *  @hw: pointer to the HW structure
407
- *  @addr: pointer to the receive address
408
- *  @index: receive address array register
409
- *
410
- *  Sets the receive address array register at index to the address passed
411
- *  in by addr.
412
- **/
413
-static void e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index)
414
-{
415
-	u32 rar_low, rar_high;
416
-
417
-	DEBUGFUNC("e1000_rar_set_82542");
418
-
419
-	/*
420
-	 * HW expects these in little endian so we reverse the byte order
421
-	 * from network order (big endian) to little endian
422
-	 */
423
-	rar_low = ((u32) addr[0] |
424
-	           ((u32) addr[1] << 8) |
425
-	           ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
426
-
427
-	rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
428
-
429
-	/* If MAC address zero, no need to set the AV bit */
430
-	if (rar_low || rar_high)
431
-		rar_high |= E1000_RAH_AV;
432
-
433
-	E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);
434
-	E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
435
-}
436
-
437
-/**
438
- *  e1000_translate_register_82542 - Translate the proper register offset
439
- *  @reg: e1000 register to be read
440
- *
441
- *  Registers in 82542 are located in different offsets than other adapters
442
- *  even though they function in the same manner.  This function takes in
443
- *  the name of the register to read and returns the correct offset for
444
- *  82542 silicon.
445
- **/
446
-u32 e1000_translate_register_82542(u32 reg)
447
-{
448
-	/*
449
-	 * Some of the 82542 registers are located at different
450
-	 * offsets than they are in newer adapters.
451
-	 * Despite the difference in location, the registers
452
-	 * function in the same manner.
453
-	 */
454
-	switch (reg) {
455
-	case E1000_RA:
456
-		reg = 0x00040;
457
-		break;
458
-	case E1000_RDTR:
459
-		reg = 0x00108;
460
-		break;
461
-	case E1000_RDBAL(0):
462
-		reg = 0x00110;
463
-		break;
464
-	case E1000_RDBAH(0):
465
-		reg = 0x00114;
466
-		break;
467
-	case E1000_RDLEN(0):
468
-		reg = 0x00118;
469
-		break;
470
-	case E1000_RDH(0):
471
-		reg = 0x00120;
472
-		break;
473
-	case E1000_RDT(0):
474
-		reg = 0x00128;
475
-		break;
476
-	case E1000_RDBAL(1):
477
-		reg = 0x00138;
478
-		break;
479
-	case E1000_RDBAH(1):
480
-		reg = 0x0013C;
481
-		break;
482
-	case E1000_RDLEN(1):
483
-		reg = 0x00140;
484
-		break;
485
-	case E1000_RDH(1):
486
-		reg = 0x00148;
487
-		break;
488
-	case E1000_RDT(1):
489
-		reg = 0x00150;
490
-		break;
491
-	case E1000_FCRTH:
492
-		reg = 0x00160;
493
-		break;
494
-	case E1000_FCRTL:
495
-		reg = 0x00168;
496
-		break;
497
-	case E1000_MTA:
498
-		reg = 0x00200;
499
-		break;
500
-	case E1000_TDBAL(0):
501
-		reg = 0x00420;
502
-		break;
503
-	case E1000_TDBAH(0):
504
-		reg = 0x00424;
505
-		break;
506
-	case E1000_TDLEN(0):
507
-		reg = 0x00428;
508
-		break;
509
-	case E1000_TDH(0):
510
-		reg = 0x00430;
511
-		break;
512
-	case E1000_TDT(0):
513
-		reg = 0x00438;
514
-		break;
515
-	case E1000_TIDV:
516
-		reg = 0x00440;
517
-		break;
518
-	case E1000_VFTA:
519
-		reg = 0x00600;
520
-		break;
521
-	case E1000_TDFH:
522
-		reg = 0x08010;
523
-		break;
524
-	case E1000_TDFT:
525
-		reg = 0x08018;
526
-		break;
527
-	default:
528
-		break;
529
-	}
530
-
531
-	return reg;
532
-}
533
-
534
-/**
535
- *  e1000_clear_hw_cntrs_82542 - Clear device specific hardware counters
536
- *  @hw: pointer to the HW structure
537
- *
538
- *  Clears the hardware counters by reading the counter registers.
539
- **/
540
-static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw)
541
-{
542
-	DEBUGFUNC("e1000_clear_hw_cntrs_82542");
543
-
544
-	e1000_clear_hw_cntrs_base_generic(hw);
545
-
546
-#if 0
547
-	E1000_READ_REG(hw, E1000_PRC64);
548
-	E1000_READ_REG(hw, E1000_PRC127);
549
-	E1000_READ_REG(hw, E1000_PRC255);
550
-	E1000_READ_REG(hw, E1000_PRC511);
551
-	E1000_READ_REG(hw, E1000_PRC1023);
552
-	E1000_READ_REG(hw, E1000_PRC1522);
553
-	E1000_READ_REG(hw, E1000_PTC64);
554
-	E1000_READ_REG(hw, E1000_PTC127);
555
-	E1000_READ_REG(hw, E1000_PTC255);
556
-	E1000_READ_REG(hw, E1000_PTC511);
557
-	E1000_READ_REG(hw, E1000_PTC1023);
558
-	E1000_READ_REG(hw, E1000_PTC1522);
559
-#endif
560
-}
561
-
562
-static struct pci_device_id e1000_82542_nics[] = {
563
-     PCI_ROM(0x8086, 0x1000, "E1000_DEV_ID_82542", "E1000_DEV_ID_82542", e1000_82542),
564
-};
565
-
566
-struct pci_driver e1000_82542_driver __pci_driver = {
567
-	.ids = e1000_82542_nics,
568
-	.id_count = (sizeof (e1000_82542_nics) / sizeof (e1000_82542_nics[0])),
569
-	.probe = e1000_probe,
570
-	.remove = e1000_remove,
571
-};

+ 0
- 1635
src/drivers/net/e1000/e1000_82543.c
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Прегледај датотеку


+ 0
- 45
src/drivers/net/e1000/e1000_82543.h Прегледај датотеку

@@ -1,45 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2008 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-#ifndef _E1000_82543_H_
32
-#define _E1000_82543_H_
33
-
34
-#define PHY_PREAMBLE      0xFFFFFFFF
35
-#define PHY_PREAMBLE_SIZE 32
36
-#define PHY_SOF           0x1
37
-#define PHY_OP_READ       0x2
38
-#define PHY_OP_WRITE      0x1
39
-#define PHY_TURNAROUND    0x2
40
-
41
-#define TBI_COMPAT_ENABLED 0x1 /* Global "knob" for the workaround */
42
-/* If TBI_COMPAT_ENABLED, then this is the current state (on/off) */
43
-#define TBI_SBP_ENABLED    0x2
44
-
45
-#endif

+ 0
- 1108
src/drivers/net/e1000/e1000_api.c
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+ 0
- 127
src/drivers/net/e1000/e1000_api.h Прегледај датотеку

@@ -1,127 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2008 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-#ifndef _E1000_API_H_
32
-#define _E1000_API_H_
33
-
34
-#include <stdint.h>
35
-#include <stdlib.h>
36
-#include <stdio.h>
37
-#include <string.h>
38
-#include <unistd.h>
39
-#include <ipxe/io.h>
40
-#include <errno.h>
41
-#include <byteswap.h>
42
-#include <ipxe/pci.h>
43
-#include <ipxe/malloc.h>
44
-#include <ipxe/if_ether.h>
45
-#include <ipxe/ethernet.h>
46
-#include <ipxe/iobuf.h>
47
-#include <ipxe/netdevice.h>
48
-
49
-#include "e1000_hw.h"
50
-
51
-extern void    e1000_init_function_pointers_82542(struct e1000_hw *hw) __attribute__((weak));
52
-extern void    e1000_init_function_pointers_82543(struct e1000_hw *hw) __attribute__((weak));
53
-extern void    e1000_init_function_pointers_82540(struct e1000_hw *hw) __attribute__((weak));
54
-extern void    e1000_init_function_pointers_82541(struct e1000_hw *hw) __attribute__((weak));
55
-
56
-s32  e1000_set_mac_type(struct e1000_hw *hw);
57
-s32  e1000_setup_init_funcs(struct e1000_hw *hw, bool init_device);
58
-s32  e1000_init_mac_params(struct e1000_hw *hw);
59
-s32  e1000_init_nvm_params(struct e1000_hw *hw);
60
-s32  e1000_init_phy_params(struct e1000_hw *hw);
61
-s32  e1000_get_bus_info(struct e1000_hw *hw);
62
-void e1000_clear_vfta(struct e1000_hw *hw);
63
-void e1000_write_vfta(struct e1000_hw *hw, u32 offset, u32 value);
64
-s32  e1000_force_mac_fc(struct e1000_hw *hw);
65
-s32  e1000_check_for_link(struct e1000_hw *hw);
66
-s32  e1000_reset_hw(struct e1000_hw *hw);
67
-s32  e1000_init_hw(struct e1000_hw *hw);
68
-s32  e1000_setup_link(struct e1000_hw *hw);
69
-s32  e1000_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed,
70
-                                u16 *duplex);
71
-s32  e1000_disable_pcie_master(struct e1000_hw *hw);
72
-void e1000_config_collision_dist(struct e1000_hw *hw);
73
-void e1000_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
74
-void e1000_mta_set(struct e1000_hw *hw, u32 hash_value);
75
-u32  e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr);
76
-void e1000_update_mc_addr_list(struct e1000_hw *hw,
77
-                               u8 *mc_addr_list, u32 mc_addr_count);
78
-s32  e1000_setup_led(struct e1000_hw *hw);
79
-s32  e1000_cleanup_led(struct e1000_hw *hw);
80
-s32  e1000_check_reset_block(struct e1000_hw *hw);
81
-s32  e1000_blink_led(struct e1000_hw *hw);
82
-s32  e1000_led_on(struct e1000_hw *hw);
83
-s32  e1000_led_off(struct e1000_hw *hw);
84
-s32 e1000_id_led_init(struct e1000_hw *hw);
85
-void e1000_reset_adaptive(struct e1000_hw *hw);
86
-void e1000_update_adaptive(struct e1000_hw *hw);
87
-#if 0
88
-s32  e1000_get_cable_length(struct e1000_hw *hw);
89
-#endif
90
-s32  e1000_validate_mdi_setting(struct e1000_hw *hw);
91
-s32  e1000_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data);
92
-s32  e1000_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data);
93
-s32  e1000_get_phy_info(struct e1000_hw *hw);
94
-void e1000_release_phy(struct e1000_hw *hw);
95
-s32  e1000_acquire_phy(struct e1000_hw *hw);
96
-s32  e1000_phy_hw_reset(struct e1000_hw *hw);
97
-s32  e1000_phy_commit(struct e1000_hw *hw);
98
-void e1000_power_up_phy(struct e1000_hw *hw);
99
-void e1000_power_down_phy(struct e1000_hw *hw);
100
-s32  e1000_read_mac_addr(struct e1000_hw *hw);
101
-s32  e1000_read_pba_num(struct e1000_hw *hw, u32 *part_num);
102
-void e1000_reload_nvm(struct e1000_hw *hw);
103
-s32  e1000_update_nvm_checksum(struct e1000_hw *hw);
104
-s32  e1000_validate_nvm_checksum(struct e1000_hw *hw);
105
-s32  e1000_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
106
-s32  e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
107
-s32  e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
108
-s32  e1000_write_nvm(struct e1000_hw *hw, u16 offset, u16 words,
109
-                     u16 *data);
110
-s32  e1000_wait_autoneg(struct e1000_hw *hw);
111
-s32  e1000_set_d3_lplu_state(struct e1000_hw *hw, bool active);
112
-s32  e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
113
-bool e1000_check_mng_mode(struct e1000_hw *hw);
114
-bool e1000_enable_tx_pkt_filtering(struct e1000_hw *hw);
115
-s32  e1000_mng_enable_host_if(struct e1000_hw *hw);
116
-s32  e1000_mng_host_if_write(struct e1000_hw *hw,
117
-                             u8 *buffer, u16 length, u16 offset, u8 *sum);
118
-s32  e1000_mng_write_cmd_header(struct e1000_hw *hw,
119
-                                struct e1000_host_mng_command_header *hdr);
120
-s32  e1000_mng_write_dhcp_info(struct e1000_hw * hw,
121
-                                    u8 *buffer, u16 length);
122
-u32  e1000_translate_register_82542(u32 reg) __attribute__((weak));
123
-
124
-extern int e1000_probe(struct pci_device *pdev);
125
-extern void e1000_remove(struct pci_device *pdev);
126
-
127
-#endif

+ 0
- 1416
src/drivers/net/e1000/e1000_defines.h
Разлика између датотеке није приказан због своје велике величине
Прегледај датотеку


+ 0
- 728
src/drivers/net/e1000/e1000_hw.h Прегледај датотеку

@@ -1,728 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2008 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-#ifndef _E1000_HW_H_
32
-#define _E1000_HW_H_
33
-
34
-#include "e1000_osdep.h"
35
-#include "e1000_regs.h"
36
-#include "e1000_defines.h"
37
-
38
-struct e1000_hw;
39
-
40
-#define E1000_DEV_ID_82542                    0x1000
41
-#define E1000_DEV_ID_82543GC_FIBER            0x1001
42
-#define E1000_DEV_ID_82543GC_COPPER           0x1004
43
-#define E1000_DEV_ID_82544EI_COPPER           0x1008
44
-#define E1000_DEV_ID_82544EI_FIBER            0x1009
45
-#define E1000_DEV_ID_82544GC_COPPER           0x100C
46
-#define E1000_DEV_ID_82544GC_LOM              0x100D
47
-#define E1000_DEV_ID_82540EM                  0x100E
48
-#define E1000_DEV_ID_82540EM_LOM              0x1015
49
-#define E1000_DEV_ID_82540EP_LOM              0x1016
50
-#define E1000_DEV_ID_82540EP                  0x1017
51
-#define E1000_DEV_ID_82540EP_LP               0x101E
52
-#define E1000_DEV_ID_82545EM_COPPER           0x100F
53
-#define E1000_DEV_ID_82545EM_FIBER            0x1011
54
-#define E1000_DEV_ID_82545GM_COPPER           0x1026
55
-#define E1000_DEV_ID_82545GM_FIBER            0x1027
56
-#define E1000_DEV_ID_82545GM_SERDES           0x1028
57
-#define E1000_DEV_ID_82546EB_COPPER           0x1010
58
-#define E1000_DEV_ID_82546EB_FIBER            0x1012
59
-#define E1000_DEV_ID_82546EB_QUAD_COPPER      0x101D
60
-#define E1000_DEV_ID_82546GB_COPPER           0x1079
61
-#define E1000_DEV_ID_82546GB_FIBER            0x107A
62
-#define E1000_DEV_ID_82546GB_SERDES           0x107B
63
-#define E1000_DEV_ID_82546GB_PCIE             0x108A
64
-#define E1000_DEV_ID_82546GB_QUAD_COPPER      0x1099
65
-#define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5
66
-#define E1000_DEV_ID_82541EI                  0x1013
67
-#define E1000_DEV_ID_82541EI_MOBILE           0x1018
68
-#define E1000_DEV_ID_82541ER_LOM              0x1014
69
-#define E1000_DEV_ID_82541ER                  0x1078
70
-#define E1000_DEV_ID_82541GI                  0x1076
71
-#define E1000_DEV_ID_82541GI_LF               0x107C
72
-#define E1000_DEV_ID_82541GI_MOBILE           0x1077
73
-#define E1000_DEV_ID_82547EI                  0x1019
74
-#define E1000_DEV_ID_82547EI_MOBILE           0x101A
75
-#define E1000_DEV_ID_82547GI                  0x1075
76
-#define E1000_REVISION_0 0
77
-#define E1000_REVISION_1 1
78
-#define E1000_REVISION_2 2
79
-#define E1000_REVISION_3 3
80
-#define E1000_REVISION_4 4
81
-
82
-#define E1000_FUNC_0     0
83
-#define E1000_FUNC_1     1
84
-
85
-#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
86
-#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
87
-
88
-enum e1000_mac_type {
89
-	e1000_undefined = 0,
90
-	e1000_82542,
91
-	e1000_82543,
92
-	e1000_82544,
93
-	e1000_82540,
94
-	e1000_82545,
95
-	e1000_82545_rev_3,
96
-	e1000_82546,
97
-	e1000_82546_rev_3,
98
-	e1000_82541,
99
-	e1000_82541_rev_2,
100
-	e1000_82547,
101
-	e1000_82547_rev_2,
102
-	e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
103
-};
104
-
105
-enum e1000_media_type {
106
-	e1000_media_type_unknown = 0,
107
-	e1000_media_type_copper = 1,
108
-	e1000_media_type_fiber = 2,
109
-	e1000_media_type_internal_serdes = 3,
110
-	e1000_num_media_types
111
-};
112
-
113
-enum e1000_nvm_type {
114
-	e1000_nvm_unknown = 0,
115
-	e1000_nvm_none,
116
-	e1000_nvm_eeprom_spi,
117
-	e1000_nvm_eeprom_microwire,
118
-	e1000_nvm_flash_hw,
119
-	e1000_nvm_flash_sw
120
-};
121
-
122
-enum e1000_nvm_override {
123
-	e1000_nvm_override_none = 0,
124
-	e1000_nvm_override_spi_small,
125
-	e1000_nvm_override_spi_large,
126
-	e1000_nvm_override_microwire_small,
127
-	e1000_nvm_override_microwire_large
128
-};
129
-
130
-enum e1000_phy_type {
131
-	e1000_phy_unknown = 0,
132
-	e1000_phy_none,
133
-	e1000_phy_m88,
134
-	e1000_phy_igp,
135
-	e1000_phy_igp_2,
136
-	e1000_phy_gg82563,
137
-	e1000_phy_igp_3,
138
-	e1000_phy_ife,
139
-};
140
-
141
-enum e1000_bus_type {
142
-	e1000_bus_type_unknown = 0,
143
-	e1000_bus_type_pci,
144
-	e1000_bus_type_pcix,
145
-	e1000_bus_type_pci_express,
146
-	e1000_bus_type_reserved
147
-};
148
-
149
-enum e1000_bus_speed {
150
-	e1000_bus_speed_unknown = 0,
151
-	e1000_bus_speed_33,
152
-	e1000_bus_speed_66,
153
-	e1000_bus_speed_100,
154
-	e1000_bus_speed_120,
155
-	e1000_bus_speed_133,
156
-	e1000_bus_speed_2500,
157
-	e1000_bus_speed_5000,
158
-	e1000_bus_speed_reserved
159
-};
160
-
161
-enum e1000_bus_width {
162
-	e1000_bus_width_unknown = 0,
163
-	e1000_bus_width_pcie_x1,
164
-	e1000_bus_width_pcie_x2,
165
-	e1000_bus_width_pcie_x4 = 4,
166
-	e1000_bus_width_pcie_x8 = 8,
167
-	e1000_bus_width_32,
168
-	e1000_bus_width_64,
169
-	e1000_bus_width_reserved
170
-};
171
-
172
-enum e1000_1000t_rx_status {
173
-	e1000_1000t_rx_status_not_ok = 0,
174
-	e1000_1000t_rx_status_ok,
175
-	e1000_1000t_rx_status_undefined = 0xFF
176
-};
177
-
178
-enum e1000_rev_polarity {
179
-	e1000_rev_polarity_normal = 0,
180
-	e1000_rev_polarity_reversed,
181
-	e1000_rev_polarity_undefined = 0xFF
182
-};
183
-
184
-enum e1000_fc_mode {
185
-	e1000_fc_none = 0,
186
-	e1000_fc_rx_pause,
187
-	e1000_fc_tx_pause,
188
-	e1000_fc_full,
189
-	e1000_fc_default = 0xFF
190
-};
191
-
192
-enum e1000_ffe_config {
193
-	e1000_ffe_config_enabled = 0,
194
-	e1000_ffe_config_active,
195
-	e1000_ffe_config_blocked
196
-};
197
-
198
-enum e1000_dsp_config {
199
-	e1000_dsp_config_disabled = 0,
200
-	e1000_dsp_config_enabled,
201
-	e1000_dsp_config_activated,
202
-	e1000_dsp_config_undefined = 0xFF
203
-};
204
-
205
-enum e1000_ms_type {
206
-	e1000_ms_hw_default = 0,
207
-	e1000_ms_force_master,
208
-	e1000_ms_force_slave,
209
-	e1000_ms_auto
210
-};
211
-
212
-enum e1000_smart_speed {
213
-	e1000_smart_speed_default = 0,
214
-	e1000_smart_speed_on,
215
-	e1000_smart_speed_off
216
-};
217
-
218
-enum e1000_serdes_link_state {
219
-	e1000_serdes_link_down = 0,
220
-	e1000_serdes_link_autoneg_progress,
221
-	e1000_serdes_link_autoneg_complete,
222
-	e1000_serdes_link_forced_up
223
-};
224
-
225
-/* Receive Descriptor */
226
-struct e1000_rx_desc {
227
-	__le64 buffer_addr; /* Address of the descriptor's data buffer */
228
-	__le16 length;      /* Length of data DMAed into data buffer */
229
-	__le16 csum;        /* Packet checksum */
230
-	u8  status;         /* Descriptor status */
231
-	u8  errors;         /* Descriptor Errors */
232
-	__le16 special;
233
-};
234
-
235
-/* Receive Descriptor - Extended */
236
-union e1000_rx_desc_extended {
237
-	struct {
238
-		__le64 buffer_addr;
239
-		__le64 reserved;
240
-	} read;
241
-	struct {
242
-		struct {
243
-			__le32 mrq;           /* Multiple Rx Queues */
244
-			union {
245
-				__le32 rss;         /* RSS Hash */
246
-				struct {
247
-					__le16 ip_id;  /* IP id */
248
-					__le16 csum;   /* Packet Checksum */
249
-				} csum_ip;
250
-			} hi_dword;
251
-		} lower;
252
-		struct {
253
-			__le32 status_error;  /* ext status/error */
254
-			__le16 length;
255
-			__le16 vlan;          /* VLAN tag */
256
-		} upper;
257
-	} wb;  /* writeback */
258
-};
259
-
260
-#define MAX_PS_BUFFERS 4
261
-/* Receive Descriptor - Packet Split */
262
-union e1000_rx_desc_packet_split {
263
-	struct {
264
-		/* one buffer for protocol header(s), three data buffers */
265
-		__le64 buffer_addr[MAX_PS_BUFFERS];
266
-	} read;
267
-	struct {
268
-		struct {
269
-			__le32 mrq;           /* Multiple Rx Queues */
270
-			union {
271
-				__le32 rss;           /* RSS Hash */
272
-				struct {
273
-					__le16 ip_id;    /* IP id */
274
-					__le16 csum;     /* Packet Checksum */
275
-				} csum_ip;
276
-			} hi_dword;
277
-		} lower;
278
-		struct {
279
-			__le32 status_error;  /* ext status/error */
280
-			__le16 length0;       /* length of buffer 0 */
281
-			__le16 vlan;          /* VLAN tag */
282
-		} middle;
283
-		struct {
284
-			__le16 header_status;
285
-			__le16 length[3];     /* length of buffers 1-3 */
286
-		} upper;
287
-		__le64 reserved;
288
-	} wb; /* writeback */
289
-};
290
-
291
-/* Transmit Descriptor */
292
-struct e1000_tx_desc {
293
-	__le64 buffer_addr;   /* Address of the descriptor's data buffer */
294
-	union {
295
-		__le32 data;
296
-		struct {
297
-			__le16 length;    /* Data buffer length */
298
-			u8 cso;           /* Checksum offset */
299
-			u8 cmd;           /* Descriptor control */
300
-		} flags;
301
-	} lower;
302
-	union {
303
-		__le32 data;
304
-		struct {
305
-			u8 status;        /* Descriptor status */
306
-			u8 css;           /* Checksum start */
307
-			__le16 special;
308
-		} fields;
309
-	} upper;
310
-};
311
-
312
-/* Offload Context Descriptor */
313
-struct e1000_context_desc {
314
-	union {
315
-		__le32 ip_config;
316
-		struct {
317
-			u8 ipcss;         /* IP checksum start */
318
-			u8 ipcso;         /* IP checksum offset */
319
-			__le16 ipcse;     /* IP checksum end */
320
-		} ip_fields;
321
-	} lower_setup;
322
-	union {
323
-		__le32 tcp_config;
324
-		struct {
325
-			u8 tucss;         /* TCP checksum start */
326
-			u8 tucso;         /* TCP checksum offset */
327
-			__le16 tucse;     /* TCP checksum end */
328
-		} tcp_fields;
329
-	} upper_setup;
330
-	__le32 cmd_and_length;
331
-	union {
332
-		__le32 data;
333
-		struct {
334
-			u8 status;        /* Descriptor status */
335
-			u8 hdr_len;       /* Header length */
336
-			__le16 mss;       /* Maximum segment size */
337
-		} fields;
338
-	} tcp_seg_setup;
339
-};
340
-
341
-/* Offload data descriptor */
342
-struct e1000_data_desc {
343
-	__le64 buffer_addr;   /* Address of the descriptor's buffer address */
344
-	union {
345
-		__le32 data;
346
-		struct {
347
-			__le16 length;    /* Data buffer length */
348
-			u8 typ_len_ext;
349
-			u8 cmd;
350
-		} flags;
351
-	} lower;
352
-	union {
353
-		__le32 data;
354
-		struct {
355
-			u8 status;        /* Descriptor status */
356
-			u8 popts;         /* Packet Options */
357
-			__le16 special;
358
-		} fields;
359
-	} upper;
360
-};
361
-
362
-/* Statistics counters collected by the MAC */
363
-struct e1000_hw_stats {
364
-	u64 crcerrs;
365
-	u64 algnerrc;
366
-	u64 symerrs;
367
-	u64 rxerrc;
368
-	u64 mpc;
369
-	u64 scc;
370
-	u64 ecol;
371
-	u64 mcc;
372
-	u64 latecol;
373
-	u64 colc;
374
-	u64 dc;
375
-	u64 tncrs;
376
-	u64 sec;
377
-	u64 cexterr;
378
-	u64 rlec;
379
-	u64 xonrxc;
380
-	u64 xontxc;
381
-	u64 xoffrxc;
382
-	u64 xofftxc;
383
-	u64 fcruc;
384
-	u64 prc64;
385
-	u64 prc127;
386
-	u64 prc255;
387
-	u64 prc511;
388
-	u64 prc1023;
389
-	u64 prc1522;
390
-	u64 gprc;
391
-	u64 bprc;
392
-	u64 mprc;
393
-	u64 gptc;
394
-	u64 gorc;
395
-	u64 gotc;
396
-	u64 rnbc;
397
-	u64 ruc;
398
-	u64 rfc;
399
-	u64 roc;
400
-	u64 rjc;
401
-	u64 mgprc;
402
-	u64 mgpdc;
403
-	u64 mgptc;
404
-	u64 tor;
405
-	u64 tot;
406
-	u64 tpr;
407
-	u64 tpt;
408
-	u64 ptc64;
409
-	u64 ptc127;
410
-	u64 ptc255;
411
-	u64 ptc511;
412
-	u64 ptc1023;
413
-	u64 ptc1522;
414
-	u64 mptc;
415
-	u64 bptc;
416
-	u64 tsctc;
417
-	u64 tsctfc;
418
-	u64 iac;
419
-	u64 icrxptc;
420
-	u64 icrxatc;
421
-	u64 ictxptc;
422
-	u64 ictxatc;
423
-	u64 ictxqec;
424
-	u64 ictxqmtc;
425
-	u64 icrxdmtc;
426
-	u64 icrxoc;
427
-	u64 cbtmpc;
428
-	u64 htdpmc;
429
-	u64 cbrdpc;
430
-	u64 cbrmpc;
431
-	u64 rpthc;
432
-	u64 hgptc;
433
-	u64 htcbdpc;
434
-	u64 hgorc;
435
-	u64 hgotc;
436
-	u64 lenerrs;
437
-	u64 scvpc;
438
-	u64 hrmpc;
439
-	u64 doosync;
440
-};
441
-
442
-
443
-struct e1000_phy_stats {
444
-	u32 idle_errors;
445
-	u32 receive_errors;
446
-};
447
-
448
-struct e1000_host_mng_dhcp_cookie {
449
-	u32 signature;
450
-	u8  status;
451
-	u8  reserved0;
452
-	u16 vlan_id;
453
-	u32 reserved1;
454
-	u16 reserved2;
455
-	u8  reserved3;
456
-	u8  checksum;
457
-};
458
-
459
-/* Host Interface "Rev 1" */
460
-struct e1000_host_command_header {
461
-	u8 command_id;
462
-	u8 command_length;
463
-	u8 command_options;
464
-	u8 checksum;
465
-};
466
-
467
-#define E1000_HI_MAX_DATA_LENGTH     252
468
-struct e1000_host_command_info {
469
-	struct e1000_host_command_header command_header;
470
-	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
471
-};
472
-
473
-/* Host Interface "Rev 2" */
474
-struct e1000_host_mng_command_header {
475
-	u8  command_id;
476
-	u8  checksum;
477
-	u16 reserved1;
478
-	u16 reserved2;
479
-	u16 command_length;
480
-};
481
-
482
-#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
483
-struct e1000_host_mng_command_info {
484
-	struct e1000_host_mng_command_header command_header;
485
-	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
486
-};
487
-
488
-#include "e1000_mac.h"
489
-#include "e1000_phy.h"
490
-#include "e1000_nvm.h"
491
-#include "e1000_manage.h"
492
-
493
-struct e1000_mac_operations {
494
-	/* Function pointers for the MAC. */
495
-	s32  (*init_params)(struct e1000_hw *);
496
-	s32  (*id_led_init)(struct e1000_hw *);
497
-	s32  (*blink_led)(struct e1000_hw *);
498
-	s32  (*check_for_link)(struct e1000_hw *);
499
-	bool (*check_mng_mode)(struct e1000_hw *hw);
500
-	s32  (*cleanup_led)(struct e1000_hw *);
501
-	void (*clear_hw_cntrs)(struct e1000_hw *);
502
-	void (*clear_vfta)(struct e1000_hw *);
503
-	s32  (*get_bus_info)(struct e1000_hw *);
504
-	void (*set_lan_id)(struct e1000_hw *);
505
-	s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
506
-	s32  (*led_on)(struct e1000_hw *);
507
-	s32  (*led_off)(struct e1000_hw *);
508
-	void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
509
-	s32  (*reset_hw)(struct e1000_hw *);
510
-	s32  (*init_hw)(struct e1000_hw *);
511
-	s32  (*setup_link)(struct e1000_hw *);
512
-	s32  (*setup_physical_interface)(struct e1000_hw *);
513
-	s32  (*setup_led)(struct e1000_hw *);
514
-	void (*write_vfta)(struct e1000_hw *, u32, u32);
515
-	void (*mta_set)(struct e1000_hw *, u32);
516
-	void (*config_collision_dist)(struct e1000_hw *);
517
-	void (*rar_set)(struct e1000_hw *, u8*, u32);
518
-	s32  (*read_mac_addr)(struct e1000_hw *);
519
-	s32  (*validate_mdi_setting)(struct e1000_hw *);
520
-	s32  (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
521
-	s32  (*mng_write_cmd_header)(struct e1000_hw *hw,
522
-                      struct e1000_host_mng_command_header*);
523
-	s32  (*mng_enable_host_if)(struct e1000_hw *);
524
-	s32  (*wait_autoneg)(struct e1000_hw *);
525
-};
526
-
527
-struct e1000_phy_operations {
528
-	s32  (*init_params)(struct e1000_hw *);
529
-	s32  (*acquire)(struct e1000_hw *);
530
-	s32  (*check_polarity)(struct e1000_hw *);
531
-	s32  (*check_reset_block)(struct e1000_hw *);
532
-	s32  (*commit)(struct e1000_hw *);
533
-#if 0
534
-	s32  (*force_speed_duplex)(struct e1000_hw *);
535
-#endif
536
-	s32  (*get_cfg_done)(struct e1000_hw *hw);
537
-#if 0
538
-	s32  (*get_cable_length)(struct e1000_hw *);
539
-#endif
540
-	s32  (*get_info)(struct e1000_hw *);
541
-	s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
542
-	void (*release)(struct e1000_hw *);
543
-	s32  (*reset)(struct e1000_hw *);
544
-	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
545
-	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
546
-	s32  (*write_reg)(struct e1000_hw *, u32, u16);
547
-	void (*power_up)(struct e1000_hw *);
548
-	void (*power_down)(struct e1000_hw *);
549
-};
550
-
551
-struct e1000_nvm_operations {
552
-	s32  (*init_params)(struct e1000_hw *);
553
-	s32  (*acquire)(struct e1000_hw *);
554
-	s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
555
-	void (*release)(struct e1000_hw *);
556
-	void (*reload)(struct e1000_hw *);
557
-	s32  (*update)(struct e1000_hw *);
558
-	s32  (*valid_led_default)(struct e1000_hw *, u16 *);
559
-	s32  (*validate)(struct e1000_hw *);
560
-	s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
561
-};
562
-
563
-struct e1000_mac_info {
564
-	struct e1000_mac_operations ops;
565
-	u8 addr[6];
566
-	u8 perm_addr[6];
567
-
568
-	enum e1000_mac_type type;
569
-
570
-	u32 collision_delta;
571
-	u32 ledctl_default;
572
-	u32 ledctl_mode1;
573
-	u32 ledctl_mode2;
574
-	u32 mc_filter_type;
575
-	u32 tx_packet_delta;
576
-	u32 txcw;
577
-
578
-	u16 current_ifs_val;
579
-	u16 ifs_max_val;
580
-	u16 ifs_min_val;
581
-	u16 ifs_ratio;
582
-	u16 ifs_step_size;
583
-	u16 mta_reg_count;
584
-
585
-	/* Maximum size of the MTA register table in all supported adapters */
586
-	#define MAX_MTA_REG 128
587
-	u32 mta_shadow[MAX_MTA_REG];
588
-	u16 rar_entry_count;
589
-
590
-	u8  forced_speed_duplex;
591
-
592
-	bool adaptive_ifs;
593
-	bool arc_subsystem_valid;
594
-	bool asf_firmware_present;
595
-	bool autoneg;
596
-	bool autoneg_failed;
597
-	bool get_link_status;
598
-	bool in_ifs_mode;
599
-	bool report_tx_early;
600
-	enum e1000_serdes_link_state serdes_link_state;
601
-	bool serdes_has_link;
602
-	bool tx_pkt_filtering;
603
-};
604
-
605
-struct e1000_phy_info {
606
-	struct e1000_phy_operations ops;
607
-	enum e1000_phy_type type;
608
-
609
-	enum e1000_1000t_rx_status local_rx;
610
-	enum e1000_1000t_rx_status remote_rx;
611
-	enum e1000_ms_type ms_type;
612
-	enum e1000_ms_type original_ms_type;
613
-	enum e1000_rev_polarity cable_polarity;
614
-	enum e1000_smart_speed smart_speed;
615
-
616
-	u32 addr;
617
-	u32 id;
618
-	u32 reset_delay_us; /* in usec */
619
-	u32 revision;
620
-
621
-	enum e1000_media_type media_type;
622
-
623
-	u16 autoneg_advertised;
624
-	u16 autoneg_mask;
625
-	u16 cable_length;
626
-	u16 max_cable_length;
627
-	u16 min_cable_length;
628
-
629
-	u8 mdix;
630
-
631
-	bool disable_polarity_correction;
632
-	bool is_mdix;
633
-	bool polarity_correction;
634
-	bool reset_disable;
635
-	bool speed_downgraded;
636
-	bool autoneg_wait_to_complete;
637
-};
638
-
639
-struct e1000_nvm_info {
640
-	struct e1000_nvm_operations ops;
641
-	enum e1000_nvm_type type;
642
-	enum e1000_nvm_override override;
643
-
644
-	u32 flash_bank_size;
645
-	u32 flash_base_addr;
646
-
647
-	u16 word_size;
648
-	u16 delay_usec;
649
-	u16 address_bits;
650
-	u16 opcode_bits;
651
-	u16 page_size;
652
-};
653
-
654
-struct e1000_bus_info {
655
-	enum e1000_bus_type type;
656
-	enum e1000_bus_speed speed;
657
-	enum e1000_bus_width width;
658
-
659
-	u16 func;
660
-	u16 pci_cmd_word;
661
-};
662
-
663
-struct e1000_fc_info {
664
-	u32 high_water;          /* Flow control high-water mark */
665
-	u32 low_water;           /* Flow control low-water mark */
666
-	u16 pause_time;          /* Flow control pause timer */
667
-	bool send_xon;           /* Flow control send XON */
668
-	bool strict_ieee;        /* Strict IEEE mode */
669
-	enum e1000_fc_mode current_mode; /* FC mode in effect */
670
-	enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
671
-};
672
-
673
-struct e1000_dev_spec_82541 {
674
-	enum e1000_dsp_config dsp_config;
675
-	enum e1000_ffe_config ffe_config;
676
-	u16 spd_default;
677
-	bool phy_init_script;
678
-};
679
-
680
-struct e1000_dev_spec_82542 {
681
-	bool dma_fairness;
682
-};
683
-
684
-struct e1000_dev_spec_82543 {
685
-	u32  tbi_compatibility;
686
-	bool dma_fairness;
687
-	bool init_phy_disabled;
688
-};
689
-
690
-struct e1000_hw {
691
-	void *back;
692
-
693
-	u8 __iomem *hw_addr;
694
-	u8 __iomem *flash_address;
695
-	unsigned long io_base;
696
-
697
-	struct e1000_mac_info  mac;
698
-	struct e1000_fc_info   fc;
699
-	struct e1000_phy_info  phy;
700
-	struct e1000_nvm_info  nvm;
701
-	struct e1000_bus_info  bus;
702
-	struct e1000_host_mng_dhcp_cookie mng_cookie;
703
-
704
-	union {
705
-		struct e1000_dev_spec_82541	_82541;
706
-		struct e1000_dev_spec_82542	_82542;
707
-		struct e1000_dev_spec_82543	_82543;
708
-	} dev_spec;
709
-
710
-	u16 device_id;
711
-	u16 subsystem_vendor_id;
712
-	u16 subsystem_device_id;
713
-	u16 vendor_id;
714
-
715
-	u8  revision_id;
716
-};
717
-
718
-#include "e1000_82541.h"
719
-#include "e1000_82543.h"
720
-
721
-/* These functions must be implemented by drivers */
722
-void e1000_pci_clear_mwi(struct e1000_hw *hw);
723
-void e1000_pci_set_mwi(struct e1000_hw *hw);
724
-s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
725
-void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
726
-void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
727
-
728
-#endif

+ 0
- 2196
src/drivers/net/e1000/e1000_mac.c
Разлика између датотеке није приказан због своје велике величине
Прегледај датотеку


+ 0
- 94
src/drivers/net/e1000/e1000_mac.h Прегледај датотеку

@@ -1,94 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2008 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-#ifndef _E1000_MAC_H_
32
-#define _E1000_MAC_H_
33
-
34
-/*
35
- * Functions that should not be called directly from drivers but can be used
36
- * by other files in this 'shared code'
37
- */
38
-void e1000_init_mac_ops_generic(struct e1000_hw *hw);
39
-void e1000_null_mac_generic(struct e1000_hw *hw);
40
-s32  e1000_null_ops_generic(struct e1000_hw *hw);
41
-s32  e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d);
42
-bool e1000_null_mng_mode(struct e1000_hw *hw);
43
-void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a);
44
-void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b);
45
-void e1000_null_mta_set(struct e1000_hw *hw, u32 a);
46
-void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a);
47
-s32  e1000_blink_led_generic(struct e1000_hw *hw);
48
-s32  e1000_check_for_copper_link_generic(struct e1000_hw *hw);
49
-s32  e1000_check_for_fiber_link_generic(struct e1000_hw *hw);
50
-s32  e1000_check_for_serdes_link_generic(struct e1000_hw *hw);
51
-s32  e1000_cleanup_led_generic(struct e1000_hw *hw);
52
-s32  e1000_commit_fc_settings_generic(struct e1000_hw *hw);
53
-s32  e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw);
54
-s32  e1000_config_fc_after_link_up_generic(struct e1000_hw *hw);
55
-s32  e1000_disable_pcie_master_generic(struct e1000_hw *hw);
56
-s32  e1000_force_mac_fc_generic(struct e1000_hw *hw);
57
-s32  e1000_get_auto_rd_done_generic(struct e1000_hw *hw);
58
-s32  e1000_get_bus_info_pci_generic(struct e1000_hw *hw);
59
-s32  e1000_get_bus_info_pcie_generic(struct e1000_hw *hw);
60
-void e1000_set_lan_id_single_port(struct e1000_hw *hw);
61
-void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw);
62
-s32  e1000_get_hw_semaphore_generic(struct e1000_hw *hw);
63
-s32  e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
64
-                                               u16 *duplex);
65
-s32  e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
66
-                                                     u16 *speed, u16 *duplex);
67
-s32  e1000_id_led_init_generic(struct e1000_hw *hw);
68
-s32  e1000_led_on_generic(struct e1000_hw *hw);
69
-s32  e1000_led_off_generic(struct e1000_hw *hw);
70
-void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
71
-	                               u8 *mc_addr_list, u32 mc_addr_count);
72
-s32  e1000_set_default_fc_generic(struct e1000_hw *hw);
73
-s32  e1000_set_fc_watermarks_generic(struct e1000_hw *hw);
74
-s32  e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw);
75
-s32  e1000_setup_led_generic(struct e1000_hw *hw);
76
-s32  e1000_setup_link_generic(struct e1000_hw *hw);
77
-
78
-u32  e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr);
79
-
80
-void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw);
81
-void e1000_clear_vfta_generic(struct e1000_hw *hw);
82
-void e1000_config_collision_dist_generic(struct e1000_hw *hw);
83
-void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count);
84
-void e1000_mta_set_generic(struct e1000_hw *hw, u32 hash_value);
85
-void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw);
86
-void e1000_put_hw_semaphore_generic(struct e1000_hw *hw);
87
-void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
88
-s32  e1000_check_alt_mac_addr_generic(struct e1000_hw *hw);
89
-void e1000_reset_adaptive_generic(struct e1000_hw *hw);
90
-void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop);
91
-void e1000_update_adaptive_generic(struct e1000_hw *hw);
92
-void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
93
-
94
-#endif

+ 0
- 909
src/drivers/net/e1000/e1000_main.c Прегледај датотеку

@@ -1,909 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2008 Intel Corporation.
5
-
6
-  Portions Copyright(c) 2010 Marty Connor <mdc@etherboot.org>
7
-  Portions Copyright(c) 2010 Entity Cyber, Inc.
8
-
9
-  This program is free software; you can redistribute it and/or modify it
10
-  under the terms and conditions of the GNU General Public License,
11
-  version 2, as published by the Free Software Foundation.
12
-
13
-  This program is distributed in the hope it will be useful, but WITHOUT
14
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
16
-  more details.
17
-
18
-  You should have received a copy of the GNU General Public License along with
19
-  this program; if not, write to the Free Software Foundation, Inc.,
20
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21
-
22
-  The full GNU General Public License is included in this distribution in
23
-  the file called "COPYING".
24
-
25
-  Contact Information:
26
-  Linux NICS <linux.nics@intel.com>
27
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
28
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
29
-
30
-*******************************************************************************/
31
-
32
-FILE_LICENCE ( GPL2_ONLY );
33
-
34
-#include "e1000.h"
35
-
36
-/**
37
- * e1000_irq_disable - Disable interrupt generation
38
- *
39
- * @adapter: board private structure
40
- **/
41
-static void e1000_irq_disable ( struct e1000_adapter *adapter )
42
-{
43
-	E1000_WRITE_REG ( &adapter->hw, E1000_IMC, ~0 );
44
-	E1000_WRITE_FLUSH ( &adapter->hw );
45
-}
46
-
47
-/**
48
- * e1000_irq_enable - Enable interrupt generation
49
- *
50
- * @adapter: board private structure
51
- **/
52
-static void e1000_irq_enable ( struct e1000_adapter *adapter )
53
-{
54
-	E1000_WRITE_REG(&adapter->hw, E1000_IMS, IMS_ENABLE_MASK);
55
-	E1000_WRITE_FLUSH(&adapter->hw);
56
-}
57
-
58
-/**
59
- * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
60
- * @adapter: board private structure to initialize
61
- *
62
- * e1000_sw_init initializes the Adapter private data structure.
63
- * Fields are initialized based on PCI device information and
64
- * OS network device settings (MTU size).
65
- **/
66
-static int e1000_sw_init(struct e1000_adapter *adapter)
67
-{
68
-	struct e1000_hw *hw = &adapter->hw;
69
-	struct pci_device  *pdev = adapter->pdev;
70
-
71
-	/* PCI config space info */
72
-
73
-	hw->vendor_id = pdev->vendor;
74
-	hw->device_id = pdev->device;
75
-
76
-	pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &hw->subsystem_vendor_id);
77
-	pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_device_id);
78
-
79
-	pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
80
-
81
-	pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);
82
-
83
-	adapter->rx_buffer_len = MAXIMUM_ETHERNET_VLAN_SIZE;
84
-	adapter->max_frame_size = MAXIMUM_ETHERNET_VLAN_SIZE +
85
-                                  ETH_HLEN + ETH_FCS_LEN;
86
-	adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
87
-
88
-	hw->fc.requested_mode = e1000_fc_none;
89
-
90
-	/* Initialize the hardware-specific values */
91
-	if (e1000_setup_init_funcs(hw, false)) {
92
-		DBG ("Hardware Initialization Failure\n");
93
-		return -EIO;
94
-	}
95
-
96
-	/* Explicitly disable IRQ since the NIC can be in any state. */
97
-	e1000_irq_disable ( adapter );
98
-
99
-	return 0;
100
-}
101
-
102
-int32_t e1000_read_pcie_cap_reg(struct e1000_hw *hw, uint32_t reg, uint16_t *value)
103
-{
104
-    struct e1000_adapter *adapter = hw->back;
105
-    uint16_t cap_offset;
106
-
107
-#define  PCI_CAP_ID_EXP        0x10    /* PCI Express */
108
-    cap_offset = pci_find_capability(adapter->pdev, PCI_CAP_ID_EXP);
109
-    if (!cap_offset)
110
-        return -E1000_ERR_CONFIG;
111
-
112
-    pci_read_config_word(adapter->pdev, cap_offset + reg, value);
113
-
114
-    return 0;
115
-}
116
-
117
-void e1000_pci_clear_mwi ( struct e1000_hw *hw )
118
-{
119
-	struct e1000_adapter *adapter = hw->back;
120
-
121
-	pci_write_config_word ( adapter->pdev, PCI_COMMAND,
122
-			        hw->bus.pci_cmd_word & ~PCI_COMMAND_INVALIDATE );
123
-}
124
-
125
-void e1000_pci_set_mwi ( struct e1000_hw *hw )
126
-{
127
-	struct e1000_adapter *adapter = hw->back;
128
-
129
-	pci_write_config_word ( adapter->pdev, PCI_COMMAND,
130
-                                hw->bus.pci_cmd_word );
131
-}
132
-
133
-void e1000_read_pci_cfg ( struct e1000_hw *hw, uint32_t reg, uint16_t *value )
134
-{
135
-	struct e1000_adapter *adapter = hw->back;
136
-
137
-	pci_read_config_word ( adapter->pdev, reg, value );
138
-}
139
-
140
-void e1000_write_pci_cfg ( struct e1000_hw *hw, uint32_t reg, uint16_t *value )
141
-{
142
-	struct e1000_adapter *adapter = hw->back;
143
-
144
-	pci_write_config_word ( adapter->pdev, reg, *value );
145
-}
146
-
147
-/**
148
- * e1000_init_manageability - disable interception of ARP packets
149
- *
150
- * @v adapter	e1000 private structure
151
- **/
152
-static void e1000_init_manageability ( struct e1000_adapter *adapter )
153
-{
154
-	if (adapter->en_mng_pt) {
155
-		u32 manc = E1000_READ_REG(&adapter->hw, E1000_MANC);
156
-
157
-		/* disable hardware interception of ARP */
158
-		manc &= ~(E1000_MANC_ARP_EN);
159
-
160
-		E1000_WRITE_REG(&adapter->hw, E1000_MANC, manc);
161
-	}
162
-}
163
-
164
-/**
165
- * e1000_setup_tx_resources - allocate Tx resources (Descriptors)
166
- *
167
- * @v adapter	e1000 private structure
168
- *
169
- * @ret rc       Returns 0 on success, negative on failure
170
- **/
171
-static int e1000_setup_tx_resources ( struct e1000_adapter *adapter )
172
-{
173
-	DBG ( "e1000_setup_tx_resources\n" );
174
-
175
-	/* Allocate transmit descriptor ring memory.
176
-	   It must not cross a 64K boundary because of hardware errata #23
177
-	   so we use malloc_dma() requesting a 128 byte block that is
178
-	   128 byte aligned. This should guarantee that the memory
179
-	   allocated will not cross a 64K boundary, because 128 is an
180
-	   even multiple of 65536 ( 65536 / 128 == 512 ), so all possible
181
-	   allocations of 128 bytes on a 128 byte boundary will not
182
-	   cross 64K bytes.
183
-	 */
184
-
185
-        adapter->tx_base =
186
-		malloc_dma ( adapter->tx_ring_size, adapter->tx_ring_size );
187
-
188
-	if ( ! adapter->tx_base ) {
189
-		return -ENOMEM;
190
-	}
191
-
192
-	memset ( adapter->tx_base, 0, adapter->tx_ring_size );
193
-
194
-	DBG ( "adapter->tx_base = %#08lx\n", virt_to_bus ( adapter->tx_base ) );
195
-
196
-	return 0;
197
-}
198
-
199
-/**
200
- * e1000_process_tx_packets - process transmitted packets
201
- *
202
- * @v netdev	network interface device structure
203
- **/
204
-static void e1000_process_tx_packets ( struct net_device *netdev )
205
-{
206
-	struct e1000_adapter *adapter = netdev_priv ( netdev );
207
-	uint32_t i;
208
-	uint32_t tx_status;
209
-	struct e1000_tx_desc *tx_curr_desc;
210
-
211
-	/* Check status of transmitted packets
212
-	 */
213
-	while ( ( i = adapter->tx_head ) != adapter->tx_tail ) {
214
-
215
-		tx_curr_desc = ( void * )  ( adapter->tx_base ) +
216
-					   ( i * sizeof ( *adapter->tx_base ) );
217
-
218
-		tx_status = tx_curr_desc->upper.data;
219
-
220
-		/* if the packet at tx_head is not owned by hardware it is for us */
221
-		if ( ! ( tx_status & E1000_TXD_STAT_DD ) )
222
-			break;
223
-
224
-		DBG ( "Sent packet. tx_head: %d tx_tail: %d tx_status: %#08x\n",
225
-		      adapter->tx_head, adapter->tx_tail, tx_status );
226
-
227
-		if ( tx_status & ( E1000_TXD_STAT_EC | E1000_TXD_STAT_LC |
228
-				   E1000_TXD_STAT_TU ) ) {
229
-			netdev_tx_complete_err ( netdev, adapter->tx_iobuf[i], -EINVAL );
230
-			DBG ( "Error transmitting packet, tx_status: %#08x\n",
231
-			      tx_status );
232
-		} else {
233
-			netdev_tx_complete ( netdev, adapter->tx_iobuf[i] );
234
-			DBG ( "Success transmitting packet, tx_status: %#08x\n",
235
-			      tx_status );
236
-		}
237
-
238
-		/* Decrement count of used descriptors, clear this descriptor
239
-		 */
240
-		adapter->tx_fill_ctr--;
241
-		memset ( tx_curr_desc, 0, sizeof ( *tx_curr_desc ) );
242
-
243
-		adapter->tx_head = ( adapter->tx_head + 1 ) % NUM_TX_DESC;
244
-	}
245
-}
246
-
247
-static void e1000_free_tx_resources ( struct e1000_adapter *adapter )
248
-{
249
-	DBG ( "e1000_free_tx_resources\n" );
250
-
251
-        free_dma ( adapter->tx_base, adapter->tx_ring_size );
252
-}
253
-
254
-/**
255
- * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
256
- * @adapter: board private structure
257
- *
258
- * Configure the Tx unit of the MAC after a reset.
259
- **/
260
-static void e1000_configure_tx ( struct e1000_adapter *adapter )
261
-{
262
-	struct e1000_hw *hw = &adapter->hw;
263
-	uint32_t tctl;
264
-
265
-	DBG ( "e1000_configure_tx\n" );
266
-
267
-	E1000_WRITE_REG ( hw, E1000_TDBAH(0), 0 );
268
-	E1000_WRITE_REG ( hw, E1000_TDBAL(0), virt_to_bus ( adapter->tx_base ) );
269
-	E1000_WRITE_REG ( hw, E1000_TDLEN(0), adapter->tx_ring_size );
270
-
271
-        DBG ( "E1000_TDBAL(0): %#08x\n",  E1000_READ_REG ( hw, E1000_TDBAL(0) ) );
272
-        DBG ( "E1000_TDLEN(0): %d\n",     E1000_READ_REG ( hw, E1000_TDLEN(0) ) );
273
-
274
-	/* Setup the HW Tx Head and Tail descriptor pointers */
275
-	E1000_WRITE_REG ( hw, E1000_TDH(0), 0 );
276
-	E1000_WRITE_REG ( hw, E1000_TDT(0), 0 );
277
-
278
-	adapter->tx_head = 0;
279
-	adapter->tx_tail = 0;
280
-	adapter->tx_fill_ctr = 0;
281
-
282
-	/* Setup Transmit Descriptor Settings for eop descriptor */
283
-	tctl = E1000_TCTL_PSP | E1000_TCTL_EN |
284
-		(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) |
285
-		(E1000_COLLISION_DISTANCE  << E1000_COLD_SHIFT);
286
-
287
-	e1000_config_collision_dist ( hw );
288
-
289
-	E1000_WRITE_REG ( hw, E1000_TCTL, tctl );
290
-        E1000_WRITE_FLUSH ( hw );
291
-}
292
-
293
-static void e1000_free_rx_resources ( struct e1000_adapter *adapter )
294
-{
295
-	int i;
296
-
297
-	DBG ( "e1000_free_rx_resources\n" );
298
-
299
-	free_dma ( adapter->rx_base, adapter->rx_ring_size );
300
-
301
-	for ( i = 0; i < NUM_RX_DESC; i++ ) {
302
-		free_iob ( adapter->rx_iobuf[i] );
303
-	}
304
-}
305
-
306
-/**
307
- * e1000_refill_rx_ring - allocate Rx io_buffers
308
- *
309
- * @v adapter	e1000 private structure
310
- *
311
- * @ret rc       Returns 0 on success, negative on failure
312
- **/
313
-static int e1000_refill_rx_ring ( struct e1000_adapter *adapter )
314
-{
315
-	int i, rx_curr;
316
-	int rc = 0;
317
-	struct e1000_rx_desc *rx_curr_desc;
318
-	struct e1000_hw *hw = &adapter->hw;
319
-	struct io_buffer *iob;
320
-
321
-	DBG ("e1000_refill_rx_ring\n");
322
-
323
-	for ( i = 0; i < NUM_RX_DESC; i++ ) {
324
-		rx_curr = ( ( adapter->rx_curr + i ) % NUM_RX_DESC );
325
-		rx_curr_desc = adapter->rx_base + rx_curr;
326
-
327
-		if ( rx_curr_desc->status & E1000_RXD_STAT_DD )
328
-			continue;
329
-
330
-		if ( adapter->rx_iobuf[rx_curr] != NULL )
331
-			continue;
332
-
333
-		DBG2 ( "Refilling rx desc %d\n", rx_curr );
334
-
335
-		iob = alloc_iob ( MAXIMUM_ETHERNET_VLAN_SIZE );
336
-		adapter->rx_iobuf[rx_curr] = iob;
337
-
338
-		if ( ! iob ) {
339
-			DBG ( "alloc_iob failed\n" );
340
-			rc = -ENOMEM;
341
-			break;
342
-		} else {
343
-			rx_curr_desc->buffer_addr = virt_to_bus ( iob->data );
344
-
345
-			E1000_WRITE_REG ( hw, E1000_RDT(0), rx_curr );
346
-		}
347
-	}
348
-	return rc;
349
-}
350
-
351
-/**
352
- * e1000_setup_rx_resources - allocate Rx resources (Descriptors)
353
- *
354
- * @v adapter	e1000 private structure
355
- *
356
- * @ret rc       Returns 0 on success, negative on failure
357
- **/
358
-static int e1000_setup_rx_resources ( struct e1000_adapter *adapter )
359
-{
360
-	int i, rc = 0;
361
-
362
-	DBG ( "e1000_setup_rx_resources\n" );
363
-
364
-	/* Allocate receive descriptor ring memory.
365
-	   It must not cross a 64K boundary because of hardware errata
366
-	 */
367
-
368
-        adapter->rx_base =
369
-		malloc_dma ( adapter->rx_ring_size, adapter->rx_ring_size );
370
-
371
-	if ( ! adapter->rx_base ) {
372
-		return -ENOMEM;
373
-	}
374
-	memset ( adapter->rx_base, 0, adapter->rx_ring_size );
375
-
376
-	for ( i = 0; i < NUM_RX_DESC; i++ ) {
377
-		/* let e1000_refill_rx_ring() io_buffer allocations */
378
-		adapter->rx_iobuf[i] = NULL;
379
-	}
380
-
381
-	/* allocate io_buffers */
382
-	rc = e1000_refill_rx_ring ( adapter );
383
-	if ( rc < 0 )
384
-		e1000_free_rx_resources ( adapter );
385
-
386
-	return rc;
387
-}
388
-
389
-/**
390
- * e1000_configure_rx - Configure 8254x Receive Unit after Reset
391
- * @adapter: board private structure
392
- *
393
- * Configure the Rx unit of the MAC after a reset.
394
- **/
395
-static void e1000_configure_rx ( struct e1000_adapter *adapter )
396
-{
397
-	struct e1000_hw *hw = &adapter->hw;
398
-	uint32_t rctl;
399
-
400
-	DBG ( "e1000_configure_rx\n" );
401
-
402
-	/* disable receives while setting up the descriptors */
403
-	rctl = E1000_READ_REG ( hw, E1000_RCTL );
404
-	E1000_WRITE_REG ( hw, E1000_RCTL, rctl & ~E1000_RCTL_EN );
405
-	E1000_WRITE_FLUSH ( hw );
406
-	mdelay(10);
407
-
408
-	adapter->rx_curr = 0;
409
-
410
-	/* Setup the HW Rx Head and Tail Descriptor Pointers and
411
-	 * the Base and Length of the Rx Descriptor Ring */
412
-
413
-	E1000_WRITE_REG ( hw, E1000_RDBAL(0), virt_to_bus ( adapter->rx_base ) );
414
-	E1000_WRITE_REG ( hw, E1000_RDBAH(0), 0 );
415
-	E1000_WRITE_REG ( hw, E1000_RDLEN(0), adapter->rx_ring_size );
416
-
417
-	E1000_WRITE_REG ( hw, E1000_RDH(0), 0 );
418
-	E1000_WRITE_REG ( hw, E1000_RDT(0), NUM_RX_DESC - 1 );
419
-
420
-	/* Enable Receives */
421
-	rctl |=  E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
422
-		 E1000_RCTL_MPE | E1000_RCTL_SECRC;
423
-	E1000_WRITE_REG ( hw, E1000_RCTL, rctl );
424
-	E1000_WRITE_FLUSH ( hw );
425
-
426
-        DBG ( "E1000_RDBAL(0): %#08x\n",  E1000_READ_REG ( hw, E1000_RDBAL(0) ) );
427
-        DBG ( "E1000_RDLEN(0): %d\n",     E1000_READ_REG ( hw, E1000_RDLEN(0) ) );
428
-        DBG ( "E1000_RCTL:  %#08x\n",  E1000_READ_REG ( hw, E1000_RCTL ) );
429
-}
430
-
431
-/**
432
- * e1000_process_rx_packets - process received packets
433
- *
434
- * @v netdev	network interface device structure
435
- **/
436
-static void e1000_process_rx_packets ( struct net_device *netdev )
437
-{
438
-	struct e1000_adapter *adapter = netdev_priv ( netdev );
439
-	uint32_t i;
440
-	uint32_t rx_status;
441
-	uint32_t rx_len;
442
-	uint32_t rx_err;
443
-	struct e1000_rx_desc *rx_curr_desc;
444
-
445
-	/* Process received packets
446
-	 */
447
-	while ( 1 ) {
448
-
449
-		i = adapter->rx_curr;
450
-
451
-		rx_curr_desc = ( void * )  ( adapter->rx_base ) +
452
-			          ( i * sizeof ( *adapter->rx_base ) );
453
-		rx_status = rx_curr_desc->status;
454
-
455
-		DBG2 ( "Before DD Check RX_status: %#08x\n", rx_status );
456
-
457
-		if ( ! ( rx_status & E1000_RXD_STAT_DD ) )
458
-			break;
459
-
460
-		if ( adapter->rx_iobuf[i] == NULL )
461
-			break;
462
-
463
-		DBG ( "E1000_RCTL = %#08x\n", E1000_READ_REG ( &adapter->hw, E1000_RCTL ) );
464
-
465
-		rx_len = rx_curr_desc->length;
466
-
467
-                DBG ( "Received packet, rx_curr: %d  rx_status: %#08x  rx_len: %d\n",
468
-                      i, rx_status, rx_len );
469
-
470
-                rx_err = rx_curr_desc->errors;
471
-
472
-		iob_put ( adapter->rx_iobuf[i], rx_len );
473
-
474
-		if ( rx_err & E1000_RXD_ERR_FRAME_ERR_MASK ) {
475
-
476
-			netdev_rx_err ( netdev, adapter->rx_iobuf[i], -EINVAL );
477
-			DBG ( "e1000_poll: Corrupted packet received!"
478
-			      " rx_err: %#08x\n", rx_err );
479
-		} else {
480
-			/* Add this packet to the receive queue. */
481
-			netdev_rx ( netdev, adapter->rx_iobuf[i] );
482
-		}
483
-		adapter->rx_iobuf[i] = NULL;
484
-
485
-		memset ( rx_curr_desc, 0, sizeof ( *rx_curr_desc ) );
486
-
487
-		adapter->rx_curr = ( adapter->rx_curr + 1 ) % NUM_RX_DESC;
488
-	}
489
-}
490
-
491
-/**
492
- * e1000_reset - Put e1000 NIC in known initial state
493
- *
494
- * @v adapter	e1000 private structure
495
- **/
496
-void e1000_reset ( struct e1000_adapter *adapter )
497
-{
498
-	struct e1000_mac_info *mac = &adapter->hw.mac;
499
-	u32 pba = 0;
500
-
501
-	DBG ( "e1000_reset\n" );
502
-
503
-	switch (mac->type) {
504
-	case e1000_82542:
505
-	case e1000_82543:
506
-	case e1000_82544:
507
-	case e1000_82540:
508
-	case e1000_82541:
509
-	case e1000_82541_rev_2:
510
-		pba = E1000_PBA_48K;
511
-		break;
512
-	case e1000_82545:
513
-	case e1000_82545_rev_3:
514
-	case e1000_82546:
515
-	case e1000_82546_rev_3:
516
-		pba = E1000_PBA_48K;
517
-		break;
518
-	case e1000_82547:
519
-	case e1000_82547_rev_2:
520
-		pba = E1000_PBA_30K;
521
-		break;
522
-	case e1000_undefined:
523
-	case e1000_num_macs:
524
-		break;
525
-	}
526
-
527
-	E1000_WRITE_REG ( &adapter->hw, E1000_PBA, pba );
528
-
529
-	/* Allow time for pending master requests to run */
530
-	e1000_reset_hw ( &adapter->hw );
531
-
532
-	if ( mac->type >= e1000_82544 )
533
-		E1000_WRITE_REG ( &adapter->hw, E1000_WUC, 0 );
534
-
535
-	if ( e1000_init_hw ( &adapter->hw ) )
536
-		DBG ( "Hardware Error\n" );
537
-
538
-	e1000_reset_adaptive ( &adapter->hw );
539
-	e1000_get_phy_info ( &adapter->hw );
540
-
541
-	e1000_init_manageability ( adapter );
542
-}
543
-
544
-/** Functions that implement the iPXE driver API **/
545
-
546
-/**
547
- * e1000_close - Disables a network interface
548
- *
549
- * @v netdev	network interface device structure
550
- *
551
- **/
552
-static void e1000_close ( struct net_device *netdev )
553
-{
554
-	struct e1000_adapter *adapter = netdev_priv ( netdev );
555
-	struct e1000_hw *hw = &adapter->hw;
556
-	uint32_t rctl;
557
-
558
-	DBG ( "e1000_close\n" );
559
-
560
-	/* Disable and acknowledge interrupts */
561
-	e1000_irq_disable ( adapter );
562
-	E1000_READ_REG ( hw, E1000_ICR );
563
-
564
-	/* disable receives */
565
-	rctl = E1000_READ_REG ( hw, E1000_RCTL );
566
-	E1000_WRITE_REG ( hw, E1000_RCTL, rctl & ~E1000_RCTL_EN );
567
-	E1000_WRITE_FLUSH ( hw );
568
-
569
-	e1000_reset_hw ( hw );
570
-
571
-	e1000_free_tx_resources ( adapter );
572
-	e1000_free_rx_resources ( adapter );
573
-}
574
-
575
-/**
576
- * e1000_transmit - Transmit a packet
577
- *
578
- * @v netdev	Network device
579
- * @v iobuf	I/O buffer
580
- *
581
- * @ret rc       Returns 0 on success, negative on failure
582
- */
583
-static int e1000_transmit ( struct net_device *netdev, struct io_buffer *iobuf )
584
-{
585
-	struct e1000_adapter *adapter = netdev_priv( netdev );
586
-	struct e1000_hw *hw = &adapter->hw;
587
-	uint32_t tx_curr = adapter->tx_tail;
588
-	struct e1000_tx_desc *tx_curr_desc;
589
-
590
-	DBG ("e1000_transmit\n");
591
-
592
-	if ( adapter->tx_fill_ctr == NUM_TX_DESC ) {
593
-		DBG ("TX overflow\n");
594
-		return -ENOBUFS;
595
-	}
596
-
597
-	/* Save pointer to iobuf we have been given to transmit,
598
-	   netdev_tx_complete() will need it later
599
-	 */
600
-	adapter->tx_iobuf[tx_curr] = iobuf;
601
-
602
-	tx_curr_desc = ( void * ) ( adapter->tx_base ) +
603
-		       ( tx_curr * sizeof ( *adapter->tx_base ) );
604
-
605
-	DBG ( "tx_curr_desc = %#08lx\n", virt_to_bus ( tx_curr_desc ) );
606
-	DBG ( "tx_curr_desc + 16 = %#08lx\n", virt_to_bus ( tx_curr_desc ) + 16 );
607
-	DBG ( "iobuf->data = %#08lx\n", virt_to_bus ( iobuf->data ) );
608
-
609
-	/* Add the packet to TX ring
610
-	 */
611
-	tx_curr_desc->buffer_addr =
612
-		virt_to_bus ( iobuf->data );
613
-	tx_curr_desc->lower.data =
614
-		E1000_TXD_CMD_RS | E1000_TXD_CMD_EOP |
615
-		E1000_TXD_CMD_IFCS | iob_len ( iobuf );
616
-	tx_curr_desc->upper.data = 0;
617
-
618
-	DBG ( "TX fill: %d tx_curr: %d addr: %#08lx len: %zd\n", adapter->tx_fill_ctr,
619
-	      tx_curr, virt_to_bus ( iobuf->data ), iob_len ( iobuf ) );
620
-
621
-	/* Point to next free descriptor */
622
-	adapter->tx_tail = ( adapter->tx_tail + 1 ) % NUM_TX_DESC;
623
-	adapter->tx_fill_ctr++;
624
-
625
-	/* Write new tail to NIC, making packet available for transmit
626
-	 */
627
-	wmb();
628
-	E1000_WRITE_REG ( hw, E1000_TDT(0), adapter->tx_tail );
629
-
630
-	return 0;
631
-}
632
-
633
-/**
634
- * e1000_poll - Poll for received packets
635
- *
636
- * @v netdev	Network device
637
- */
638
-static void e1000_poll ( struct net_device *netdev )
639
-{
640
-	struct e1000_adapter *adapter = netdev_priv( netdev );
641
-	struct e1000_hw *hw = &adapter->hw;
642
-
643
-	uint32_t icr;
644
-
645
-	DBGP ( "e1000_poll\n" );
646
-
647
-	/* Acknowledge interrupts */
648
-	icr = E1000_READ_REG ( hw, E1000_ICR );
649
-	if ( ! icr )
650
-		return;
651
-
652
-        DBG ( "e1000_poll: intr_status = %#08x\n", icr );
653
-
654
-	e1000_process_tx_packets ( netdev );
655
-
656
-	e1000_process_rx_packets ( netdev );
657
-
658
-	e1000_refill_rx_ring(adapter);
659
-}
660
-
661
-/**
662
- * e1000_irq - enable or Disable interrupts
663
- *
664
- * @v adapter   e1000 adapter
665
- * @v action    requested interrupt action
666
- **/
667
-static void e1000_irq ( struct net_device *netdev, int enable )
668
-{
669
-	struct e1000_adapter *adapter = netdev_priv ( netdev );
670
-
671
-	DBG ( "e1000_irq\n" );
672
-
673
-	if ( enable ) {
674
-		e1000_irq_enable ( adapter );
675
-	} else {
676
-		e1000_irq_disable ( adapter );
677
-	}
678
-}
679
-
680
-static struct net_device_operations e1000_operations;
681
-
682
-/**
683
- * e1000_probe - Initial configuration of e1000 NIC
684
- *
685
- * @v pci	PCI device
686
- * @v id	PCI IDs
687
- *
688
- * @ret rc	Return status code
689
- **/
690
-int e1000_probe ( struct pci_device *pdev )
691
-{
692
-	int i, err;
693
-	struct net_device *netdev;
694
-	struct e1000_adapter *adapter;
695
-	unsigned long mmio_start, mmio_len;
696
-
697
-	DBG ( "e1000_probe\n" );
698
-
699
-	err = -ENOMEM;
700
-
701
-	/* Allocate net device ( also allocates memory for netdev->priv
702
-	   and makes netdev-priv point to it ) */
703
-	netdev = alloc_etherdev ( sizeof ( struct e1000_adapter ) );
704
-	if ( ! netdev )
705
-		goto err_alloc_etherdev;
706
-
707
-	/* Associate e1000-specific network operations operations with
708
-	 * generic network device layer */
709
-	netdev_init ( netdev, &e1000_operations );
710
-
711
-	/* Associate this network device with given PCI device */
712
-	pci_set_drvdata ( pdev, netdev );
713
-	netdev->dev = &pdev->dev;
714
-
715
-	/* Initialize driver private storage */
716
-	adapter = netdev_priv ( netdev );
717
-        memset ( adapter, 0, ( sizeof ( *adapter ) ) );
718
-
719
-	adapter->pdev       = pdev;
720
-
721
-	adapter->ioaddr     = pdev->ioaddr;
722
-        adapter->hw.io_base = pdev->ioaddr;
723
-
724
-        adapter->irqno      = pdev->irq;
725
-	adapter->netdev     = netdev;
726
-	adapter->hw.back    = adapter;
727
-
728
-	adapter->tx_ring_size = sizeof ( *adapter->tx_base ) * NUM_TX_DESC;
729
-	adapter->rx_ring_size = sizeof ( *adapter->rx_base ) * NUM_RX_DESC;
730
-
731
-	mmio_start = pci_bar_start ( pdev, PCI_BASE_ADDRESS_0 );
732
-	mmio_len   = pci_bar_size  ( pdev, PCI_BASE_ADDRESS_0 );
733
-
734
-	DBG ( "mmio_start: %#08lx\n", mmio_start );
735
-	DBG ( "mmio_len: %#08lx\n", mmio_len );
736
-
737
-	/* Fix up PCI device */
738
-	adjust_pci_device ( pdev );
739
-
740
-	err = -EIO;
741
-
742
-	adapter->hw.hw_addr = ioremap ( mmio_start, mmio_len );
743
-	DBG ( "adapter->hw.hw_addr: %p\n", adapter->hw.hw_addr );
744
-
745
-	if ( ! adapter->hw.hw_addr )
746
-		goto err_ioremap;
747
-
748
-	/* Hardware features, flags and workarounds */
749
-	if (adapter->hw.mac.type >= e1000_82540) {
750
-		adapter->flags |= E1000_FLAG_HAS_SMBUS;
751
-		adapter->flags |= E1000_FLAG_HAS_INTR_MODERATION;
752
-	}
753
-
754
-	if (adapter->hw.mac.type == e1000_82543)
755
-		adapter->flags |= E1000_FLAG_BAD_TX_CARRIER_STATS_FD;
756
-
757
-	adapter->hw.phy.autoneg_wait_to_complete = true;
758
-	adapter->hw.mac.adaptive_ifs = true;
759
-
760
-	/* setup the private structure */
761
-	if ( ( err = e1000_sw_init ( adapter ) ) )
762
-		goto err_sw_init;
763
-
764
-	if ((err = e1000_init_mac_params(&adapter->hw)))
765
-		goto err_hw_init;
766
-
767
-	if ((err = e1000_init_nvm_params(&adapter->hw)))
768
-		goto err_hw_init;
769
-
770
-        /* Force auto-negotiated speed and duplex */
771
-        adapter->hw.mac.autoneg = 1;
772
-
773
-	if ((err = e1000_init_phy_params(&adapter->hw)))
774
-		goto err_hw_init;
775
-
776
-	DBG ( "adapter->hw.mac.type: %#08x\n", adapter->hw.mac.type );
777
-
778
-	/* before reading the EEPROM, reset the controller to
779
-	 * put the device in a known good starting state
780
-	 */
781
-	err = e1000_reset_hw ( &adapter->hw );
782
-	if ( err < 0 ) {
783
-		DBG ( "Hardware Initialization Failed\n" );
784
-		goto err_reset;
785
-	}
786
-	/* make sure the NVM is good */
787
-
788
-	if ( e1000_validate_nvm_checksum(&adapter->hw) < 0 ) {
789
-		DBG ( "The NVM Checksum Is Not Valid\n" );
790
-		err = -EIO;
791
-		goto err_eeprom;
792
-	}
793
-
794
-	/* copy the MAC address out of the EEPROM */
795
-	if ( e1000_read_mac_addr ( &adapter->hw ) )
796
-		DBG ( "EEPROM Read Error\n" );
797
-
798
-        memcpy ( netdev->hw_addr, adapter->hw.mac.perm_addr, ETH_ALEN );
799
-
800
-	/* reset the hardware with the new settings */
801
-	e1000_reset ( adapter );
802
-
803
-	if ( ( err = register_netdev ( netdev ) ) != 0)
804
-		goto err_register;
805
-
806
-	/* Mark as link up; we don't yet handle link state */
807
-	netdev_link_up ( netdev );
808
-
809
-	for (i = 0; i < 6; i++)
810
-		DBG ("%02x%s", netdev->ll_addr[i], i == 5 ? "\n" : ":");
811
-
812
-	DBG ( "e1000_probe succeeded!\n" );
813
-
814
-	/* No errors, return success */
815
-	return 0;
816
-
817
-/* Error return paths */
818
-err_reset:
819
-err_register:
820
-err_hw_init:
821
-err_eeprom:
822
-	if (!e1000_check_reset_block(&adapter->hw))
823
-		e1000_phy_hw_reset(&adapter->hw);
824
-	if (adapter->hw.flash_address)
825
-		iounmap(adapter->hw.flash_address);
826
-err_sw_init:
827
-	iounmap ( adapter->hw.hw_addr );
828
-err_ioremap:
829
-	netdev_put ( netdev );
830
-err_alloc_etherdev:
831
-	return err;
832
-}
833
-
834
-/**
835
- * e1000_remove - Device Removal Routine
836
- *
837
- * @v pdev PCI device information struct
838
- *
839
- **/
840
-void e1000_remove ( struct pci_device *pdev )
841
-{
842
-	struct net_device *netdev = pci_get_drvdata ( pdev );
843
-	struct e1000_adapter *adapter = netdev_priv ( netdev );
844
-
845
-	DBG ( "e1000_remove\n" );
846
-
847
-	if ( adapter->hw.flash_address )
848
-		iounmap ( adapter->hw.flash_address );
849
-	if  ( adapter->hw.hw_addr )
850
-		iounmap ( adapter->hw.hw_addr );
851
-
852
-	unregister_netdev ( netdev );
853
-	e1000_reset_hw ( &adapter->hw );
854
-	netdev_nullify ( netdev );
855
-	netdev_put ( netdev );
856
-}
857
-
858
-/**
859
- * e1000_open - Called when a network interface is made active
860
- *
861
- * @v netdev	network interface device structure
862
- * @ret rc	Return status code, 0 on success, negative value on failure
863
- *
864
- **/
865
-static int e1000_open ( struct net_device *netdev )
866
-{
867
-	struct e1000_adapter *adapter = netdev_priv(netdev);
868
-	int err;
869
-
870
-	DBG ( "e1000_open\n" );
871
-
872
-	/* allocate transmit descriptors */
873
-	err = e1000_setup_tx_resources ( adapter );
874
-	if ( err ) {
875
-		DBG ( "Error setting up TX resources!\n" );
876
-		goto err_setup_tx;
877
-	}
878
-
879
-	/* allocate receive descriptors */
880
-	err = e1000_setup_rx_resources ( adapter );
881
-	if ( err ) {
882
-		DBG ( "Error setting up RX resources!\n" );
883
-		goto err_setup_rx;
884
-	}
885
-
886
-	e1000_configure_tx ( adapter );
887
-
888
-	e1000_configure_rx ( adapter );
889
-
890
-        DBG ( "E1000_RXDCTL(0): %#08x\n",  E1000_READ_REG ( &adapter->hw, E1000_RXDCTL(0) ) );
891
-
892
-	return 0;
893
-
894
-err_setup_rx:
895
-	e1000_free_tx_resources ( adapter );
896
-err_setup_tx:
897
-	e1000_reset ( adapter );
898
-
899
-	return err;
900
-}
901
-
902
-/** e1000 net device operations */
903
-static struct net_device_operations e1000_operations = {
904
-        .open           = e1000_open,
905
-        .close          = e1000_close,
906
-        .transmit       = e1000_transmit,
907
-        .poll           = e1000_poll,
908
-        .irq            = e1000_irq,
909
-};

+ 0
- 389
src/drivers/net/e1000/e1000_manage.c Прегледај датотеку

@@ -1,389 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2008 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-#if 0
32
-
33
-#include "e1000_api.h"
34
-
35
-static u8 e1000_calculate_checksum(u8 *buffer, u32 length);
36
-
37
-/**
38
- *  e1000_calculate_checksum - Calculate checksum for buffer
39
- *  @buffer: pointer to EEPROM
40
- *  @length: size of EEPROM to calculate a checksum for
41
- *
42
- *  Calculates the checksum for some buffer on a specified length.  The
43
- *  checksum calculated is returned.
44
- **/
45
-static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
46
-{
47
-	u32 i;
48
-	u8  sum = 0;
49
-
50
-	DEBUGFUNC("e1000_calculate_checksum");
51
-
52
-	if (!buffer)
53
-		return 0;
54
-
55
-	for (i = 0; i < length; i++)
56
-		sum += buffer[i];
57
-
58
-	return (u8) (0 - sum);
59
-}
60
-
61
-/**
62
- *  e1000_mng_enable_host_if_generic - Checks host interface is enabled
63
- *  @hw: pointer to the HW structure
64
- *
65
- *  Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
66
- *
67
- *  This function checks whether the HOST IF is enabled for command operation
68
- *  and also checks whether the previous command is completed.  It busy waits
69
- *  in case of previous command is not completed.
70
- **/
71
-s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw)
72
-{
73
-	u32 hicr;
74
-	s32 ret_val = E1000_SUCCESS;
75
-	u8  i;
76
-
77
-	DEBUGFUNC("e1000_mng_enable_host_if_generic");
78
-
79
-	/* Check that the host interface is enabled. */
80
-	hicr = E1000_READ_REG(hw, E1000_HICR);
81
-	if ((hicr & E1000_HICR_EN) == 0) {
82
-		DEBUGOUT("E1000_HOST_EN bit disabled.\n");
83
-		ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
84
-		goto out;
85
-	}
86
-	/* check the previous command is completed */
87
-	for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
88
-		hicr = E1000_READ_REG(hw, E1000_HICR);
89
-		if (!(hicr & E1000_HICR_C))
90
-			break;
91
-		msec_delay_irq(1);
92
-	}
93
-
94
-	if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
95
-		DEBUGOUT("Previous command timeout failed .\n");
96
-		ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
97
-		goto out;
98
-	}
99
-
100
-out:
101
-	return ret_val;
102
-}
103
-
104
-/**
105
- *  e1000_check_mng_mode_generic - Generic check management mode
106
- *  @hw: pointer to the HW structure
107
- *
108
- *  Reads the firmware semaphore register and returns true (>0) if
109
- *  manageability is enabled, else false (0).
110
- **/
111
-bool e1000_check_mng_mode_generic(struct e1000_hw *hw)
112
-{
113
-	u32 fwsm;
114
-
115
-	DEBUGFUNC("e1000_check_mng_mode_generic");
116
-
117
-	fwsm = E1000_READ_REG(hw, E1000_FWSM);
118
-
119
-	return (fwsm & E1000_FWSM_MODE_MASK) ==
120
-	        (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
121
-}
122
-
123
-/**
124
- *  e1000_enable_tx_pkt_filtering_generic - Enable packet filtering on TX
125
- *  @hw: pointer to the HW structure
126
- *
127
- *  Enables packet filtering on transmit packets if manageability is enabled
128
- *  and host interface is enabled.
129
- **/
130
-bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw)
131
-{
132
-	struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
133
-	u32 *buffer = (u32 *)&hw->mng_cookie;
134
-	u32 offset;
135
-	s32 ret_val, hdr_csum, csum;
136
-	u8 i, len;
137
-	bool tx_filter = true;
138
-
139
-	DEBUGFUNC("e1000_enable_tx_pkt_filtering_generic");
140
-
141
-	/* No manageability, no filtering */
142
-	if (!hw->mac.ops.check_mng_mode(hw)) {
143
-		tx_filter = false;
144
-		goto out;
145
-	}
146
-
147
-	/*
148
-	 * If we can't read from the host interface for whatever
149
-	 * reason, disable filtering.
150
-	 */
151
-	ret_val = hw->mac.ops.mng_enable_host_if(hw);
152
-	if (ret_val != E1000_SUCCESS) {
153
-		tx_filter = false;
154
-		goto out;
155
-	}
156
-
157
-	/* Read in the header.  Length and offset are in dwords. */
158
-	len    = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
159
-	offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
160
-	for (i = 0; i < len; i++) {
161
-		*(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw,
162
-		                                           E1000_HOST_IF,
163
-		                                           offset + i);
164
-	}
165
-	hdr_csum = hdr->checksum;
166
-	hdr->checksum = 0;
167
-	csum = e1000_calculate_checksum((u8 *)hdr,
168
-	                                E1000_MNG_DHCP_COOKIE_LENGTH);
169
-	/*
170
-	 * If either the checksums or signature don't match, then
171
-	 * the cookie area isn't considered valid, in which case we
172
-	 * take the safe route of assuming Tx filtering is enabled.
173
-	 */
174
-	if (hdr_csum != csum)
175
-		goto out;
176
-	if (hdr->signature != E1000_IAMT_SIGNATURE)
177
-		goto out;
178
-
179
-	/* Cookie area is valid, make the final check for filtering. */
180
-	if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))
181
-		tx_filter = false;
182
-
183
-out:
184
-	hw->mac.tx_pkt_filtering = tx_filter;
185
-	return tx_filter;
186
-}
187
-
188
-/**
189
- *  e1000_mng_write_dhcp_info_generic - Writes DHCP info to host interface
190
- *  @hw: pointer to the HW structure
191
- *  @buffer: pointer to the host interface
192
- *  @length: size of the buffer
193
- *
194
- *  Writes the DHCP information to the host interface.
195
- **/
196
-s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, u8 *buffer,
197
-                                      u16 length)
198
-{
199
-	struct e1000_host_mng_command_header hdr;
200
-	s32 ret_val;
201
-	u32 hicr;
202
-
203
-	DEBUGFUNC("e1000_mng_write_dhcp_info_generic");
204
-
205
-	hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
206
-	hdr.command_length = length;
207
-	hdr.reserved1 = 0;
208
-	hdr.reserved2 = 0;
209
-	hdr.checksum = 0;
210
-
211
-	/* Enable the host interface */
212
-	ret_val = hw->mac.ops.mng_enable_host_if(hw);
213
-	if (ret_val)
214
-		goto out;
215
-
216
-	/* Populate the host interface with the contents of "buffer". */
217
-	ret_val = hw->mac.ops.mng_host_if_write(hw, buffer, length,
218
-	                                  sizeof(hdr), &(hdr.checksum));
219
-	if (ret_val)
220
-		goto out;
221
-
222
-	/* Write the manageability command header */
223
-	ret_val = hw->mac.ops.mng_write_cmd_header(hw, &hdr);
224
-	if (ret_val)
225
-		goto out;
226
-
227
-	/* Tell the ARC a new command is pending. */
228
-	hicr = E1000_READ_REG(hw, E1000_HICR);
229
-	E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
230
-
231
-out:
232
-	return ret_val;
233
-}
234
-
235
-/**
236
- *  e1000_mng_write_cmd_header_generic - Writes manageability command header
237
- *  @hw: pointer to the HW structure
238
- *  @hdr: pointer to the host interface command header
239
- *
240
- *  Writes the command header after does the checksum calculation.
241
- **/
242
-s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
243
-                                    struct e1000_host_mng_command_header *hdr)
244
-{
245
-	u16 i, length = sizeof(struct e1000_host_mng_command_header);
246
-
247
-	DEBUGFUNC("e1000_mng_write_cmd_header_generic");
248
-
249
-	/* Write the whole command header structure with new checksum. */
250
-
251
-	hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
252
-
253
-	length >>= 2;
254
-	/* Write the relevant command block into the ram area. */
255
-	for (i = 0; i < length; i++) {
256
-		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
257
-		                            *((u32 *) hdr + i));
258
-		E1000_WRITE_FLUSH(hw);
259
-	}
260
-
261
-	return E1000_SUCCESS;
262
-}
263
-
264
-/**
265
- *  e1000_mng_host_if_write_generic - Write to the manageability host interface
266
- *  @hw: pointer to the HW structure
267
- *  @buffer: pointer to the host interface buffer
268
- *  @length: size of the buffer
269
- *  @offset: location in the buffer to write to
270
- *  @sum: sum of the data (not checksum)
271
- *
272
- *  This function writes the buffer content at the offset given on the host if.
273
- *  It also does alignment considerations to do the writes in most efficient
274
- *  way.  Also fills up the sum of the buffer in *buffer parameter.
275
- **/
276
-s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
277
-                                    u16 length, u16 offset, u8 *sum)
278
-{
279
-	u8 *tmp;
280
-	u8 *bufptr = buffer;
281
-	u32 data = 0;
282
-	s32 ret_val = E1000_SUCCESS;
283
-	u16 remaining, i, j, prev_bytes;
284
-
285
-	DEBUGFUNC("e1000_mng_host_if_write_generic");
286
-
287
-	/* sum = only sum of the data and it is not checksum */
288
-
289
-	if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
290
-		ret_val = -E1000_ERR_PARAM;
291
-		goto out;
292
-	}
293
-
294
-	tmp = (u8 *)&data;
295
-	prev_bytes = offset & 0x3;
296
-	offset >>= 2;
297
-
298
-	if (prev_bytes) {
299
-		data = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset);
300
-		for (j = prev_bytes; j < sizeof(u32); j++) {
301
-			*(tmp + j) = *bufptr++;
302
-			*sum += *(tmp + j);
303
-		}
304
-		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset, data);
305
-		length -= j - prev_bytes;
306
-		offset++;
307
-	}
308
-
309
-	remaining = length & 0x3;
310
-	length -= remaining;
311
-
312
-	/* Calculate length in DWORDs */
313
-	length >>= 2;
314
-
315
-	/*
316
-	 * The device driver writes the relevant command block into the
317
-	 * ram area.
318
-	 */
319
-	for (i = 0; i < length; i++) {
320
-		for (j = 0; j < sizeof(u32); j++) {
321
-			*(tmp + j) = *bufptr++;
322
-			*sum += *(tmp + j);
323
-		}
324
-
325
-		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
326
-		                            data);
327
-	}
328
-	if (remaining) {
329
-		for (j = 0; j < sizeof(u32); j++) {
330
-			if (j < remaining)
331
-				*(tmp + j) = *bufptr++;
332
-			else
333
-				*(tmp + j) = 0;
334
-
335
-			*sum += *(tmp + j);
336
-		}
337
-		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i, data);
338
-	}
339
-
340
-out:
341
-	return ret_val;
342
-}
343
-
344
-/**
345
- *  e1000_enable_mng_pass_thru - Enable processing of ARP's
346
- *  @hw: pointer to the HW structure
347
- *
348
- *  Verifies the hardware needs to allow ARPs to be processed by the host.
349
- **/
350
-bool e1000_enable_mng_pass_thru(struct e1000_hw *hw)
351
-{
352
-	u32 manc;
353
-	u32 fwsm, factps;
354
-	bool ret_val = false;
355
-
356
-	DEBUGFUNC("e1000_enable_mng_pass_thru");
357
-
358
-	if (!hw->mac.asf_firmware_present)
359
-		goto out;
360
-
361
-	manc = E1000_READ_REG(hw, E1000_MANC);
362
-
363
-	if (!(manc & E1000_MANC_RCV_TCO_EN) ||
364
-	    !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
365
-		goto out;
366
-
367
-	if (hw->mac.arc_subsystem_valid) {
368
-		fwsm = E1000_READ_REG(hw, E1000_FWSM);
369
-		factps = E1000_READ_REG(hw, E1000_FACTPS);
370
-
371
-		if (!(factps & E1000_FACTPS_MNGCG) &&
372
-		    ((fwsm & E1000_FWSM_MODE_MASK) ==
373
-		     (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
374
-			ret_val = true;
375
-			goto out;
376
-		}
377
-	} else {
378
-		if ((manc & E1000_MANC_SMBUS_EN) &&
379
-		    !(manc & E1000_MANC_ASF_EN)) {
380
-			ret_val = true;
381
-			goto out;
382
-		}
383
-	}
384
-
385
-out:
386
-	return ret_val;
387
-}
388
-
389
-#endif

+ 0
- 84
src/drivers/net/e1000/e1000_manage.h Прегледај датотеку

@@ -1,84 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2008 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-#ifndef _E1000_MANAGE_H_
32
-#define _E1000_MANAGE_H_
33
-
34
-bool e1000_check_mng_mode_generic(struct e1000_hw *hw);
35
-bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw);
36
-s32  e1000_mng_enable_host_if_generic(struct e1000_hw *hw);
37
-s32  e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
38
-                                     u16 length, u16 offset, u8 *sum);
39
-s32  e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
40
-                                    struct e1000_host_mng_command_header *hdr);
41
-s32  e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw,
42
-                                       u8 *buffer, u16 length);
43
-bool e1000_enable_mng_pass_thru(struct e1000_hw *hw);
44
-
45
-enum e1000_mng_mode {
46
-	e1000_mng_mode_none = 0,
47
-	e1000_mng_mode_asf,
48
-	e1000_mng_mode_pt,
49
-	e1000_mng_mode_ipmi,
50
-	e1000_mng_mode_host_if_only
51
-};
52
-
53
-#define E1000_FACTPS_MNGCG    0x20000000
54
-
55
-#define E1000_FWSM_MODE_MASK  0xE
56
-#define E1000_FWSM_MODE_SHIFT 1
57
-
58
-#define E1000_MNG_IAMT_MODE                  0x3
59
-#define E1000_MNG_DHCP_COOKIE_LENGTH         0x10
60
-#define E1000_MNG_DHCP_COOKIE_OFFSET         0x6F0
61
-#define E1000_MNG_DHCP_COMMAND_TIMEOUT       10
62
-#define E1000_MNG_DHCP_TX_PAYLOAD_CMD        64
63
-#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
64
-#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN    0x2
65
-
66
-#define E1000_VFTA_ENTRY_SHIFT               5
67
-#define E1000_VFTA_ENTRY_MASK                0x7F
68
-#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK      0x1F
69
-
70
-#define E1000_HI_MAX_BLOCK_BYTE_LENGTH       1792 /* Num of bytes in range */
71
-#define E1000_HI_MAX_BLOCK_DWORD_LENGTH      448 /* Num of dwords in range */
72
-#define E1000_HI_COMMAND_TIMEOUT             500 /* Process HI command limit */
73
-
74
-#define E1000_HICR_EN              0x01  /* Enable bit - RO */
75
-/* Driver sets this bit when done to put command in RAM */
76
-#define E1000_HICR_C               0x02
77
-#define E1000_HICR_SV              0x04  /* Status Validity */
78
-#define E1000_HICR_FW_RESET_ENABLE 0x40
79
-#define E1000_HICR_FW_RESET        0x80
80
-
81
-/* Intel(R) Active Management Technology signature */
82
-#define E1000_IAMT_SIGNATURE  0x544D4149
83
-
84
-#endif

+ 0
- 923
src/drivers/net/e1000/e1000_nvm.c Прегледај датотеку

@@ -1,923 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2008 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-#include "e1000_api.h"
32
-
33
-static void e1000_reload_nvm_generic(struct e1000_hw *hw);
34
-
35
-/**
36
- *  e1000_init_nvm_ops_generic - Initialize NVM function pointers
37
- *  @hw: pointer to the HW structure
38
- *
39
- *  Setups up the function pointers to no-op functions
40
- **/
41
-void e1000_init_nvm_ops_generic(struct e1000_hw *hw)
42
-{
43
-	struct e1000_nvm_info *nvm = &hw->nvm;
44
-	DEBUGFUNC("e1000_init_nvm_ops_generic");
45
-
46
-	/* Initialize function pointers */
47
-	nvm->ops.init_params = e1000_null_ops_generic;
48
-	nvm->ops.acquire = e1000_null_ops_generic;
49
-	nvm->ops.read = e1000_null_read_nvm;
50
-	nvm->ops.release = e1000_null_nvm_generic;
51
-	nvm->ops.reload = e1000_reload_nvm_generic;
52
-	nvm->ops.update = e1000_null_ops_generic;
53
-	nvm->ops.valid_led_default = e1000_null_led_default;
54
-	nvm->ops.validate = e1000_null_ops_generic;
55
-	nvm->ops.write = e1000_null_write_nvm;
56
-}
57
-
58
-/**
59
- *  e1000_null_nvm_read - No-op function, return 0
60
- *  @hw: pointer to the HW structure
61
- **/
62
-s32 e1000_null_read_nvm(struct e1000_hw *hw __unused, u16 a __unused,
63
-                        u16 b __unused, u16 *c __unused)
64
-{
65
-	DEBUGFUNC("e1000_null_read_nvm");
66
-	return E1000_SUCCESS;
67
-}
68
-
69
-/**
70
- *  e1000_null_nvm_generic - No-op function, return void
71
- *  @hw: pointer to the HW structure
72
- **/
73
-void e1000_null_nvm_generic(struct e1000_hw *hw __unused)
74
-{
75
-	DEBUGFUNC("e1000_null_nvm_generic");
76
-	return;
77
-}
78
-
79
-/**
80
- *  e1000_null_led_default - No-op function, return 0
81
- *  @hw: pointer to the HW structure
82
- **/
83
-s32 e1000_null_led_default(struct e1000_hw *hw __unused,
84
-                           u16 *data __unused)
85
-{
86
-	DEBUGFUNC("e1000_null_led_default");
87
-	return E1000_SUCCESS;
88
-}
89
-
90
-/**
91
- *  e1000_null_write_nvm - No-op function, return 0
92
- *  @hw: pointer to the HW structure
93
- **/
94
-s32 e1000_null_write_nvm(struct e1000_hw *hw __unused, u16 a __unused,
95
-                         u16 b __unused, u16 *c __unused)
96
-{
97
-	DEBUGFUNC("e1000_null_write_nvm");
98
-	return E1000_SUCCESS;
99
-}
100
-
101
-/**
102
- *  e1000_raise_eec_clk - Raise EEPROM clock
103
- *  @hw: pointer to the HW structure
104
- *  @eecd: pointer to the EEPROM
105
- *
106
- *  Enable/Raise the EEPROM clock bit.
107
- **/
108
-static void e1000_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
109
-{
110
-	*eecd = *eecd | E1000_EECD_SK;
111
-	E1000_WRITE_REG(hw, E1000_EECD, *eecd);
112
-	E1000_WRITE_FLUSH(hw);
113
-	usec_delay(hw->nvm.delay_usec);
114
-}
115
-
116
-/**
117
- *  e1000_lower_eec_clk - Lower EEPROM clock
118
- *  @hw: pointer to the HW structure
119
- *  @eecd: pointer to the EEPROM
120
- *
121
- *  Clear/Lower the EEPROM clock bit.
122
- **/
123
-static void e1000_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
124
-{
125
-	*eecd = *eecd & ~E1000_EECD_SK;
126
-	E1000_WRITE_REG(hw, E1000_EECD, *eecd);
127
-	E1000_WRITE_FLUSH(hw);
128
-	usec_delay(hw->nvm.delay_usec);
129
-}
130
-
131
-/**
132
- *  e1000_shift_out_eec_bits - Shift data bits our to the EEPROM
133
- *  @hw: pointer to the HW structure
134
- *  @data: data to send to the EEPROM
135
- *  @count: number of bits to shift out
136
- *
137
- *  We need to shift 'count' bits out to the EEPROM.  So, the value in the
138
- *  "data" parameter will be shifted out to the EEPROM one bit at a time.
139
- *  In order to do this, "data" must be broken down into bits.
140
- **/
141
-static void e1000_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
142
-{
143
-	struct e1000_nvm_info *nvm = &hw->nvm;
144
-	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
145
-	u32 mask;
146
-
147
-	DEBUGFUNC("e1000_shift_out_eec_bits");
148
-
149
-	mask = 0x01 << (count - 1);
150
-	if (nvm->type == e1000_nvm_eeprom_microwire)
151
-		eecd &= ~E1000_EECD_DO;
152
-	else
153
-	if (nvm->type == e1000_nvm_eeprom_spi)
154
-		eecd |= E1000_EECD_DO;
155
-
156
-	do {
157
-		eecd &= ~E1000_EECD_DI;
158
-
159
-		if (data & mask)
160
-			eecd |= E1000_EECD_DI;
161
-
162
-		E1000_WRITE_REG(hw, E1000_EECD, eecd);
163
-		E1000_WRITE_FLUSH(hw);
164
-
165
-		usec_delay(nvm->delay_usec);
166
-
167
-		e1000_raise_eec_clk(hw, &eecd);
168
-		e1000_lower_eec_clk(hw, &eecd);
169
-
170
-		mask >>= 1;
171
-	} while (mask);
172
-
173
-	eecd &= ~E1000_EECD_DI;
174
-	E1000_WRITE_REG(hw, E1000_EECD, eecd);
175
-}
176
-
177
-/**
178
- *  e1000_shift_in_eec_bits - Shift data bits in from the EEPROM
179
- *  @hw: pointer to the HW structure
180
- *  @count: number of bits to shift in
181
- *
182
- *  In order to read a register from the EEPROM, we need to shift 'count' bits
183
- *  in from the EEPROM.  Bits are "shifted in" by raising the clock input to
184
- *  the EEPROM (setting the SK bit), and then reading the value of the data out
185
- *  "DO" bit.  During this "shifting in" process the data in "DI" bit should
186
- *  always be clear.
187
- **/
188
-static u16 e1000_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
189
-{
190
-	u32 eecd;
191
-	u32 i;
192
-	u16 data;
193
-
194
-	DEBUGFUNC("e1000_shift_in_eec_bits");
195
-
196
-	eecd = E1000_READ_REG(hw, E1000_EECD);
197
-
198
-	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
199
-	data = 0;
200
-
201
-	for (i = 0; i < count; i++) {
202
-		data <<= 1;
203
-		e1000_raise_eec_clk(hw, &eecd);
204
-
205
-		eecd = E1000_READ_REG(hw, E1000_EECD);
206
-
207
-		eecd &= ~E1000_EECD_DI;
208
-		if (eecd & E1000_EECD_DO)
209
-			data |= 1;
210
-
211
-		e1000_lower_eec_clk(hw, &eecd);
212
-	}
213
-
214
-	return data;
215
-}
216
-
217
-/**
218
- *  e1000_poll_eerd_eewr_done - Poll for EEPROM read/write completion
219
- *  @hw: pointer to the HW structure
220
- *  @ee_reg: EEPROM flag for polling
221
- *
222
- *  Polls the EEPROM status bit for either read or write completion based
223
- *  upon the value of 'ee_reg'.
224
- **/
225
-s32 e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
226
-{
227
-	u32 attempts = 100000;
228
-	u32 i, reg = 0;
229
-	s32 ret_val = -E1000_ERR_NVM;
230
-
231
-	DEBUGFUNC("e1000_poll_eerd_eewr_done");
232
-
233
-	for (i = 0; i < attempts; i++) {
234
-		if (ee_reg == E1000_NVM_POLL_READ)
235
-			reg = E1000_READ_REG(hw, E1000_EERD);
236
-		else
237
-			reg = E1000_READ_REG(hw, E1000_EEWR);
238
-
239
-		if (reg & E1000_NVM_RW_REG_DONE) {
240
-			ret_val = E1000_SUCCESS;
241
-			break;
242
-		}
243
-
244
-		usec_delay(5);
245
-	}
246
-
247
-	return ret_val;
248
-}
249
-
250
-/**
251
- *  e1000_acquire_nvm_generic - Generic request for access to EEPROM
252
- *  @hw: pointer to the HW structure
253
- *
254
- *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
255
- *  Return successful if access grant bit set, else clear the request for
256
- *  EEPROM access and return -E1000_ERR_NVM (-1).
257
- **/
258
-s32 e1000_acquire_nvm_generic(struct e1000_hw *hw)
259
-{
260
-	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
261
-	s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
262
-	s32 ret_val = E1000_SUCCESS;
263
-
264
-	DEBUGFUNC("e1000_acquire_nvm_generic");
265
-
266
-	E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
267
-	eecd = E1000_READ_REG(hw, E1000_EECD);
268
-
269
-	while (timeout) {
270
-		if (eecd & E1000_EECD_GNT)
271
-			break;
272
-		usec_delay(5);
273
-		eecd = E1000_READ_REG(hw, E1000_EECD);
274
-		timeout--;
275
-	}
276
-
277
-	if (!timeout) {
278
-		eecd &= ~E1000_EECD_REQ;
279
-		E1000_WRITE_REG(hw, E1000_EECD, eecd);
280
-		DEBUGOUT("Could not acquire NVM grant\n");
281
-		ret_val = -E1000_ERR_NVM;
282
-	}
283
-
284
-	return ret_val;
285
-}
286
-
287
-/**
288
- *  e1000_standby_nvm - Return EEPROM to standby state
289
- *  @hw: pointer to the HW structure
290
- *
291
- *  Return the EEPROM to a standby state.
292
- **/
293
-static void e1000_standby_nvm(struct e1000_hw *hw)
294
-{
295
-	struct e1000_nvm_info *nvm = &hw->nvm;
296
-	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
297
-
298
-	DEBUGFUNC("e1000_standby_nvm");
299
-
300
-	if (nvm->type == e1000_nvm_eeprom_microwire) {
301
-		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
302
-		E1000_WRITE_REG(hw, E1000_EECD, eecd);
303
-		E1000_WRITE_FLUSH(hw);
304
-		usec_delay(nvm->delay_usec);
305
-
306
-		e1000_raise_eec_clk(hw, &eecd);
307
-
308
-		/* Select EEPROM */
309
-		eecd |= E1000_EECD_CS;
310
-		E1000_WRITE_REG(hw, E1000_EECD, eecd);
311
-		E1000_WRITE_FLUSH(hw);
312
-		usec_delay(nvm->delay_usec);
313
-
314
-		e1000_lower_eec_clk(hw, &eecd);
315
-	} else
316
-	if (nvm->type == e1000_nvm_eeprom_spi) {
317
-		/* Toggle CS to flush commands */
318
-		eecd |= E1000_EECD_CS;
319
-		E1000_WRITE_REG(hw, E1000_EECD, eecd);
320
-		E1000_WRITE_FLUSH(hw);
321
-		usec_delay(nvm->delay_usec);
322
-		eecd &= ~E1000_EECD_CS;
323
-		E1000_WRITE_REG(hw, E1000_EECD, eecd);
324
-		E1000_WRITE_FLUSH(hw);
325
-		usec_delay(nvm->delay_usec);
326
-	}
327
-}
328
-
329
-/**
330
- *  e1000_stop_nvm - Terminate EEPROM command
331
- *  @hw: pointer to the HW structure
332
- *
333
- *  Terminates the current command by inverting the EEPROM's chip select pin.
334
- **/
335
-void e1000_stop_nvm(struct e1000_hw *hw)
336
-{
337
-	u32 eecd;
338
-
339
-	DEBUGFUNC("e1000_stop_nvm");
340
-
341
-	eecd = E1000_READ_REG(hw, E1000_EECD);
342
-	if (hw->nvm.type == e1000_nvm_eeprom_spi) {
343
-		/* Pull CS high */
344
-		eecd |= E1000_EECD_CS;
345
-		e1000_lower_eec_clk(hw, &eecd);
346
-	} else if (hw->nvm.type == e1000_nvm_eeprom_microwire) {
347
-		/* CS on Microwire is active-high */
348
-		eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
349
-		E1000_WRITE_REG(hw, E1000_EECD, eecd);
350
-		e1000_raise_eec_clk(hw, &eecd);
351
-		e1000_lower_eec_clk(hw, &eecd);
352
-	}
353
-}
354
-
355
-/**
356
- *  e1000_release_nvm_generic - Release exclusive access to EEPROM
357
- *  @hw: pointer to the HW structure
358
- *
359
- *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
360
- **/
361
-void e1000_release_nvm_generic(struct e1000_hw *hw)
362
-{
363
-	u32 eecd;
364
-
365
-	DEBUGFUNC("e1000_release_nvm_generic");
366
-
367
-	e1000_stop_nvm(hw);
368
-
369
-	eecd = E1000_READ_REG(hw, E1000_EECD);
370
-	eecd &= ~E1000_EECD_REQ;
371
-	E1000_WRITE_REG(hw, E1000_EECD, eecd);
372
-}
373
-
374
-/**
375
- *  e1000_ready_nvm_eeprom - Prepares EEPROM for read/write
376
- *  @hw: pointer to the HW structure
377
- *
378
- *  Setups the EEPROM for reading and writing.
379
- **/
380
-static s32 e1000_ready_nvm_eeprom(struct e1000_hw *hw)
381
-{
382
-	struct e1000_nvm_info *nvm = &hw->nvm;
383
-	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
384
-	s32 ret_val = E1000_SUCCESS;
385
-	u16 timeout = 0;
386
-	u8 spi_stat_reg;
387
-
388
-	DEBUGFUNC("e1000_ready_nvm_eeprom");
389
-
390
-	if (nvm->type == e1000_nvm_eeprom_microwire) {
391
-		/* Clear SK and DI */
392
-		eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
393
-		E1000_WRITE_REG(hw, E1000_EECD, eecd);
394
-		/* Set CS */
395
-		eecd |= E1000_EECD_CS;
396
-		E1000_WRITE_REG(hw, E1000_EECD, eecd);
397
-	} else
398
-	if (nvm->type == e1000_nvm_eeprom_spi) {
399
-		/* Clear SK and CS */
400
-		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
401
-		E1000_WRITE_REG(hw, E1000_EECD, eecd);
402
-		usec_delay(1);
403
-		timeout = NVM_MAX_RETRY_SPI;
404
-
405
-		/*
406
-		 * Read "Status Register" repeatedly until the LSB is cleared.
407
-		 * The EEPROM will signal that the command has been completed
408
-		 * by clearing bit 0 of the internal status register.  If it's
409
-		 * not cleared within 'timeout', then error out.
410
-		 */
411
-		while (timeout) {
412
-			e1000_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
413
-			                         hw->nvm.opcode_bits);
414
-			spi_stat_reg = (u8)e1000_shift_in_eec_bits(hw, 8);
415
-			if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
416
-				break;
417
-
418
-			usec_delay(5);
419
-			e1000_standby_nvm(hw);
420
-			timeout--;
421
-		}
422
-
423
-		if (!timeout) {
424
-			DEBUGOUT("SPI NVM Status error\n");
425
-			ret_val = -E1000_ERR_NVM;
426
-			goto out;
427
-		}
428
-	}
429
-
430
-out:
431
-	return ret_val;
432
-}
433
-
434
-/**
435
- *  e1000_read_nvm_spi - Read EEPROM's using SPI
436
- *  @hw: pointer to the HW structure
437
- *  @offset: offset of word in the EEPROM to read
438
- *  @words: number of words to read
439
- *  @data: word read from the EEPROM
440
- *
441
- *  Reads a 16 bit word from the EEPROM.
442
- **/
443
-s32 e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
444
-{
445
-	struct e1000_nvm_info *nvm = &hw->nvm;
446
-	u32 i = 0;
447
-	s32 ret_val;
448
-	u16 word_in;
449
-	u8 read_opcode = NVM_READ_OPCODE_SPI;
450
-
451
-	DEBUGFUNC("e1000_read_nvm_spi");
452
-
453
-	/*
454
-	 * A check for invalid values:  offset too large, too many words,
455
-	 * and not enough words.
456
-	 */
457
-	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
458
-	    (words == 0)) {
459
-		DEBUGOUT("nvm parameter(s) out of bounds\n");
460
-		ret_val = -E1000_ERR_NVM;
461
-		goto out;
462
-	}
463
-
464
-	ret_val = nvm->ops.acquire(hw);
465
-	if (ret_val)
466
-		goto out;
467
-
468
-	ret_val = e1000_ready_nvm_eeprom(hw);
469
-	if (ret_val)
470
-		goto release;
471
-
472
-	e1000_standby_nvm(hw);
473
-
474
-	if ((nvm->address_bits == 8) && (offset >= 128))
475
-		read_opcode |= NVM_A8_OPCODE_SPI;
476
-
477
-	/* Send the READ command (opcode + addr) */
478
-	e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
479
-	e1000_shift_out_eec_bits(hw, (u16)(offset*2), nvm->address_bits);
480
-
481
-	/*
482
-	 * Read the data.  SPI NVMs increment the address with each byte
483
-	 * read and will roll over if reading beyond the end.  This allows
484
-	 * us to read the whole NVM from any offset
485
-	 */
486
-	for (i = 0; i < words; i++) {
487
-		word_in = e1000_shift_in_eec_bits(hw, 16);
488
-		data[i] = (word_in >> 8) | (word_in << 8);
489
-	}
490
-
491
-release:
492
-	nvm->ops.release(hw);
493
-
494
-out:
495
-	return ret_val;
496
-}
497
-
498
-/**
499
- *  e1000_read_nvm_microwire - Reads EEPROM's using microwire
500
- *  @hw: pointer to the HW structure
501
- *  @offset: offset of word in the EEPROM to read
502
- *  @words: number of words to read
503
- *  @data: word read from the EEPROM
504
- *
505
- *  Reads a 16 bit word from the EEPROM.
506
- **/
507
-s32 e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
508
-                             u16 *data)
509
-{
510
-	struct e1000_nvm_info *nvm = &hw->nvm;
511
-	u32 i = 0;
512
-	s32 ret_val;
513
-	u8 read_opcode = NVM_READ_OPCODE_MICROWIRE;
514
-
515
-	DEBUGFUNC("e1000_read_nvm_microwire");
516
-
517
-	/*
518
-	 * A check for invalid values:  offset too large, too many words,
519
-	 * and not enough words.
520
-	 */
521
-	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
522
-	    (words == 0)) {
523
-		DEBUGOUT("nvm parameter(s) out of bounds\n");
524
-		ret_val = -E1000_ERR_NVM;
525
-		goto out;
526
-	}
527
-
528
-	ret_val = nvm->ops.acquire(hw);
529
-	if (ret_val)
530
-		goto out;
531
-
532
-	ret_val = e1000_ready_nvm_eeprom(hw);
533
-	if (ret_val)
534
-		goto release;
535
-
536
-	for (i = 0; i < words; i++) {
537
-		/* Send the READ command (opcode + addr) */
538
-		e1000_shift_out_eec_bits(hw, read_opcode, nvm->opcode_bits);
539
-		e1000_shift_out_eec_bits(hw, (u16)(offset + i),
540
-					nvm->address_bits);
541
-
542
-		/*
543
-		 * Read the data.  For microwire, each word requires the
544
-		 * overhead of setup and tear-down.
545
-		 */
546
-		data[i] = e1000_shift_in_eec_bits(hw, 16);
547
-		e1000_standby_nvm(hw);
548
-	}
549
-
550
-release:
551
-	nvm->ops.release(hw);
552
-
553
-out:
554
-	return ret_val;
555
-}
556
-
557
-/**
558
- *  e1000_read_nvm_eerd - Reads EEPROM using EERD register
559
- *  @hw: pointer to the HW structure
560
- *  @offset: offset of word in the EEPROM to read
561
- *  @words: number of words to read
562
- *  @data: word read from the EEPROM
563
- *
564
- *  Reads a 16 bit word from the EEPROM using the EERD register.
565
- **/
566
-s32 e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
567
-{
568
-	struct e1000_nvm_info *nvm = &hw->nvm;
569
-	u32 i, eerd = 0;
570
-	s32 ret_val = E1000_SUCCESS;
571
-
572
-	DEBUGFUNC("e1000_read_nvm_eerd");
573
-
574
-	/*
575
-	 * A check for invalid values:  offset too large, too many words,
576
-	 * too many words for the offset, and not enough words.
577
-	 */
578
-	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
579
-	    (words == 0)) {
580
-		DEBUGOUT("nvm parameter(s) out of bounds\n");
581
-		ret_val = -E1000_ERR_NVM;
582
-		goto out;
583
-	}
584
-
585
-	for (i = 0; i < words; i++) {
586
-		eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
587
-		       E1000_NVM_RW_REG_START;
588
-
589
-		E1000_WRITE_REG(hw, E1000_EERD, eerd);
590
-		ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
591
-		if (ret_val)
592
-			break;
593
-
594
-		data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
595
-		           E1000_NVM_RW_REG_DATA);
596
-	}
597
-
598
-out:
599
-	return ret_val;
600
-}
601
-
602
-/**
603
- *  e1000_write_nvm_spi - Write to EEPROM using SPI
604
- *  @hw: pointer to the HW structure
605
- *  @offset: offset within the EEPROM to be written to
606
- *  @words: number of words to write
607
- *  @data: 16 bit word(s) to be written to the EEPROM
608
- *
609
- *  Writes data to EEPROM at offset using SPI interface.
610
- *
611
- *  If e1000_update_nvm_checksum is not called after this function , the
612
- *  EEPROM will most likely contain an invalid checksum.
613
- **/
614
-s32 e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
615
-{
616
-	struct e1000_nvm_info *nvm = &hw->nvm;
617
-	s32 ret_val;
618
-	u16 widx = 0;
619
-
620
-	DEBUGFUNC("e1000_write_nvm_spi");
621
-
622
-	/*
623
-	 * A check for invalid values:  offset too large, too many words,
624
-	 * and not enough words.
625
-	 */
626
-	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
627
-	    (words == 0)) {
628
-		DEBUGOUT("nvm parameter(s) out of bounds\n");
629
-		ret_val = -E1000_ERR_NVM;
630
-		goto out;
631
-	}
632
-
633
-	ret_val = nvm->ops.acquire(hw);
634
-	if (ret_val)
635
-		goto out;
636
-
637
-	while (widx < words) {
638
-		u8 write_opcode = NVM_WRITE_OPCODE_SPI;
639
-
640
-		ret_val = e1000_ready_nvm_eeprom(hw);
641
-		if (ret_val)
642
-			goto release;
643
-
644
-		e1000_standby_nvm(hw);
645
-
646
-		/* Send the WRITE ENABLE command (8 bit opcode) */
647
-		e1000_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
648
-		                         nvm->opcode_bits);
649
-
650
-		e1000_standby_nvm(hw);
651
-
652
-		/*
653
-		 * Some SPI eeproms use the 8th address bit embedded in the
654
-		 * opcode
655
-		 */
656
-		if ((nvm->address_bits == 8) && (offset >= 128))
657
-			write_opcode |= NVM_A8_OPCODE_SPI;
658
-
659
-		/* Send the Write command (8-bit opcode + addr) */
660
-		e1000_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
661
-		e1000_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
662
-		                         nvm->address_bits);
663
-
664
-		/* Loop to allow for up to whole page write of eeprom */
665
-		while (widx < words) {
666
-			u16 word_out = data[widx];
667
-			word_out = (word_out >> 8) | (word_out << 8);
668
-			e1000_shift_out_eec_bits(hw, word_out, 16);
669
-			widx++;
670
-
671
-			if ((((offset + widx) * 2) % nvm->page_size) == 0) {
672
-				e1000_standby_nvm(hw);
673
-				break;
674
-			}
675
-		}
676
-	}
677
-
678
-	msec_delay(10);
679
-release:
680
-	nvm->ops.release(hw);
681
-
682
-out:
683
-	return ret_val;
684
-}
685
-
686
-/**
687
- *  e1000_write_nvm_microwire - Writes EEPROM using microwire
688
- *  @hw: pointer to the HW structure
689
- *  @offset: offset within the EEPROM to be written to
690
- *  @words: number of words to write
691
- *  @data: 16 bit word(s) to be written to the EEPROM
692
- *
693
- *  Writes data to EEPROM at offset using microwire interface.
694
- *
695
- *  If e1000_update_nvm_checksum is not called after this function , the
696
- *  EEPROM will most likely contain an invalid checksum.
697
- **/
698
-s32 e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset, u16 words,
699
-                              u16 *data)
700
-{
701
-	struct e1000_nvm_info *nvm = &hw->nvm;
702
-	s32  ret_val;
703
-	u32 eecd;
704
-	u16 words_written = 0;
705
-	u16 widx = 0;
706
-
707
-	DEBUGFUNC("e1000_write_nvm_microwire");
708
-
709
-	/*
710
-	 * A check for invalid values:  offset too large, too many words,
711
-	 * and not enough words.
712
-	 */
713
-	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
714
-	    (words == 0)) {
715
-		DEBUGOUT("nvm parameter(s) out of bounds\n");
716
-		ret_val = -E1000_ERR_NVM;
717
-		goto out;
718
-	}
719
-
720
-	ret_val = nvm->ops.acquire(hw);
721
-	if (ret_val)
722
-		goto out;
723
-
724
-	ret_val = e1000_ready_nvm_eeprom(hw);
725
-	if (ret_val)
726
-		goto release;
727
-
728
-	e1000_shift_out_eec_bits(hw, NVM_EWEN_OPCODE_MICROWIRE,
729
-	                         (u16)(nvm->opcode_bits + 2));
730
-
731
-	e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
732
-
733
-	e1000_standby_nvm(hw);
734
-
735
-	while (words_written < words) {
736
-		e1000_shift_out_eec_bits(hw, NVM_WRITE_OPCODE_MICROWIRE,
737
-		                         nvm->opcode_bits);
738
-
739
-		e1000_shift_out_eec_bits(hw, (u16)(offset + words_written),
740
-		                         nvm->address_bits);
741
-
742
-		e1000_shift_out_eec_bits(hw, data[words_written], 16);
743
-
744
-		e1000_standby_nvm(hw);
745
-
746
-		for (widx = 0; widx < 200; widx++) {
747
-			eecd = E1000_READ_REG(hw, E1000_EECD);
748
-			if (eecd & E1000_EECD_DO)
749
-				break;
750
-			usec_delay(50);
751
-		}
752
-
753
-		if (widx == 200) {
754
-			DEBUGOUT("NVM Write did not complete\n");
755
-			ret_val = -E1000_ERR_NVM;
756
-			goto release;
757
-		}
758
-
759
-		e1000_standby_nvm(hw);
760
-
761
-		words_written++;
762
-	}
763
-
764
-	e1000_shift_out_eec_bits(hw, NVM_EWDS_OPCODE_MICROWIRE,
765
-	                         (u16)(nvm->opcode_bits + 2));
766
-
767
-	e1000_shift_out_eec_bits(hw, 0, (u16)(nvm->address_bits - 2));
768
-
769
-release:
770
-	nvm->ops.release(hw);
771
-
772
-out:
773
-	return ret_val;
774
-}
775
-
776
-/**
777
- *  e1000_read_pba_num_generic - Read device part number
778
- *  @hw: pointer to the HW structure
779
- *  @pba_num: pointer to device part number
780
- *
781
- *  Reads the product board assembly (PBA) number from the EEPROM and stores
782
- *  the value in pba_num.
783
- **/
784
-s32 e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
785
-{
786
-	s32  ret_val;
787
-	u16 nvm_data;
788
-
789
-	DEBUGFUNC("e1000_read_pba_num_generic");
790
-
791
-	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
792
-	if (ret_val) {
793
-		DEBUGOUT("NVM Read Error\n");
794
-		goto out;
795
-	}
796
-	*pba_num = (u32)(nvm_data << 16);
797
-
798
-	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
799
-	if (ret_val) {
800
-		DEBUGOUT("NVM Read Error\n");
801
-		goto out;
802
-	}
803
-	*pba_num |= nvm_data;
804
-
805
-out:
806
-	return ret_val;
807
-}
808
-
809
-/**
810
- *  e1000_read_mac_addr_generic - Read device MAC address
811
- *  @hw: pointer to the HW structure
812
- *
813
- *  Reads the device MAC address from the EEPROM and stores the value.
814
- *  Since devices with two ports use the same EEPROM, we increment the
815
- *  last bit in the MAC address for the second port.
816
- **/
817
-s32 e1000_read_mac_addr_generic(struct e1000_hw *hw)
818
-{
819
-	u32 rar_high;
820
-	u32 rar_low;
821
-	u16 i;
822
-
823
-	rar_high = E1000_READ_REG(hw, E1000_RAH(0));
824
-	rar_low = E1000_READ_REG(hw, E1000_RAL(0));
825
-
826
-	for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
827
-		hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
828
-
829
-	for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
830
-		hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
831
-
832
-	for (i = 0; i < ETH_ADDR_LEN; i++)
833
-		hw->mac.addr[i] = hw->mac.perm_addr[i];
834
-
835
-	return E1000_SUCCESS;
836
-}
837
-
838
-/**
839
- *  e1000_validate_nvm_checksum_generic - Validate EEPROM checksum
840
- *  @hw: pointer to the HW structure
841
- *
842
- *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
843
- *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
844
- **/
845
-s32 e1000_validate_nvm_checksum_generic(struct e1000_hw *hw)
846
-{
847
-	s32 ret_val = E1000_SUCCESS;
848
-	u16 checksum = 0;
849
-	u16 i, nvm_data;
850
-
851
-	DEBUGFUNC("e1000_validate_nvm_checksum_generic");
852
-
853
-	for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
854
-		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
855
-		if (ret_val) {
856
-			DEBUGOUT("NVM Read Error\n");
857
-			goto out;
858
-		}
859
-		checksum += nvm_data;
860
-	}
861
-
862
-	if (checksum != (u16) NVM_SUM) {
863
-		DEBUGOUT("NVM Checksum Invalid\n");
864
-		ret_val = -E1000_ERR_NVM;
865
-		goto out;
866
-	}
867
-
868
-out:
869
-	return ret_val;
870
-}
871
-
872
-/**
873
- *  e1000_update_nvm_checksum_generic - Update EEPROM checksum
874
- *  @hw: pointer to the HW structure
875
- *
876
- *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
877
- *  up to the checksum.  Then calculates the EEPROM checksum and writes the
878
- *  value to the EEPROM.
879
- **/
880
-s32 e1000_update_nvm_checksum_generic(struct e1000_hw *hw)
881
-{
882
-	s32  ret_val;
883
-	u16 checksum = 0;
884
-	u16 i, nvm_data;
885
-
886
-	DEBUGFUNC("e1000_update_nvm_checksum");
887
-
888
-	for (i = 0; i < NVM_CHECKSUM_REG; i++) {
889
-		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
890
-		if (ret_val) {
891
-			DEBUGOUT("NVM Read Error while updating checksum.\n");
892
-			goto out;
893
-		}
894
-		checksum += nvm_data;
895
-	}
896
-	checksum = (u16) NVM_SUM - checksum;
897
-	ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
898
-	if (ret_val)
899
-		DEBUGOUT("NVM Write Error while updating checksum.\n");
900
-
901
-out:
902
-	return ret_val;
903
-}
904
-
905
-/**
906
- *  e1000_reload_nvm_generic - Reloads EEPROM
907
- *  @hw: pointer to the HW structure
908
- *
909
- *  Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
910
- *  extended control register.
911
- **/
912
-static void e1000_reload_nvm_generic(struct e1000_hw *hw)
913
-{
914
-	u32 ctrl_ext;
915
-
916
-	DEBUGFUNC("e1000_reload_nvm_generic");
917
-
918
-	usec_delay(10);
919
-	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
920
-	ctrl_ext |= E1000_CTRL_EXT_EE_RST;
921
-	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
922
-	E1000_WRITE_FLUSH(hw);
923
-}

+ 0
- 63
src/drivers/net/e1000/e1000_nvm.h Прегледај датотеку

@@ -1,63 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2008 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-#ifndef _E1000_NVM_H_
32
-#define _E1000_NVM_H_
33
-
34
-void e1000_init_nvm_ops_generic(struct e1000_hw *hw);
35
-s32  e1000_null_read_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c);
36
-void e1000_null_nvm_generic(struct e1000_hw *hw);
37
-s32  e1000_null_led_default(struct e1000_hw *hw, u16 *data);
38
-s32  e1000_null_write_nvm(struct e1000_hw *hw, u16 a, u16 b, u16 *c);
39
-s32  e1000_acquire_nvm_generic(struct e1000_hw *hw);
40
-
41
-s32  e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
42
-s32  e1000_read_mac_addr_generic(struct e1000_hw *hw);
43
-s32  e1000_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num);
44
-s32  e1000_read_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
45
-s32  e1000_read_nvm_microwire(struct e1000_hw *hw, u16 offset,
46
-                              u16 words, u16 *data);
47
-s32  e1000_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words,
48
-                         u16 *data);
49
-s32  e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data);
50
-s32  e1000_validate_nvm_checksum_generic(struct e1000_hw *hw);
51
-s32  e1000_write_nvm_eewr(struct e1000_hw *hw, u16 offset,
52
-                          u16 words, u16 *data);
53
-s32  e1000_write_nvm_microwire(struct e1000_hw *hw, u16 offset,
54
-                               u16 words, u16 *data);
55
-s32  e1000_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words,
56
-                         u16 *data);
57
-s32  e1000_update_nvm_checksum_generic(struct e1000_hw *hw);
58
-void e1000_stop_nvm(struct e1000_hw *hw);
59
-void e1000_release_nvm_generic(struct e1000_hw *hw);
60
-
61
-#define E1000_STM_OPCODE  0xDB00
62
-
63
-#endif

+ 0
- 118
src/drivers/net/e1000/e1000_osdep.h Прегледај датотеку

@@ -1,118 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2008 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-/* glue for the OS-dependent part of e1000
32
- * includes register access macros
33
- */
34
-
35
-#ifndef _E1000_OSDEP_H_
36
-#define _E1000_OSDEP_H_
37
-
38
-#define u8         unsigned char
39
-#define bool       boolean_t
40
-#define dma_addr_t unsigned long
41
-#define __le16     uint16_t
42
-#define __le32     uint32_t
43
-#define __le64     uint64_t
44
-
45
-#define __iomem
46
-
47
-#define ETH_FCS_LEN 4
48
-
49
-typedef int spinlock_t;
50
-typedef enum {
51
-    false = 0,
52
-    true = 1
53
-} boolean_t;
54
-
55
-#define usec_delay(x) udelay(x)
56
-#define msec_delay(x) mdelay(x)
57
-#define msec_delay_irq(x) mdelay(x)
58
-
59
-#define PCI_COMMAND_REGISTER   PCI_COMMAND
60
-#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
61
-#define ETH_ADDR_LEN           ETH_ALEN
62
-
63
-#define DEBUGFUNC(F) DBG(F "\n")
64
-
65
-#define DEBUGOUT(S)             DBG(S)
66
-#define DEBUGOUT1(S, A...)      DBG(S, A)
67
-
68
-#define DEBUGOUT2 DEBUGOUT1
69
-#define DEBUGOUT3 DEBUGOUT2
70
-#define DEBUGOUT7 DEBUGOUT3
71
-
72
-#define E1000_REGISTER(a, reg) (((a)->mac.type >= e1000_82543) \
73
-                               ? reg                           \
74
-                               : e1000_translate_register_82542(reg))
75
-
76
-#define E1000_WRITE_REG(a, reg, value) \
77
-    writel((value), ((a)->hw_addr + E1000_REGISTER(a, reg)))
78
-
79
-#define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_REGISTER(a, reg)))
80
-
81
-#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) \
82
-    writel((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 2)))
83
-
84
-#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
85
-    readl((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 2)))
86
-
87
-#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
88
-#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
89
-
90
-#define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
91
-    writew((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 1))))
92
-
93
-#define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
94
-    readw((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 1)))
95
-
96
-#define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
97
-    writeb((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + (offset))))
98
-
99
-#define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
100
-    readb((a)->hw_addr + E1000_REGISTER(a, reg) + (offset)))
101
-
102
-#define E1000_WRITE_REG_IO(a, reg, offset) do { \
103
-    outl(reg, ((a)->io_base));                  \
104
-    outl(offset, ((a)->io_base + 4));      } while(0)
105
-
106
-#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS)
107
-
108
-#define E1000_WRITE_FLASH_REG(a, reg, value) ( \
109
-    writel((value), ((a)->flash_address + reg)))
110
-
111
-#define E1000_WRITE_FLASH_REG16(a, reg, value) ( \
112
-    writew((value), ((a)->flash_address + reg)))
113
-
114
-#define E1000_READ_FLASH_REG(a, reg) (readl((a)->flash_address + reg))
115
-
116
-#define E1000_READ_FLASH_REG16(a, reg) (readw((a)->flash_address + reg))
117
-
118
-#endif /* _E1000_OSDEP_H_ */

+ 0
- 2308
src/drivers/net/e1000/e1000_phy.c
Разлика између датотеке није приказан због своје велике величине
Прегледај датотеку


+ 0
- 171
src/drivers/net/e1000/e1000_phy.h Прегледај датотеку

@@ -1,171 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2008 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-#ifndef _E1000_PHY_H_
32
-#define _E1000_PHY_H_
33
-
34
-void e1000_init_phy_ops_generic(struct e1000_hw *hw);
35
-s32  e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data);
36
-void e1000_null_phy_generic(struct e1000_hw *hw);
37
-s32  e1000_null_lplu_state(struct e1000_hw *hw, bool active);
38
-s32  e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data);
39
-s32  e1000_check_downshift_generic(struct e1000_hw *hw);
40
-s32  e1000_check_polarity_m88(struct e1000_hw *hw);
41
-s32  e1000_check_polarity_igp(struct e1000_hw *hw);
42
-s32  e1000_check_polarity_ife(struct e1000_hw *hw);
43
-s32  e1000_check_reset_block_generic(struct e1000_hw *hw);
44
-s32  e1000_copper_link_autoneg(struct e1000_hw *hw);
45
-s32  e1000_copper_link_setup_igp(struct e1000_hw *hw);
46
-s32  e1000_copper_link_setup_m88(struct e1000_hw *hw);
47
-#if 0
48
-s32  e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw);
49
-s32  e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw);
50
-s32  e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
51
-#endif
52
-#if 0
53
-s32  e1000_get_cable_length_m88(struct e1000_hw *hw);
54
-s32  e1000_get_cable_length_igp_2(struct e1000_hw *hw);
55
-#endif
56
-s32  e1000_get_cfg_done_generic(struct e1000_hw *hw);
57
-s32  e1000_get_phy_id(struct e1000_hw *hw);
58
-s32  e1000_get_phy_info_igp(struct e1000_hw *hw);
59
-s32  e1000_get_phy_info_m88(struct e1000_hw *hw);
60
-s32  e1000_phy_sw_reset_generic(struct e1000_hw *hw);
61
-#if 0
62
-void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
63
-#endif
64
-s32  e1000_phy_hw_reset_generic(struct e1000_hw *hw);
65
-s32  e1000_phy_reset_dsp_generic(struct e1000_hw *hw);
66
-s32  e1000_phy_setup_autoneg(struct e1000_hw *hw);
67
-s32  e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);
68
-s32  e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
69
-s32  e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
70
-s32  e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active);
71
-s32  e1000_setup_copper_link_generic(struct e1000_hw *hw);
72
-s32  e1000_wait_autoneg_generic(struct e1000_hw *hw);
73
-s32  e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);
74
-s32  e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
75
-s32  e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
76
-s32  e1000_phy_reset_dsp(struct e1000_hw *hw);
77
-s32  e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
78
-                                u32 usec_interval, bool *success);
79
-s32  e1000_phy_init_script_igp3(struct e1000_hw *hw);
80
-enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id);
81
-s32  e1000_determine_phy_address(struct e1000_hw *hw);
82
-void e1000_power_up_phy_copper(struct e1000_hw *hw);
83
-void e1000_power_down_phy_copper(struct e1000_hw *hw);
84
-s32  e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
85
-s32  e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
86
-
87
-#define E1000_MAX_PHY_ADDR                4
88
-
89
-/* IGP01E1000 Specific Registers */
90
-#define IGP01E1000_PHY_PORT_CONFIG        0x10 /* Port Config */
91
-#define IGP01E1000_PHY_PORT_STATUS        0x11 /* Status */
92
-#define IGP01E1000_PHY_PORT_CTRL          0x12 /* Control */
93
-#define IGP01E1000_PHY_LINK_HEALTH        0x13 /* PHY Link Health */
94
-#define IGP01E1000_GMII_FIFO              0x14 /* GMII FIFO */
95
-#define IGP01E1000_PHY_CHANNEL_QUALITY    0x15 /* PHY Channel Quality */
96
-#define IGP02E1000_PHY_POWER_MGMT         0x19 /* Power Management */
97
-#define IGP01E1000_PHY_PAGE_SELECT        0x1F /* Page Select */
98
-#define BM_PHY_PAGE_SELECT                22   /* Page Select for BM */
99
-#define IGP_PAGE_SHIFT                    5
100
-#define PHY_REG_MASK                      0x1F
101
-
102
-#define IGP01E1000_PHY_PCS_INIT_REG       0x00B4
103
-#define IGP01E1000_PHY_POLARITY_MASK      0x0078
104
-
105
-#define IGP01E1000_PSCR_AUTO_MDIX         0x1000
106
-#define IGP01E1000_PSCR_FORCE_MDI_MDIX    0x2000 /* 0=MDI, 1=MDIX */
107
-
108
-#define IGP01E1000_PSCFR_SMART_SPEED      0x0080
109
-
110
-/* Enable flexible speed on link-up */
111
-#define IGP01E1000_GMII_FLEX_SPD          0x0010
112
-#define IGP01E1000_GMII_SPD               0x0020 /* Enable SPD */
113
-
114
-#define IGP02E1000_PM_SPD                 0x0001 /* Smart Power Down */
115
-#define IGP02E1000_PM_D0_LPLU             0x0002 /* For D0a states */
116
-#define IGP02E1000_PM_D3_LPLU             0x0004 /* For all other states */
117
-
118
-#define IGP01E1000_PLHR_SS_DOWNGRADE      0x8000
119
-
120
-#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
121
-#define IGP01E1000_PSSR_MDIX              0x0800
122
-#define IGP01E1000_PSSR_SPEED_MASK        0xC000
123
-#define IGP01E1000_PSSR_SPEED_1000MBPS    0xC000
124
-
125
-#define IGP02E1000_PHY_CHANNEL_NUM        4
126
-#define IGP02E1000_PHY_AGC_A              0x11B1
127
-#define IGP02E1000_PHY_AGC_B              0x12B1
128
-#define IGP02E1000_PHY_AGC_C              0x14B1
129
-#define IGP02E1000_PHY_AGC_D              0x18B1
130
-
131
-#define IGP02E1000_AGC_LENGTH_SHIFT       9   /* Course - 15:13, Fine - 12:9 */
132
-#define IGP02E1000_AGC_LENGTH_MASK        0x7F
133
-#define IGP02E1000_AGC_RANGE              15
134
-
135
-#define IGP03E1000_PHY_MISC_CTRL          0x1B
136
-#define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET  0x1000 /* Manually Set Duplex */
137
-
138
-#define E1000_CABLE_LENGTH_UNDEFINED      0xFF
139
-
140
-#define E1000_KMRNCTRLSTA_OFFSET          0x001F0000
141
-#define E1000_KMRNCTRLSTA_OFFSET_SHIFT    16
142
-#define E1000_KMRNCTRLSTA_REN             0x00200000
143
-#define E1000_KMRNCTRLSTA_DIAG_OFFSET     0x3    /* Kumeran Diagnostic */
144
-#define E1000_KMRNCTRLSTA_TIMEOUTS        0x4    /* Kumeran Timeouts */
145
-#define E1000_KMRNCTRLSTA_INBAND_PARAM    0x9    /* Kumeran InBand Parameters */
146
-#define E1000_KMRNCTRLSTA_DIAG_NELPBK     0x1000 /* Nearend Loopback mode */
147
-
148
-#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
149
-#define IFE_PHY_SPECIAL_CONTROL     0x11 /* 100BaseTx PHY Special Control */
150
-#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
151
-#define IFE_PHY_MDIX_CONTROL        0x1C /* MDI/MDI-X Control */
152
-
153
-/* IFE PHY Extended Status Control */
154
-#define IFE_PESC_POLARITY_REVERSED    0x0100
155
-
156
-/* IFE PHY Special Control */
157
-#define IFE_PSC_AUTO_POLARITY_DISABLE      0x0010
158
-#define IFE_PSC_FORCE_POLARITY             0x0020
159
-#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
160
-
161
-/* IFE PHY Special Control and LED Control */
162
-#define IFE_PSCL_PROBE_MODE            0x0020
163
-#define IFE_PSCL_PROBE_LEDS_OFF        0x0006 /* Force LEDs 0 and 2 off */
164
-#define IFE_PSCL_PROBE_LEDS_ON         0x0007 /* Force LEDs 0 and 2 on */
165
-
166
-/* IFE PHY MDIX Control */
167
-#define IFE_PMC_MDIX_STATUS      0x0020 /* 1=MDI-X, 0=MDI */
168
-#define IFE_PMC_FORCE_MDIX       0x0040 /* 1=force MDI-X, 0=force MDI */
169
-#define IFE_PMC_AUTO_MDIX        0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
170
-
171
-#endif

+ 0
- 329
src/drivers/net/e1000/e1000_regs.h Прегледај датотеку

@@ -1,329 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2008 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-#ifndef _E1000_REGS_H_
32
-#define _E1000_REGS_H_
33
-
34
-#define E1000_CTRL     0x00000  /* Device Control - RW */
35
-#define E1000_CTRL_DUP 0x00004  /* Device Control Duplicate (Shadow) - RW */
36
-#define E1000_STATUS   0x00008  /* Device Status - RO */
37
-#define E1000_EECD     0x00010  /* EEPROM/Flash Control - RW */
38
-#define E1000_EERD     0x00014  /* EEPROM Read - RW */
39
-#define E1000_CTRL_EXT 0x00018  /* Extended Device Control - RW */
40
-#define E1000_FLA      0x0001C  /* Flash Access - RW */
41
-#define E1000_MDIC     0x00020  /* MDI Control - RW */
42
-#define E1000_SCTL     0x00024  /* SerDes Control - RW */
43
-#define E1000_FCAL     0x00028  /* Flow Control Address Low - RW */
44
-#define E1000_FCAH     0x0002C  /* Flow Control Address High -RW */
45
-#define E1000_FEXT     0x0002C  /* Future Extended - RW */
46
-#define E1000_FEXTNVM  0x00028  /* Future Extended NVM - RW */
47
-#define E1000_FCT      0x00030  /* Flow Control Type - RW */
48
-#define E1000_CONNSW   0x00034  /* Copper/Fiber switch control - RW */
49
-#define E1000_VET      0x00038  /* VLAN Ether Type - RW */
50
-#define E1000_ICR      0x000C0  /* Interrupt Cause Read - R/clr */
51
-#define E1000_ITR      0x000C4  /* Interrupt Throttling Rate - RW */
52
-#define E1000_ICS      0x000C8  /* Interrupt Cause Set - WO */
53
-#define E1000_IMS      0x000D0  /* Interrupt Mask Set - RW */
54
-#define E1000_IMC      0x000D8  /* Interrupt Mask Clear - WO */
55
-#define E1000_IAM      0x000E0  /* Interrupt Acknowledge Auto Mask */
56
-#define E1000_RCTL     0x00100  /* Rx Control - RW */
57
-#define E1000_FCTTV    0x00170  /* Flow Control Transmit Timer Value - RW */
58
-#define E1000_TXCW     0x00178  /* Tx Configuration Word - RW */
59
-#define E1000_RXCW     0x00180  /* Rx Configuration Word - RO */
60
-#define E1000_TCTL     0x00400  /* Tx Control - RW */
61
-#define E1000_TCTL_EXT 0x00404  /* Extended Tx Control - RW */
62
-#define E1000_TIPG     0x00410  /* Tx Inter-packet gap -RW */
63
-#define E1000_TBT      0x00448  /* Tx Burst Timer - RW */
64
-#define E1000_AIT      0x00458  /* Adaptive Interframe Spacing Throttle - RW */
65
-#define E1000_LEDCTL   0x00E00  /* LED Control - RW */
66
-#define E1000_EXTCNF_CTRL  0x00F00  /* Extended Configuration Control */
67
-#define E1000_EXTCNF_SIZE  0x00F08  /* Extended Configuration Size */
68
-#define E1000_PHY_CTRL     0x00F10  /* PHY Control Register in CSR */
69
-#define E1000_PBA      0x01000  /* Packet Buffer Allocation - RW */
70
-#define E1000_PBS      0x01008  /* Packet Buffer Size */
71
-#define E1000_EEMNGCTL 0x01010  /* MNG EEprom Control */
72
-#define E1000_EEARBC   0x01024  /* EEPROM Auto Read Bus Control */
73
-#define E1000_FLASHT   0x01028  /* FLASH Timer Register */
74
-#define E1000_EEWR     0x0102C  /* EEPROM Write Register - RW */
75
-#define E1000_FLSWCTL  0x01030  /* FLASH control register */
76
-#define E1000_FLSWDATA 0x01034  /* FLASH data register */
77
-#define E1000_FLSWCNT  0x01038  /* FLASH Access Counter */
78
-#define E1000_FLOP     0x0103C  /* FLASH Opcode Register */
79
-#define E1000_I2CCMD   0x01028  /* SFPI2C Command Register - RW */
80
-#define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */
81
-#define E1000_WDSTP    0x01040  /* Watchdog Setup - RW */
82
-#define E1000_SWDSTS   0x01044  /* SW Device Status - RW */
83
-#define E1000_FRTIMER  0x01048  /* Free Running Timer - RW */
84
-#define E1000_ERT      0x02008  /* Early Rx Threshold - RW */
85
-#define E1000_FCRTL    0x02160  /* Flow Control Receive Threshold Low - RW */
86
-#define E1000_FCRTH    0x02168  /* Flow Control Receive Threshold High - RW */
87
-#define E1000_PSRCTL   0x02170  /* Packet Split Receive Control - RW */
88
-#define E1000_RDFPCQ(_n)  (0x02430 + (0x4 * (_n)))
89
-#define E1000_PBRTH    0x02458  /* PB Rx Arbitration Threshold - RW */
90
-#define E1000_FCRTV    0x02460  /* Flow Control Refresh Timer Value - RW */
91
-/* Split and Replication Rx Control - RW */
92
-#define E1000_RDPUMB   0x025CC  /* DMA Rx Descriptor uC Mailbox - RW */
93
-#define E1000_RDPUAD   0x025D0  /* DMA Rx Descriptor uC Addr Command - RW */
94
-#define E1000_RDPUWD   0x025D4  /* DMA Rx Descriptor uC Data Write - RW */
95
-#define E1000_RDPURD   0x025D8  /* DMA Rx Descriptor uC Data Read - RW */
96
-#define E1000_RDPUCTL  0x025DC  /* DMA Rx Descriptor uC Control - RW */
97
-#define E1000_RXCTL(_n)   (0x0C014 + (0x40 * (_n)))
98
-#define E1000_RQDPC(_n)   (0x0C030 + (0x40 * (_n)))
99
-#define E1000_RDTR     0x02820  /* Rx Delay Timer - RW */
100
-#define E1000_RADV     0x0282C  /* Rx Interrupt Absolute Delay Timer - RW */
101
-/*
102
- * Convenience macros
103
- *
104
- * Note: "_n" is the queue number of the register to be written to.
105
- *
106
- * Example usage:
107
- * E1000_RDBAL_REG(current_rx_queue)
108
- */
109
-#define E1000_RDBAL(_n)      ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \
110
-                                         (0x0C000 + ((_n) * 0x40)))
111
-#define E1000_RDBAH(_n)      ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \
112
-                                         (0x0C004 + ((_n) * 0x40)))
113
-#define E1000_RDLEN(_n)      ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \
114
-                                         (0x0C008 + ((_n) * 0x40)))
115
-#define E1000_SRRCTL(_n)     ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
116
-                                         (0x0C00C + ((_n) * 0x40)))
117
-#define E1000_RDH(_n)        ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \
118
-                                         (0x0C010 + ((_n) * 0x40)))
119
-#define E1000_RDT(_n)        ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \
120
-                                         (0x0C018 + ((_n) * 0x40)))
121
-#define E1000_RXDCTL(_n)     ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \
122
-                                         (0x0C028 + ((_n) * 0x40)))
123
-#define E1000_TDBAL(_n)      ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \
124
-                                         (0x0E000 + ((_n) * 0x40)))
125
-#define E1000_TDBAH(_n)      ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \
126
-                                         (0x0E004 + ((_n) * 0x40)))
127
-#define E1000_TDLEN(_n)      ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \
128
-                                         (0x0E008 + ((_n) * 0x40)))
129
-#define E1000_TDH(_n)        ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \
130
-                                         (0x0E010 + ((_n) * 0x40)))
131
-#define E1000_TDT(_n)        ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \
132
-                                         (0x0E018 + ((_n) * 0x40)))
133
-#define E1000_TXDCTL(_n)     ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \
134
-                                         (0x0E028 + ((_n) * 0x40)))
135
-#define E1000_TARC(_n)       (0x03840 + (_n << 8))
136
-#define E1000_DCA_TXCTRL(_n) (0x03814 + (_n << 8))
137
-#define E1000_DCA_RXCTRL(_n) (0x02814 + (_n << 8))
138
-#define E1000_TDWBAL(_n)     ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : \
139
-                                         (0x0E038 + ((_n) * 0x40)))
140
-#define E1000_TDWBAH(_n)     ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : \
141
-                                         (0x0E03C + ((_n) * 0x40)))
142
-#define E1000_RSRPD    0x02C00  /* Rx Small Packet Detect - RW */
143
-#define E1000_RAID     0x02C08  /* Receive Ack Interrupt Delay - RW */
144
-#define E1000_TXDMAC   0x03000  /* Tx DMA Control - RW */
145
-#define E1000_KABGTXD  0x03004  /* AFE Band Gap Transmit Ref Data */
146
-#define E1000_PSRTYPE(_i)       (0x05480 + ((_i) * 4))
147
-#define E1000_RAL(_i)  (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
148
-                                       (0x054E0 + ((_i - 16) * 8)))
149
-#define E1000_RAH(_i)  (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
150
-                                       (0x054E4 + ((_i - 16) * 8)))
151
-#define E1000_IP4AT_REG(_i)     (0x05840 + ((_i) * 8))
152
-#define E1000_IP6AT_REG(_i)     (0x05880 + ((_i) * 4))
153
-#define E1000_WUPM_REG(_i)      (0x05A00 + ((_i) * 4))
154
-#define E1000_FFMT_REG(_i)      (0x09000 + ((_i) * 8))
155
-#define E1000_FFVT_REG(_i)      (0x09800 + ((_i) * 8))
156
-#define E1000_FFLT_REG(_i)      (0x05F00 + ((_i) * 8))
157
-#define E1000_TDFH     0x03410  /* Tx Data FIFO Head - RW */
158
-#define E1000_TDFT     0x03418  /* Tx Data FIFO Tail - RW */
159
-#define E1000_TDFHS    0x03420  /* Tx Data FIFO Head Saved - RW */
160
-#define E1000_TDFTS    0x03428  /* Tx Data FIFO Tail Saved - RW */
161
-#define E1000_TDFPC    0x03430  /* Tx Data FIFO Packet Count - RW */
162
-#define E1000_TDPUMB   0x0357C  /* DMA Tx Descriptor uC Mail Box - RW */
163
-#define E1000_TDPUAD   0x03580  /* DMA Tx Descriptor uC Addr Command - RW */
164
-#define E1000_TDPUWD   0x03584  /* DMA Tx Descriptor uC Data Write - RW */
165
-#define E1000_TDPURD   0x03588  /* DMA Tx Descriptor uC Data  Read  - RW */
166
-#define E1000_TDPUCTL  0x0358C  /* DMA Tx Descriptor uC Control - RW */
167
-#define E1000_DTXCTL   0x03590  /* DMA Tx Control - RW */
168
-#define E1000_TIDV     0x03820  /* Tx Interrupt Delay Value - RW */
169
-#define E1000_TADV     0x0382C  /* Tx Interrupt Absolute Delay Val - RW */
170
-#define E1000_TSPMT    0x03830  /* TCP Segmentation PAD & Min Threshold - RW */
171
-#define E1000_CRCERRS  0x04000  /* CRC Error Count - R/clr */
172
-#define E1000_ALGNERRC 0x04004  /* Alignment Error Count - R/clr */
173
-#define E1000_SYMERRS  0x04008  /* Symbol Error Count - R/clr */
174
-#define E1000_RXERRC   0x0400C  /* Receive Error Count - R/clr */
175
-#define E1000_MPC      0x04010  /* Missed Packet Count - R/clr */
176
-#define E1000_SCC      0x04014  /* Single Collision Count - R/clr */
177
-#define E1000_ECOL     0x04018  /* Excessive Collision Count - R/clr */
178
-#define E1000_MCC      0x0401C  /* Multiple Collision Count - R/clr */
179
-#define E1000_LATECOL  0x04020  /* Late Collision Count - R/clr */
180
-#define E1000_COLC     0x04028  /* Collision Count - R/clr */
181
-#define E1000_DC       0x04030  /* Defer Count - R/clr */
182
-#define E1000_TNCRS    0x04034  /* Tx-No CRS - R/clr */
183
-#define E1000_SEC      0x04038  /* Sequence Error Count - R/clr */
184
-#define E1000_CEXTERR  0x0403C  /* Carrier Extension Error Count - R/clr */
185
-#define E1000_RLEC     0x04040  /* Receive Length Error Count - R/clr */
186
-#define E1000_XONRXC   0x04048  /* XON Rx Count - R/clr */
187
-#define E1000_XONTXC   0x0404C  /* XON Tx Count - R/clr */
188
-#define E1000_XOFFRXC  0x04050  /* XOFF Rx Count - R/clr */
189
-#define E1000_XOFFTXC  0x04054  /* XOFF Tx Count - R/clr */
190
-#define E1000_FCRUC    0x04058  /* Flow Control Rx Unsupported Count- R/clr */
191
-#define E1000_PRC64    0x0405C  /* Packets Rx (64 bytes) - R/clr */
192
-#define E1000_PRC127   0x04060  /* Packets Rx (65-127 bytes) - R/clr */
193
-#define E1000_PRC255   0x04064  /* Packets Rx (128-255 bytes) - R/clr */
194
-#define E1000_PRC511   0x04068  /* Packets Rx (255-511 bytes) - R/clr */
195
-#define E1000_PRC1023  0x0406C  /* Packets Rx (512-1023 bytes) - R/clr */
196
-#define E1000_PRC1522  0x04070  /* Packets Rx (1024-1522 bytes) - R/clr */
197
-#define E1000_GPRC     0x04074  /* Good Packets Rx Count - R/clr */
198
-#define E1000_BPRC     0x04078  /* Broadcast Packets Rx Count - R/clr */
199
-#define E1000_MPRC     0x0407C  /* Multicast Packets Rx Count - R/clr */
200
-#define E1000_GPTC     0x04080  /* Good Packets Tx Count - R/clr */
201
-#define E1000_GORCL    0x04088  /* Good Octets Rx Count Low - R/clr */
202
-#define E1000_GORCH    0x0408C  /* Good Octets Rx Count High - R/clr */
203
-#define E1000_GOTCL    0x04090  /* Good Octets Tx Count Low - R/clr */
204
-#define E1000_GOTCH    0x04094  /* Good Octets Tx Count High - R/clr */
205
-#define E1000_RNBC     0x040A0  /* Rx No Buffers Count - R/clr */
206
-#define E1000_RUC      0x040A4  /* Rx Undersize Count - R/clr */
207
-#define E1000_RFC      0x040A8  /* Rx Fragment Count - R/clr */
208
-#define E1000_ROC      0x040AC  /* Rx Oversize Count - R/clr */
209
-#define E1000_RJC      0x040B0  /* Rx Jabber Count - R/clr */
210
-#define E1000_MGTPRC   0x040B4  /* Management Packets Rx Count - R/clr */
211
-#define E1000_MGTPDC   0x040B8  /* Management Packets Dropped Count - R/clr */
212
-#define E1000_MGTPTC   0x040BC  /* Management Packets Tx Count - R/clr */
213
-#define E1000_TORL     0x040C0  /* Total Octets Rx Low - R/clr */
214
-#define E1000_TORH     0x040C4  /* Total Octets Rx High - R/clr */
215
-#define E1000_TOTL     0x040C8  /* Total Octets Tx Low - R/clr */
216
-#define E1000_TOTH     0x040CC  /* Total Octets Tx High - R/clr */
217
-#define E1000_TPR      0x040D0  /* Total Packets Rx - R/clr */
218
-#define E1000_TPT      0x040D4  /* Total Packets Tx - R/clr */
219
-#define E1000_PTC64    0x040D8  /* Packets Tx (64 bytes) - R/clr */
220
-#define E1000_PTC127   0x040DC  /* Packets Tx (65-127 bytes) - R/clr */
221
-#define E1000_PTC255   0x040E0  /* Packets Tx (128-255 bytes) - R/clr */
222
-#define E1000_PTC511   0x040E4  /* Packets Tx (256-511 bytes) - R/clr */
223
-#define E1000_PTC1023  0x040E8  /* Packets Tx (512-1023 bytes) - R/clr */
224
-#define E1000_PTC1522  0x040EC  /* Packets Tx (1024-1522 Bytes) - R/clr */
225
-#define E1000_MPTC     0x040F0  /* Multicast Packets Tx Count - R/clr */
226
-#define E1000_BPTC     0x040F4  /* Broadcast Packets Tx Count - R/clr */
227
-#define E1000_TSCTC    0x040F8  /* TCP Segmentation Context Tx - R/clr */
228
-#define E1000_TSCTFC   0x040FC  /* TCP Segmentation Context Tx Fail - R/clr */
229
-#define E1000_IAC      0x04100  /* Interrupt Assertion Count */
230
-#define E1000_ICRXPTC  0x04104  /* Interrupt Cause Rx Pkt Timer Expire Count */
231
-#define E1000_ICRXATC  0x04108  /* Interrupt Cause Rx Abs Timer Expire Count */
232
-#define E1000_ICTXPTC  0x0410C  /* Interrupt Cause Tx Pkt Timer Expire Count */
233
-#define E1000_ICTXATC  0x04110  /* Interrupt Cause Tx Abs Timer Expire Count */
234
-#define E1000_ICTXQEC  0x04118  /* Interrupt Cause Tx Queue Empty Count */
235
-#define E1000_ICTXQMTC 0x0411C  /* Interrupt Cause Tx Queue Min Thresh Count */
236
-#define E1000_ICRXDMTC 0x04120  /* Interrupt Cause Rx Desc Min Thresh Count */
237
-#define E1000_ICRXOC   0x04124  /* Interrupt Cause Receiver Overrun Count */
238
-
239
-#define E1000_PCS_CFG0    0x04200  /* PCS Configuration 0 - RW */
240
-#define E1000_PCS_LCTL    0x04208  /* PCS Link Control - RW */
241
-#define E1000_PCS_LSTAT   0x0420C  /* PCS Link Status - RO */
242
-#define E1000_CBTMPC      0x0402C  /* Circuit Breaker Tx Packet Count */
243
-#define E1000_HTDPMC      0x0403C  /* Host Transmit Discarded Packets */
244
-#define E1000_CBRDPC      0x04044  /* Circuit Breaker Rx Dropped Count */
245
-#define E1000_CBRMPC      0x040FC  /* Circuit Breaker Rx Packet Count */
246
-#define E1000_RPTHC       0x04104  /* Rx Packets To Host */
247
-#define E1000_HGPTC       0x04118  /* Host Good Packets Tx Count */
248
-#define E1000_HTCBDPC     0x04124  /* Host Tx Circuit Breaker Dropped Count */
249
-#define E1000_HGORCL      0x04128  /* Host Good Octets Received Count Low */
250
-#define E1000_HGORCH      0x0412C  /* Host Good Octets Received Count High */
251
-#define E1000_HGOTCL      0x04130  /* Host Good Octets Transmit Count Low */
252
-#define E1000_HGOTCH      0x04134  /* Host Good Octets Transmit Count High */
253
-#define E1000_LENERRS     0x04138  /* Length Errors Count */
254
-#define E1000_SCVPC       0x04228  /* SerDes/SGMII Code Violation Pkt Count */
255
-#define E1000_HRMPC       0x0A018  /* Header Redirection Missed Packet Count */
256
-#define E1000_PCS_ANADV   0x04218  /* AN advertisement - RW */
257
-#define E1000_PCS_LPAB    0x0421C  /* Link Partner Ability - RW */
258
-#define E1000_PCS_NPTX    0x04220  /* AN Next Page Transmit - RW */
259
-#define E1000_PCS_LPABNP  0x04224  /* Link Partner Ability Next Page - RW */
260
-#define E1000_1GSTAT_RCV  0x04228  /* 1GSTAT Code Violation Packet Count - RW */
261
-#define E1000_RXCSUM   0x05000  /* Rx Checksum Control - RW */
262
-#define E1000_RLPML    0x05004  /* Rx Long Packet Max Length */
263
-#define E1000_RFCTL    0x05008  /* Receive Filter Control*/
264
-#define E1000_MTA      0x05200  /* Multicast Table Array - RW Array */
265
-#define E1000_RA       0x05400  /* Receive Address - RW Array */
266
-#define E1000_VFTA     0x05600  /* VLAN Filter Table Array - RW Array */
267
-#define E1000_VT_CTL   0x0581C  /* VMDq Control - RW */
268
-#define E1000_VFQA0    0x0B000  /* VLAN Filter Queue Array 0 - RW Array */
269
-#define E1000_VFQA1    0x0B200  /* VLAN Filter Queue Array 1 - RW Array */
270
-#define E1000_WUC      0x05800  /* Wakeup Control - RW */
271
-#define E1000_WUFC     0x05808  /* Wakeup Filter Control - RW */
272
-#define E1000_WUS      0x05810  /* Wakeup Status - RO */
273
-#define E1000_MANC     0x05820  /* Management Control - RW */
274
-#define E1000_IPAV     0x05838  /* IP Address Valid - RW */
275
-#define E1000_IP4AT    0x05840  /* IPv4 Address Table - RW Array */
276
-#define E1000_IP6AT    0x05880  /* IPv6 Address Table - RW Array */
277
-#define E1000_WUPL     0x05900  /* Wakeup Packet Length - RW */
278
-#define E1000_WUPM     0x05A00  /* Wakeup Packet Memory - RO A */
279
-#define E1000_PBACL    0x05B68  /* MSIx PBA Clear - Read/Write 1's to clear */
280
-#define E1000_FFLT     0x05F00  /* Flexible Filter Length Table - RW Array */
281
-#define E1000_HOST_IF  0x08800  /* Host Interface */
282
-#define E1000_FFMT     0x09000  /* Flexible Filter Mask Table - RW Array */
283
-#define E1000_FFVT     0x09800  /* Flexible Filter Value Table - RW Array */
284
-
285
-#define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */
286
-#define E1000_MDPHYA      0x0003C /* PHY address - RW */
287
-#define E1000_MANC2H      0x05860 /* Management Control To Host - RW */
288
-#define E1000_SW_FW_SYNC  0x05B5C /* Software-Firmware Synchronization - RW */
289
-#define E1000_CCMCTL      0x05B48 /* CCM Control Register */
290
-#define E1000_GIOCTL      0x05B44 /* GIO Analog Control Register */
291
-#define E1000_SCCTL       0x05B4C /* PCIc PLL Configuration Register */
292
-#define E1000_GCR         0x05B00 /* PCI-Ex Control */
293
-#define E1000_GCR2        0x05B64 /* PCI-Ex Control #2 */
294
-#define E1000_GSCL_1    0x05B10 /* PCI-Ex Statistic Control #1 */
295
-#define E1000_GSCL_2    0x05B14 /* PCI-Ex Statistic Control #2 */
296
-#define E1000_GSCL_3    0x05B18 /* PCI-Ex Statistic Control #3 */
297
-#define E1000_GSCL_4    0x05B1C /* PCI-Ex Statistic Control #4 */
298
-#define E1000_FACTPS    0x05B30 /* Function Active and Power State to MNG */
299
-#define E1000_SWSM      0x05B50 /* SW Semaphore */
300
-#define E1000_FWSM      0x05B54 /* FW Semaphore */
301
-#define E1000_SWSM2     0x05B58 /* Driver-only SW semaphore (not used by BOOT agents) */
302
-#define E1000_DCA_ID    0x05B70 /* DCA Requester ID Information - RO */
303
-#define E1000_DCA_CTRL  0x05B74 /* DCA Control - RW */
304
-#define E1000_FFLT_DBG  0x05F04 /* Debug Register */
305
-#define E1000_HICR      0x08F00 /* Host Interface Control */
306
-
307
-/* RSS registers */
308
-#define E1000_CPUVEC    0x02C10 /* CPU Vector Register - RW */
309
-#define E1000_MRQC      0x05818 /* Multiple Receive Control - RW */
310
-#define E1000_IMIR(_i)      (0x05A80 + ((_i) * 4))  /* Immediate Interrupt */
311
-#define E1000_IMIREXT(_i)   (0x05AA0 + ((_i) * 4))  /* Immediate Interrupt Ext*/
312
-#define E1000_IMIRVP    0x05AC0 /* Immediate Interrupt Rx VLAN Priority - RW */
313
-#define E1000_MSIXBM(_i)    (0x01600 + ((_i) * 4)) /* MSI-X Allocation Register
314
-                                                    * (_i) - RW */
315
-#define E1000_MSIXTADD(_i)  (0x0C000 + ((_i) * 0x10)) /* MSI-X Table entry addr
316
-                                                       * low reg - RW */
317
-#define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10)) /* MSI-X Table entry addr
318
-                                                       * upper reg - RW */
319
-#define E1000_MSIXTMSG(_i)  (0x0C008 + ((_i) * 0x10)) /* MSI-X Table entry
320
-                                                       * message reg - RW */
321
-#define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10)) /* MSI-X Table entry
322
-                                                       * vector ctrl reg - RW */
323
-#define E1000_MSIXPBA    0x0E000 /* MSI-X Pending bit array */
324
-#define E1000_RETA(_i)  (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */
325
-#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */
326
-#define E1000_RSSIM     0x05864 /* RSS Interrupt Mask */
327
-#define E1000_RSSIR     0x05868 /* RSS Interrupt Request */
328
-
329
-#endif

+ 0
- 34
src/drivers/net/e1000e/e1000e.c Прегледај датотеку

@@ -1,34 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2008 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_ONLY );
30
-
31
-REQUIRE_OBJECT(e1000e_main);
32
-REQUIRE_OBJECT(e1000e_80003es2lan);
33
-REQUIRE_OBJECT(e1000e_82571);
34
-REQUIRE_OBJECT(e1000e_ich8lan);

+ 0
- 534
src/drivers/net/e1000e/e1000e.h Прегледај датотеку

@@ -1,534 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2009 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-/* Linux PRO/1000 Ethernet Driver main header file */
32
-
33
-#ifndef _E1000E_H_
34
-#define _E1000E_H_
35
-
36
-#include <stdint.h>
37
-#include <stdlib.h>
38
-#include <stdio.h>
39
-#include <string.h>
40
-#include <unistd.h>
41
-#include <ipxe/io.h>
42
-#include <errno.h>
43
-#include <byteswap.h>
44
-#include <ipxe/pci.h>
45
-#include <ipxe/malloc.h>
46
-#include <ipxe/if_ether.h>
47
-#include <ipxe/ethernet.h>
48
-#include <ipxe/iobuf.h>
49
-#include <ipxe/netdevice.h>
50
-
51
-/* Begin OS Dependencies */
52
-
53
-#define u8         unsigned char
54
-#define bool       boolean_t
55
-#define dma_addr_t unsigned long
56
-#define __le16     uint16_t
57
-#define __le32     uint32_t
58
-#define __le64     uint64_t
59
-
60
-#define __iomem
61
-
62
-#define msleep(x) mdelay(x)
63
-
64
-#define ETH_FCS_LEN 4
65
-
66
-typedef int spinlock_t;
67
-typedef enum {
68
-    false = 0,
69
-    true = 1
70
-} boolean_t;
71
-
72
-/* End OS Dependencies */
73
-
74
-#include "e1000e_hw.h"
75
-
76
-#define E1000_TX_FLAGS_CSUM		0x00000001
77
-#define E1000_TX_FLAGS_VLAN		0x00000002
78
-#define E1000_TX_FLAGS_TSO		0x00000004
79
-#define E1000_TX_FLAGS_IPV4		0x00000008
80
-#define E1000_TX_FLAGS_VLAN_MASK	0xffff0000
81
-#define E1000_TX_FLAGS_VLAN_SHIFT	16
82
-
83
-#define E1000_MAX_PER_TXD	8192
84
-#define E1000_MAX_TXD_PWR	12
85
-
86
-#define MINIMUM_DHCP_PACKET_SIZE 282
87
-
88
-struct e1000_info;
89
-
90
-#define e_dbg(arg...) if (0) { printf (arg); };
91
-
92
-#ifdef CONFIG_E1000E_MSIX
93
-/* Interrupt modes, as used by the IntMode paramter */
94
-#define E1000E_INT_MODE_LEGACY		0
95
-#define E1000E_INT_MODE_MSI		1
96
-#define E1000E_INT_MODE_MSIX		2
97
-
98
-#endif /* CONFIG_E1000E_MSIX */
99
-#ifndef CONFIG_E1000E_NAPI
100
-#define E1000_MAX_INTR 10
101
-
102
-#endif /* CONFIG_E1000E_NAPI */
103
-/* Tx/Rx descriptor defines */
104
-#define E1000_DEFAULT_TXD		256
105
-#define E1000_MAX_TXD			4096
106
-#define E1000_MIN_TXD			64
107
-
108
-#define E1000_DEFAULT_RXD		256
109
-#define E1000_MAX_RXD			4096
110
-#define E1000_MIN_RXD			64
111
-
112
-#define E1000_MIN_ITR_USECS		10 /* 100000 irq/sec */
113
-#define E1000_MAX_ITR_USECS		10000 /* 100    irq/sec */
114
-
115
-/* Early Receive defines */
116
-#define E1000_ERT_2048			0x100
117
-
118
-#define E1000_FC_PAUSE_TIME		0x0680 /* 858 usec */
119
-
120
-/* How many Tx Descriptors do we need to call netif_wake_queue ? */
121
-/* How many Rx Buffers do we bundle into one write to the hardware ? */
122
-#define E1000_RX_BUFFER_WRITE		16 /* Must be power of 2 */
123
-
124
-#define AUTO_ALL_MODES			0
125
-#define E1000_EEPROM_APME		0x0400
126
-
127
-#define E1000_MNG_VLAN_NONE		(-1)
128
-
129
-/* Number of packet split data buffers (not including the header buffer) */
130
-#define PS_PAGE_BUFFERS			(MAX_PS_BUFFERS - 1)
131
-
132
-#define MAXIMUM_ETHERNET_VLAN_SIZE 	1522
133
-
134
-#define DEFAULT_JUMBO			9234
135
-
136
-enum e1000_boards {
137
-	board_82571,
138
-	board_82572,
139
-	board_82573,
140
-	board_82574,
141
-	board_80003es2lan,
142
-	board_ich8lan,
143
-	board_ich9lan,
144
-	board_ich10lan,
145
-	board_pchlan,
146
-	board_pch2lan,
147
-	board_82583,
148
-};
149
-
150
-/* board specific private data structure */
151
-struct e1000_adapter {
152
-	const struct e1000_info *ei;
153
-
154
-	/* OS defined structs */
155
-	struct net_device *netdev;
156
-	struct pci_device *pdev;
157
-	struct net_device_stats net_stats;
158
-
159
-	/* structs defined in e1000_hw.h */
160
-	struct e1000_hw hw;
161
-
162
-	struct e1000_phy_info phy_info;
163
-
164
-	u32 wol;
165
-	u32 pba;
166
-	u32 max_hw_frame_size;
167
-
168
-	bool fc_autoneg;
169
-
170
-	unsigned int flags;
171
-	unsigned int flags2;
172
-
173
-#define NUM_TX_DESC	8
174
-#define NUM_RX_DESC	8
175
-
176
-	struct io_buffer *tx_iobuf[NUM_TX_DESC];
177
-	struct io_buffer *rx_iobuf[NUM_RX_DESC];
178
-
179
-	struct e1000_tx_desc *tx_base;
180
-	struct e1000_rx_desc *rx_base;
181
-
182
-	uint32_t tx_ring_size;
183
-	uint32_t rx_ring_size;
184
-
185
-	uint32_t tx_head;
186
-	uint32_t tx_tail;
187
-	uint32_t tx_fill_ctr;
188
-
189
-	uint32_t rx_curr;
190
-
191
-	uint32_t ioaddr;
192
-	uint32_t irqno;
193
-
194
-        uint32_t tx_int_delay;
195
-        uint32_t tx_abs_int_delay;
196
-        uint32_t txd_cmd;
197
-};
198
-
199
-struct e1000_info {
200
-	enum e1000_mac_type	mac;
201
-	unsigned int		flags;
202
-	unsigned int		flags2;
203
-	u32			pba;
204
-	u32			max_hw_frame_size;
205
-	s32			(*get_variants)(struct e1000_adapter *);
206
-	void			(*init_ops)(struct e1000_hw *);
207
-};
208
-
209
-/* hardware capability, feature, and workaround flags */
210
-#define FLAG_HAS_AMT                      (1 << 0)
211
-#define FLAG_HAS_FLASH                    (1 << 1)
212
-#define FLAG_HAS_HW_VLAN_FILTER           (1 << 2)
213
-#define FLAG_HAS_WOL                      (1 << 3)
214
-#define FLAG_HAS_ERT                      (1 << 4)
215
-#define FLAG_HAS_CTRLEXT_ON_LOAD          (1 << 5)
216
-#define FLAG_HAS_SWSM_ON_LOAD             (1 << 6)
217
-#define FLAG_HAS_JUMBO_FRAMES             (1 << 7)
218
-#define FLAG_IS_ICH                       (1 << 9)
219
-#ifdef CONFIG_E1000E_MSIX
220
-#define FLAG_HAS_MSIX                     (1 << 10)
221
-#endif
222
-#define FLAG_HAS_SMART_POWER_DOWN         (1 << 11)
223
-#define FLAG_IS_QUAD_PORT_A               (1 << 12)
224
-#define FLAG_IS_QUAD_PORT                 (1 << 13)
225
-#define FLAG_TIPG_MEDIUM_FOR_80003ESLAN   (1 << 14)
226
-#define FLAG_APME_IN_WUC                  (1 << 15)
227
-#define FLAG_APME_IN_CTRL3                (1 << 16)
228
-#define FLAG_APME_CHECK_PORT_B            (1 << 17)
229
-#define FLAG_DISABLE_FC_PAUSE_TIME        (1 << 18)
230
-#define FLAG_NO_WAKE_UCAST                (1 << 19)
231
-#define FLAG_MNG_PT_ENABLED               (1 << 20)
232
-#define FLAG_RESET_OVERWRITES_LAA         (1 << 21)
233
-#define FLAG_TARC_SPEED_MODE_BIT          (1 << 22)
234
-#define FLAG_TARC_SET_BIT_ZERO            (1 << 23)
235
-#define FLAG_RX_NEEDS_RESTART             (1 << 24)
236
-#define FLAG_LSC_GIG_SPEED_DROP           (1 << 25)
237
-#define FLAG_SMART_POWER_DOWN             (1 << 26)
238
-#define FLAG_MSI_ENABLED                  (1 << 27)
239
-#define FLAG_RX_CSUM_ENABLED              (1 << 28)
240
-#define FLAG_TSO_FORCE                    (1 << 29)
241
-#define FLAG_RX_RESTART_NOW               (1 << 30)
242
-#define FLAG_MSI_TEST_FAILED              (1 << 31)
243
-
244
-/* CRC Stripping defines */
245
-#define FLAG2_CRC_STRIPPING               (1 << 0)
246
-#define FLAG2_HAS_PHY_WAKEUP              (1 << 1)
247
-
248
-#define E1000_RX_DESC_PS(R, i)	    \
249
-	(&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
250
-#define E1000_GET_DESC(R, i, type)	(&(((struct type *)((R).desc))[i]))
251
-#define E1000_RX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_rx_desc)
252
-#define E1000_TX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_tx_desc)
253
-#define E1000_CONTEXT_DESC(R, i)	E1000_GET_DESC(R, i, e1000_context_desc)
254
-
255
-enum e1000_state_t {
256
-	__E1000E_TESTING,
257
-	__E1000E_RESETTING,
258
-	__E1000E_DOWN
259
-};
260
-
261
-enum latency_range {
262
-	lowest_latency = 0,
263
-	low_latency = 1,
264
-	bulk_latency = 2,
265
-	latency_invalid = 255
266
-};
267
-
268
-extern void e1000e_check_options(struct e1000_adapter *adapter);
269
-
270
-extern void e1000e_reset(struct e1000_adapter *adapter);
271
-extern void e1000e_power_up_phy(struct e1000_adapter *adapter);
272
-
273
-extern void e1000e_init_function_pointers_82571(struct e1000_hw *hw)
274
-						__attribute__((weak));
275
-extern void e1000e_init_function_pointers_80003es2lan(struct e1000_hw *hw)
276
-						__attribute__((weak));
277
-extern void e1000e_init_function_pointers_ich8lan(struct e1000_hw *hw)
278
-						__attribute__((weak));
279
-
280
-extern int e1000e_probe(struct pci_device *pdev);
281
-
282
-extern void e1000e_remove(struct pci_device *pdev);
283
-
284
-extern s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num);
285
-
286
-static inline s32 e1000e_commit_phy(struct e1000_hw *hw)
287
-{
288
-	if (hw->phy.ops.commit)
289
-		return hw->phy.ops.commit(hw);
290
-
291
-	return 0;
292
-}
293
-
294
-extern bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
295
-
296
-extern bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
297
-extern void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
298
-
299
-extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
300
-						 bool state);
301
-extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
302
-extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
303
-extern void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw);
304
-extern s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
305
-
306
-extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
307
-extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);
308
-extern s32 e1000e_check_for_serdes_link(struct e1000_hw *hw);
309
-extern s32 e1000e_cleanup_led_generic(struct e1000_hw *hw);
310
-extern s32 e1000e_led_on_generic(struct e1000_hw *hw);
311
-extern s32 e1000e_led_off_generic(struct e1000_hw *hw);
312
-extern s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw);
313
-extern s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, u16 *duplex);
314
-extern s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, u16 *duplex);
315
-extern s32 e1000e_disable_pcie_master(struct e1000_hw *hw);
316
-extern s32 e1000e_get_auto_rd_done(struct e1000_hw *hw);
317
-extern s32 e1000e_id_led_init(struct e1000_hw *hw);
318
-extern void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
319
-extern s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
320
-extern s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw);
321
-extern s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw);
322
-extern s32 e1000e_setup_link(struct e1000_hw *hw);
323
-static inline void e1000e_clear_vfta(struct e1000_hw *hw)
324
-{
325
-	hw->mac.ops.clear_vfta(hw);
326
-}
327
-extern void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
328
-extern void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
329
-					       u8 *mc_addr_list,
330
-					       u32 mc_addr_count);
331
-extern void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
332
-extern s32 e1000e_set_fc_watermarks(struct e1000_hw *hw);
333
-extern void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
334
-extern s32 e1000e_get_hw_semaphore(struct e1000_hw *hw);
335
-extern s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
336
-extern void e1000e_config_collision_dist(struct e1000_hw *hw);
337
-extern s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw);
338
-extern s32 e1000e_force_mac_fc(struct e1000_hw *hw);
339
-extern s32 e1000e_blink_led(struct e1000_hw *hw);
340
-extern void e1000e_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
341
-static inline void e1000e_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
342
-{
343
-	if (hw->mac.ops.write_vfta)
344
-		hw->mac.ops.write_vfta(hw, offset, value);
345
-}
346
-extern void e1000e_reset_adaptive(struct e1000_hw *hw);
347
-extern void e1000e_update_adaptive(struct e1000_hw *hw);
348
-
349
-extern s32 e1000e_setup_copper_link(struct e1000_hw *hw);
350
-extern void e1000e_put_hw_semaphore(struct e1000_hw *hw);
351
-extern s32 e1000e_check_reset_block_generic(struct e1000_hw *hw);
352
-#if 0
353
-extern s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
354
-#endif
355
-#if 0
356
-extern s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
357
-#endif
358
-extern s32 e1000e_get_phy_info_igp(struct e1000_hw *hw);
359
-extern s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
360
-extern s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
361
-extern s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
362
-extern s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
363
-extern s32 e1000e_phy_sw_reset(struct e1000_hw *hw);
364
-#if 0
365
-extern s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
366
-#endif
367
-extern s32 e1000e_get_cfg_done(struct e1000_hw *hw);
368
-#if 0
369
-extern s32 e1000e_get_cable_length_m88(struct e1000_hw *hw);
370
-#endif
371
-extern s32 e1000e_get_phy_info_m88(struct e1000_hw *hw);
372
-extern s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
373
-extern s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
374
-extern enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
375
-extern s32 e1000e_determine_phy_address(struct e1000_hw *hw);
376
-extern s32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
377
-extern s32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
378
-#if 0
379
-extern void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
380
-#endif
381
-extern s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
382
-extern s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
383
-extern s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
384
-			       u32 usec_interval, bool *success);
385
-extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
386
-extern s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
387
-extern s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
388
-extern s32 e1000e_check_downshift(struct e1000_hw *hw);
389
-
390
-static inline s32 e1000e_phy_hw_reset(struct e1000_hw *hw)
391
-{
392
-	if (hw->phy.ops.reset)
393
-		return hw->phy.ops.reset(hw);
394
-
395
-	return 0;
396
-}
397
-
398
-static inline s32 e1000e_check_reset_block(struct e1000_hw *hw)
399
-{
400
-	if (hw->phy.ops.check_reset_block)
401
-		return hw->phy.ops.check_reset_block(hw);
402
-
403
-	return 0;
404
-}
405
-
406
-static inline s32 e1e_rphy(struct e1000_hw *hw, u32 offset, u16 *data)
407
-{
408
-	if (hw->phy.ops.read_reg)
409
-		return hw->phy.ops.read_reg(hw, offset, data);
410
-
411
-	return 0;
412
-}
413
-
414
-static inline s32 e1e_wphy(struct e1000_hw *hw, u32 offset, u16 data)
415
-{
416
-	if (hw->phy.ops.write_reg)
417
-		return hw->phy.ops.write_reg(hw, offset, data);
418
-
419
-	return 0;
420
-}
421
-
422
-#if 0
423
-static inline s32 e1000e_get_cable_length(struct e1000_hw *hw)
424
-{
425
-	if (hw->phy.ops.get_cable_length)
426
-		return hw->phy.ops.get_cable_length(hw);
427
-
428
-	return 0;
429
-}
430
-#endif
431
-
432
-extern s32 e1000e_acquire_nvm(struct e1000_hw *hw);
433
-extern s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
434
-extern s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
435
-extern s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
436
-extern s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
437
-extern s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
438
-extern void e1000e_release_nvm(struct e1000_hw *hw);
439
-
440
-static inline s32 e1000e_read_mac_addr(struct e1000_hw *hw)
441
-{
442
-       if (hw->mac.ops.read_mac_addr)
443
-               return hw->mac.ops.read_mac_addr(hw);
444
-
445
-       return e1000e_read_mac_addr_generic(hw);
446
-}
447
-
448
-static inline s32 e1000e_validate_nvm_checksum(struct e1000_hw *hw)
449
-{
450
-	return hw->nvm.ops.validate(hw);
451
-}
452
-
453
-static inline s32 e1000e_update_nvm_checksum(struct e1000_hw *hw)
454
-{
455
-	return hw->nvm.ops.update(hw);
456
-}
457
-
458
-static inline s32 e1000e_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
459
-{
460
-	return hw->nvm.ops.read(hw, offset, words, data);
461
-}
462
-
463
-static inline s32 e1000e_write_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
464
-{
465
-	return hw->nvm.ops.write(hw, offset, words, data);
466
-}
467
-
468
-static inline s32 e1000e_get_phy_info(struct e1000_hw *hw)
469
-{
470
-	if (hw->phy.ops.get_info)
471
-		return hw->phy.ops.get_info(hw);
472
-
473
-	return 0;
474
-}
475
-
476
-extern bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
477
-#if 0
478
-extern s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer, u16 length);
479
-#endif
480
-
481
-static inline u32 __er32(struct e1000_hw *hw, unsigned long reg)
482
-{
483
-	return readl(hw->hw_addr + reg);
484
-}
485
-
486
-static inline void __ew32(struct e1000_hw *hw, unsigned long reg, u32 val)
487
-{
488
-	writel(val, hw->hw_addr + reg);
489
-}
490
-
491
-#define er32(reg)	__er32(hw, E1000_##reg)
492
-#define ew32(reg, val)	__ew32(hw, E1000_##reg, (val))
493
-#define e1e_flush()	er32(STATUS)
494
-
495
-#define E1000_WRITE_REG(a, reg, value)  \
496
-    writel((value), ((a)->hw_addr + reg))
497
-
498
-#define E1000_READ_REG(a, reg) (readl((a)->hw_addr + reg))
499
-
500
-#define E1000_WRITE_REG_ARRAY(a, reg, offset, value)  \
501
-    writel((value), ((a)->hw_addr + reg + ((offset) << 2)))
502
-
503
-#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
504
-    readl((a)->hw_addr + reg + ((offset) << 2)))
505
-
506
-#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
507
-#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
508
-
509
-static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
510
-{
511
-	return readw(hw->flash_address + reg);
512
-}
513
-
514
-static inline u32 __er32flash(struct e1000_hw *hw, unsigned long reg)
515
-{
516
-	return readl(hw->flash_address + reg);
517
-}
518
-
519
-static inline void __ew16flash(struct e1000_hw *hw, unsigned long reg, u16 val)
520
-{
521
-	writew(val, hw->flash_address + reg);
522
-}
523
-
524
-static inline void __ew32flash(struct e1000_hw *hw, unsigned long reg, u32 val)
525
-{
526
-	writel(val, hw->flash_address + reg);
527
-}
528
-
529
-#define er16flash(reg)		__er16flash(hw, (reg))
530
-#define er32flash(reg)		__er32flash(hw, (reg))
531
-#define ew16flash(reg, val)	__ew16flash(hw, (reg), (val))
532
-#define ew32flash(reg, val)	__ew32flash(hw, (reg), (val))
533
-
534
-#endif /* _E1000E_H_ */

+ 0
- 1533
src/drivers/net/e1000e/e1000e_80003es2lan.c
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Прегледај датотеку


+ 0
- 100
src/drivers/net/e1000e/e1000e_80003es2lan.h Прегледај датотеку

@@ -1,100 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2009 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-#ifndef _E1000E_80003ES2LAN_H_
32
-#define _E1000E_80003ES2LAN_H_
33
-
34
-#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL       0x00
35
-#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL        0x02
36
-#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL         0x10
37
-#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE  0x1F
38
-
39
-#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS    0x0008
40
-#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS    0x0800
41
-#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING   0x0010
42
-
43
-#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
44
-#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT   0x0000
45
-#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE          0x2000
46
-
47
-#define E1000_KMRNCTRLSTA_OPMODE_MASK            0x000C
48
-#define E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO     0x0004
49
-
50
-#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */
51
-#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN        0x00010000
52
-
53
-#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN       0x8
54
-#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN     0x9
55
-
56
-/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
57
-#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE  0x0002 /* 1=Reversal Disabled */
58
-#define GG82563_PSCR_CROSSOVER_MODE_MASK        0x0060
59
-#define GG82563_PSCR_CROSSOVER_MODE_MDI         0x0000 /* 00=Manual MDI */
60
-#define GG82563_PSCR_CROSSOVER_MODE_MDIX        0x0020 /* 01=Manual MDIX */
61
-#define GG82563_PSCR_CROSSOVER_MODE_AUTO        0x0060 /* 11=Auto crossover */
62
-
63
-/* PHY Specific Control Register 2 (Page 0, Register 26) */
64
-#define GG82563_PSCR2_REVERSE_AUTO_NEG          0x2000
65
-                                               /* 1=Reverse Auto-Negotiation */
66
-
67
-/* MAC Specific Control Register (Page 2, Register 21) */
68
-/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
69
-#define GG82563_MSCR_TX_CLK_MASK                0x0007
70
-#define GG82563_MSCR_TX_CLK_10MBPS_2_5          0x0004
71
-#define GG82563_MSCR_TX_CLK_100MBPS_25          0x0005
72
-#define GG82563_MSCR_TX_CLK_1000MBPS_2_5        0x0006
73
-#define GG82563_MSCR_TX_CLK_1000MBPS_25         0x0007
74
-
75
-#define GG82563_MSCR_ASSERT_CRS_ON_TX           0x0010 /* 1=Assert */
76
-
77
-/* DSP Distance Register (Page 5, Register 26) */
78
-/*
79
- * 0 = <50M
80
- * 1 = 50-80M
81
- * 2 = 80-100M
82
- * 3 = 110-140M
83
- * 4 = >140M
84
- */
85
-#define GG82563_DSPD_CABLE_LENGTH               0x0007
86
-
87
-/* Kumeran Mode Control Register (Page 193, Register 16) */
88
-#define GG82563_KMCR_PASS_FALSE_CARRIER         0x0800
89
-
90
-/* Max number of times Kumeran read/write should be validated */
91
-#define GG82563_MAX_KMRN_RETRY                  0x5
92
-
93
-/* Power Management Control Register (Page 193, Register 20) */
94
-#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE     0x0001
95
-                                          /* 1=Enable SERDES Electrical Idle */
96
-
97
-/* In-Band Control Register (Page 194, Register 18) */
98
-#define GG82563_ICR_DIS_PADDING                 0x0010 /* Disable Padding */
99
-
100
-#endif

+ 0
- 1818
src/drivers/net/e1000e/e1000e_82571.c
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Прегледај датотеку


+ 0
- 55
src/drivers/net/e1000e/e1000e_82571.h Прегледај датотеку

@@ -1,55 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2009 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-#ifndef _E1000E_82571_H_
32
-#define _E1000E_82571_H_
33
-
34
-#define ID_LED_RESERVED_F746 0xF746
35
-#define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
36
-                              (ID_LED_OFF1_ON2  <<  8) | \
37
-                              (ID_LED_DEF1_DEF2 <<  4) | \
38
-                              (ID_LED_DEF1_DEF2))
39
-
40
-#define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
41
-
42
-/* Intr Throttling - RW */
43
-#define E1000_EITR_82574(_n)    (0x000E8 + (0x4 * (_n)))
44
-
45
-#define E1000_EIAC_82574        0x000DC /* Ext. Interrupt Auto Clear - RW */
46
-#define E1000_EIAC_MASK_82574   0x01F00000
47
-
48
-#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
49
-
50
-#define E1000_RXCFGL    0x0B634 /* TimeSync Rx EtherType & Msg Type Reg - RW */
51
-
52
-bool e1000e_get_laa_state_82571(struct e1000_hw *hw);
53
-void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state);
54
-
55
-#endif

+ 0
- 1471
src/drivers/net/e1000e/e1000e_defines.h
Разлика између датотеке није приказан због своје велике величине
Прегледај датотеку


+ 0
- 723
src/drivers/net/e1000e/e1000e_hw.h Прегледај датотеку

@@ -1,723 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2009 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-#ifndef _E1000E_HW_H_
32
-#define _E1000E_HW_H_
33
-
34
-#include "e1000e_regs.h"
35
-#include "e1000e_defines.h"
36
-
37
-struct e1000_hw;
38
-
39
-#define E1000_DEV_ID_82571EB_COPPER           0x105E
40
-#define E1000_DEV_ID_82571EB_FIBER            0x105F
41
-#define E1000_DEV_ID_82571EB_SERDES           0x1060
42
-#define E1000_DEV_ID_82571EB_SERDES_DUAL      0x10D9
43
-#define E1000_DEV_ID_82571EB_SERDES_QUAD      0x10DA
44
-#define E1000_DEV_ID_82571EB_QUAD_COPPER      0x10A4
45
-#define E1000_DEV_ID_82571PT_QUAD_COPPER      0x10D5
46
-#define E1000_DEV_ID_82571EB_QUAD_FIBER       0x10A5
47
-#define E1000_DEV_ID_82571EB_QUAD_COPPER_LP   0x10BC
48
-#define E1000_DEV_ID_82572EI_COPPER           0x107D
49
-#define E1000_DEV_ID_82572EI_FIBER            0x107E
50
-#define E1000_DEV_ID_82572EI_SERDES           0x107F
51
-#define E1000_DEV_ID_82572EI                  0x10B9
52
-#define E1000_DEV_ID_82573E                   0x108B
53
-#define E1000_DEV_ID_82573E_IAMT              0x108C
54
-#define E1000_DEV_ID_82573L                   0x109A
55
-#define E1000_DEV_ID_82574L                   0x10D3
56
-#define E1000_DEV_ID_82574LA                  0x10F6
57
-#define E1000_DEV_ID_82583V                   0x150C
58
-#define E1000_DEV_ID_80003ES2LAN_COPPER_DPT   0x1096
59
-#define E1000_DEV_ID_80003ES2LAN_SERDES_DPT   0x1098
60
-#define E1000_DEV_ID_80003ES2LAN_COPPER_SPT   0x10BA
61
-#define E1000_DEV_ID_80003ES2LAN_SERDES_SPT   0x10BB
62
-#define E1000_DEV_ID_ICH8_82567V_3            0x1501
63
-#define E1000_DEV_ID_ICH8_IGP_M_AMT           0x1049
64
-#define E1000_DEV_ID_ICH8_IGP_AMT             0x104A
65
-#define E1000_DEV_ID_ICH8_IGP_C               0x104B
66
-#define E1000_DEV_ID_ICH8_IFE                 0x104C
67
-#define E1000_DEV_ID_ICH8_IFE_GT              0x10C4
68
-#define E1000_DEV_ID_ICH8_IFE_G               0x10C5
69
-#define E1000_DEV_ID_ICH8_IGP_M               0x104D
70
-#define E1000_DEV_ID_ICH9_IGP_M               0x10BF
71
-#define E1000_DEV_ID_ICH9_IGP_M_AMT           0x10F5
72
-#define E1000_DEV_ID_ICH9_IGP_M_V             0x10CB
73
-#define E1000_DEV_ID_ICH9_IGP_AMT             0x10BD
74
-#define E1000_DEV_ID_ICH9_BM                  0x10E5
75
-#define E1000_DEV_ID_ICH9_IGP_C               0x294C
76
-#define E1000_DEV_ID_ICH9_IFE                 0x10C0
77
-#define E1000_DEV_ID_ICH9_IFE_GT              0x10C3
78
-#define E1000_DEV_ID_ICH9_IFE_G               0x10C2
79
-#define E1000_DEV_ID_ICH10_R_BM_LM            0x10CC
80
-#define E1000_DEV_ID_ICH10_R_BM_LF            0x10CD
81
-#define E1000_DEV_ID_ICH10_R_BM_V             0x10CE
82
-#define E1000_DEV_ID_ICH10_D_BM_LM            0x10DE
83
-#define E1000_DEV_ID_ICH10_D_BM_LF            0x10DF
84
-#define E1000_DEV_ID_PCH_M_HV_LM              0x10EA
85
-#define E1000_DEV_ID_PCH_M_HV_LC              0x10EB
86
-#define E1000_DEV_ID_PCH_D_HV_DM              0x10EF
87
-#define E1000_DEV_ID_PCH_D_HV_DC              0x10F0
88
-#define E1000_DEV_ID_PCH2_LV_LM               0x1502
89
-#define E1000_DEV_ID_PCH2_LV_V                0x1503
90
-#define E1000_REVISION_0 0
91
-#define E1000_REVISION_1 1
92
-#define E1000_REVISION_2 2
93
-#define E1000_REVISION_3 3
94
-#define E1000_REVISION_4 4
95
-
96
-#define E1000_FUNC_0     0
97
-#define E1000_FUNC_1     1
98
-
99
-#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
100
-#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
101
-
102
-enum e1000_mac_type {
103
-	e1000_undefined = 0,
104
-	e1000_82571,
105
-	e1000_82572,
106
-	e1000_82573,
107
-	e1000_82574,
108
-	e1000_82583,
109
-	e1000_80003es2lan,
110
-	e1000_ich8lan,
111
-	e1000_ich9lan,
112
-	e1000_ich10lan,
113
-	e1000_pchlan,
114
-	e1000_pch2lan,
115
-	e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
116
-};
117
-
118
-enum e1000_media_type {
119
-	e1000_media_type_unknown = 0,
120
-	e1000_media_type_copper = 1,
121
-	e1000_media_type_fiber = 2,
122
-	e1000_media_type_internal_serdes = 3,
123
-	e1000_num_media_types
124
-};
125
-
126
-enum e1000_nvm_type {
127
-	e1000_nvm_unknown = 0,
128
-	e1000_nvm_none,
129
-	e1000_nvm_eeprom_spi,
130
-	e1000_nvm_flash_hw,
131
-	e1000_nvm_flash_sw
132
-};
133
-
134
-enum e1000_nvm_override {
135
-	e1000_nvm_override_none = 0,
136
-	e1000_nvm_override_spi_small,
137
-	e1000_nvm_override_spi_large,
138
-};
139
-
140
-enum e1000_phy_type {
141
-	e1000_phy_unknown = 0,
142
-	e1000_phy_none,
143
-	e1000_phy_m88,
144
-	e1000_phy_igp,
145
-	e1000_phy_igp_2,
146
-	e1000_phy_gg82563,
147
-	e1000_phy_igp_3,
148
-	e1000_phy_ife,
149
-	e1000_phy_bm,
150
-	e1000_phy_82578,
151
-	e1000_phy_82577,
152
-	e1000_phy_82579,
153
-};
154
-
155
-enum e1000_bus_type {
156
-	e1000_bus_type_unknown = 0,
157
-	e1000_bus_type_pci,
158
-	e1000_bus_type_pcix,
159
-	e1000_bus_type_pci_express,
160
-	e1000_bus_type_reserved
161
-};
162
-
163
-enum e1000_bus_speed {
164
-	e1000_bus_speed_unknown = 0,
165
-	e1000_bus_speed_33,
166
-	e1000_bus_speed_66,
167
-	e1000_bus_speed_100,
168
-	e1000_bus_speed_120,
169
-	e1000_bus_speed_133,
170
-	e1000_bus_speed_2500,
171
-	e1000_bus_speed_5000,
172
-	e1000_bus_speed_reserved
173
-};
174
-
175
-enum e1000_bus_width {
176
-	e1000_bus_width_unknown = 0,
177
-	e1000_bus_width_pcie_x1,
178
-	e1000_bus_width_pcie_x2,
179
-	e1000_bus_width_pcie_x4 = 4,
180
-	e1000_bus_width_pcie_x8 = 8,
181
-	e1000_bus_width_32,
182
-	e1000_bus_width_64,
183
-	e1000_bus_width_reserved
184
-};
185
-
186
-enum e1000_1000t_rx_status {
187
-	e1000_1000t_rx_status_not_ok = 0,
188
-	e1000_1000t_rx_status_ok,
189
-	e1000_1000t_rx_status_undefined = 0xFF
190
-};
191
-
192
-enum e1000_rev_polarity {
193
-	e1000_rev_polarity_normal = 0,
194
-	e1000_rev_polarity_reversed,
195
-	e1000_rev_polarity_undefined = 0xFF
196
-};
197
-
198
-enum e1000_fc_mode {
199
-	e1000_fc_none = 0,
200
-	e1000_fc_rx_pause,
201
-	e1000_fc_tx_pause,
202
-	e1000_fc_full,
203
-	e1000_fc_default = 0xFF
204
-};
205
-
206
-enum e1000_ms_type {
207
-	e1000_ms_hw_default = 0,
208
-	e1000_ms_force_master,
209
-	e1000_ms_force_slave,
210
-	e1000_ms_auto
211
-};
212
-
213
-enum e1000_smart_speed {
214
-	e1000_smart_speed_default = 0,
215
-	e1000_smart_speed_on,
216
-	e1000_smart_speed_off
217
-};
218
-
219
-enum e1000_serdes_link_state {
220
-	e1000_serdes_link_down = 0,
221
-	e1000_serdes_link_autoneg_progress,
222
-	e1000_serdes_link_autoneg_complete,
223
-	e1000_serdes_link_forced_up
224
-};
225
-
226
-/* Receive Descriptor */
227
-struct e1000_rx_desc {
228
-	__le64 buffer_addr; /* Address of the descriptor's data buffer */
229
-	__le16 length;      /* Length of data DMAed into data buffer */
230
-	__le16 csum;        /* Packet checksum */
231
-	u8  status;         /* Descriptor status */
232
-	u8  errors;         /* Descriptor Errors */
233
-	__le16 special;
234
-};
235
-
236
-/* Receive Descriptor - Extended */
237
-union e1000_rx_desc_extended {
238
-	struct {
239
-		__le64 buffer_addr;
240
-		__le64 reserved;
241
-	} read;
242
-	struct {
243
-		struct {
244
-			__le32 mrq;           /* Multiple Rx Queues */
245
-			union {
246
-				__le32 rss;         /* RSS Hash */
247
-				struct {
248
-					__le16 ip_id;  /* IP id */
249
-					__le16 csum;   /* Packet Checksum */
250
-				} csum_ip;
251
-			} hi_dword;
252
-		} lower;
253
-		struct {
254
-			__le32 status_error;  /* ext status/error */
255
-			__le16 length;
256
-			__le16 vlan;          /* VLAN tag */
257
-		} upper;
258
-	} wb;  /* writeback */
259
-};
260
-
261
-#define MAX_PS_BUFFERS 4
262
-/* Receive Descriptor - Packet Split */
263
-union e1000_rx_desc_packet_split {
264
-	struct {
265
-		/* one buffer for protocol header(s), three data buffers */
266
-		__le64 buffer_addr[MAX_PS_BUFFERS];
267
-	} read;
268
-	struct {
269
-		struct {
270
-			__le32 mrq;           /* Multiple Rx Queues */
271
-			union {
272
-				__le32 rss;           /* RSS Hash */
273
-				struct {
274
-					__le16 ip_id;    /* IP id */
275
-					__le16 csum;     /* Packet Checksum */
276
-				} csum_ip;
277
-			} hi_dword;
278
-		} lower;
279
-		struct {
280
-			__le32 status_error;  /* ext status/error */
281
-			__le16 length0;       /* length of buffer 0 */
282
-			__le16 vlan;          /* VLAN tag */
283
-		} middle;
284
-		struct {
285
-			__le16 header_status;
286
-			__le16 length[3];     /* length of buffers 1-3 */
287
-		} upper;
288
-		__le64 reserved;
289
-	} wb; /* writeback */
290
-};
291
-
292
-/* Transmit Descriptor */
293
-struct e1000_tx_desc {
294
-	__le64 buffer_addr;   /* Address of the descriptor's data buffer */
295
-	union {
296
-		__le32 data;
297
-		struct {
298
-			__le16 length;    /* Data buffer length */
299
-			u8 cso;           /* Checksum offset */
300
-			u8 cmd;           /* Descriptor control */
301
-		} flags;
302
-	} lower;
303
-	union {
304
-		__le32 data;
305
-		struct {
306
-			u8 status;        /* Descriptor status */
307
-			u8 css;           /* Checksum start */
308
-			__le16 special;
309
-		} fields;
310
-	} upper;
311
-};
312
-
313
-/* Offload Context Descriptor */
314
-struct e1000_context_desc {
315
-	union {
316
-		__le32 ip_config;
317
-		struct {
318
-			u8 ipcss;         /* IP checksum start */
319
-			u8 ipcso;         /* IP checksum offset */
320
-			__le16 ipcse;     /* IP checksum end */
321
-		} ip_fields;
322
-	} lower_setup;
323
-	union {
324
-		__le32 tcp_config;
325
-		struct {
326
-			u8 tucss;         /* TCP checksum start */
327
-			u8 tucso;         /* TCP checksum offset */
328
-			__le16 tucse;     /* TCP checksum end */
329
-		} tcp_fields;
330
-	} upper_setup;
331
-	__le32 cmd_and_length;
332
-	union {
333
-		__le32 data;
334
-		struct {
335
-			u8 status;        /* Descriptor status */
336
-			u8 hdr_len;       /* Header length */
337
-			__le16 mss;       /* Maximum segment size */
338
-		} fields;
339
-	} tcp_seg_setup;
340
-};
341
-
342
-/* Offload data descriptor */
343
-struct e1000_data_desc {
344
-	__le64 buffer_addr;   /* Address of the descriptor's buffer address */
345
-	union {
346
-		__le32 data;
347
-		struct {
348
-			__le16 length;    /* Data buffer length */
349
-			u8 typ_len_ext;
350
-			u8 cmd;
351
-		} flags;
352
-	} lower;
353
-	union {
354
-		__le32 data;
355
-		struct {
356
-			u8 status;        /* Descriptor status */
357
-			u8 popts;         /* Packet Options */
358
-			__le16 special;
359
-		} fields;
360
-	} upper;
361
-};
362
-
363
-/* Statistics counters collected by the MAC */
364
-struct e1000_hw_stats {
365
-	u64 crcerrs;
366
-	u64 algnerrc;
367
-	u64 symerrs;
368
-	u64 rxerrc;
369
-	u64 mpc;
370
-	u64 scc;
371
-	u64 ecol;
372
-	u64 mcc;
373
-	u64 latecol;
374
-	u64 colc;
375
-	u64 dc;
376
-	u64 tncrs;
377
-	u64 sec;
378
-	u64 cexterr;
379
-	u64 rlec;
380
-	u64 xonrxc;
381
-	u64 xontxc;
382
-	u64 xoffrxc;
383
-	u64 xofftxc;
384
-	u64 fcruc;
385
-	u64 prc64;
386
-	u64 prc127;
387
-	u64 prc255;
388
-	u64 prc511;
389
-	u64 prc1023;
390
-	u64 prc1522;
391
-	u64 gprc;
392
-	u64 bprc;
393
-	u64 mprc;
394
-	u64 gptc;
395
-	u64 gorc;
396
-	u64 gotc;
397
-	u64 rnbc;
398
-	u64 ruc;
399
-	u64 rfc;
400
-	u64 roc;
401
-	u64 rjc;
402
-	u64 mgprc;
403
-	u64 mgpdc;
404
-	u64 mgptc;
405
-	u64 tor;
406
-	u64 tot;
407
-	u64 tpr;
408
-	u64 tpt;
409
-	u64 ptc64;
410
-	u64 ptc127;
411
-	u64 ptc255;
412
-	u64 ptc511;
413
-	u64 ptc1023;
414
-	u64 ptc1522;
415
-	u64 mptc;
416
-	u64 bptc;
417
-	u64 tsctc;
418
-	u64 tsctfc;
419
-	u64 iac;
420
-	u64 icrxptc;
421
-	u64 icrxatc;
422
-	u64 ictxptc;
423
-	u64 ictxatc;
424
-	u64 ictxqec;
425
-	u64 ictxqmtc;
426
-	u64 icrxdmtc;
427
-	u64 icrxoc;
428
-	u64 doosync;
429
-};
430
-
431
-
432
-struct e1000_phy_stats {
433
-	u32 idle_errors;
434
-	u32 receive_errors;
435
-};
436
-
437
-struct e1000_host_mng_dhcp_cookie {
438
-	u32 signature;
439
-	u8  status;
440
-	u8  reserved0;
441
-	u16 vlan_id;
442
-	u32 reserved1;
443
-	u16 reserved2;
444
-	u8  reserved3;
445
-	u8  checksum;
446
-};
447
-
448
-/* Host Interface "Rev 1" */
449
-struct e1000_host_command_header {
450
-	u8 command_id;
451
-	u8 command_length;
452
-	u8 command_options;
453
-	u8 checksum;
454
-};
455
-
456
-#define E1000_HI_MAX_DATA_LENGTH     252
457
-struct e1000_host_command_info {
458
-	struct e1000_host_command_header command_header;
459
-	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
460
-};
461
-
462
-/* Host Interface "Rev 2" */
463
-struct e1000_host_mng_command_header {
464
-	u8  command_id;
465
-	u8  checksum;
466
-	u16 reserved1;
467
-	u16 reserved2;
468
-	u16 command_length;
469
-};
470
-
471
-#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
472
-struct e1000_host_mng_command_info {
473
-	struct e1000_host_mng_command_header command_header;
474
-	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
475
-};
476
-
477
-#include "e1000e_mac.h"
478
-#include "e1000e_phy.h"
479
-#include "e1000e_nvm.h"
480
-#include "e1000e_manage.h"
481
-
482
-struct e1000_mac_operations {
483
-	/* Function pointers for the MAC. */
484
-	s32  (*init_params)(struct e1000_hw *);
485
-	s32  (*id_led_init)(struct e1000_hw *);
486
-	s32  (*blink_led)(struct e1000_hw *);
487
-	s32  (*check_for_link)(struct e1000_hw *);
488
-	bool (*check_mng_mode)(struct e1000_hw *hw);
489
-	s32  (*cleanup_led)(struct e1000_hw *);
490
-	void (*clear_hw_cntrs)(struct e1000_hw *);
491
-	void (*clear_vfta)(struct e1000_hw *);
492
-	s32  (*get_bus_info)(struct e1000_hw *);
493
-	void (*set_lan_id)(struct e1000_hw *);
494
-	s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
495
-	s32  (*led_on)(struct e1000_hw *);
496
-	s32  (*led_off)(struct e1000_hw *);
497
-	void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
498
-	s32  (*reset_hw)(struct e1000_hw *);
499
-	s32  (*init_hw)(struct e1000_hw *);
500
-	s32  (*setup_link)(struct e1000_hw *);
501
-	s32  (*setup_physical_interface)(struct e1000_hw *);
502
-	s32  (*setup_led)(struct e1000_hw *);
503
-	void (*write_vfta)(struct e1000_hw *, u32, u32);
504
-	void (*mta_set)(struct e1000_hw *, u32);
505
-	void (*config_collision_dist)(struct e1000_hw *);
506
-	void (*rar_set)(struct e1000_hw *, u8*, u32);
507
-	s32  (*read_mac_addr)(struct e1000_hw *);
508
-	s32  (*validate_mdi_setting)(struct e1000_hw *);
509
-	s32  (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
510
-	s32  (*mng_write_cmd_header)(struct e1000_hw *hw,
511
-                      struct e1000_host_mng_command_header*);
512
-	s32  (*mng_enable_host_if)(struct e1000_hw *);
513
-	s32  (*wait_autoneg)(struct e1000_hw *);
514
-};
515
-
516
-struct e1000_phy_operations {
517
-	s32  (*init_params)(struct e1000_hw *);
518
-	s32  (*acquire)(struct e1000_hw *);
519
-	s32  (*cfg_on_link_up)(struct e1000_hw *);
520
-	s32  (*check_polarity)(struct e1000_hw *);
521
-	s32  (*check_reset_block)(struct e1000_hw *);
522
-	s32  (*commit)(struct e1000_hw *);
523
-#if 0
524
-	s32  (*force_speed_duplex)(struct e1000_hw *);
525
-#endif
526
-	s32  (*get_cfg_done)(struct e1000_hw *hw);
527
-#if 0
528
-	s32  (*get_cable_length)(struct e1000_hw *);
529
-#endif
530
-	s32  (*get_info)(struct e1000_hw *);
531
-	s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
532
-	s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
533
-	void (*release)(struct e1000_hw *);
534
-	s32  (*reset)(struct e1000_hw *);
535
-	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
536
-	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
537
-	s32  (*write_reg)(struct e1000_hw *, u32, u16);
538
-	s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
539
-	void (*power_up)(struct e1000_hw *);
540
-	void (*power_down)(struct e1000_hw *);
541
-};
542
-
543
-struct e1000_nvm_operations {
544
-	s32  (*init_params)(struct e1000_hw *);
545
-	s32  (*acquire)(struct e1000_hw *);
546
-	s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
547
-	void (*release)(struct e1000_hw *);
548
-	void (*reload)(struct e1000_hw *);
549
-	s32  (*update)(struct e1000_hw *);
550
-	s32  (*valid_led_default)(struct e1000_hw *, u16 *);
551
-	s32  (*validate)(struct e1000_hw *);
552
-	s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
553
-};
554
-
555
-struct e1000_mac_info {
556
-	struct e1000_mac_operations ops;
557
-	u8 addr[6];
558
-	u8 perm_addr[6];
559
-
560
-	enum e1000_mac_type type;
561
-
562
-	u32 collision_delta;
563
-	u32 ledctl_default;
564
-	u32 ledctl_mode1;
565
-	u32 ledctl_mode2;
566
-	u32 mc_filter_type;
567
-	u32 tx_packet_delta;
568
-	u32 txcw;
569
-
570
-	u16 current_ifs_val;
571
-	u16 ifs_max_val;
572
-	u16 ifs_min_val;
573
-	u16 ifs_ratio;
574
-	u16 ifs_step_size;
575
-	u16 mta_reg_count;
576
-
577
-	/* Maximum size of the MTA register table in all supported adapters */
578
-	#define MAX_MTA_REG 128
579
-	u32 mta_shadow[MAX_MTA_REG];
580
-	u16 rar_entry_count;
581
-
582
-	u8  forced_speed_duplex;
583
-
584
-	bool adaptive_ifs;
585
-	bool arc_subsystem_valid;
586
-	bool asf_firmware_present;
587
-	bool autoneg;
588
-	bool autoneg_failed;
589
-	bool get_link_status;
590
-	bool in_ifs_mode;
591
-	enum e1000_serdes_link_state serdes_link_state;
592
-	bool serdes_has_link;
593
-	bool tx_pkt_filtering;
594
-};
595
-
596
-struct e1000_phy_info {
597
-	struct e1000_phy_operations ops;
598
-	enum e1000_phy_type type;
599
-
600
-	enum e1000_1000t_rx_status local_rx;
601
-	enum e1000_1000t_rx_status remote_rx;
602
-	enum e1000_ms_type ms_type;
603
-	enum e1000_ms_type original_ms_type;
604
-	enum e1000_rev_polarity cable_polarity;
605
-	enum e1000_smart_speed smart_speed;
606
-
607
-	u32 addr;
608
-	u32 id;
609
-	u32 reset_delay_us; /* in usec */
610
-	u32 revision;
611
-
612
-	enum e1000_media_type media_type;
613
-
614
-	u16 autoneg_advertised;
615
-	u16 autoneg_mask;
616
-	u16 cable_length;
617
-	u16 max_cable_length;
618
-	u16 min_cable_length;
619
-
620
-	u8 mdix;
621
-
622
-	bool disable_polarity_correction;
623
-	bool is_mdix;
624
-	bool polarity_correction;
625
-	bool reset_disable;
626
-	bool speed_downgraded;
627
-	bool autoneg_wait_to_complete;
628
-};
629
-
630
-struct e1000_nvm_info {
631
-	struct e1000_nvm_operations ops;
632
-	enum e1000_nvm_type type;
633
-	enum e1000_nvm_override override;
634
-
635
-	u32 flash_bank_size;
636
-	u32 flash_base_addr;
637
-
638
-	u16 word_size;
639
-	u16 delay_usec;
640
-	u16 address_bits;
641
-	u16 opcode_bits;
642
-	u16 page_size;
643
-};
644
-
645
-struct e1000_bus_info {
646
-	enum e1000_bus_type type;
647
-	enum e1000_bus_speed speed;
648
-	enum e1000_bus_width width;
649
-
650
-	u16 func;
651
-	u16 pci_cmd_word;
652
-};
653
-
654
-struct e1000_fc_info {
655
-	u32 high_water;          /* Flow control high-water mark */
656
-	u32 low_water;           /* Flow control low-water mark */
657
-	u16 pause_time;          /* Flow control pause timer */
658
-	bool send_xon;           /* Flow control send XON */
659
-	bool strict_ieee;        /* Strict IEEE mode */
660
-	enum e1000_fc_mode current_mode; /* FC mode in effect */
661
-	enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
662
-};
663
-
664
-struct e1000_dev_spec_82571 {
665
-	bool laa_is_present;
666
-	u32 smb_counter;
667
-};
668
-
669
-struct e1000_dev_spec_80003es2lan {
670
-	bool  mdic_wa_enable;
671
-};
672
-
673
-struct e1000_shadow_ram {
674
-	u16  value;
675
-	bool modified;
676
-};
677
-
678
-#define E1000_ICH8_SHADOW_RAM_WORDS		2048
679
-
680
-struct e1000_dev_spec_ich8lan {
681
-	bool kmrn_lock_loss_workaround_enabled;
682
-	struct e1000_shadow_ram shadow_ram[E1000_ICH8_SHADOW_RAM_WORDS];
683
-	bool nvm_k1_enabled;
684
-};
685
-
686
-struct e1000_hw {
687
-	struct e1000_adapter *adapter;
688
-
689
-	u8 __iomem *hw_addr;
690
-	u8 __iomem *flash_address;
691
-
692
-	void *back;
693
-	unsigned long io_base;
694
-
695
-	struct e1000_mac_info  mac;
696
-	struct e1000_fc_info   fc;
697
-	struct e1000_phy_info  phy;
698
-	struct e1000_nvm_info  nvm;
699
-	struct e1000_bus_info  bus;
700
-	struct e1000_host_mng_dhcp_cookie mng_cookie;
701
-
702
-	union {
703
-		struct e1000_dev_spec_82571	_82571;
704
-		struct e1000_dev_spec_80003es2lan _80003es2lan;
705
-		struct e1000_dev_spec_ich8lan	ich8lan;
706
-	} dev_spec;
707
-
708
-	u16 device_id;
709
-	u16 subsystem_vendor_id;
710
-	u16 subsystem_device_id;
711
-	u16 vendor_id;
712
-
713
-	u8  revision_id;
714
-};
715
-
716
-#include "e1000e_82571.h"
717
-#include "e1000e_80003es2lan.h"
718
-#include "e1000e_ich8lan.h"
719
-
720
-/* These functions must be implemented by drivers */
721
-s32  e1000e_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
722
-
723
-#endif

+ 0
- 3465
src/drivers/net/e1000e/e1000e_ich8lan.c
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Прегледај датотеку


+ 0
- 199
src/drivers/net/e1000e/e1000e_ich8lan.h Прегледај датотеку

@@ -1,199 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2009 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-#ifndef _E1000E_ICH8LAN_H_
32
-#define _E1000E_ICH8LAN_H_
33
-
34
-#define ICH_FLASH_GFPREG                 0x0000
35
-#define ICH_FLASH_HSFSTS                 0x0004
36
-#define ICH_FLASH_HSFCTL                 0x0006
37
-#define ICH_FLASH_FADDR                  0x0008
38
-#define ICH_FLASH_FDATA0                 0x0010
39
-
40
-/* Requires up to 10 seconds when MNG might be accessing part. */
41
-#define ICH_FLASH_READ_COMMAND_TIMEOUT   10000000
42
-#define ICH_FLASH_WRITE_COMMAND_TIMEOUT  10000000
43
-#define ICH_FLASH_ERASE_COMMAND_TIMEOUT  10000000
44
-#define ICH_FLASH_LINEAR_ADDR_MASK       0x00FFFFFF
45
-#define ICH_FLASH_CYCLE_REPEAT_COUNT     10
46
-
47
-#define ICH_CYCLE_READ                   0
48
-#define ICH_CYCLE_WRITE                  2
49
-#define ICH_CYCLE_ERASE                  3
50
-
51
-#define FLASH_GFPREG_BASE_MASK           0x1FFF
52
-#define FLASH_SECTOR_ADDR_SHIFT          12
53
-
54
-#define ICH_FLASH_SEG_SIZE_256           256
55
-#define ICH_FLASH_SEG_SIZE_4K            4096
56
-#define ICH_FLASH_SEG_SIZE_8K            8192
57
-#define ICH_FLASH_SEG_SIZE_64K           65536
58
-#define ICH_FLASH_SECTOR_SIZE            4096
59
-
60
-#define ICH_FLASH_REG_MAPSIZE            0x00A0
61
-
62
-#define E1000_ICH_FWSM_RSPCIPHY          0x00000040 /* Reset PHY on PCI Reset */
63
-#define E1000_ICH_FWSM_DISSW             0x10000000 /* FW Disables SW Writes */
64
-/* FW established a valid mode */
65
-#define E1000_ICH_FWSM_FW_VALID          0x00008000
66
-
67
-#define E1000_ICH_MNG_IAMT_MODE          0x2
68
-
69
-#define ID_LED_DEFAULT_ICH8LAN  ((ID_LED_DEF1_DEF2 << 12) | \
70
-                                 (ID_LED_OFF1_OFF2 <<  8) | \
71
-                                 (ID_LED_OFF1_ON2  <<  4) | \
72
-                                 (ID_LED_DEF1_DEF2))
73
-
74
-#define E1000_ICH_NVM_SIG_WORD           0x13
75
-#define E1000_ICH_NVM_SIG_MASK           0xC000
76
-#define E1000_ICH_NVM_VALID_SIG_MASK     0xC0
77
-#define E1000_ICH_NVM_SIG_VALUE          0x80
78
-
79
-#define E1000_ICH8_LAN_INIT_TIMEOUT      1500
80
-
81
-#define E1000_FEXTNVM_SW_CONFIG        1
82
-#define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M */
83
-
84
-#define PCIE_ICH8_SNOOP_ALL   PCIE_NO_SNOOP_ALL
85
-
86
-#define E1000_ICH_RAR_ENTRIES            7
87
-
88
-#define PHY_PAGE_SHIFT 5
89
-#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \
90
-                           ((reg) & MAX_PHY_REG_ADDRESS))
91
-#define IGP3_KMRN_DIAG  PHY_REG(770, 19) /* KMRN Diagnostic */
92
-#define IGP3_VR_CTRL    PHY_REG(776, 18) /* Voltage Regulator Control */
93
-#define IGP3_CAPABILITY PHY_REG(776, 19) /* Capability */
94
-#define IGP3_PM_CTRL    PHY_REG(769, 20) /* Power Management Control */
95
-
96
-#define IGP3_KMRN_DIAG_PCS_LOCK_LOSS         0x0002
97
-#define IGP3_VR_CTRL_DEV_POWERDOWN_MODE_MASK 0x0300
98
-#define IGP3_VR_CTRL_MODE_SHUTDOWN           0x0200
99
-#define IGP3_PM_CTRL_FORCE_PWR_DOWN          0x0020
100
-
101
-/* PHY Wakeup Registers and defines */
102
-#define BM_RCTL         PHY_REG(BM_WUC_PAGE, 0)
103
-#define BM_WUC          PHY_REG(BM_WUC_PAGE, 1)
104
-#define BM_WUFC         PHY_REG(BM_WUC_PAGE, 2)
105
-#define BM_WUS          PHY_REG(BM_WUC_PAGE, 3)
106
-#define BM_RAR_L(_i)    (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
107
-#define BM_RAR_M(_i)    (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
108
-#define BM_RAR_H(_i)    (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
109
-#define BM_RAR_CTRL(_i) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
110
-#define BM_MTA(_i)      (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
111
-
112
-#define BM_RCTL_UPE           0x0001          /* Unicast Promiscuous Mode */
113
-#define BM_RCTL_MPE           0x0002          /* Multicast Promiscuous Mode */
114
-#define BM_RCTL_MO_SHIFT      3               /* Multicast Offset Shift */
115
-#define BM_RCTL_MO_MASK       (3 << 3)        /* Multicast Offset Mask */
116
-#define BM_RCTL_BAM           0x0020          /* Broadcast Accept Mode */
117
-#define BM_RCTL_PMCF          0x0040          /* Pass MAC Control Frames */
118
-#define BM_RCTL_RFCE          0x0080          /* Rx Flow Control Enable */
119
-
120
-#define HV_LED_CONFIG		PHY_REG(768, 30) /* LED Configuration */
121
-#define HV_MUX_DATA_CTRL               PHY_REG(776, 16)
122
-#define HV_MUX_DATA_CTRL_GEN_TO_MAC    0x0400
123
-#define HV_MUX_DATA_CTRL_FORCE_SPEED   0x0004
124
-#define HV_SCC_UPPER		PHY_REG(778, 16) /* Single Collision Count */
125
-#define HV_SCC_LOWER		PHY_REG(778, 17)
126
-#define HV_ECOL_UPPER		PHY_REG(778, 18) /* Excessive Collision Count */
127
-#define HV_ECOL_LOWER		PHY_REG(778, 19)
128
-#define HV_MCC_UPPER		PHY_REG(778, 20) /* Multiple Collision Count */
129
-#define HV_MCC_LOWER		PHY_REG(778, 21)
130
-#define HV_LATECOL_UPPER	PHY_REG(778, 23) /* Late Collision Count */
131
-#define HV_LATECOL_LOWER	PHY_REG(778, 24)
132
-#define HV_COLC_UPPER		PHY_REG(778, 25) /* Collision Count */
133
-#define HV_COLC_LOWER		PHY_REG(778, 26)
134
-#define HV_DC_UPPER		PHY_REG(778, 27) /* Defer Count */
135
-#define HV_DC_LOWER		PHY_REG(778, 28)
136
-#define HV_TNCRS_UPPER		PHY_REG(778, 29) /* Transmit with no CRS */
137
-#define HV_TNCRS_LOWER		PHY_REG(778, 30)
138
-
139
-#define E1000_FCRTV_PCH     0x05F40 /* PCH Flow Control Refresh Timer Value */
140
-
141
-#define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */
142
-#define E1000_NVM_K1_ENABLE 0x1  /* NVM Enable K1 bit */
143
-
144
-/* SMBus Address Phy Register */
145
-#define HV_SMB_ADDR            PHY_REG(768, 26)
146
-#define HV_SMB_ADDR_PEC_EN     0x0200
147
-#define HV_SMB_ADDR_VALID      0x0080
148
-
149
-/* PHY Power Management Control */
150
-#define HV_PM_CTRL             PHY_REG(770, 17)
151
-
152
-/* Strapping Option Register - RO */
153
-#define E1000_STRAP                     0x0000C
154
-#define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000
155
-#define E1000_STRAP_SMBUS_ADDRESS_SHIFT 17
156
-
157
-/* OEM Bits Phy Register */
158
-#define HV_OEM_BITS            PHY_REG(768, 25)
159
-#define HV_OEM_BITS_LPLU       0x0004 /* Low Power Link Up */
160
-#define HV_OEM_BITS_GBE_DIS    0x0040 /* Gigabit Disable */
161
-#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
162
-
163
-#define LCD_CFG_PHY_ADDR_BIT   0x0020 /* Phy address bit from LCD Config word */
164
-
165
-#define SW_FLAG_TIMEOUT    1000 /* SW Semaphore flag timeout in milliseconds */
166
-
167
-/*
168
- * Additional interrupts need to be handled for ICH family:
169
- *  DSW = The FW changed the status of the DISSW bit in FWSM
170
- *  PHYINT = The LAN connected device generates an interrupt
171
- *  EPRST = Manageability reset event
172
- */
173
-#define IMS_ICH_ENABLE_MASK (\
174
-    E1000_IMS_DSW   | \
175
-    E1000_IMS_PHYINT | \
176
-    E1000_IMS_EPRST)
177
-
178
-/* Additional interrupt register bit definitions */
179
-#define E1000_ICR_LSECPNC       0x00004000          /* PN threshold - client */
180
-#define E1000_IMS_LSECPNC       E1000_ICR_LSECPNC   /* PN threshold - client */
181
-#define E1000_ICS_LSECPNC       E1000_ICR_LSECPNC   /* PN threshold - client */
182
-
183
-/* Security Processing bit Indication */
184
-#define E1000_RXDEXT_LINKSEC_STATUS_LSECH       0x01000000
185
-#define E1000_RXDEXT_LINKSEC_ERROR_BIT_MASK     0x60000000
186
-#define E1000_RXDEXT_LINKSEC_ERROR_NO_SA_MATCH  0x20000000
187
-#define E1000_RXDEXT_LINKSEC_ERROR_REPLAY_ERROR 0x40000000
188
-#define E1000_RXDEXT_LINKSEC_ERROR_BAD_SIG      0x60000000
189
-
190
-
191
-void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
192
-                                                 bool state);
193
-void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
194
-void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
195
-void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw);
196
-s32 e1000e_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable);
197
-s32 e1000e_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_config);
198
-
199
-#endif

+ 0
- 1883
src/drivers/net/e1000e/e1000e_mac.c
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Прегледај датотеку


+ 0
- 79
src/drivers/net/e1000e/e1000e_mac.h Прегледај датотеку

@@ -1,79 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2009 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-#ifndef _E1000E_MAC_H_
32
-#define _E1000E_MAC_H_
33
-
34
-/*
35
- * Functions that should not be called directly from drivers but can be used
36
- * by other files in this 'shared code'
37
- */
38
-void e1000e_init_mac_ops_generic(struct e1000_hw *hw);
39
-s32  e1000e_blink_led(struct e1000_hw *hw);
40
-s32  e1000e_check_for_copper_link(struct e1000_hw *hw);
41
-s32  e1000e_check_for_fiber_link(struct e1000_hw *hw);
42
-s32  e1000e_check_for_serdes_link(struct e1000_hw *hw);
43
-s32  e1000e_cleanup_led_generic(struct e1000_hw *hw);
44
-s32  e1000e_config_fc_after_link_up(struct e1000_hw *hw);
45
-s32  e1000e_disable_pcie_master(struct e1000_hw *hw);
46
-s32  e1000e_force_mac_fc(struct e1000_hw *hw);
47
-s32  e1000e_get_auto_rd_done(struct e1000_hw *hw);
48
-s32  e1000e_get_bus_info_pcie(struct e1000_hw *hw);
49
-void e1000e_set_lan_id_single_port(struct e1000_hw *hw);
50
-s32  e1000e_get_hw_semaphore(struct e1000_hw *hw);
51
-s32  e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
52
-                                               u16 *duplex);
53
-s32  e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw,
54
-                                                     u16 *speed, u16 *duplex);
55
-s32  e1000e_id_led_init(struct e1000_hw *hw);
56
-s32  e1000e_led_on_generic(struct e1000_hw *hw);
57
-s32  e1000e_led_off_generic(struct e1000_hw *hw);
58
-void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
59
-	                               u8 *mc_addr_list, u32 mc_addr_count);
60
-s32  e1000e_set_fc_watermarks(struct e1000_hw *hw);
61
-s32  e1000e_setup_fiber_serdes_link(struct e1000_hw *hw);
62
-s32  e1000e_setup_led_generic(struct e1000_hw *hw);
63
-s32  e1000e_setup_link(struct e1000_hw *hw);
64
-
65
-void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw);
66
-void e1000e_clear_vfta_generic(struct e1000_hw *hw);
67
-void e1000e_config_collision_dist(struct e1000_hw *hw);
68
-void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count);
69
-void e1000e_mta_set_generic(struct e1000_hw *hw, u32 hash_value);
70
-void e1000e_pcix_mmrbc_workaround_generic(struct e1000_hw *hw);
71
-void e1000e_put_hw_semaphore(struct e1000_hw *hw);
72
-void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
73
-s32  e1000e_check_alt_mac_addr_generic(struct e1000_hw *hw);
74
-void e1000e_reset_adaptive(struct e1000_hw *hw);
75
-void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop);
76
-void e1000e_update_adaptive(struct e1000_hw *hw);
77
-void e1000e_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
78
-
79
-#endif

+ 0
- 1282
src/drivers/net/e1000e/e1000e_main.c
Разлика између датотеке није приказан због своје велике величине
Прегледај датотеку


+ 0
- 372
src/drivers/net/e1000e/e1000e_manage.c Прегледај датотеку

@@ -1,372 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2009 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-#if 0
32
-
33
-#include "e1000e.h"
34
-
35
-static u8 e1000e_calculate_checksum(u8 *buffer, u32 length);
36
-
37
-/**
38
- *  e1000e_calculate_checksum - Calculate checksum for buffer
39
- *  @buffer: pointer to EEPROM
40
- *  @length: size of EEPROM to calculate a checksum for
41
- *
42
- *  Calculates the checksum for some buffer on a specified length.  The
43
- *  checksum calculated is returned.
44
- **/
45
-static u8 e1000e_calculate_checksum(u8 *buffer, u32 length)
46
-{
47
-	u32 i;
48
-	u8  sum = 0;
49
-
50
-	if (!buffer)
51
-		return 0;
52
-	for (i = 0; i < length; i++)
53
-		sum += buffer[i];
54
-
55
-	return (u8) (0 - sum);
56
-}
57
-
58
-/**
59
- *  e1000e_mng_enable_host_if_generic - Checks host interface is enabled
60
- *  @hw: pointer to the HW structure
61
- *
62
- *  Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
63
- *
64
- *  This function checks whether the HOST IF is enabled for command operation
65
- *  and also checks whether the previous command is completed.  It busy waits
66
- *  in case of previous command is not completed.
67
- **/
68
-s32 e1000e_mng_enable_host_if_generic(struct e1000_hw *hw)
69
-{
70
-	u32 hicr;
71
-	s32 ret_val = E1000_SUCCESS;
72
-	u8  i;
73
-
74
-	/* Check that the host interface is enabled. */
75
-	hicr = er32(HICR);
76
-	if ((hicr & E1000_HICR_EN) == 0) {
77
-		e_dbg("E1000_HOST_EN bit disabled.\n");
78
-		ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
79
-		goto out;
80
-	}
81
-	/* check the previous command is completed */
82
-	for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
83
-		hicr = er32(HICR);
84
-		if (!(hicr & E1000_HICR_C))
85
-			break;
86
-		mdelay(1);
87
-	}
88
-
89
-	if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
90
-		e_dbg("Previous command timeout failed .\n");
91
-		ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
92
-		goto out;
93
-	}
94
-
95
-out:
96
-	return ret_val;
97
-}
98
-
99
-/**
100
- *  e1000e_check_mng_mode_generic - Generic check management mode
101
- *  @hw: pointer to the HW structure
102
- *
103
- *  Reads the firmware semaphore register and returns true (>0) if
104
- *  manageability is enabled, else false (0).
105
- **/
106
-bool e1000e_check_mng_mode_generic(struct e1000_hw *hw)
107
-{
108
-	u32 fwsm;
109
-
110
-	fwsm = er32(FWSM);
111
-	return (fwsm & E1000_FWSM_MODE_MASK) ==
112
-	        (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
113
-}
114
-
115
-/**
116
- *  e1000e_enable_tx_pkt_filtering - Enable packet filtering on TX
117
- *  @hw: pointer to the HW structure
118
- *
119
- *  Enables packet filtering on transmit packets if manageability is enabled
120
- *  and host interface is enabled.
121
- **/
122
-bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw)
123
-{
124
-	struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
125
-	u32 *buffer = (u32 *)&hw->mng_cookie;
126
-	u32 offset;
127
-	s32 ret_val, hdr_csum, csum;
128
-	u8 i, len;
129
-	bool tx_filter = true;
130
-
131
-	/* No manageability, no filtering */
132
-	if (!hw->mac.ops.check_mng_mode(hw)) {
133
-		tx_filter = false;
134
-		goto out;
135
-	}
136
-
137
-	/*
138
-	 * If we can't read from the host interface for whatever
139
-	 * reason, disable filtering.
140
-	 */
141
-	ret_val = hw->mac.ops.mng_enable_host_if(hw);
142
-	if (ret_val != E1000_SUCCESS) {
143
-		tx_filter = false;
144
-		goto out;
145
-	}
146
-
147
-	/* Read in the header.  Length and offset are in dwords. */
148
-	len    = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
149
-	offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
150
-	for (i = 0; i < len; i++) {
151
-		*(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw,
152
-		                                           E1000_HOST_IF,
153
-		                                           offset + i);
154
-	}
155
-	hdr_csum = hdr->checksum;
156
-	hdr->checksum = 0;
157
-	csum = e1000e_calculate_checksum((u8 *)hdr,
158
-	                                E1000_MNG_DHCP_COOKIE_LENGTH);
159
-	/*
160
-	 * If either the checksums or signature don't match, then
161
-	 * the cookie area isn't considered valid, in which case we
162
-	 * take the safe route of assuming Tx filtering is enabled.
163
-	 */
164
-	if (hdr_csum != csum)
165
-		goto out;
166
-	if (hdr->signature != E1000_IAMT_SIGNATURE)
167
-		goto out;
168
-
169
-	/* Cookie area is valid, make the final check for filtering. */
170
-	if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))
171
-		tx_filter = false;
172
-
173
-out:
174
-	hw->mac.tx_pkt_filtering = tx_filter;
175
-	return tx_filter;
176
-}
177
-
178
-/**
179
- *  e1000e_mng_write_dhcp_info - Writes DHCP info to host interface
180
- *  @hw: pointer to the HW structure
181
- *  @buffer: pointer to the host interface
182
- *  @length: size of the buffer
183
- *
184
- *  Writes the DHCP information to the host interface.
185
- **/
186
-s32 e1000e_mng_write_dhcp_info(struct e1000_hw *hw, u8 *buffer,
187
-                                      u16 length)
188
-{
189
-	struct e1000_host_mng_command_header hdr;
190
-	s32 ret_val;
191
-	u32 hicr;
192
-
193
-	hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
194
-	hdr.command_length = length;
195
-	hdr.reserved1 = 0;
196
-	hdr.reserved2 = 0;
197
-	hdr.checksum = 0;
198
-
199
-	/* Enable the host interface */
200
-	ret_val = hw->mac.ops.mng_enable_host_if(hw);
201
-	if (ret_val)
202
-		goto out;
203
-
204
-	/* Populate the host interface with the contents of "buffer". */
205
-	ret_val = hw->mac.ops.mng_host_if_write(hw, buffer, length,
206
-	                                  sizeof(hdr), &(hdr.checksum));
207
-	if (ret_val)
208
-		goto out;
209
-
210
-	/* Write the manageability command header */
211
-	ret_val = hw->mac.ops.mng_write_cmd_header(hw, &hdr);
212
-	if (ret_val)
213
-		goto out;
214
-
215
-	/* Tell the ARC a new command is pending. */
216
-	hicr = er32(HICR);
217
-	ew32(HICR, hicr | E1000_HICR_C);
218
-
219
-out:
220
-	return ret_val;
221
-}
222
-
223
-/**
224
- *  e1000e_mng_write_cmd_header_generic - Writes manageability command header
225
- *  @hw: pointer to the HW structure
226
- *  @hdr: pointer to the host interface command header
227
- *
228
- *  Writes the command header after does the checksum calculation.
229
- **/
230
-s32 e1000e_mng_write_cmd_header_generic(struct e1000_hw *hw,
231
-                                    struct e1000_host_mng_command_header *hdr)
232
-{
233
-	u16 i, length = sizeof(struct e1000_host_mng_command_header);
234
-
235
-	/* Write the whole command header structure with new checksum. */
236
-
237
-	hdr->checksum = e1000e_calculate_checksum((u8 *)hdr, length);
238
-
239
-	length >>= 2;
240
-	/* Write the relevant command block into the ram area. */
241
-	for (i = 0; i < length; i++) {
242
-		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
243
-		                            *((u32 *) hdr + i));
244
-		e1e_flush();
245
-	}
246
-
247
-	return E1000_SUCCESS;
248
-}
249
-
250
-/**
251
- *  e1000e_mng_host_if_write_generic - Write to the manageability host interface
252
- *  @hw: pointer to the HW structure
253
- *  @buffer: pointer to the host interface buffer
254
- *  @length: size of the buffer
255
- *  @offset: location in the buffer to write to
256
- *  @sum: sum of the data (not checksum)
257
- *
258
- *  This function writes the buffer content at the offset given on the host if.
259
- *  It also does alignment considerations to do the writes in most efficient
260
- *  way.  Also fills up the sum of the buffer in *buffer parameter.
261
- **/
262
-s32 e1000e_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
263
-                                    u16 length, u16 offset, u8 *sum)
264
-{
265
-	u8 *tmp;
266
-	u8 *bufptr = buffer;
267
-	u32 data = 0;
268
-	s32 ret_val = E1000_SUCCESS;
269
-	u16 remaining, i, j, prev_bytes;
270
-
271
-	/* sum = only sum of the data and it is not checksum */
272
-
273
-	if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
274
-		ret_val = -E1000_ERR_PARAM;
275
-		goto out;
276
-	}
277
-
278
-	tmp = (u8 *)&data;
279
-	prev_bytes = offset & 0x3;
280
-	offset >>= 2;
281
-
282
-	if (prev_bytes) {
283
-		data = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset);
284
-		for (j = prev_bytes; j < sizeof(u32); j++) {
285
-			*(tmp + j) = *bufptr++;
286
-			*sum += *(tmp + j);
287
-		}
288
-		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset, data);
289
-		length -= j - prev_bytes;
290
-		offset++;
291
-	}
292
-
293
-	remaining = length & 0x3;
294
-	length -= remaining;
295
-
296
-	/* Calculate length in DWORDs */
297
-	length >>= 2;
298
-
299
-	/*
300
-	 * The device driver writes the relevant command block into the
301
-	 * ram area.
302
-	 */
303
-	for (i = 0; i < length; i++) {
304
-		for (j = 0; j < sizeof(u32); j++) {
305
-			*(tmp + j) = *bufptr++;
306
-			*sum += *(tmp + j);
307
-		}
308
-
309
-		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
310
-		                            data);
311
-	}
312
-	if (remaining) {
313
-		for (j = 0; j < sizeof(u32); j++) {
314
-			if (j < remaining)
315
-				*(tmp + j) = *bufptr++;
316
-			else
317
-				*(tmp + j) = 0;
318
-
319
-			*sum += *(tmp + j);
320
-		}
321
-		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i, data);
322
-	}
323
-
324
-out:
325
-	return ret_val;
326
-}
327
-
328
-/**
329
- *  e1000e_enable_mng_pass_thru - Enable processing of ARP's
330
- *  @hw: pointer to the HW structure
331
- *
332
- *  Verifies the hardware needs to allow ARPs to be processed by the host.
333
- **/
334
-bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw)
335
-{
336
-	u32 manc;
337
-	u32 fwsm, factps;
338
-	bool ret_val = false;
339
-
340
-	if (!hw->mac.asf_firmware_present)
341
-		goto out;
342
-
343
-	manc = er32(MANC);
344
-
345
-	if (!(manc & E1000_MANC_RCV_TCO_EN) ||
346
-	    !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
347
-		goto out;
348
-
349
-	if (hw->mac.arc_subsystem_valid) {
350
-		fwsm = er32(FWSM);
351
-		factps = er32(FACTPS);
352
-
353
-		if (!(factps & E1000_FACTPS_MNGCG) &&
354
-		    ((fwsm & E1000_FWSM_MODE_MASK) ==
355
-		     (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
356
-			ret_val = true;
357
-			goto out;
358
-		}
359
-	} else {
360
-		if ((manc & E1000_MANC_SMBUS_EN) &&
361
-		    !(manc & E1000_MANC_ASF_EN)) {
362
-			ret_val = true;
363
-			goto out;
364
-		}
365
-	}
366
-
367
-out:
368
-	return ret_val;
369
-}
370
-
371
-#endif
372
-

+ 0
- 86
src/drivers/net/e1000e/e1000e_manage.h Прегледај датотеку

@@ -1,86 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2009 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-#ifndef _E1000E_MANAGE_H_
32
-#define _E1000E_MANAGE_H_
33
-
34
-bool e1000e_check_mng_mode_generic(struct e1000_hw *hw);
35
-bool e1000e_enable_tx_pkt_filtering(struct e1000_hw *hw);
36
-s32  e1000e_mng_enable_host_if_generic(struct e1000_hw *hw);
37
-s32  e1000e_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
38
-                                     u16 length, u16 offset, u8 *sum);
39
-s32  e1000e_mng_write_cmd_header_generic(struct e1000_hw *hw,
40
-                                    struct e1000_host_mng_command_header *hdr);
41
-#if 0
42
-s32  e1000e_mng_write_dhcp_info(struct e1000_hw *hw,
43
-                                       u8 *buffer, u16 length);
44
-#endif
45
-bool e1000e_enable_mng_pass_thru(struct e1000_hw *hw);
46
-
47
-enum e1000_mng_mode {
48
-	e1000_mng_mode_none = 0,
49
-	e1000_mng_mode_asf,
50
-	e1000_mng_mode_pt,
51
-	e1000_mng_mode_ipmi,
52
-	e1000_mng_mode_host_if_only
53
-};
54
-
55
-#define E1000_FACTPS_MNGCG    0x20000000
56
-
57
-#define E1000_FWSM_MODE_MASK  0xE
58
-#define E1000_FWSM_MODE_SHIFT 1
59
-
60
-#define E1000_MNG_IAMT_MODE                  0x3
61
-#define E1000_MNG_DHCP_COOKIE_LENGTH         0x10
62
-#define E1000_MNG_DHCP_COOKIE_OFFSET         0x6F0
63
-#define E1000_MNG_DHCP_COMMAND_TIMEOUT       10
64
-#define E1000_MNG_DHCP_TX_PAYLOAD_CMD        64
65
-#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
66
-#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN    0x2
67
-
68
-#define E1000_VFTA_ENTRY_SHIFT               5
69
-#define E1000_VFTA_ENTRY_MASK                0x7F
70
-#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK      0x1F
71
-
72
-#define E1000_HI_MAX_BLOCK_BYTE_LENGTH       1792 /* Num of bytes in range */
73
-#define E1000_HI_MAX_BLOCK_DWORD_LENGTH      448 /* Num of dwords in range */
74
-#define E1000_HI_COMMAND_TIMEOUT             500 /* Process HI command limit */
75
-
76
-#define E1000_HICR_EN              0x01  /* Enable bit - RO */
77
-/* Driver sets this bit when done to put command in RAM */
78
-#define E1000_HICR_C               0x02
79
-#define E1000_HICR_SV              0x04  /* Status Validity */
80
-#define E1000_HICR_FW_RESET_ENABLE 0x40
81
-#define E1000_HICR_FW_RESET        0x80
82
-
83
-/* Intel(R) Active Management Technology signature */
84
-#define E1000_IAMT_SIGNATURE  0x544D4149
85
-
86
-#endif

+ 0
- 596
src/drivers/net/e1000e/e1000e_nvm.c Прегледај датотеку

@@ -1,596 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2009 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-#include "e1000e.h"
32
-
33
-static void e1000e_stop_nvm(struct e1000_hw *hw);
34
-static void e1000e_reload_nvm(struct e1000_hw *hw);
35
-
36
-/**
37
- *  e1000e_init_nvm_ops_generic - Initialize NVM function pointers
38
- *  @hw: pointer to the HW structure
39
- *
40
- *  Setups up the function pointers to no-op functions
41
- **/
42
-void e1000e_init_nvm_ops_generic(struct e1000_hw *hw)
43
-{
44
-	struct e1000_nvm_info *nvm = &hw->nvm;
45
-	/* Initialize function pointers */
46
-	nvm->ops.reload = e1000e_reload_nvm;
47
-}
48
-
49
-/**
50
- *  e1000e_raise_eec_clk - Raise EEPROM clock
51
- *  @hw: pointer to the HW structure
52
- *  @eecd: pointer to the EEPROM
53
- *
54
- *  Enable/Raise the EEPROM clock bit.
55
- **/
56
-static void e1000e_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
57
-{
58
-	*eecd = *eecd | E1000_EECD_SK;
59
-	ew32(EECD, *eecd);
60
-	e1e_flush();
61
-	udelay(hw->nvm.delay_usec);
62
-}
63
-
64
-/**
65
- *  e1000e_lower_eec_clk - Lower EEPROM clock
66
- *  @hw: pointer to the HW structure
67
- *  @eecd: pointer to the EEPROM
68
- *
69
- *  Clear/Lower the EEPROM clock bit.
70
- **/
71
-static void e1000e_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
72
-{
73
-	*eecd = *eecd & ~E1000_EECD_SK;
74
-	ew32(EECD, *eecd);
75
-	e1e_flush();
76
-	udelay(hw->nvm.delay_usec);
77
-}
78
-
79
-/**
80
- *  e1000e_shift_out_eec_bits - Shift data bits our to the EEPROM
81
- *  @hw: pointer to the HW structure
82
- *  @data: data to send to the EEPROM
83
- *  @count: number of bits to shift out
84
- *
85
- *  We need to shift 'count' bits out to the EEPROM.  So, the value in the
86
- *  "data" parameter will be shifted out to the EEPROM one bit at a time.
87
- *  In order to do this, "data" must be broken down into bits.
88
- **/
89
-static void e1000e_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
90
-{
91
-	struct e1000_nvm_info *nvm = &hw->nvm;
92
-	u32 eecd = er32(EECD);
93
-	u32 mask;
94
-
95
-	mask = 0x01 << (count - 1);
96
-	if (nvm->type == e1000_nvm_eeprom_spi)
97
-		eecd |= E1000_EECD_DO;
98
-
99
-	do {
100
-		eecd &= ~E1000_EECD_DI;
101
-
102
-		if (data & mask)
103
-			eecd |= E1000_EECD_DI;
104
-
105
-		ew32(EECD, eecd);
106
-		e1e_flush();
107
-
108
-		udelay(nvm->delay_usec);
109
-
110
-		e1000e_raise_eec_clk(hw, &eecd);
111
-		e1000e_lower_eec_clk(hw, &eecd);
112
-
113
-		mask >>= 1;
114
-	} while (mask);
115
-
116
-	eecd &= ~E1000_EECD_DI;
117
-	ew32(EECD, eecd);
118
-}
119
-
120
-/**
121
- *  e1000e_shift_in_eec_bits - Shift data bits in from the EEPROM
122
- *  @hw: pointer to the HW structure
123
- *  @count: number of bits to shift in
124
- *
125
- *  In order to read a register from the EEPROM, we need to shift 'count' bits
126
- *  in from the EEPROM.  Bits are "shifted in" by raising the clock input to
127
- *  the EEPROM (setting the SK bit), and then reading the value of the data out
128
- *  "DO" bit.  During this "shifting in" process the data in "DI" bit should
129
- *  always be clear.
130
- **/
131
-static u16 e1000e_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
132
-{
133
-	u32 eecd;
134
-	u32 i;
135
-	u16 data;
136
-
137
-	eecd = er32(EECD);
138
-	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
139
-	data = 0;
140
-
141
-	for (i = 0; i < count; i++) {
142
-		data <<= 1;
143
-		e1000e_raise_eec_clk(hw, &eecd);
144
-
145
-		eecd = er32(EECD);
146
-
147
-		eecd &= ~E1000_EECD_DI;
148
-		if (eecd & E1000_EECD_DO)
149
-			data |= 1;
150
-
151
-		e1000e_lower_eec_clk(hw, &eecd);
152
-	}
153
-
154
-	return data;
155
-}
156
-
157
-/**
158
- *  e1000e_poll_eerd_eewr_done - Poll for EEPROM read/write completion
159
- *  @hw: pointer to the HW structure
160
- *  @ee_reg: EEPROM flag for polling
161
- *
162
- *  Polls the EEPROM status bit for either read or write completion based
163
- *  upon the value of 'ee_reg'.
164
- **/
165
-s32 e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
166
-{
167
-	u32 attempts = 100000;
168
-	u32 i, reg = 0;
169
-	s32 ret_val = -E1000_ERR_NVM;
170
-
171
-	for (i = 0; i < attempts; i++) {
172
-		if (ee_reg == E1000_NVM_POLL_READ)
173
-			reg = er32(EERD);
174
-		else
175
-			reg = er32(EEWR);
176
-
177
-		if (reg & E1000_NVM_RW_REG_DONE) {
178
-			ret_val = E1000_SUCCESS;
179
-			break;
180
-		}
181
-
182
-		udelay(5);
183
-	}
184
-
185
-	return ret_val;
186
-}
187
-
188
-/**
189
- *  e1000e_acquire_nvm - Generic request for access to EEPROM
190
- *  @hw: pointer to the HW structure
191
- *
192
- *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
193
- *  Return successful if access grant bit set, else clear the request for
194
- *  EEPROM access and return -E1000_ERR_NVM (-1).
195
- **/
196
-s32 e1000e_acquire_nvm(struct e1000_hw *hw)
197
-{
198
-	u32 eecd = er32(EECD);
199
-	s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
200
-	s32 ret_val = E1000_SUCCESS;
201
-
202
-	ew32(EECD, eecd | E1000_EECD_REQ);
203
-	eecd = er32(EECD);
204
-	while (timeout) {
205
-		if (eecd & E1000_EECD_GNT)
206
-			break;
207
-		udelay(5);
208
-		eecd = er32(EECD);
209
-		timeout--;
210
-	}
211
-
212
-	if (!timeout) {
213
-		eecd &= ~E1000_EECD_REQ;
214
-		ew32(EECD, eecd);
215
-		e_dbg("Could not acquire NVM grant\n");
216
-		ret_val = -E1000_ERR_NVM;
217
-	}
218
-
219
-	return ret_val;
220
-}
221
-
222
-/**
223
- *  e1000e_standby_nvm - Return EEPROM to standby state
224
- *  @hw: pointer to the HW structure
225
- *
226
- *  Return the EEPROM to a standby state.
227
- **/
228
-static void e1000e_standby_nvm(struct e1000_hw *hw)
229
-{
230
-	struct e1000_nvm_info *nvm = &hw->nvm;
231
-	u32 eecd = er32(EECD);
232
-
233
-	if (nvm->type == e1000_nvm_eeprom_spi) {
234
-		/* Toggle CS to flush commands */
235
-		eecd |= E1000_EECD_CS;
236
-		ew32(EECD, eecd);
237
-		e1e_flush();
238
-		udelay(nvm->delay_usec);
239
-		eecd &= ~E1000_EECD_CS;
240
-		ew32(EECD, eecd);
241
-		e1e_flush();
242
-		udelay(nvm->delay_usec);
243
-	}
244
-}
245
-
246
-/**
247
- *  e1000e_stop_nvm - Terminate EEPROM command
248
- *  @hw: pointer to the HW structure
249
- *
250
- *  Terminates the current command by inverting the EEPROM's chip select pin.
251
- **/
252
-static void e1000e_stop_nvm(struct e1000_hw *hw)
253
-{
254
-	u32 eecd;
255
-
256
-	eecd = er32(EECD);
257
-	if (hw->nvm.type == e1000_nvm_eeprom_spi) {
258
-		/* Pull CS high */
259
-		eecd |= E1000_EECD_CS;
260
-		e1000e_lower_eec_clk(hw, &eecd);
261
-	}
262
-}
263
-
264
-/**
265
- *  e1000e_release_nvm - Release exclusive access to EEPROM
266
- *  @hw: pointer to the HW structure
267
- *
268
- *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
269
- **/
270
-void e1000e_release_nvm(struct e1000_hw *hw)
271
-{
272
-	u32 eecd;
273
-
274
-	e1000e_stop_nvm(hw);
275
-
276
-	eecd = er32(EECD);
277
-	eecd &= ~E1000_EECD_REQ;
278
-	ew32(EECD, eecd);
279
-}
280
-
281
-/**
282
- *  e1000e_ready_nvm_eeprom - Prepares EEPROM for read/write
283
- *  @hw: pointer to the HW structure
284
- *
285
- *  Setups the EEPROM for reading and writing.
286
- **/
287
-static s32 e1000e_ready_nvm_eeprom(struct e1000_hw *hw)
288
-{
289
-	struct e1000_nvm_info *nvm = &hw->nvm;
290
-	u32 eecd = er32(EECD);
291
-	s32 ret_val = E1000_SUCCESS;
292
-	u16 timeout = 0;
293
-	u8 spi_stat_reg;
294
-
295
-	if (nvm->type == e1000_nvm_eeprom_spi) {
296
-		/* Clear SK and CS */
297
-		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
298
-		ew32(EECD, eecd);
299
-		udelay(1);
300
-		timeout = NVM_MAX_RETRY_SPI;
301
-
302
-		/*
303
-		 * Read "Status Register" repeatedly until the LSB is cleared.
304
-		 * The EEPROM will signal that the command has been completed
305
-		 * by clearing bit 0 of the internal status register.  If it's
306
-		 * not cleared within 'timeout', then error out.
307
-		 */
308
-		while (timeout) {
309
-			e1000e_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
310
-			                         hw->nvm.opcode_bits);
311
-			spi_stat_reg = (u8)e1000e_shift_in_eec_bits(hw, 8);
312
-			if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
313
-				break;
314
-
315
-			udelay(5);
316
-			e1000e_standby_nvm(hw);
317
-			timeout--;
318
-		}
319
-
320
-		if (!timeout) {
321
-			e_dbg("SPI NVM Status error\n");
322
-			ret_val = -E1000_ERR_NVM;
323
-			goto out;
324
-		}
325
-	}
326
-
327
-out:
328
-	return ret_val;
329
-}
330
-
331
-/**
332
- *  e1000e_read_nvm_eerd - Reads EEPROM using EERD register
333
- *  @hw: pointer to the HW structure
334
- *  @offset: offset of word in the EEPROM to read
335
- *  @words: number of words to read
336
- *  @data: word read from the EEPROM
337
- *
338
- *  Reads a 16 bit word from the EEPROM using the EERD register.
339
- **/
340
-s32 e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
341
-{
342
-	struct e1000_nvm_info *nvm = &hw->nvm;
343
-	u32 i, eerd = 0;
344
-	s32 ret_val = E1000_SUCCESS;
345
-
346
-	/*
347
-	 * A check for invalid values:  offset too large, too many words,
348
-	 * too many words for the offset, and not enough words.
349
-	 */
350
-	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
351
-	    (words == 0)) {
352
-		e_dbg("nvm parameter(s) out of bounds\n");
353
-		ret_val = -E1000_ERR_NVM;
354
-		goto out;
355
-	}
356
-
357
-	for (i = 0; i < words; i++) {
358
-		eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
359
-		       E1000_NVM_RW_REG_START;
360
-
361
-		ew32(EERD, eerd);
362
-		ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
363
-		if (ret_val)
364
-			break;
365
-
366
-		data[i] = (er32(EERD) >>
367
-		           E1000_NVM_RW_REG_DATA);
368
-	}
369
-
370
-out:
371
-	return ret_val;
372
-}
373
-
374
-/**
375
- *  e1000e_write_nvm_spi - Write to EEPROM using SPI
376
- *  @hw: pointer to the HW structure
377
- *  @offset: offset within the EEPROM to be written to
378
- *  @words: number of words to write
379
- *  @data: 16 bit word(s) to be written to the EEPROM
380
- *
381
- *  Writes data to EEPROM at offset using SPI interface.
382
- *
383
- *  If e1000e_update_nvm_checksum is not called after this function , the
384
- *  EEPROM will most likely contain an invalid checksum.
385
- **/
386
-s32 e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
387
-{
388
-	struct e1000_nvm_info *nvm = &hw->nvm;
389
-	s32 ret_val;
390
-	u16 widx = 0;
391
-
392
-	/*
393
-	 * A check for invalid values:  offset too large, too many words,
394
-	 * and not enough words.
395
-	 */
396
-	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
397
-	    (words == 0)) {
398
-		e_dbg("nvm parameter(s) out of bounds\n");
399
-		ret_val = -E1000_ERR_NVM;
400
-		goto out;
401
-	}
402
-
403
-	ret_val = nvm->ops.acquire(hw);
404
-	if (ret_val)
405
-		goto out;
406
-
407
-	while (widx < words) {
408
-		u8 write_opcode = NVM_WRITE_OPCODE_SPI;
409
-
410
-		ret_val = e1000e_ready_nvm_eeprom(hw);
411
-		if (ret_val)
412
-			goto release;
413
-
414
-		e1000e_standby_nvm(hw);
415
-
416
-		/* Send the WRITE ENABLE command (8 bit opcode) */
417
-		e1000e_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
418
-		                         nvm->opcode_bits);
419
-
420
-		e1000e_standby_nvm(hw);
421
-
422
-		/*
423
-		 * Some SPI eeproms use the 8th address bit embedded in the
424
-		 * opcode
425
-		 */
426
-		if ((nvm->address_bits == 8) && (offset >= 128))
427
-			write_opcode |= NVM_A8_OPCODE_SPI;
428
-
429
-		/* Send the Write command (8-bit opcode + addr) */
430
-		e1000e_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
431
-		e1000e_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
432
-		                         nvm->address_bits);
433
-
434
-		/* Loop to allow for up to whole page write of eeprom */
435
-		while (widx < words) {
436
-			u16 word_out = data[widx];
437
-			word_out = (word_out >> 8) | (word_out << 8);
438
-			e1000e_shift_out_eec_bits(hw, word_out, 16);
439
-			widx++;
440
-
441
-			if ((((offset + widx) * 2) % nvm->page_size) == 0) {
442
-				e1000e_standby_nvm(hw);
443
-				break;
444
-			}
445
-		}
446
-	}
447
-
448
-	msleep(10);
449
-release:
450
-	nvm->ops.release(hw);
451
-
452
-out:
453
-	return ret_val;
454
-}
455
-
456
-/**
457
- *  e1000e_read_pba_num - Read device part number
458
- *  @hw: pointer to the HW structure
459
- *  @pba_num: pointer to device part number
460
- *
461
- *  Reads the product board assembly (PBA) number from the EEPROM and stores
462
- *  the value in pba_num.
463
- **/
464
-s32 e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num)
465
-{
466
-	s32  ret_val;
467
-	u16 nvm_data;
468
-
469
-	ret_val = e1000e_read_nvm(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
470
-	if (ret_val) {
471
-		e_dbg("NVM Read Error\n");
472
-		goto out;
473
-	}
474
-	*pba_num = (u32)(nvm_data << 16);
475
-
476
-	ret_val = e1000e_read_nvm(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
477
-	if (ret_val) {
478
-		e_dbg("NVM Read Error\n");
479
-		goto out;
480
-	}
481
-	*pba_num |= nvm_data;
482
-
483
-out:
484
-	return ret_val;
485
-}
486
-
487
-/**
488
- *  e1000e_read_mac_addr_generic - Read device MAC address
489
- *  @hw: pointer to the HW structure
490
- *
491
- *  Reads the device MAC address from the EEPROM and stores the value.
492
- *  Since devices with two ports use the same EEPROM, we increment the
493
- *  last bit in the MAC address for the second port.
494
- **/
495
-s32 e1000e_read_mac_addr_generic(struct e1000_hw *hw)
496
-{
497
-	u32 rar_high;
498
-	u32 rar_low;
499
-	u16 i;
500
-
501
-	rar_high = er32(RAH(0));
502
-	rar_low = er32(RAL(0));
503
-
504
-	for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
505
-		hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
506
-
507
-	for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
508
-		hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
509
-
510
-	for (i = 0; i < ETH_ADDR_LEN; i++)
511
-		hw->mac.addr[i] = hw->mac.perm_addr[i];
512
-
513
-	return E1000_SUCCESS;
514
-}
515
-
516
-/**
517
- *  e1000e_validate_nvm_checksum_generic - Validate EEPROM checksum
518
- *  @hw: pointer to the HW structure
519
- *
520
- *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
521
- *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
522
- **/
523
-s32 e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw)
524
-{
525
-	s32 ret_val = E1000_SUCCESS;
526
-	u16 checksum = 0;
527
-	u16 i, nvm_data;
528
-
529
-	for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
530
-		ret_val = e1000e_read_nvm(hw, i, 1, &nvm_data);
531
-		if (ret_val) {
532
-			e_dbg("NVM Read Error\n");
533
-			goto out;
534
-		}
535
-		checksum += nvm_data;
536
-	}
537
-
538
-	if (checksum != (u16) NVM_SUM) {
539
-		e_dbg("NVM Checksum Invalid\n");
540
-		ret_val = -E1000_ERR_NVM;
541
-		goto out;
542
-	}
543
-
544
-out:
545
-	return ret_val;
546
-}
547
-
548
-/**
549
- *  e1000e_update_nvm_checksum_generic - Update EEPROM checksum
550
- *  @hw: pointer to the HW structure
551
- *
552
- *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
553
- *  up to the checksum.  Then calculates the EEPROM checksum and writes the
554
- *  value to the EEPROM.
555
- **/
556
-s32 e1000e_update_nvm_checksum_generic(struct e1000_hw *hw)
557
-{
558
-	s32  ret_val;
559
-	u16 checksum = 0;
560
-	u16 i, nvm_data;
561
-
562
-	for (i = 0; i < NVM_CHECKSUM_REG; i++) {
563
-		ret_val = e1000e_read_nvm(hw, i, 1, &nvm_data);
564
-		if (ret_val) {
565
-			e_dbg("NVM Read Error while updating checksum.\n");
566
-			goto out;
567
-		}
568
-		checksum += nvm_data;
569
-	}
570
-	checksum = (u16) NVM_SUM - checksum;
571
-	ret_val = e1000e_write_nvm(hw, NVM_CHECKSUM_REG, 1, &checksum);
572
-	if (ret_val)
573
-		e_dbg("NVM Write Error while updating checksum.\n");
574
-
575
-out:
576
-	return ret_val;
577
-}
578
-
579
-/**
580
- *  e1000e_reload_nvm - Reloads EEPROM
581
- *  @hw: pointer to the HW structure
582
- *
583
- *  Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
584
- *  extended control register.
585
- **/
586
-static void e1000e_reload_nvm(struct e1000_hw *hw)
587
-{
588
-	u32 ctrl_ext;
589
-
590
-	udelay(10);
591
-	ctrl_ext = er32(CTRL_EXT);
592
-	ctrl_ext |= E1000_CTRL_EXT_EE_RST;
593
-	ew32(CTRL_EXT, ctrl_ext);
594
-	e1e_flush();
595
-}
596
-

+ 0
- 53
src/drivers/net/e1000e/e1000e_nvm.h Прегледај датотеку

@@ -1,53 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2009 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-#ifndef _E1000E_NVM_H_
32
-#define _E1000E_NVM_H_
33
-
34
-void e1000e_init_nvm_ops_generic(struct e1000_hw *hw);
35
-s32  e1000e_acquire_nvm(struct e1000_hw *hw);
36
-
37
-s32  e1000e_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
38
-s32  e1000e_read_mac_addr_generic(struct e1000_hw *hw);
39
-s32  e1000e_read_pba_num(struct e1000_hw *hw, u32 *pba_num);
40
-s32  e1000e_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words,
41
-                         u16 *data);
42
-s32  e1000e_valid_led_default(struct e1000_hw *hw, u16 *data);
43
-s32  e1000e_validate_nvm_checksum_generic(struct e1000_hw *hw);
44
-s32  e1000e_write_nvm_eewr(struct e1000_hw *hw, u16 offset,
45
-                          u16 words, u16 *data);
46
-s32  e1000e_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words,
47
-                         u16 *data);
48
-s32  e1000e_update_nvm_checksum_generic(struct e1000_hw *hw);
49
-void e1000e_release_nvm(struct e1000_hw *hw);
50
-
51
-#define E1000_STM_OPCODE  0xDB00
52
-
53
-#endif

+ 0
- 3326
src/drivers/net/e1000e/e1000e_phy.c
Разлика између датотеке није приказан због своје велике величине
Прегледај датотеку


+ 0
- 261
src/drivers/net/e1000e/e1000e_phy.h Прегледај датотеку

@@ -1,261 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2009 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-#ifndef _E1000E_PHY_H_
32
-#define _E1000E_PHY_H_
33
-
34
-void e1000e_init_phy_ops_generic(struct e1000_hw *hw);
35
-s32  e1000e_check_downshift(struct e1000_hw *hw);
36
-s32  e1000e_check_polarity_m88(struct e1000_hw *hw);
37
-s32  e1000e_check_polarity_igp(struct e1000_hw *hw);
38
-s32  e1000e_check_polarity_ife(struct e1000_hw *hw);
39
-s32  e1000e_check_reset_block_generic(struct e1000_hw *hw);
40
-s32  e1000e_copper_link_setup_igp(struct e1000_hw *hw);
41
-s32  e1000e_copper_link_setup_m88(struct e1000_hw *hw);
42
-#if 0
43
-s32  e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw);
44
-s32  e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw);
45
-s32  e1000e_phy_force_speed_duplex_ife(struct e1000_hw *hw);
46
-#endif
47
-#if 0
48
-s32  e1000e_get_cable_length_m88(struct e1000_hw *hw);
49
-s32  e1000e_get_cable_length_igp_2(struct e1000_hw *hw);
50
-#endif
51
-s32  e1000e_get_cfg_done(struct e1000_hw *hw);
52
-s32  e1000e_get_phy_id(struct e1000_hw *hw);
53
-s32  e1000e_get_phy_info_igp(struct e1000_hw *hw);
54
-s32  e1000e_get_phy_info_m88(struct e1000_hw *hw);
55
-s32  e1000e_phy_sw_reset(struct e1000_hw *hw);
56
-#if 0
57
-void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
58
-#endif
59
-s32  e1000e_phy_hw_reset_generic(struct e1000_hw *hw);
60
-s32  e1000e_phy_reset_dsp(struct e1000_hw *hw);
61
-s32  e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
62
-s32  e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);
63
-s32  e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
64
-s32  e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);
65
-s32  e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
66
-s32  e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active);
67
-s32  e1000e_setup_copper_link(struct e1000_hw *hw);
68
-s32  e1000e_wait_autoneg(struct e1000_hw *hw);
69
-s32  e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
70
-s32  e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data);
71
-s32  e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
72
-s32  e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);
73
-s32  e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
74
-s32  e1000e_phy_reset_dsp(struct e1000_hw *hw);
75
-s32  e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
76
-                                u32 usec_interval, bool *success);
77
-s32  e1000e_phy_init_script_igp3(struct e1000_hw *hw);
78
-enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id);
79
-s32  e1000e_determine_phy_address(struct e1000_hw *hw);
80
-s32  e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data);
81
-s32  e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data);
82
-s32  e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data);
83
-s32  e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data);
84
-void e1000e_power_up_phy_copper(struct e1000_hw *hw);
85
-void e1000e_power_down_phy_copper(struct e1000_hw *hw);
86
-s32  e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
87
-s32  e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
88
-s32  e1000e_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data);
89
-s32  e1000e_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data);
90
-s32  e1000e_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data);
91
-s32  e1000e_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data);
92
-s32  e1000e_set_mdio_slow_mode_hv(struct e1000_hw *hw, bool slow);
93
-s32  e1000e_link_stall_workaround_hv(struct e1000_hw *hw);
94
-s32  e1000e_copper_link_setup_82577(struct e1000_hw *hw);
95
-s32  e1000e_check_polarity_82577(struct e1000_hw *hw);
96
-s32  e1000e_get_phy_info_82577(struct e1000_hw *hw);
97
-#if 0
98
-s32  e1000e_phy_force_speed_duplex_82577(struct e1000_hw *hw);
99
-#endif
100
-#if 0
101
-s32  e1000e_get_cable_length_82577(struct e1000_hw *hw);
102
-#endif
103
-
104
-#define E1000_MAX_PHY_ADDR                4
105
-
106
-/* IGP01E1000 Specific Registers */
107
-#define IGP01E1000_PHY_PORT_CONFIG        0x10 /* Port Config */
108
-#define IGP01E1000_PHY_PORT_STATUS        0x11 /* Status */
109
-#define IGP01E1000_PHY_PORT_CTRL          0x12 /* Control */
110
-#define IGP01E1000_PHY_LINK_HEALTH        0x13 /* PHY Link Health */
111
-#define IGP01E1000_GMII_FIFO              0x14 /* GMII FIFO */
112
-#define IGP01E1000_PHY_CHANNEL_QUALITY    0x15 /* PHY Channel Quality */
113
-#define IGP02E1000_PHY_POWER_MGMT         0x19 /* Power Management */
114
-#define IGP01E1000_PHY_PAGE_SELECT        0x1F /* Page Select */
115
-#define BM_PHY_PAGE_SELECT                22   /* Page Select for BM */
116
-#define IGP_PAGE_SHIFT                    5
117
-#define PHY_REG_MASK                      0x1F
118
-
119
-/* BM/HV Specific Registers */
120
-#define BM_PORT_CTRL_PAGE                 769
121
-#define BM_PCIE_PAGE                      770
122
-#define BM_WUC_PAGE                       800
123
-#define BM_WUC_ADDRESS_OPCODE             0x11
124
-#define BM_WUC_DATA_OPCODE                0x12
125
-#define BM_WUC_ENABLE_PAGE                BM_PORT_CTRL_PAGE
126
-#define BM_WUC_ENABLE_REG                 17
127
-#define BM_WUC_ENABLE_BIT                 (1 << 2)
128
-#define BM_WUC_HOST_WU_BIT                (1 << 4)
129
-
130
-#define PHY_UPPER_SHIFT                   21
131
-#define BM_PHY_REG(page, reg) \
132
-	(((reg) & MAX_PHY_REG_ADDRESS) |\
133
-	 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
134
-	 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
135
-#define BM_PHY_REG_PAGE(offset) \
136
-	((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF))
137
-#define BM_PHY_REG_NUM(offset) \
138
-	((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\
139
-	 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\
140
-		~MAX_PHY_REG_ADDRESS)))
141
-
142
-#define HV_INTC_FC_PAGE_START             768
143
-#define I82578_ADDR_REG                   29
144
-#define I82577_ADDR_REG                   16
145
-#define I82577_CFG_REG                    22
146
-#define I82577_CFG_ASSERT_CRS_ON_TX       (1 << 15)
147
-#define I82577_CFG_ENABLE_DOWNSHIFT       (3 << 10) /* auto downshift 100/10 */
148
-#define I82577_CTRL_REG                   23
149
-
150
-/* 82577 specific PHY registers */
151
-#define I82577_PHY_CTRL_2            18
152
-#define I82577_PHY_LBK_CTRL          19
153
-#define I82577_PHY_STATUS_2          26
154
-#define I82577_PHY_DIAG_STATUS       31
155
-
156
-/* I82577 PHY Status 2 */
157
-#define I82577_PHY_STATUS2_REV_POLARITY   0x0400
158
-#define I82577_PHY_STATUS2_MDIX           0x0800
159
-#define I82577_PHY_STATUS2_SPEED_MASK     0x0300
160
-#define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200
161
-#define I82577_PHY_STATUS2_SPEED_100MBPS  0x0100
162
-
163
-/* I82577 PHY Control 2 */
164
-#define I82577_PHY_CTRL2_AUTO_MDIX        0x0400
165
-#define I82577_PHY_CTRL2_FORCE_MDI_MDIX   0x0200
166
-
167
-/* I82577 PHY Diagnostics Status */
168
-#define I82577_DSTATUS_CABLE_LENGTH       0x03FC
169
-#define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2
170
-
171
-/* BM PHY Copper Specific Control 1 */
172
-#define BM_CS_CTRL1                       16
173
-#define BM_CS_CTRL1_ENERGY_DETECT         0x0300 /* Enable Energy Detect */
174
-
175
-/* BM PHY Copper Specific Status */
176
-#define BM_CS_STATUS                      17
177
-#define BM_CS_STATUS_ENERGY_DETECT        0x0010 /* Energy Detect Status */
178
-#define BM_CS_STATUS_LINK_UP              0x0400
179
-#define BM_CS_STATUS_RESOLVED             0x0800
180
-#define BM_CS_STATUS_SPEED_MASK           0xC000
181
-#define BM_CS_STATUS_SPEED_1000           0x8000
182
-
183
-/* 82577 Mobile Phy Status Register */
184
-#define HV_M_STATUS                       26
185
-#define HV_M_STATUS_AUTONEG_COMPLETE      0x1000
186
-#define HV_M_STATUS_SPEED_MASK            0x0300
187
-#define HV_M_STATUS_SPEED_1000            0x0200
188
-#define HV_M_STATUS_LINK_UP               0x0040
189
-
190
-#define IGP01E1000_PHY_PCS_INIT_REG       0x00B4
191
-#define IGP01E1000_PHY_POLARITY_MASK      0x0078
192
-
193
-#define IGP01E1000_PSCR_AUTO_MDIX         0x1000
194
-#define IGP01E1000_PSCR_FORCE_MDI_MDIX    0x2000 /* 0=MDI, 1=MDIX */
195
-
196
-#define IGP01E1000_PSCFR_SMART_SPEED      0x0080
197
-
198
-/* Enable flexible speed on link-up */
199
-#define IGP01E1000_GMII_FLEX_SPD          0x0010
200
-#define IGP01E1000_GMII_SPD               0x0020 /* Enable SPD */
201
-
202
-#define IGP02E1000_PM_SPD                 0x0001 /* Smart Power Down */
203
-#define IGP02E1000_PM_D0_LPLU             0x0002 /* For D0a states */
204
-#define IGP02E1000_PM_D3_LPLU             0x0004 /* For all other states */
205
-
206
-#define IGP01E1000_PLHR_SS_DOWNGRADE      0x8000
207
-
208
-#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
209
-#define IGP01E1000_PSSR_MDIX              0x0800
210
-#define IGP01E1000_PSSR_SPEED_MASK        0xC000
211
-#define IGP01E1000_PSSR_SPEED_1000MBPS    0xC000
212
-
213
-#define IGP02E1000_PHY_CHANNEL_NUM        4
214
-#define IGP02E1000_PHY_AGC_A              0x11B1
215
-#define IGP02E1000_PHY_AGC_B              0x12B1
216
-#define IGP02E1000_PHY_AGC_C              0x14B1
217
-#define IGP02E1000_PHY_AGC_D              0x18B1
218
-
219
-#define IGP02E1000_AGC_LENGTH_SHIFT       9   /* Course - 15:13, Fine - 12:9 */
220
-#define IGP02E1000_AGC_LENGTH_MASK        0x7F
221
-#define IGP02E1000_AGC_RANGE              15
222
-
223
-#define IGP03E1000_PHY_MISC_CTRL          0x1B
224
-#define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET  0x1000 /* Manually Set Duplex */
225
-
226
-#define E1000_CABLE_LENGTH_UNDEFINED      0xFF
227
-
228
-#define E1000_KMRNCTRLSTA_OFFSET          0x001F0000
229
-#define E1000_KMRNCTRLSTA_OFFSET_SHIFT    16
230
-#define E1000_KMRNCTRLSTA_REN             0x00200000
231
-#define E1000_KMRNCTRLSTA_DIAG_OFFSET     0x3    /* Kumeran Diagnostic */
232
-#define E1000_KMRNCTRLSTA_TIMEOUTS        0x4    /* Kumeran Timeouts */
233
-#define E1000_KMRNCTRLSTA_INBAND_PARAM    0x9    /* Kumeran InBand Parameters */
234
-#define E1000_KMRNCTRLSTA_DIAG_NELPBK     0x1000 /* Nearend Loopback mode */
235
-#define E1000_KMRNCTRLSTA_K1_CONFIG        0x7
236
-#define E1000_KMRNCTRLSTA_K1_ENABLE        0x0002
237
-
238
-#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
239
-#define IFE_PHY_SPECIAL_CONTROL     0x11 /* 100BaseTx PHY Special Control */
240
-#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
241
-#define IFE_PHY_MDIX_CONTROL        0x1C /* MDI/MDI-X Control */
242
-
243
-/* IFE PHY Extended Status Control */
244
-#define IFE_PESC_POLARITY_REVERSED    0x0100
245
-
246
-/* IFE PHY Special Control */
247
-#define IFE_PSC_AUTO_POLARITY_DISABLE      0x0010
248
-#define IFE_PSC_FORCE_POLARITY             0x0020
249
-#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
250
-
251
-/* IFE PHY Special Control and LED Control */
252
-#define IFE_PSCL_PROBE_MODE            0x0020
253
-#define IFE_PSCL_PROBE_LEDS_OFF        0x0006 /* Force LEDs 0 and 2 off */
254
-#define IFE_PSCL_PROBE_LEDS_ON         0x0007 /* Force LEDs 0 and 2 on */
255
-
256
-/* IFE PHY MDIX Control */
257
-#define IFE_PMC_MDIX_STATUS      0x0020 /* 1=MDI-X, 0=MDI */
258
-#define IFE_PMC_FORCE_MDIX       0x0040 /* 1=force MDI-X, 0=force MDI */
259
-#define IFE_PMC_AUTO_MDIX        0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
260
-
261
-#endif

+ 0
- 340
src/drivers/net/e1000e/e1000e_regs.h Прегледај датотеку

@@ -1,340 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2009 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_OR_LATER );
30
-
31
-#ifndef _E1000E_REGS_H_
32
-#define _E1000E_REGS_H_
33
-
34
-#define E1000_CTRL     0x00000  /* Device Control - RW */
35
-#define E1000_CTRL_DUP 0x00004  /* Device Control Duplicate (Shadow) - RW */
36
-#define E1000_STATUS   0x00008  /* Device Status - RO */
37
-#define E1000_EECD     0x00010  /* EEPROM/Flash Control - RW */
38
-#define E1000_EERD     0x00014  /* EEPROM Read - RW */
39
-#define E1000_CTRL_EXT 0x00018  /* Extended Device Control - RW */
40
-#define E1000_FLA      0x0001C  /* Flash Access - RW */
41
-#define E1000_MDIC     0x00020  /* MDI Control - RW */
42
-#define E1000_SCTL     0x00024  /* SerDes Control - RW */
43
-#define E1000_FCAL     0x00028  /* Flow Control Address Low - RW */
44
-#define E1000_FCAH     0x0002C  /* Flow Control Address High -RW */
45
-#define E1000_FEXT     0x0002C  /* Future Extended - RW */
46
-#define E1000_FEXTNVM  0x00028  /* Future Extended NVM - RW */
47
-#define E1000_FCT      0x00030  /* Flow Control Type - RW */
48
-#define E1000_CONNSW   0x00034  /* Copper/Fiber switch control - RW */
49
-#define E1000_VET      0x00038  /* VLAN Ether Type - RW */
50
-#define E1000_ICR      0x000C0  /* Interrupt Cause Read - R/clr */
51
-#define E1000_ITR      0x000C4  /* Interrupt Throttling Rate - RW */
52
-#define E1000_ICS      0x000C8  /* Interrupt Cause Set - WO */
53
-#define E1000_IMS      0x000D0  /* Interrupt Mask Set - RW */
54
-#define E1000_IMC      0x000D8  /* Interrupt Mask Clear - WO */
55
-#define E1000_IAM      0x000E0  /* Interrupt Acknowledge Auto Mask */
56
-#define E1000_IVAR     0x000E4  /* Interrupt Vector Allocation Register - RW */
57
-#define E1000_SVCR     0x000F0
58
-#define E1000_SVT       0x000F4
59
-#define E1000_RCTL     0x00100  /* Rx Control - RW */
60
-#define E1000_FCTTV    0x00170  /* Flow Control Transmit Timer Value - RW */
61
-#define E1000_TXCW     0x00178  /* Tx Configuration Word - RW */
62
-#define E1000_RXCW     0x00180  /* Rx Configuration Word - RO */
63
-#define E1000_PBA_ECC  0x01100  /* PBA ECC Register */
64
-#define E1000_TCTL     0x00400  /* Tx Control - RW */
65
-#define E1000_TCTL_EXT 0x00404  /* Extended Tx Control - RW */
66
-#define E1000_TIPG     0x00410  /* Tx Inter-packet gap -RW */
67
-#define E1000_TBT      0x00448  /* Tx Burst Timer - RW */
68
-#define E1000_AIT      0x00458  /* Adaptive Interframe Spacing Throttle - RW */
69
-#define E1000_LEDCTL   0x00E00  /* LED Control - RW */
70
-#define E1000_EXTCNF_CTRL  0x00F00  /* Extended Configuration Control */
71
-#define E1000_EXTCNF_SIZE  0x00F08  /* Extended Configuration Size */
72
-#define E1000_PHY_CTRL     0x00F10  /* PHY Control Register in CSR */
73
-#define E1000_PBA      0x01000  /* Packet Buffer Allocation - RW */
74
-#define E1000_PBS      0x01008  /* Packet Buffer Size */
75
-#define E1000_EEMNGCTL 0x01010  /* MNG EEprom Control */
76
-#define E1000_EEARBC   0x01024  /* EEPROM Auto Read Bus Control */
77
-#define E1000_FLASHT   0x01028  /* FLASH Timer Register */
78
-#define E1000_EEWR     0x0102C  /* EEPROM Write Register - RW */
79
-#define E1000_FLSWCTL  0x01030  /* FLASH control register */
80
-#define E1000_FLSWDATA 0x01034  /* FLASH data register */
81
-#define E1000_FLSWCNT  0x01038  /* FLASH Access Counter */
82
-#define E1000_FLOP     0x0103C  /* FLASH Opcode Register */
83
-#define E1000_I2CCMD   0x01028  /* SFPI2C Command Register - RW */
84
-#define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */
85
-#define E1000_WDSTP    0x01040  /* Watchdog Setup - RW */
86
-#define E1000_SWDSTS   0x01044  /* SW Device Status - RW */
87
-#define E1000_FRTIMER  0x01048  /* Free Running Timer - RW */
88
-#define E1000_ERT      0x02008  /* Early Rx Threshold - RW */
89
-#define E1000_FCRTL    0x02160  /* Flow Control Receive Threshold Low - RW */
90
-#define E1000_FCRTH    0x02168  /* Flow Control Receive Threshold High - RW */
91
-#define E1000_PSRCTL   0x02170  /* Packet Split Receive Control - RW */
92
-#define E1000_RDFPCQ(_n)  (0x02430 + (0x4 * (_n)))
93
-#define E1000_PBRTH    0x02458  /* PB Rx Arbitration Threshold - RW */
94
-#define E1000_FCRTV    0x02460  /* Flow Control Refresh Timer Value - RW */
95
-/* Split and Replication Rx Control - RW */
96
-#define E1000_RDPUMB   0x025CC  /* DMA Rx Descriptor uC Mailbox - RW */
97
-#define E1000_RDPUAD   0x025D0  /* DMA Rx Descriptor uC Addr Command - RW */
98
-#define E1000_RDPUWD   0x025D4  /* DMA Rx Descriptor uC Data Write - RW */
99
-#define E1000_RDPURD   0x025D8  /* DMA Rx Descriptor uC Data Read - RW */
100
-#define E1000_RDPUCTL  0x025DC  /* DMA Rx Descriptor uC Control - RW */
101
-#define E1000_RDTR     0x02820  /* Rx Delay Timer - RW */
102
-#define E1000_RADV     0x0282C  /* Rx Interrupt Absolute Delay Timer - RW */
103
-/*
104
- * Convenience macros
105
- *
106
- * Note: "_n" is the queue number of the register to be written to.
107
- *
108
- * Example usage:
109
- * E1000_RDBAL_REG(current_rx_queue)
110
- */
111
-#define E1000_RDBAL(_n)      ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \
112
-                                         (0x0C000 + ((_n) * 0x40)))
113
-#define E1000_RDBAH(_n)      ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \
114
-                                         (0x0C004 + ((_n) * 0x40)))
115
-#define E1000_RDLEN(_n)      ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \
116
-                                         (0x0C008 + ((_n) * 0x40)))
117
-#define E1000_SRRCTL(_n)     ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
118
-                                         (0x0C00C + ((_n) * 0x40)))
119
-#define E1000_RDH(_n)        ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \
120
-                                         (0x0C010 + ((_n) * 0x40)))
121
-#define E1000_RXCTL(_n)      ((_n) < 4 ? (0x02814 + ((_n) * 0x100)) : \
122
-                                         (0x0C014 + ((_n) * 0x40)))
123
-#define E1000_DCA_RXCTRL(_n) E1000_RXCTL(_n)
124
-#define E1000_RDT(_n)        ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \
125
-                                         (0x0C018 + ((_n) * 0x40)))
126
-#define E1000_RXDCTL(_n)     ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \
127
-                                         (0x0C028 + ((_n) * 0x40)))
128
-#define E1000_RQDPC(_n)      ((_n) < 4 ? (0x02830 + ((_n) * 0x100)) : \
129
-                                         (0x0C030 + ((_n) * 0x40)))
130
-#define E1000_TDBAL(_n)      ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \
131
-                                         (0x0E000 + ((_n) * 0x40)))
132
-#define E1000_TDBAH(_n)      ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \
133
-                                         (0x0E004 + ((_n) * 0x40)))
134
-#define E1000_TDLEN(_n)      ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \
135
-                                         (0x0E008 + ((_n) * 0x40)))
136
-#define E1000_TDH(_n)        ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \
137
-                                         (0x0E010 + ((_n) * 0x40)))
138
-#define E1000_TXCTL(_n)      ((_n) < 4 ? (0x03814 + ((_n) * 0x100)) : \
139
-                                         (0x0E014 + ((_n) * 0x40)))
140
-#define E1000_DCA_TXCTRL(_n) E1000_TXCTL(_n)
141
-#define E1000_TDT(_n)        ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \
142
-                                         (0x0E018 + ((_n) * 0x40)))
143
-#define E1000_TXDCTL(_n)     ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \
144
-                                         (0x0E028 + ((_n) * 0x40)))
145
-#define E1000_TDWBAL(_n)     ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : \
146
-                                         (0x0E038 + ((_n) * 0x40)))
147
-#define E1000_TDWBAH(_n)     ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : \
148
-                                         (0x0E03C + ((_n) * 0x40)))
149
-#define E1000_TARC(_n)                   (0x03840 + ((_n) * 0x100))
150
-#define E1000_RSRPD    0x02C00  /* Rx Small Packet Detect - RW */
151
-#define E1000_RAID     0x02C08  /* Receive Ack Interrupt Delay - RW */
152
-#define E1000_TXDMAC   0x03000  /* Tx DMA Control - RW */
153
-#define E1000_KABGTXD  0x03004  /* AFE Band Gap Transmit Ref Data */
154
-#define E1000_PSRTYPE(_i)       (0x05480 + ((_i) * 4))
155
-#define E1000_RAL(_i)  (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
156
-                                       (0x054E0 + ((_i - 16) * 8)))
157
-#define E1000_RAH(_i)  (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
158
-                                       (0x054E4 + ((_i - 16) * 8)))
159
-#define E1000_IP4AT_REG(_i)     (0x05840 + ((_i) * 8))
160
-#define E1000_IP6AT_REG(_i)     (0x05880 + ((_i) * 4))
161
-#define E1000_WUPM_REG(_i)      (0x05A00 + ((_i) * 4))
162
-#define E1000_FFMT_REG(_i)      (0x09000 + ((_i) * 8))
163
-#define E1000_FFVT_REG(_i)      (0x09800 + ((_i) * 8))
164
-#define E1000_FFLT_REG(_i)      (0x05F00 + ((_i) * 8))
165
-#define E1000_TDFH     0x03410  /* Tx Data FIFO Head - RW */
166
-#define E1000_TDFT     0x03418  /* Tx Data FIFO Tail - RW */
167
-#define E1000_TDFHS    0x03420  /* Tx Data FIFO Head Saved - RW */
168
-#define E1000_TDFTS    0x03428  /* Tx Data FIFO Tail Saved - RW */
169
-#define E1000_TDFPC    0x03430  /* Tx Data FIFO Packet Count - RW */
170
-#define E1000_TDPUMB   0x0357C  /* DMA Tx Descriptor uC Mail Box - RW */
171
-#define E1000_TDPUAD   0x03580  /* DMA Tx Descriptor uC Addr Command - RW */
172
-#define E1000_TDPUWD   0x03584  /* DMA Tx Descriptor uC Data Write - RW */
173
-#define E1000_TDPURD   0x03588  /* DMA Tx Descriptor uC Data  Read  - RW */
174
-#define E1000_TDPUCTL  0x0358C  /* DMA Tx Descriptor uC Control - RW */
175
-#define E1000_DTXCTL   0x03590  /* DMA Tx Control - RW */
176
-#define E1000_TIDV     0x03820  /* Tx Interrupt Delay Value - RW */
177
-#define E1000_TADV     0x0382C  /* Tx Interrupt Absolute Delay Val - RW */
178
-#define E1000_TSPMT    0x03830  /* TCP Segmentation PAD & Min Threshold - RW */
179
-#define E1000_CRCERRS  0x04000  /* CRC Error Count - R/clr */
180
-#define E1000_ALGNERRC 0x04004  /* Alignment Error Count - R/clr */
181
-#define E1000_SYMERRS  0x04008  /* Symbol Error Count - R/clr */
182
-#define E1000_RXERRC   0x0400C  /* Receive Error Count - R/clr */
183
-#define E1000_MPC      0x04010  /* Missed Packet Count - R/clr */
184
-#define E1000_SCC      0x04014  /* Single Collision Count - R/clr */
185
-#define E1000_ECOL     0x04018  /* Excessive Collision Count - R/clr */
186
-#define E1000_MCC      0x0401C  /* Multiple Collision Count - R/clr */
187
-#define E1000_LATECOL  0x04020  /* Late Collision Count - R/clr */
188
-#define E1000_COLC     0x04028  /* Collision Count - R/clr */
189
-#define E1000_DC       0x04030  /* Defer Count - R/clr */
190
-#define E1000_TNCRS    0x04034  /* Tx-No CRS - R/clr */
191
-#define E1000_SEC      0x04038  /* Sequence Error Count - R/clr */
192
-#define E1000_CEXTERR  0x0403C  /* Carrier Extension Error Count - R/clr */
193
-#define E1000_RLEC     0x04040  /* Receive Length Error Count - R/clr */
194
-#define E1000_XONRXC   0x04048  /* XON Rx Count - R/clr */
195
-#define E1000_XONTXC   0x0404C  /* XON Tx Count - R/clr */
196
-#define E1000_XOFFRXC  0x04050  /* XOFF Rx Count - R/clr */
197
-#define E1000_XOFFTXC  0x04054  /* XOFF Tx Count - R/clr */
198
-#define E1000_FCRUC    0x04058  /* Flow Control Rx Unsupported Count- R/clr */
199
-#define E1000_PRC64    0x0405C  /* Packets Rx (64 bytes) - R/clr */
200
-#define E1000_PRC127   0x04060  /* Packets Rx (65-127 bytes) - R/clr */
201
-#define E1000_PRC255   0x04064  /* Packets Rx (128-255 bytes) - R/clr */
202
-#define E1000_PRC511   0x04068  /* Packets Rx (255-511 bytes) - R/clr */
203
-#define E1000_PRC1023  0x0406C  /* Packets Rx (512-1023 bytes) - R/clr */
204
-#define E1000_PRC1522  0x04070  /* Packets Rx (1024-1522 bytes) - R/clr */
205
-#define E1000_GPRC     0x04074  /* Good Packets Rx Count - R/clr */
206
-#define E1000_BPRC     0x04078  /* Broadcast Packets Rx Count - R/clr */
207
-#define E1000_MPRC     0x0407C  /* Multicast Packets Rx Count - R/clr */
208
-#define E1000_GPTC     0x04080  /* Good Packets Tx Count - R/clr */
209
-#define E1000_GORCL    0x04088  /* Good Octets Rx Count Low - R/clr */
210
-#define E1000_GORCH    0x0408C  /* Good Octets Rx Count High - R/clr */
211
-#define E1000_GOTCL    0x04090  /* Good Octets Tx Count Low - R/clr */
212
-#define E1000_GOTCH    0x04094  /* Good Octets Tx Count High - R/clr */
213
-#define E1000_RNBC     0x040A0  /* Rx No Buffers Count - R/clr */
214
-#define E1000_RUC      0x040A4  /* Rx Undersize Count - R/clr */
215
-#define E1000_RFC      0x040A8  /* Rx Fragment Count - R/clr */
216
-#define E1000_ROC      0x040AC  /* Rx Oversize Count - R/clr */
217
-#define E1000_RJC      0x040B0  /* Rx Jabber Count - R/clr */
218
-#define E1000_MGTPRC   0x040B4  /* Management Packets Rx Count - R/clr */
219
-#define E1000_MGTPDC   0x040B8  /* Management Packets Dropped Count - R/clr */
220
-#define E1000_MGTPTC   0x040BC  /* Management Packets Tx Count - R/clr */
221
-#define E1000_TORL     0x040C0  /* Total Octets Rx Low - R/clr */
222
-#define E1000_TORH     0x040C4  /* Total Octets Rx High - R/clr */
223
-#define E1000_TOTL     0x040C8  /* Total Octets Tx Low - R/clr */
224
-#define E1000_TOTH     0x040CC  /* Total Octets Tx High - R/clr */
225
-#define E1000_TPR      0x040D0  /* Total Packets Rx - R/clr */
226
-#define E1000_TPT      0x040D4  /* Total Packets Tx - R/clr */
227
-#define E1000_PTC64    0x040D8  /* Packets Tx (64 bytes) - R/clr */
228
-#define E1000_PTC127   0x040DC  /* Packets Tx (65-127 bytes) - R/clr */
229
-#define E1000_PTC255   0x040E0  /* Packets Tx (128-255 bytes) - R/clr */
230
-#define E1000_PTC511   0x040E4  /* Packets Tx (256-511 bytes) - R/clr */
231
-#define E1000_PTC1023  0x040E8  /* Packets Tx (512-1023 bytes) - R/clr */
232
-#define E1000_PTC1522  0x040EC  /* Packets Tx (1024-1522 Bytes) - R/clr */
233
-#define E1000_MPTC     0x040F0  /* Multicast Packets Tx Count - R/clr */
234
-#define E1000_BPTC     0x040F4  /* Broadcast Packets Tx Count - R/clr */
235
-#define E1000_TSCTC    0x040F8  /* TCP Segmentation Context Tx - R/clr */
236
-#define E1000_TSCTFC   0x040FC  /* TCP Segmentation Context Tx Fail - R/clr */
237
-#define E1000_IAC      0x04100  /* Interrupt Assertion Count */
238
-#define E1000_ICRXPTC  0x04104  /* Interrupt Cause Rx Pkt Timer Expire Count */
239
-#define E1000_ICRXATC  0x04108  /* Interrupt Cause Rx Abs Timer Expire Count */
240
-#define E1000_ICTXPTC  0x0410C  /* Interrupt Cause Tx Pkt Timer Expire Count */
241
-#define E1000_ICTXATC  0x04110  /* Interrupt Cause Tx Abs Timer Expire Count */
242
-#define E1000_ICTXQEC  0x04118  /* Interrupt Cause Tx Queue Empty Count */
243
-#define E1000_ICTXQMTC 0x0411C  /* Interrupt Cause Tx Queue Min Thresh Count */
244
-#define E1000_ICRXDMTC 0x04120  /* Interrupt Cause Rx Desc Min Thresh Count */
245
-#define E1000_ICRXOC   0x04124  /* Interrupt Cause Receiver Overrun Count */
246
-#define E1000_CRC_OFFSET 0x05F50  /* CRC Offset register */
247
-
248
-#define E1000_PCS_CFG0    0x04200  /* PCS Configuration 0 - RW */
249
-#define E1000_PCS_LCTL    0x04208  /* PCS Link Control - RW */
250
-#define E1000_PCS_LSTAT   0x0420C  /* PCS Link Status - RO */
251
-#define E1000_CBTMPC      0x0402C  /* Circuit Breaker Tx Packet Count */
252
-#define E1000_HTDPMC      0x0403C  /* Host Transmit Discarded Packets */
253
-#define E1000_CBRDPC      0x04044  /* Circuit Breaker Rx Dropped Count */
254
-#define E1000_CBRMPC      0x040FC  /* Circuit Breaker Rx Packet Count */
255
-#define E1000_RPTHC       0x04104  /* Rx Packets To Host */
256
-#define E1000_HGPTC       0x04118  /* Host Good Packets Tx Count */
257
-#define E1000_HTCBDPC     0x04124  /* Host Tx Circuit Breaker Dropped Count */
258
-#define E1000_HGORCL      0x04128  /* Host Good Octets Received Count Low */
259
-#define E1000_HGORCH      0x0412C  /* Host Good Octets Received Count High */
260
-#define E1000_HGOTCL      0x04130  /* Host Good Octets Transmit Count Low */
261
-#define E1000_HGOTCH      0x04134  /* Host Good Octets Transmit Count High */
262
-#define E1000_LENERRS     0x04138  /* Length Errors Count */
263
-#define E1000_SCVPC       0x04228  /* SerDes/SGMII Code Violation Pkt Count */
264
-#define E1000_HRMPC       0x0A018  /* Header Redirection Missed Packet Count */
265
-#define E1000_PCS_ANADV   0x04218  /* AN advertisement - RW */
266
-#define E1000_PCS_LPAB    0x0421C  /* Link Partner Ability - RW */
267
-#define E1000_PCS_NPTX    0x04220  /* AN Next Page Transmit - RW */
268
-#define E1000_PCS_LPABNP  0x04224  /* Link Partner Ability Next Page - RW */
269
-#define E1000_1GSTAT_RCV  0x04228  /* 1GSTAT Code Violation Packet Count - RW */
270
-#define E1000_RXCSUM   0x05000  /* Rx Checksum Control - RW */
271
-#define E1000_RLPML    0x05004  /* Rx Long Packet Max Length */
272
-#define E1000_RFCTL    0x05008  /* Receive Filter Control*/
273
-#define E1000_MTA      0x05200  /* Multicast Table Array - RW Array */
274
-#define E1000_RA       0x05400  /* Receive Address - RW Array */
275
-#define E1000_VFTA     0x05600  /* VLAN Filter Table Array - RW Array */
276
-#define E1000_VT_CTL   0x0581C  /* VMDq Control - RW */
277
-#define E1000_VFQA0    0x0B000  /* VLAN Filter Queue Array 0 - RW Array */
278
-#define E1000_VFQA1    0x0B200  /* VLAN Filter Queue Array 1 - RW Array */
279
-#define E1000_WUC      0x05800  /* Wakeup Control - RW */
280
-#define E1000_WUFC     0x05808  /* Wakeup Filter Control - RW */
281
-#define E1000_WUS      0x05810  /* Wakeup Status - RO */
282
-#define E1000_MANC     0x05820  /* Management Control - RW */
283
-#define E1000_IPAV     0x05838  /* IP Address Valid - RW */
284
-#define E1000_IP4AT    0x05840  /* IPv4 Address Table - RW Array */
285
-#define E1000_IP6AT    0x05880  /* IPv6 Address Table - RW Array */
286
-#define E1000_WUPL     0x05900  /* Wakeup Packet Length - RW */
287
-#define E1000_WUPM     0x05A00  /* Wakeup Packet Memory - RO A */
288
-#define E1000_PBACL    0x05B68  /* MSIx PBA Clear - Read/Write 1's to clear */
289
-#define E1000_FFLT     0x05F00  /* Flexible Filter Length Table - RW Array */
290
-#define E1000_HOST_IF  0x08800  /* Host Interface */
291
-#define E1000_FFMT     0x09000  /* Flexible Filter Mask Table - RW Array */
292
-#define E1000_FFVT     0x09800  /* Flexible Filter Value Table - RW Array */
293
-
294
-#define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */
295
-#define E1000_MDPHYA      0x0003C /* PHY address - RW */
296
-#define E1000_MANC2H      0x05860 /* Management Control To Host - RW */
297
-#define E1000_SW_FW_SYNC  0x05B5C /* Software-Firmware Synchronization - RW */
298
-#define E1000_CCMCTL      0x05B48 /* CCM Control Register */
299
-#define E1000_GIOCTL      0x05B44 /* GIO Analog Control Register */
300
-#define E1000_SCCTL       0x05B4C /* PCIc PLL Configuration Register */
301
-#define E1000_GCR         0x05B00 /* PCI-Ex Control */
302
-#define E1000_GCR2        0x05B64 /* PCI-Ex Control #2 */
303
-#define E1000_GSCL_1    0x05B10 /* PCI-Ex Statistic Control #1 */
304
-#define E1000_GSCL_2    0x05B14 /* PCI-Ex Statistic Control #2 */
305
-#define E1000_GSCL_3    0x05B18 /* PCI-Ex Statistic Control #3 */
306
-#define E1000_GSCL_4    0x05B1C /* PCI-Ex Statistic Control #4 */
307
-#define E1000_FACTPS    0x05B30 /* Function Active and Power State to MNG */
308
-#define E1000_SWSM      0x05B50 /* SW Semaphore */
309
-#define E1000_FWSM      0x05B54 /* FW Semaphore */
310
-#define E1000_SWSM2     0x05B58 /* Driver-only SW semaphore (not used by BOOT agents) */
311
-#define E1000_DCA_ID    0x05B70 /* DCA Requester ID Information - RO */
312
-#define E1000_DCA_CTRL  0x05B74 /* DCA Control - RW */
313
-#define E1000_FFLT_DBG  0x05F04 /* Debug Register */
314
-#define E1000_HICR      0x08F00 /* Host Interface Control */
315
-
316
-/* RSS registers */
317
-#define E1000_CPUVEC    0x02C10 /* CPU Vector Register - RW */
318
-#define E1000_MRQC      0x05818 /* Multiple Receive Control - RW */
319
-#define E1000_IMIR(_i)      (0x05A80 + ((_i) * 4))  /* Immediate Interrupt */
320
-#define E1000_IMIREXT(_i)   (0x05AA0 + ((_i) * 4))  /* Immediate Interrupt Ext*/
321
-#define E1000_IMIRVP    0x05AC0 /* Immediate Interrupt Rx VLAN Priority - RW */
322
-#define E1000_MSIXBM(_i)    (0x01600 + ((_i) * 4)) /* MSI-X Allocation Register
323
-                                                    * (_i) - RW */
324
-#define E1000_MSIXTADD(_i)  (0x0C000 + ((_i) * 0x10)) /* MSI-X Table entry addr
325
-                                                       * low reg - RW */
326
-#define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10)) /* MSI-X Table entry addr
327
-                                                       * upper reg - RW */
328
-#define E1000_MSIXTMSG(_i)  (0x0C008 + ((_i) * 0x10)) /* MSI-X Table entry
329
-                                                       * message reg - RW */
330
-#define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10)) /* MSI-X Table entry
331
-                                                       * vector ctrl reg - RW */
332
-#define E1000_MSIXPBA    0x0E000 /* MSI-X Pending bit array */
333
-#define E1000_RETA(_i)  (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */
334
-#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */
335
-#define E1000_RSSIM     0x05864 /* RSS Interrupt Mask */
336
-#define E1000_RSSIR     0x05868 /* RSS Interrupt Request */
337
-#define E1000_RXMTRL     0x0B634 /* Time sync Rx EtherType and Msg Type - RW */
338
-#define E1000_RXUDP      0x0B638 /* Time Sync Rx UDP Port - RW */
339
-
340
-#endif

+ 0
- 32
src/drivers/net/igb/igb.c Прегледај датотеку

@@ -1,32 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel PRO/1000 Linux driver
4
-  Copyright(c) 1999 - 2008 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  Linux NICS <linux.nics@intel.com>
24
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
-
27
-*******************************************************************************/
28
-
29
-FILE_LICENCE ( GPL2_ONLY );
30
-
31
-REQUIRE_OBJECT(igb_main);
32
-REQUIRE_OBJECT(igb_82575);

+ 0
- 324
src/drivers/net/igb/igb.h Прегледај датотеку

@@ -1,324 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel(R) Gigabit Ethernet Linux driver
4
-  Copyright(c) 2007-2009 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
-
26
-*******************************************************************************/
27
-
28
-FILE_LICENCE ( GPL2_ONLY );
29
-
30
-/* Linux PRO/1000 Ethernet Driver main header file */
31
-
32
-#ifndef _IGB_H_
33
-#define _IGB_H_
34
-
35
-#include "igb_api.h"
36
-
37
-extern int igb_probe ( struct pci_device *pdev );
38
-extern void igb_remove ( struct pci_device *pdev );
39
-
40
-struct igb_adapter;
41
-
42
-/* Interrupt defines */
43
-#define IGB_START_ITR                    648 /* ~6000 ints/sec */
44
-
45
-/* Interrupt modes, as used by the IntMode paramter */
46
-#define IGB_INT_MODE_LEGACY                0
47
-#define IGB_INT_MODE_MSI                   1
48
-#define IGB_INT_MODE_MSIX                  2
49
-
50
-#define HW_PERF
51
-/* TX/RX descriptor defines */
52
-#define IGB_DEFAULT_TXD                  256
53
-#define IGB_MIN_TXD                       80
54
-#define IGB_MAX_TXD                     4096
55
-
56
-#define IGB_DEFAULT_RXD                  256
57
-#define IGB_MIN_RXD                       80
58
-#define IGB_MAX_RXD                     4096
59
-
60
-#define IGB_MIN_ITR_USECS                 10 /* 100k irq/sec */
61
-#define IGB_MAX_ITR_USECS               8191 /* 120  irq/sec */
62
-
63
-#define NON_Q_VECTORS                      1
64
-#define MAX_Q_VECTORS                      8
65
-
66
-/* Transmit and receive queues */
67
-#define IGB_MAX_RX_QUEUES                  (adapter->vfs_allocated_count ? 2 : \
68
-                                           (hw->mac.type > e1000_82575 ? 8 : 4))
69
-#define IGB_ABS_MAX_TX_QUEUES              8
70
-#define IGB_MAX_TX_QUEUES                  IGB_MAX_RX_QUEUES
71
-
72
-#define IGB_MAX_VF_MC_ENTRIES              30
73
-#define IGB_MAX_VF_FUNCTIONS               8
74
-#define IGB_MAX_VFTA_ENTRIES               128
75
-#define IGB_MAX_UTA_ENTRIES                128
76
-#define MAX_EMULATION_MAC_ADDRS            16
77
-#define OUI_LEN                            3
78
-
79
-struct vf_data_storage {
80
-	unsigned char vf_mac_addresses[ETH_ALEN];
81
-	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
82
-	u16 num_vf_mc_hashes;
83
-	u16 default_vf_vlan_id;
84
-	u16 vlans_enabled;
85
-	unsigned char em_mac_addresses[MAX_EMULATION_MAC_ADDRS * ETH_ALEN];
86
-	u32 uta_table_copy[IGB_MAX_UTA_ENTRIES];
87
-	u32 flags;
88
-	unsigned long last_nack;
89
-};
90
-
91
-#define IGB_VF_FLAG_CTS            0x00000001 /* VF is clear to send data */
92
-#define IGB_VF_FLAG_UNI_PROMISC    0x00000002 /* VF has unicast promisc */
93
-#define IGB_VF_FLAG_MULTI_PROMISC  0x00000004 /* VF has multicast promisc */
94
-
95
-/* RX descriptor control thresholds.
96
- * PTHRESH - MAC will consider prefetch if it has fewer than this number of
97
- *           descriptors available in its onboard memory.
98
- *           Setting this to 0 disables RX descriptor prefetch.
99
- * HTHRESH - MAC will only prefetch if there are at least this many descriptors
100
- *           available in host memory.
101
- *           If PTHRESH is 0, this should also be 0.
102
- * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
103
- *           descriptors until either it has this many to write back, or the
104
- *           ITR timer expires.
105
- */
106
-#define IGB_RX_PTHRESH                    (hw->mac.type <= e1000_82576 ? 16 : 8)
107
-#define IGB_RX_HTHRESH                     8
108
-#define IGB_RX_WTHRESH                     1
109
-#define IGB_TX_PTHRESH                     8
110
-#define IGB_TX_HTHRESH                     1
111
-#define IGB_TX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
112
-                                             adapter->msix_entries) ? 0 : 16)
113
-
114
-/* this is the size past which hardware will drop packets when setting LPE=0 */
115
-#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
116
-
117
-/* Supported Rx Buffer Sizes */
118
-#define IGB_RXBUFFER_128   128    /* Used for packet split */
119
-#define IGB_RXBUFFER_256   256    /* Used for packet split */
120
-#define IGB_RXBUFFER_512   512
121
-#define IGB_RXBUFFER_1024  1024
122
-#define IGB_RXBUFFER_2048  2048
123
-#define IGB_RXBUFFER_4096  4096
124
-#define IGB_RXBUFFER_8192  8192
125
-#define IGB_RXBUFFER_16384 16384
126
-
127
-/* Packet Buffer allocations */
128
-#define IGB_PBA_BYTES_SHIFT 0xA
129
-#define IGB_TX_HEAD_ADDR_SHIFT 7
130
-#define IGB_PBA_TX_MASK 0xFFFF0000
131
-
132
-#define IGB_FC_PAUSE_TIME 0x0680 /* 858 usec */
133
-
134
-/* How many Tx Descriptors do we need to call netif_wake_queue ? */
135
-#define IGB_TX_QUEUE_WAKE	32
136
-/* How many Rx Buffers do we bundle into one write to the hardware ? */
137
-#define IGB_RX_BUFFER_WRITE	16	/* Must be power of 2 */
138
-
139
-#define AUTO_ALL_MODES            0
140
-#define IGB_EEPROM_APME         0x0400
141
-
142
-#ifndef IGB_MASTER_SLAVE
143
-/* Switch to override PHY master/slave setting */
144
-#define IGB_MASTER_SLAVE	e1000_ms_hw_default
145
-#endif
146
-
147
-#define IGB_MNG_VLAN_NONE -1
148
-
149
-/* wrapper around a pointer to a socket buffer,
150
- * so a DMA handle can be stored along with the buffer */
151
-struct igb_buffer {
152
-	struct sk_buff *skb;
153
-	dma_addr_t dma;
154
-	dma_addr_t page_dma;
155
-	union {
156
-		/* TX */
157
-		struct {
158
-			unsigned long time_stamp;
159
-			u16 length;
160
-			u16 next_to_watch;
161
-		};
162
-
163
-#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT
164
-		/* RX */
165
-		struct {
166
-			unsigned long page_offset;
167
-			struct page *page;
168
-		};
169
-#endif
170
-	};
171
-};
172
-
173
-struct igb_queue_stats {
174
-	u64 packets;
175
-	u64 bytes;
176
-};
177
-
178
-struct igb_q_vector {
179
-	struct igb_adapter *adapter; /* backlink */
180
-	struct igb_ring *rx_ring;
181
-	struct igb_ring *tx_ring;
182
-#if 0
183
-	struct napi_struct napi;
184
-#endif
185
-	u32 eims_value;
186
-	u16 cpu;
187
-
188
-	u16 itr_val;
189
-	u8 set_itr;
190
-	u8 itr_shift;
191
-	void __iomem *itr_register;
192
-
193
-#if 0
194
-	char name[IFNAMSIZ + 9];
195
-#endif
196
-#ifndef HAVE_NETDEV_NAPI_LIST
197
-	struct net_device poll_dev;
198
-#endif
199
-};
200
-
201
-struct igb_ring {
202
-	struct igb_q_vector *q_vector; /* backlink to q_vector */
203
-	struct pci_dev *pdev;          /* pci device for dma mapping */
204
-	dma_addr_t dma;                /* phys address of the ring */
205
-	void *desc;                    /* descriptor ring memory */
206
-	unsigned int size;             /* length of desc. ring in bytes */
207
-	u16 count;                     /* number of desc. in the ring */
208
-	u16 next_to_use;
209
-	u16 next_to_clean;
210
-	u8 queue_index;
211
-	u8 reg_idx;
212
-	void __iomem *head;
213
-	void __iomem *tail;
214
-	struct igb_buffer *buffer_info; /* array of buffer info structs */
215
-
216
-	unsigned int total_bytes;
217
-	unsigned int total_packets;
218
-
219
-	struct igb_queue_stats stats;
220
-
221
-	union {
222
-		/* TX */
223
-		struct {
224
-			unsigned int restart_queue;
225
-			u32 ctx_idx;
226
-			bool detect_tx_hung;
227
-		};
228
-		/* RX */
229
-		struct {
230
-			u64 hw_csum_err;
231
-			u64 hw_csum_good;
232
-			u32 rx_buffer_len;
233
-			u16 rx_ps_hdr_size;
234
-			bool rx_csum;
235
-#ifdef IGB_LRO
236
-			struct net_lro_mgr lro_mgr;
237
-			bool lro_used;
238
-#endif
239
-		};
240
-	};
241
-};
242
-
243
-
244
-#define IGB_ADVTXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
245
-
246
-#define IGB_DESC_UNUSED(R) \
247
-	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
248
-	(R)->next_to_clean - (R)->next_to_use - 1)
249
-
250
-#define E1000_RX_DESC_ADV(R, i)	    \
251
-	(&(((union e1000_adv_rx_desc *)((R).desc))[i]))
252
-#define E1000_TX_DESC_ADV(R, i)	    \
253
-	(&(((union e1000_adv_tx_desc *)((R).desc))[i]))
254
-#define E1000_TX_CTXTDESC_ADV(R, i)	    \
255
-	(&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
256
-#define E1000_GET_DESC(R, i, type)	(&(((struct type *)((R).desc))[i]))
257
-#define E1000_TX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_tx_desc)
258
-#define E1000_RX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_rx_desc)
259
-
260
-#define MAX_MSIX_COUNT 10
261
-/* board specific private data structure */
262
-
263
-/* board specific private data structure */
264
-struct igb_adapter {
265
-
266
-	/* OS defined structs */
267
-	struct net_device *netdev;
268
-	struct pci_device *pdev;
269
-	struct net_device_stats net_stats;
270
-
271
-	/* structs defined in e1000_hw.h */
272
-	struct e1000_hw hw;
273
-
274
-	struct e1000_phy_info phy_info;
275
-
276
-        u32 min_frame_size;
277
-        u32 max_frame_size;
278
-
279
-	u32 wol;
280
-	u32 pba;
281
-	u32 max_hw_frame_size;
282
-
283
-	bool fc_autoneg;
284
-
285
-	unsigned int flags;
286
-	unsigned int flags2;
287
-
288
-#define NUM_TX_DESC	8
289
-#define NUM_RX_DESC	8
290
-
291
-	struct io_buffer *tx_iobuf[NUM_TX_DESC];
292
-	struct io_buffer *rx_iobuf[NUM_RX_DESC];
293
-
294
-	struct e1000_tx_desc *tx_base;
295
-	struct e1000_rx_desc *rx_base;
296
-
297
-	uint32_t tx_ring_size;
298
-	uint32_t rx_ring_size;
299
-
300
-	uint32_t tx_head;
301
-	uint32_t tx_tail;
302
-	uint32_t tx_fill_ctr;
303
-
304
-	uint32_t rx_curr;
305
-
306
-	uint32_t ioaddr;
307
-	uint32_t irqno;
308
-
309
-        uint32_t tx_int_delay;
310
-        uint32_t tx_abs_int_delay;
311
-        uint32_t txd_cmd;
312
-};
313
-
314
-#define IGB_FLAG_HAS_MSI           (1 << 0)
315
-#define IGB_FLAG_MSI_ENABLE        (1 << 1)
316
-#define IGB_FLAG_DCA_ENABLED       (1 << 3)
317
-#define IGB_FLAG_LLI_PUSH          (1 << 4)
318
-#define IGB_FLAG_IN_NETPOLL        (1 << 5)
319
-#define IGB_FLAG_QUAD_PORT_A       (1 << 6)
320
-#define IGB_FLAG_QUEUE_PAIRS       (1 << 7)
321
-
322
-#define IGB_82576_TSYNC_SHIFT 19
323
-
324
-#endif /* _IGB_H_ */

+ 0
- 1617
src/drivers/net/igb/igb_82575.c
Разлика између датотеке није приказан због своје велике величине
Прегледај датотеку


+ 0
- 442
src/drivers/net/igb/igb_82575.h Прегледај датотеку

@@ -1,442 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel(R) Gigabit Ethernet Linux driver
4
-  Copyright(c) 2007-2009 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
-
26
-*******************************************************************************/
27
-
28
-FILE_LICENCE ( GPL2_ONLY );
29
-
30
-#ifndef _IGB_82575_H_
31
-#define _IGB_82575_H_
32
-
33
-#define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
34
-                                     (ID_LED_DEF1_DEF2 <<  8) | \
35
-                                     (ID_LED_DEF1_DEF2 <<  4) | \
36
-                                     (ID_LED_OFF1_ON2))
37
-/*
38
- * Receive Address Register Count
39
- * Number of high/low register pairs in the RAR.  The RAR (Receive Address
40
- * Registers) holds the directed and multicast addresses that we monitor.
41
- * These entries are also used for MAC-based filtering.
42
- */
43
-/*
44
- * For 82576, there are an additional set of RARs that begin at an offset
45
- * separate from the first set of RARs.
46
- */
47
-#define E1000_RAR_ENTRIES_82575   16
48
-#define E1000_RAR_ENTRIES_82576   24
49
-
50
-struct e1000_adv_data_desc {
51
-	__le64 buffer_addr;    /* Address of the descriptor's data buffer */
52
-	union {
53
-		u32 data;
54
-		struct {
55
-			u32 datalen :16; /* Data buffer length */
56
-			u32 rsvd    :4;
57
-			u32 dtyp    :4;  /* Descriptor type */
58
-			u32 dcmd    :8;  /* Descriptor command */
59
-		} config;
60
-	} lower;
61
-	union {
62
-		u32 data;
63
-		struct {
64
-			u32 status  :4;  /* Descriptor status */
65
-			u32 idx     :4;
66
-			u32 popts   :6;  /* Packet Options */
67
-			u32 paylen  :18; /* Payload length */
68
-		} options;
69
-	} upper;
70
-};
71
-
72
-#define E1000_TXD_DTYP_ADV_C    0x2  /* Advanced Context Descriptor */
73
-#define E1000_TXD_DTYP_ADV_D    0x3  /* Advanced Data Descriptor */
74
-#define E1000_ADV_TXD_CMD_DEXT  0x20 /* Descriptor extension (0 = legacy) */
75
-#define E1000_ADV_TUCMD_IPV4    0x2  /* IP Packet Type: 1=IPv4 */
76
-#define E1000_ADV_TUCMD_IPV6    0x0  /* IP Packet Type: 0=IPv6 */
77
-#define E1000_ADV_TUCMD_L4T_UDP 0x0  /* L4 Packet TYPE of UDP */
78
-#define E1000_ADV_TUCMD_L4T_TCP 0x4  /* L4 Packet TYPE of TCP */
79
-#define E1000_ADV_TUCMD_MKRREQ  0x10 /* Indicates markers are required */
80
-#define E1000_ADV_DCMD_EOP      0x1  /* End of Packet */
81
-#define E1000_ADV_DCMD_IFCS     0x2  /* Insert FCS (Ethernet CRC) */
82
-#define E1000_ADV_DCMD_RS       0x8  /* Report Status */
83
-#define E1000_ADV_DCMD_VLE      0x40 /* Add VLAN tag */
84
-#define E1000_ADV_DCMD_TSE      0x80 /* TCP Seg enable */
85
-/* Extended Device Control */
86
-#define E1000_CTRL_EXT_NSICR    0x00000001 /* Disable Intr Clear all on read */
87
-
88
-struct e1000_adv_context_desc {
89
-	union {
90
-		u32 ip_config;
91
-		struct {
92
-			u32 iplen    :9;
93
-			u32 maclen   :7;
94
-			u32 vlan_tag :16;
95
-		} fields;
96
-	} ip_setup;
97
-	u32 seq_num;
98
-	union {
99
-		u64 l4_config;
100
-		struct {
101
-			u32 mkrloc :9;
102
-			u32 tucmd  :11;
103
-			u32 dtyp   :4;
104
-			u32 adv    :8;
105
-			u32 rsvd   :4;
106
-			u32 idx    :4;
107
-			u32 l4len  :8;
108
-			u32 mss    :16;
109
-		} fields;
110
-	} l4_setup;
111
-};
112
-
113
-/* SRRCTL bit definitions */
114
-#define E1000_SRRCTL_BSIZEPKT_SHIFT                     10 /* Shift _right_ */
115
-#define E1000_SRRCTL_BSIZEHDRSIZE_MASK                  0x00000F00
116
-#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT                 2  /* Shift _left_ */
117
-#define E1000_SRRCTL_DESCTYPE_LEGACY                    0x00000000
118
-#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF                0x02000000
119
-#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT                 0x04000000
120
-#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS          0x0A000000
121
-#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION           0x06000000
122
-#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
123
-#define E1000_SRRCTL_DESCTYPE_MASK                      0x0E000000
124
-#define E1000_SRRCTL_DROP_EN                            0x80000000
125
-
126
-#define E1000_SRRCTL_BSIZEPKT_MASK      0x0000007F
127
-#define E1000_SRRCTL_BSIZEHDR_MASK      0x00003F00
128
-
129
-#define E1000_TX_HEAD_WB_ENABLE   0x1
130
-#define E1000_TX_SEQNUM_WB_ENABLE 0x2
131
-
132
-#define E1000_MRQC_ENABLE_RSS_4Q            0x00000002
133
-#define E1000_MRQC_ENABLE_VMDQ              0x00000003
134
-#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q       0x00000005
135
-#define E1000_MRQC_RSS_FIELD_IPV4_UDP       0x00400000
136
-#define E1000_MRQC_RSS_FIELD_IPV6_UDP       0x00800000
137
-#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX    0x01000000
138
-
139
-#define E1000_VMRCTL_MIRROR_PORT_SHIFT      8
140
-#define E1000_VMRCTL_MIRROR_DSTPORT_MASK    (7 << E1000_VMRCTL_MIRROR_PORT_SHIFT)
141
-#define E1000_VMRCTL_POOL_MIRROR_ENABLE     (1 << 0)
142
-#define E1000_VMRCTL_UPLINK_MIRROR_ENABLE   (1 << 1)
143
-#define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE (1 << 2)
144
-
145
-#define E1000_EICR_TX_QUEUE ( \
146
-    E1000_EICR_TX_QUEUE0 |    \
147
-    E1000_EICR_TX_QUEUE1 |    \
148
-    E1000_EICR_TX_QUEUE2 |    \
149
-    E1000_EICR_TX_QUEUE3)
150
-
151
-#define E1000_EICR_RX_QUEUE ( \
152
-    E1000_EICR_RX_QUEUE0 |    \
153
-    E1000_EICR_RX_QUEUE1 |    \
154
-    E1000_EICR_RX_QUEUE2 |    \
155
-    E1000_EICR_RX_QUEUE3)
156
-
157
-#define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE
158
-#define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE
159
-
160
-#define EIMS_ENABLE_MASK ( \
161
-    E1000_EIMS_RX_QUEUE  | \
162
-    E1000_EIMS_TX_QUEUE  | \
163
-    E1000_EIMS_TCP_TIMER | \
164
-    E1000_EIMS_OTHER)
165
-
166
-/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
167
-#define E1000_IMIR_PORT_IM_EN     0x00010000  /* TCP port enable */
168
-#define E1000_IMIR_PORT_BP        0x00020000  /* TCP port check bypass */
169
-#define E1000_IMIREXT_SIZE_BP     0x00001000  /* Packet size bypass */
170
-#define E1000_IMIREXT_CTRL_URG    0x00002000  /* Check URG bit in header */
171
-#define E1000_IMIREXT_CTRL_ACK    0x00004000  /* Check ACK bit in header */
172
-#define E1000_IMIREXT_CTRL_PSH    0x00008000  /* Check PSH bit in header */
173
-#define E1000_IMIREXT_CTRL_RST    0x00010000  /* Check RST bit in header */
174
-#define E1000_IMIREXT_CTRL_SYN    0x00020000  /* Check SYN bit in header */
175
-#define E1000_IMIREXT_CTRL_FIN    0x00040000  /* Check FIN bit in header */
176
-#define E1000_IMIREXT_CTRL_BP     0x00080000  /* Bypass check of ctrl bits */
177
-
178
-/* Receive Descriptor - Advanced */
179
-union e1000_adv_rx_desc {
180
-	struct {
181
-		__le64 pkt_addr;             /* Packet buffer address */
182
-		__le64 hdr_addr;             /* Header buffer address */
183
-	} read;
184
-	struct {
185
-		struct {
186
-			union {
187
-				__le32 data;
188
-				struct {
189
-					__le16 pkt_info; /*RSS type, Pkt type*/
190
-					__le16 hdr_info; /* Split Header,
191
-							  * header buffer len*/
192
-				} hs_rss;
193
-			} lo_dword;
194
-			union {
195
-				__le32 rss;          /* RSS Hash */
196
-				struct {
197
-					__le16 ip_id;    /* IP id */
198
-					__le16 csum;     /* Packet Checksum */
199
-				} csum_ip;
200
-			} hi_dword;
201
-		} lower;
202
-		struct {
203
-			__le32 status_error;     /* ext status/error */
204
-			__le16 length;           /* Packet length */
205
-			__le16 vlan;             /* VLAN tag */
206
-		} upper;
207
-	} wb;  /* writeback */
208
-};
209
-
210
-#define E1000_RXDADV_RSSTYPE_MASK        0x0000000F
211
-#define E1000_RXDADV_RSSTYPE_SHIFT       12
212
-#define E1000_RXDADV_HDRBUFLEN_MASK      0x7FE0
213
-#define E1000_RXDADV_HDRBUFLEN_SHIFT     5
214
-#define E1000_RXDADV_SPLITHEADER_EN      0x00001000
215
-#define E1000_RXDADV_SPH                 0x8000
216
-#define E1000_RXDADV_STAT_TS             0x10000 /* Pkt was time stamped */
217
-#define E1000_RXDADV_ERR_HBO             0x00800000
218
-
219
-/* RSS Hash results */
220
-#define E1000_RXDADV_RSSTYPE_NONE        0x00000000
221
-#define E1000_RXDADV_RSSTYPE_IPV4_TCP    0x00000001
222
-#define E1000_RXDADV_RSSTYPE_IPV4        0x00000002
223
-#define E1000_RXDADV_RSSTYPE_IPV6_TCP    0x00000003
224
-#define E1000_RXDADV_RSSTYPE_IPV6_EX     0x00000004
225
-#define E1000_RXDADV_RSSTYPE_IPV6        0x00000005
226
-#define E1000_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
227
-#define E1000_RXDADV_RSSTYPE_IPV4_UDP    0x00000007
228
-#define E1000_RXDADV_RSSTYPE_IPV6_UDP    0x00000008
229
-#define E1000_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
230
-
231
-/* RSS Packet Types as indicated in the receive descriptor */
232
-#define E1000_RXDADV_PKTTYPE_NONE        0x00000000
233
-#define E1000_RXDADV_PKTTYPE_IPV4        0x00000010 /* IPV4 hdr present */
234
-#define E1000_RXDADV_PKTTYPE_IPV4_EX     0x00000020 /* IPV4 hdr + extensions */
235
-#define E1000_RXDADV_PKTTYPE_IPV6        0x00000040 /* IPV6 hdr present */
236
-#define E1000_RXDADV_PKTTYPE_IPV6_EX     0x00000080 /* IPV6 hdr + extensions */
237
-#define E1000_RXDADV_PKTTYPE_TCP         0x00000100 /* TCP hdr present */
238
-#define E1000_RXDADV_PKTTYPE_UDP         0x00000200 /* UDP hdr present */
239
-#define E1000_RXDADV_PKTTYPE_SCTP        0x00000400 /* SCTP hdr present */
240
-#define E1000_RXDADV_PKTTYPE_NFS         0x00000800 /* NFS hdr present */
241
-
242
-#define E1000_RXDADV_PKTTYPE_IPSEC_ESP   0x00001000 /* IPSec ESP */
243
-#define E1000_RXDADV_PKTTYPE_IPSEC_AH    0x00002000 /* IPSec AH */
244
-#define E1000_RXDADV_PKTTYPE_LINKSEC     0x00004000 /* LinkSec Encap */
245
-#define E1000_RXDADV_PKTTYPE_ETQF        0x00008000 /* PKTTYPE is ETQF index */
246
-#define E1000_RXDADV_PKTTYPE_ETQF_MASK   0x00000070 /* ETQF has 8 indices */
247
-#define E1000_RXDADV_PKTTYPE_ETQF_SHIFT  4          /* Right-shift 4 bits */
248
-
249
-/* LinkSec results */
250
-/* Security Processing bit Indication */
251
-#define E1000_RXDADV_LNKSEC_STATUS_SECP         0x00020000
252
-#define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK      0x18000000
253
-#define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH   0x08000000
254
-#define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR  0x10000000
255
-#define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG       0x18000000
256
-
257
-#define E1000_RXDADV_IPSEC_STATUS_SECP          0x00020000
258
-#define E1000_RXDADV_IPSEC_ERROR_BIT_MASK       0x18000000
259
-#define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL       0x08000000
260
-#define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH         0x10000000
261
-#define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED  0x18000000
262
-
263
-/* Transmit Descriptor - Advanced */
264
-union e1000_adv_tx_desc {
265
-	struct {
266
-		__le64 buffer_addr;    /* Address of descriptor's data buf */
267
-		__le32 cmd_type_len;
268
-		__le32 olinfo_status;
269
-	} read;
270
-	struct {
271
-		__le64 rsvd;       /* Reserved */
272
-		__le32 nxtseq_seed;
273
-		__le32 status;
274
-	} wb;
275
-};
276
-
277
-/* Adv Transmit Descriptor Config Masks */
278
-#define E1000_ADVTXD_DTYP_CTXT    0x00200000 /* Advanced Context Descriptor */
279
-#define E1000_ADVTXD_DTYP_DATA    0x00300000 /* Advanced Data Descriptor */
280
-#define E1000_ADVTXD_DCMD_EOP     0x01000000 /* End of Packet */
281
-#define E1000_ADVTXD_DCMD_IFCS    0x02000000 /* Insert FCS (Ethernet CRC) */
282
-#define E1000_ADVTXD_DCMD_RS      0x08000000 /* Report Status */
283
-#define E1000_ADVTXD_DCMD_DDTYP_ISCSI  0x10000000 /* DDP hdr type or iSCSI */
284
-#define E1000_ADVTXD_DCMD_DEXT    0x20000000 /* Descriptor extension (1=Adv) */
285
-#define E1000_ADVTXD_DCMD_VLE     0x40000000 /* VLAN pkt enable */
286
-#define E1000_ADVTXD_DCMD_TSE     0x80000000 /* TCP Seg enable */
287
-#define E1000_ADVTXD_MAC_LINKSEC  0x00040000 /* Apply LinkSec on packet */
288
-#define E1000_ADVTXD_MAC_TSTAMP   0x00080000 /* IEEE1588 Timestamp packet */
289
-#define E1000_ADVTXD_STAT_SN_CRC  0x00000002 /* NXTSEQ/SEED present in WB */
290
-#define E1000_ADVTXD_IDX_SHIFT    4  /* Adv desc Index shift */
291
-#define E1000_ADVTXD_POPTS_ISCO_1ST  0x00000000 /* 1st TSO of iSCSI PDU */
292
-#define E1000_ADVTXD_POPTS_ISCO_MDL  0x00000800 /* Middle TSO of iSCSI PDU */
293
-#define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
294
-#define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU*/
295
-#define E1000_ADVTXD_POPTS_IPSEC     0x00000400 /* IPSec offload request */
296
-#define E1000_ADVTXD_PAYLEN_SHIFT    14 /* Adv desc PAYLEN shift */
297
-
298
-/* Context descriptors */
299
-struct e1000_adv_tx_context_desc {
300
-	__le32 vlan_macip_lens;
301
-	__le32 seqnum_seed;
302
-	__le32 type_tucmd_mlhl;
303
-	__le32 mss_l4len_idx;
304
-};
305
-
306
-#define E1000_ADVTXD_MACLEN_SHIFT    9  /* Adv ctxt desc mac len shift */
307
-#define E1000_ADVTXD_VLAN_SHIFT     16  /* Adv ctxt vlan tag shift */
308
-#define E1000_ADVTXD_TUCMD_IPV4    0x00000400  /* IP Packet Type: 1=IPv4 */
309
-#define E1000_ADVTXD_TUCMD_IPV6    0x00000000  /* IP Packet Type: 0=IPv6 */
310
-#define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000  /* L4 Packet TYPE of UDP */
311
-#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800  /* L4 Packet TYPE of TCP */
312
-#define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000  /* L4 Packet TYPE of SCTP */
313
-#define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP    0x00002000 /* IPSec Type ESP */
314
-/* IPSec Encrypt Enable for ESP */
315
-#define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN  0x00004000
316
-#define E1000_ADVTXD_TUCMD_MKRREQ  0x00002000 /* Req requires Markers and CRC */
317
-#define E1000_ADVTXD_L4LEN_SHIFT     8  /* Adv ctxt L4LEN shift */
318
-#define E1000_ADVTXD_MSS_SHIFT      16  /* Adv ctxt MSS shift */
319
-/* Adv ctxt IPSec SA IDX mask */
320
-#define E1000_ADVTXD_IPSEC_SA_INDEX_MASK     0x000000FF
321
-/* Adv ctxt IPSec ESP len mask */
322
-#define E1000_ADVTXD_IPSEC_ESP_LEN_MASK      0x000000FF
323
-
324
-/* Additional Transmit Descriptor Control definitions */
325
-#define E1000_TXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Tx Queue */
326
-#define E1000_TXDCTL_SWFLSH        0x04000000 /* Tx Desc. write-back flushing */
327
-/* Tx Queue Arbitration Priority 0=low, 1=high */
328
-#define E1000_TXDCTL_PRIORITY      0x08000000
329
-
330
-/* Additional Receive Descriptor Control definitions */
331
-#define E1000_RXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Rx Queue */
332
-#define E1000_RXDCTL_SWFLSH        0x04000000 /* Rx Desc. write-back flushing */
333
-
334
-/* Direct Cache Access (DCA) definitions */
335
-#define E1000_DCA_CTRL_DCA_ENABLE  0x00000000 /* DCA Enable */
336
-#define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
337
-
338
-#define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
339
-#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
340
-
341
-#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
342
-#define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
343
-#define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
344
-#define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
345
-
346
-#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
347
-#define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
348
-#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
349
-
350
-#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
351
-#define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
352
-#define E1000_DCA_TXCTRL_CPUID_SHIFT_82576 24 /* Tx CPUID */
353
-#define E1000_DCA_RXCTRL_CPUID_SHIFT_82576 24 /* Rx CPUID */
354
-
355
-/* Additional interrupt register bit definitions */
356
-#define E1000_ICR_LSECPNS       0x00000020          /* PN threshold - server */
357
-#define E1000_IMS_LSECPNS       E1000_ICR_LSECPNS   /* PN threshold - server */
358
-#define E1000_ICS_LSECPNS       E1000_ICR_LSECPNS   /* PN threshold - server */
359
-
360
-/* ETQF register bit definitions */
361
-#define E1000_ETQF_FILTER_ENABLE   (1 << 26)
362
-#define E1000_ETQF_IMM_INT         (1 << 29)
363
-#define E1000_ETQF_1588            (1 << 30)
364
-#define E1000_ETQF_QUEUE_ENABLE    (1 << 31)
365
-/*
366
- * ETQF filter list: one static filter per filter consumer. This is
367
- *                   to avoid filter collisions later. Add new filters
368
- *                   here!!
369
- *
370
- * Current filters:
371
- *    EAPOL 802.1x (0x888e): Filter 0
372
- */
373
-#define E1000_ETQF_FILTER_EAPOL          0
374
-
375
-#define E1000_FTQF_VF_BP               0x00008000
376
-#define E1000_FTQF_1588_TIME_STAMP     0x08000000
377
-#define E1000_FTQF_MASK                0xF0000000
378
-#define E1000_FTQF_MASK_PROTO_BP       0x10000000
379
-#define E1000_FTQF_MASK_SOURCE_ADDR_BP 0x20000000
380
-#define E1000_FTQF_MASK_DEST_ADDR_BP   0x40000000
381
-#define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000
382
-
383
-#define E1000_NVM_APME_82575          0x0400
384
-#define MAX_NUM_VFS                   8
385
-
386
-#define E1000_DTXSWC_MAC_SPOOF_MASK   0x000000FF /* Per VF MAC spoof control */
387
-#define E1000_DTXSWC_VLAN_SPOOF_MASK  0x0000FF00 /* Per VF VLAN spoof control */
388
-#define E1000_DTXSWC_LLE_MASK         0x00FF0000 /* Per VF Local LB enables */
389
-#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
390
-#define E1000_DTXSWC_LLE_SHIFT        16
391
-#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31)  /* global VF LB enable */
392
-
393
-/* Easy defines for setting default pool, would normally be left a zero */
394
-#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
395
-#define E1000_VT_CTL_DEFAULT_POOL_MASK  (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
396
-
397
-/* Other useful VMD_CTL register defines */
398
-#define E1000_VT_CTL_IGNORE_MAC         (1 << 28)
399
-#define E1000_VT_CTL_DISABLE_DEF_POOL   (1 << 29)
400
-#define E1000_VT_CTL_VM_REPL_EN         (1 << 30)
401
-
402
-/* Per VM Offload register setup */
403
-#define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
404
-#define E1000_VMOLR_LPE        0x00010000 /* Accept Long packet */
405
-#define E1000_VMOLR_RSSE       0x00020000 /* Enable RSS */
406
-#define E1000_VMOLR_AUPE       0x01000000 /* Accept untagged packets */
407
-#define E1000_VMOLR_ROMPE      0x02000000 /* Accept overflow multicast */
408
-#define E1000_VMOLR_ROPE       0x04000000 /* Accept overflow unicast */
409
-#define E1000_VMOLR_BAM        0x08000000 /* Accept Broadcast packets */
410
-#define E1000_VMOLR_MPME       0x10000000 /* Multicast promiscuous mode */
411
-#define E1000_VMOLR_STRVLAN    0x40000000 /* Vlan stripping enable */
412
-#define E1000_VMOLR_STRCRC     0x80000000 /* CRC stripping enable */
413
-
414
-#define E1000_VLVF_ARRAY_SIZE     32
415
-#define E1000_VLVF_VLANID_MASK    0x00000FFF
416
-#define E1000_VLVF_POOLSEL_SHIFT  12
417
-#define E1000_VLVF_POOLSEL_MASK   (0xFF << E1000_VLVF_POOLSEL_SHIFT)
418
-#define E1000_VLVF_LVLAN          0x00100000
419
-#define E1000_VLVF_VLANID_ENABLE  0x80000000
420
-
421
-#define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
422
-
423
-#define E1000_IOVCTL 0x05BBC
424
-#define E1000_IOVCTL_REUSE_VFQ 0x00000001
425
-
426
-#define E1000_RPLOLR_STRVLAN   0x40000000
427
-#define E1000_RPLOLR_STRCRC    0x80000000
428
-
429
-#define E1000_DTXCTL_8023LL     0x0004
430
-#define E1000_DTXCTL_VLAN_ADDED 0x0008
431
-#define E1000_DTXCTL_OOS_ENABLE 0x0010
432
-#define E1000_DTXCTL_MDP_EN     0x0020
433
-#define E1000_DTXCTL_SPOOF_INT  0x0040
434
-
435
-#define ALL_QUEUES   0xFFFF
436
-
437
-/* RX packet buffer size defines */
438
-#define E1000_RXPBS_SIZE_MASK_82576  0x0000007F
439
-void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable);
440
-void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable);
441
-
442
-#endif /* _IGB_82575_H_ */

+ 0
- 1108
src/drivers/net/igb/igb_api.c
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Прегледај датотеку


+ 0
- 166
src/drivers/net/igb/igb_api.h Прегледај датотеку

@@ -1,166 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel(R) Gigabit Ethernet Linux driver
4
-  Copyright(c) 2007-2009 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
-
26
-*******************************************************************************/
27
-
28
-FILE_LICENCE ( GPL2_ONLY );
29
-
30
-#ifndef _IGB_API_H_
31
-#define _IGB_API_H_
32
-
33
-#include <stdint.h>
34
-#include <stdlib.h>
35
-#include <stdio.h>
36
-#include <string.h>
37
-#include <unistd.h>
38
-#include <ipxe/io.h>
39
-#include <errno.h>
40
-#include <byteswap.h>
41
-#include <ipxe/pci.h>
42
-#include <ipxe/malloc.h>
43
-#include <ipxe/if_ether.h>
44
-#include <ipxe/ethernet.h>
45
-#include <ipxe/iobuf.h>
46
-#include <ipxe/netdevice.h>
47
-
48
-#include "igb_hw.h"
49
-
50
-extern void    igb_init_function_pointers_82575(struct e1000_hw *hw) __attribute__((weak));
51
-extern void    igb_rx_fifo_flush_82575(struct e1000_hw *hw) __attribute__((weak));
52
-extern void    igb_init_function_pointers_vf(struct e1000_hw *hw) __attribute__((weak));
53
-extern void    igb_shutdown_fiber_serdes_link(struct e1000_hw *hw) __attribute__((weak));
54
-
55
-s32  igb_set_mac_type(struct e1000_hw *hw);
56
-s32  igb_setup_init_funcs(struct e1000_hw *hw, bool init_device);
57
-s32  igb_init_mac_params(struct e1000_hw *hw);
58
-s32  igb_init_nvm_params(struct e1000_hw *hw);
59
-s32  igb_init_phy_params(struct e1000_hw *hw);
60
-s32  igb_init_mbx_params(struct e1000_hw *hw);
61
-s32  igb_get_bus_info(struct e1000_hw *hw);
62
-void igb_clear_vfta(struct e1000_hw *hw);
63
-void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value);
64
-s32  igb_force_mac_fc(struct e1000_hw *hw);
65
-s32  igb_check_for_link(struct e1000_hw *hw);
66
-s32  igb_reset_hw(struct e1000_hw *hw);
67
-s32  igb_init_hw(struct e1000_hw *hw);
68
-s32  igb_setup_link(struct e1000_hw *hw);
69
-s32  igb_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed,
70
-                                u16 *duplex);
71
-s32  igb_disable_pcie_master(struct e1000_hw *hw);
72
-void igb_config_collision_dist(struct e1000_hw *hw);
73
-void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
74
-void igb_mta_set(struct e1000_hw *hw, u32 hash_value);
75
-u32  igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr);
76
-void igb_update_mc_addr_list(struct e1000_hw *hw,
77
-                               u8 *mc_addr_list, u32 mc_addr_count);
78
-s32  igb_setup_led(struct e1000_hw *hw);
79
-s32  igb_cleanup_led(struct e1000_hw *hw);
80
-s32  igb_check_reset_block(struct e1000_hw *hw);
81
-s32  igb_blink_led(struct e1000_hw *hw);
82
-s32  igb_led_on(struct e1000_hw *hw);
83
-s32  igb_led_off(struct e1000_hw *hw);
84
-s32 igb_id_led_init(struct e1000_hw *hw);
85
-void igb_reset_adaptive(struct e1000_hw *hw);
86
-void igb_update_adaptive(struct e1000_hw *hw);
87
-#if 0
88
-s32  igb_get_cable_length(struct e1000_hw *hw);
89
-#endif
90
-s32  igb_validate_mdi_setting(struct e1000_hw *hw);
91
-s32  igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data);
92
-s32  igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data);
93
-s32  igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg,
94
-                               u32 offset, u8 data);
95
-s32  igb_get_phy_info(struct e1000_hw *hw);
96
-void igb_release_phy(struct e1000_hw *hw);
97
-s32  igb_acquire_phy(struct e1000_hw *hw);
98
-s32  igb_phy_hw_reset(struct e1000_hw *hw);
99
-s32  igb_phy_commit(struct e1000_hw *hw);
100
-void igb_power_up_phy(struct e1000_hw *hw);
101
-void igb_power_down_phy(struct e1000_hw *hw);
102
-s32  igb_read_mac_addr(struct e1000_hw *hw);
103
-s32  igb_read_pba_num(struct e1000_hw *hw, u32 *part_num);
104
-void igb_reload_nvm(struct e1000_hw *hw);
105
-s32  igb_update_nvm_checksum(struct e1000_hw *hw);
106
-s32  igb_validate_nvm_checksum(struct e1000_hw *hw);
107
-s32  igb_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
108
-s32  igb_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
109
-s32  igb_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
110
-s32  igb_write_nvm(struct e1000_hw *hw, u16 offset, u16 words,
111
-                     u16 *data);
112
-s32  igb_wait_autoneg(struct e1000_hw *hw);
113
-s32  igb_set_d3_lplu_state(struct e1000_hw *hw, bool active);
114
-s32  igb_set_d0_lplu_state(struct e1000_hw *hw, bool active);
115
-bool igb_check_mng_mode(struct e1000_hw *hw);
116
-bool igb_enable_tx_pkt_filtering(struct e1000_hw *hw);
117
-s32  igb_mng_enable_host_if(struct e1000_hw *hw);
118
-s32  igb_mng_host_if_write(struct e1000_hw *hw,
119
-                             u8 *buffer, u16 length, u16 offset, u8 *sum);
120
-s32  igb_mng_write_cmd_header(struct e1000_hw *hw,
121
-                                struct e1000_host_mng_command_header *hdr);
122
-s32  igb_mng_write_dhcp_info(struct e1000_hw * hw,
123
-                                    u8 *buffer, u16 length);
124
-
125
-/*
126
- * TBI_ACCEPT macro definition:
127
- *
128
- * This macro requires:
129
- *      adapter = a pointer to struct e1000_hw
130
- *      status = the 8 bit status field of the Rx descriptor with EOP set
131
- *      error = the 8 bit error field of the Rx descriptor with EOP set
132
- *      length = the sum of all the length fields of the Rx descriptors that
133
- *               make up the current frame
134
- *      last_byte = the last byte of the frame DMAed by the hardware
135
- *      max_frame_length = the maximum frame length we want to accept.
136
- *      min_frame_length = the minimum frame length we want to accept.
137
- *
138
- * This macro is a conditional that should be used in the interrupt
139
- * handler's Rx processing routine when RxErrors have been detected.
140
- *
141
- * Typical use:
142
- *  ...
143
- *  if (TBI_ACCEPT) {
144
- *      accept_frame = true;
145
- *      e1000_tbi_adjust_stats(adapter, MacAddress);
146
- *      frame_length--;
147
- *  } else {
148
- *      accept_frame = false;
149
- *  }
150
- *  ...
151
- */
152
-
153
-/* The carrier extension symbol, as received by the NIC. */
154
-#define CARRIER_EXTENSION   0x0F
155
-
156
-#define TBI_ACCEPT(a, status, errors, length, last_byte, min_frame_size, max_frame_size) \
157
-    (e1000_tbi_sbp_enabled_82543(a) && \
158
-     (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
159
-     ((last_byte) == CARRIER_EXTENSION) && \
160
-     (((status) & E1000_RXD_STAT_VP) ? \
161
-          (((length) > (min_frame_size - VLAN_TAG_SIZE)) && \
162
-           ((length) <= (max_frame_size + 1))) : \
163
-          (((length) > min_frame_size) && \
164
-           ((length) <= (max_frame_size + VLAN_TAG_SIZE + 1)))))
165
-
166
-#endif /* _IGB_API_H_ */

+ 0
- 1515
src/drivers/net/igb/igb_defines.h
Разлика између датотеке није приказан због своје велике величине
Прегледај датотеку


+ 0
- 697
src/drivers/net/igb/igb_hw.h Прегледај датотеку

@@ -1,697 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel(R) Gigabit Ethernet Linux driver
4
-  Copyright(c) 2007-2009 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
-
26
-*******************************************************************************/
27
-
28
-FILE_LICENCE ( GPL2_ONLY );
29
-
30
-#ifndef _IGB_HW_H_
31
-#define _IGB_HW_H_
32
-
33
-#include "igb_osdep.h"
34
-#include "igb_regs.h"
35
-#include "igb_defines.h"
36
-
37
-struct e1000_hw;
38
-
39
-#define E1000_DEV_ID_82576                    0x10C9
40
-#define E1000_DEV_ID_82576_FIBER              0x10E6
41
-#define E1000_DEV_ID_82576_SERDES             0x10E7
42
-#define E1000_DEV_ID_82576_QUAD_COPPER        0x10E8
43
-#define E1000_DEV_ID_82576_NS                 0x150A
44
-#define E1000_DEV_ID_82576_NS_SERDES          0x1518
45
-#define E1000_DEV_ID_82576_SERDES_QUAD        0x150D
46
-#define E1000_DEV_ID_82575EB_COPPER           0x10A7
47
-#define E1000_DEV_ID_82575EB_FIBER_SERDES     0x10A9
48
-#define E1000_DEV_ID_82575GB_QUAD_COPPER      0x10D6
49
-#define E1000_REVISION_0 0
50
-#define E1000_REVISION_1 1
51
-#define E1000_REVISION_2 2
52
-#define E1000_REVISION_3 3
53
-#define E1000_REVISION_4 4
54
-
55
-#define E1000_FUNC_0     0
56
-#define E1000_FUNC_1     1
57
-
58
-#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
59
-#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
60
-
61
-enum e1000_mac_type {
62
-	e1000_undefined = 0,
63
-	e1000_82575,
64
-	e1000_82576,
65
-	e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
66
-};
67
-
68
-enum e1000_media_type {
69
-	e1000_media_type_unknown = 0,
70
-	e1000_media_type_copper = 1,
71
-	e1000_media_type_fiber = 2,
72
-	e1000_media_type_internal_serdes = 3,
73
-	e1000_num_media_types
74
-};
75
-
76
-enum e1000_nvm_type {
77
-	e1000_nvm_unknown = 0,
78
-	e1000_nvm_none,
79
-	e1000_nvm_eeprom_spi,
80
-	e1000_nvm_flash_hw,
81
-	e1000_nvm_flash_sw
82
-};
83
-
84
-enum e1000_nvm_override {
85
-	e1000_nvm_override_none = 0,
86
-	e1000_nvm_override_spi_small,
87
-	e1000_nvm_override_spi_large,
88
-};
89
-
90
-enum e1000_phy_type {
91
-	e1000_phy_unknown = 0,
92
-	e1000_phy_none,
93
-	e1000_phy_m88,
94
-	e1000_phy_igp,
95
-	e1000_phy_igp_2,
96
-	e1000_phy_gg82563,
97
-	e1000_phy_igp_3,
98
-	e1000_phy_ife,
99
-	e1000_phy_vf,
100
-};
101
-
102
-enum e1000_bus_type {
103
-	e1000_bus_type_unknown = 0,
104
-	e1000_bus_type_pci,
105
-	e1000_bus_type_pcix,
106
-	e1000_bus_type_pci_express,
107
-	e1000_bus_type_reserved
108
-};
109
-
110
-enum e1000_bus_speed {
111
-	e1000_bus_speed_unknown = 0,
112
-	e1000_bus_speed_33,
113
-	e1000_bus_speed_66,
114
-	e1000_bus_speed_100,
115
-	e1000_bus_speed_120,
116
-	e1000_bus_speed_133,
117
-	e1000_bus_speed_2500,
118
-	e1000_bus_speed_5000,
119
-	e1000_bus_speed_reserved
120
-};
121
-
122
-enum e1000_bus_width {
123
-	e1000_bus_width_unknown = 0,
124
-	e1000_bus_width_pcie_x1,
125
-	e1000_bus_width_pcie_x2,
126
-	e1000_bus_width_pcie_x4 = 4,
127
-	e1000_bus_width_pcie_x8 = 8,
128
-	e1000_bus_width_32,
129
-	e1000_bus_width_64,
130
-	e1000_bus_width_reserved
131
-};
132
-
133
-enum e1000_1000t_rx_status {
134
-	e1000_1000t_rx_status_not_ok = 0,
135
-	e1000_1000t_rx_status_ok,
136
-	e1000_1000t_rx_status_undefined = 0xFF
137
-};
138
-
139
-enum e1000_rev_polarity {
140
-	e1000_rev_polarity_normal = 0,
141
-	e1000_rev_polarity_reversed,
142
-	e1000_rev_polarity_undefined = 0xFF
143
-};
144
-
145
-enum e1000_fc_mode {
146
-	e1000_fc_none = 0,
147
-	e1000_fc_rx_pause,
148
-	e1000_fc_tx_pause,
149
-	e1000_fc_full,
150
-	e1000_fc_default = 0xFF
151
-};
152
-
153
-enum e1000_ms_type {
154
-	e1000_ms_hw_default = 0,
155
-	e1000_ms_force_master,
156
-	e1000_ms_force_slave,
157
-	e1000_ms_auto
158
-};
159
-
160
-enum e1000_smart_speed {
161
-	e1000_smart_speed_default = 0,
162
-	e1000_smart_speed_on,
163
-	e1000_smart_speed_off
164
-};
165
-
166
-enum e1000_serdes_link_state {
167
-	e1000_serdes_link_down = 0,
168
-	e1000_serdes_link_autoneg_progress,
169
-	e1000_serdes_link_autoneg_complete,
170
-	e1000_serdes_link_forced_up
171
-};
172
-
173
-/* Receive Descriptor */
174
-struct e1000_rx_desc {
175
-	__le64 buffer_addr; /* Address of the descriptor's data buffer */
176
-	__le16 length;      /* Length of data DMAed into data buffer */
177
-	__le16 csum;        /* Packet checksum */
178
-	u8  status;         /* Descriptor status */
179
-	u8  errors;         /* Descriptor Errors */
180
-	__le16 special;
181
-};
182
-
183
-/* Receive Descriptor - Extended */
184
-union e1000_rx_desc_extended {
185
-	struct {
186
-		__le64 buffer_addr;
187
-		__le64 reserved;
188
-	} read;
189
-	struct {
190
-		struct {
191
-			__le32 mrq;           /* Multiple Rx Queues */
192
-			union {
193
-				__le32 rss;         /* RSS Hash */
194
-				struct {
195
-					__le16 ip_id;  /* IP id */
196
-					__le16 csum;   /* Packet Checksum */
197
-				} csum_ip;
198
-			} hi_dword;
199
-		} lower;
200
-		struct {
201
-			__le32 status_error;  /* ext status/error */
202
-			__le16 length;
203
-			__le16 vlan;          /* VLAN tag */
204
-		} upper;
205
-	} wb;  /* writeback */
206
-};
207
-
208
-#define MAX_PS_BUFFERS 4
209
-/* Receive Descriptor - Packet Split */
210
-union e1000_rx_desc_packet_split {
211
-	struct {
212
-		/* one buffer for protocol header(s), three data buffers */
213
-		__le64 buffer_addr[MAX_PS_BUFFERS];
214
-	} read;
215
-	struct {
216
-		struct {
217
-			__le32 mrq;           /* Multiple Rx Queues */
218
-			union {
219
-				__le32 rss;           /* RSS Hash */
220
-				struct {
221
-					__le16 ip_id;    /* IP id */
222
-					__le16 csum;     /* Packet Checksum */
223
-				} csum_ip;
224
-			} hi_dword;
225
-		} lower;
226
-		struct {
227
-			__le32 status_error;  /* ext status/error */
228
-			__le16 length0;       /* length of buffer 0 */
229
-			__le16 vlan;          /* VLAN tag */
230
-		} middle;
231
-		struct {
232
-			__le16 header_status;
233
-			__le16 length[3];     /* length of buffers 1-3 */
234
-		} upper;
235
-		__le64 reserved;
236
-	} wb; /* writeback */
237
-};
238
-
239
-/* Transmit Descriptor */
240
-struct e1000_tx_desc {
241
-	__le64 buffer_addr;   /* Address of the descriptor's data buffer */
242
-	union {
243
-		__le32 data;
244
-		struct {
245
-			__le16 length;    /* Data buffer length */
246
-			u8 cso;           /* Checksum offset */
247
-			u8 cmd;           /* Descriptor control */
248
-		} flags;
249
-	} lower;
250
-	union {
251
-		__le32 data;
252
-		struct {
253
-			u8 status;        /* Descriptor status */
254
-			u8 css;           /* Checksum start */
255
-			__le16 special;
256
-		} fields;
257
-	} upper;
258
-};
259
-
260
-/* Offload Context Descriptor */
261
-struct e1000_context_desc {
262
-	union {
263
-		__le32 ip_config;
264
-		struct {
265
-			u8 ipcss;         /* IP checksum start */
266
-			u8 ipcso;         /* IP checksum offset */
267
-			__le16 ipcse;     /* IP checksum end */
268
-		} ip_fields;
269
-	} lower_setup;
270
-	union {
271
-		__le32 tcp_config;
272
-		struct {
273
-			u8 tucss;         /* TCP checksum start */
274
-			u8 tucso;         /* TCP checksum offset */
275
-			__le16 tucse;     /* TCP checksum end */
276
-		} tcp_fields;
277
-	} upper_setup;
278
-	__le32 cmd_and_length;
279
-	union {
280
-		__le32 data;
281
-		struct {
282
-			u8 status;        /* Descriptor status */
283
-			u8 hdr_len;       /* Header length */
284
-			__le16 mss;       /* Maximum segment size */
285
-		} fields;
286
-	} tcp_seg_setup;
287
-};
288
-
289
-/* Offload data descriptor */
290
-struct e1000_data_desc {
291
-	__le64 buffer_addr;   /* Address of the descriptor's buffer address */
292
-	union {
293
-		__le32 data;
294
-		struct {
295
-			__le16 length;    /* Data buffer length */
296
-			u8 typ_len_ext;
297
-			u8 cmd;
298
-		} flags;
299
-	} lower;
300
-	union {
301
-		__le32 data;
302
-		struct {
303
-			u8 status;        /* Descriptor status */
304
-			u8 popts;         /* Packet Options */
305
-			__le16 special;
306
-		} fields;
307
-	} upper;
308
-};
309
-
310
-/* Statistics counters collected by the MAC */
311
-struct e1000_hw_stats {
312
-	u64 crcerrs;
313
-	u64 algnerrc;
314
-	u64 symerrs;
315
-	u64 rxerrc;
316
-	u64 mpc;
317
-	u64 scc;
318
-	u64 ecol;
319
-	u64 mcc;
320
-	u64 latecol;
321
-	u64 colc;
322
-	u64 dc;
323
-	u64 tncrs;
324
-	u64 sec;
325
-	u64 cexterr;
326
-	u64 rlec;
327
-	u64 xonrxc;
328
-	u64 xontxc;
329
-	u64 xoffrxc;
330
-	u64 xofftxc;
331
-	u64 fcruc;
332
-	u64 prc64;
333
-	u64 prc127;
334
-	u64 prc255;
335
-	u64 prc511;
336
-	u64 prc1023;
337
-	u64 prc1522;
338
-	u64 gprc;
339
-	u64 bprc;
340
-	u64 mprc;
341
-	u64 gptc;
342
-	u64 gorc;
343
-	u64 gotc;
344
-	u64 rnbc;
345
-	u64 ruc;
346
-	u64 rfc;
347
-	u64 roc;
348
-	u64 rjc;
349
-	u64 mgprc;
350
-	u64 mgpdc;
351
-	u64 mgptc;
352
-	u64 tor;
353
-	u64 tot;
354
-	u64 tpr;
355
-	u64 tpt;
356
-	u64 ptc64;
357
-	u64 ptc127;
358
-	u64 ptc255;
359
-	u64 ptc511;
360
-	u64 ptc1023;
361
-	u64 ptc1522;
362
-	u64 mptc;
363
-	u64 bptc;
364
-	u64 tsctc;
365
-	u64 tsctfc;
366
-	u64 iac;
367
-	u64 icrxptc;
368
-	u64 icrxatc;
369
-	u64 ictxptc;
370
-	u64 ictxatc;
371
-	u64 ictxqec;
372
-	u64 ictxqmtc;
373
-	u64 icrxdmtc;
374
-	u64 icrxoc;
375
-	u64 cbtmpc;
376
-	u64 htdpmc;
377
-	u64 cbrdpc;
378
-	u64 cbrmpc;
379
-	u64 rpthc;
380
-	u64 hgptc;
381
-	u64 htcbdpc;
382
-	u64 hgorc;
383
-	u64 hgotc;
384
-	u64 lenerrs;
385
-	u64 scvpc;
386
-	u64 hrmpc;
387
-	u64 doosync;
388
-};
389
-
390
-
391
-struct e1000_phy_stats {
392
-	u32 idle_errors;
393
-	u32 receive_errors;
394
-};
395
-
396
-struct e1000_host_mng_dhcp_cookie {
397
-	u32 signature;
398
-	u8  status;
399
-	u8  reserved0;
400
-	u16 vlan_id;
401
-	u32 reserved1;
402
-	u16 reserved2;
403
-	u8  reserved3;
404
-	u8  checksum;
405
-};
406
-
407
-/* Host Interface "Rev 1" */
408
-struct e1000_host_command_header {
409
-	u8 command_id;
410
-	u8 command_length;
411
-	u8 command_options;
412
-	u8 checksum;
413
-};
414
-
415
-#define E1000_HI_MAX_DATA_LENGTH     252
416
-struct e1000_host_command_info {
417
-	struct e1000_host_command_header command_header;
418
-	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
419
-};
420
-
421
-/* Host Interface "Rev 2" */
422
-struct e1000_host_mng_command_header {
423
-	u8  command_id;
424
-	u8  checksum;
425
-	u16 reserved1;
426
-	u16 reserved2;
427
-	u16 command_length;
428
-};
429
-
430
-#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
431
-struct e1000_host_mng_command_info {
432
-	struct e1000_host_mng_command_header command_header;
433
-	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
434
-};
435
-
436
-#include "igb_mac.h"
437
-#include "igb_phy.h"
438
-#include "igb_nvm.h"
439
-#include "igb_manage.h"
440
-
441
-struct e1000_mac_operations {
442
-	/* Function pointers for the MAC. */
443
-	s32  (*init_params)(struct e1000_hw *);
444
-	s32  (*id_led_init)(struct e1000_hw *);
445
-	s32  (*blink_led)(struct e1000_hw *);
446
-	s32  (*check_for_link)(struct e1000_hw *);
447
-	bool (*check_mng_mode)(struct e1000_hw *hw);
448
-	s32  (*cleanup_led)(struct e1000_hw *);
449
-	void (*clear_hw_cntrs)(struct e1000_hw *);
450
-	void (*clear_vfta)(struct e1000_hw *);
451
-	s32  (*get_bus_info)(struct e1000_hw *);
452
-	void (*set_lan_id)(struct e1000_hw *);
453
-	s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
454
-	s32  (*led_on)(struct e1000_hw *);
455
-	s32  (*led_off)(struct e1000_hw *);
456
-	void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
457
-	s32  (*reset_hw)(struct e1000_hw *);
458
-	s32  (*init_hw)(struct e1000_hw *);
459
-	void (*shutdown_serdes)(struct e1000_hw *);
460
-	s32  (*setup_link)(struct e1000_hw *);
461
-	s32  (*setup_physical_interface)(struct e1000_hw *);
462
-	s32  (*setup_led)(struct e1000_hw *);
463
-	void (*write_vfta)(struct e1000_hw *, u32, u32);
464
-	void (*mta_set)(struct e1000_hw *, u32);
465
-	void (*config_collision_dist)(struct e1000_hw *);
466
-	void (*rar_set)(struct e1000_hw *, u8*, u32);
467
-	s32  (*read_mac_addr)(struct e1000_hw *);
468
-	s32  (*validate_mdi_setting)(struct e1000_hw *);
469
-	s32  (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
470
-	s32  (*mng_write_cmd_header)(struct e1000_hw *hw,
471
-                      struct e1000_host_mng_command_header*);
472
-	s32  (*mng_enable_host_if)(struct e1000_hw *);
473
-	s32  (*wait_autoneg)(struct e1000_hw *);
474
-};
475
-
476
-struct e1000_phy_operations {
477
-	s32  (*init_params)(struct e1000_hw *);
478
-	s32  (*acquire)(struct e1000_hw *);
479
-	s32  (*check_polarity)(struct e1000_hw *);
480
-	s32  (*check_reset_block)(struct e1000_hw *);
481
-	s32  (*commit)(struct e1000_hw *);
482
-#if 0
483
-	s32  (*force_speed_duplex)(struct e1000_hw *);
484
-#endif
485
-	s32  (*get_cfg_done)(struct e1000_hw *hw);
486
-#if 0
487
-	s32  (*get_cable_length)(struct e1000_hw *);
488
-#endif
489
-	s32  (*get_info)(struct e1000_hw *);
490
-	s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
491
-	s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
492
-	void (*release)(struct e1000_hw *);
493
-	s32  (*reset)(struct e1000_hw *);
494
-	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
495
-	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
496
-	s32  (*write_reg)(struct e1000_hw *, u32, u16);
497
-	s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
498
-	void (*power_up)(struct e1000_hw *);
499
-	void (*power_down)(struct e1000_hw *);
500
-};
501
-
502
-struct e1000_nvm_operations {
503
-	s32  (*init_params)(struct e1000_hw *);
504
-	s32  (*acquire)(struct e1000_hw *);
505
-	s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
506
-	void (*release)(struct e1000_hw *);
507
-	void (*reload)(struct e1000_hw *);
508
-	s32  (*update)(struct e1000_hw *);
509
-	s32  (*valid_led_default)(struct e1000_hw *, u16 *);
510
-	s32  (*validate)(struct e1000_hw *);
511
-	s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
512
-};
513
-
514
-struct e1000_mac_info {
515
-	struct e1000_mac_operations ops;
516
-	u8 addr[6];
517
-	u8 perm_addr[6];
518
-
519
-	enum e1000_mac_type type;
520
-
521
-	u32 collision_delta;
522
-	u32 ledctl_default;
523
-	u32 ledctl_mode1;
524
-	u32 ledctl_mode2;
525
-	u32 mc_filter_type;
526
-	u32 tx_packet_delta;
527
-	u32 txcw;
528
-
529
-	u16 current_ifs_val;
530
-	u16 ifs_max_val;
531
-	u16 ifs_min_val;
532
-	u16 ifs_ratio;
533
-	u16 ifs_step_size;
534
-	u16 mta_reg_count;
535
-	u16 uta_reg_count;
536
-
537
-	/* Maximum size of the MTA register table in all supported adapters */
538
-	#define MAX_MTA_REG 128
539
-	u32 mta_shadow[MAX_MTA_REG];
540
-	u16 rar_entry_count;
541
-
542
-	u8  forced_speed_duplex;
543
-
544
-	bool adaptive_ifs;
545
-	bool arc_subsystem_valid;
546
-	bool asf_firmware_present;
547
-	bool autoneg;
548
-	bool autoneg_failed;
549
-	bool get_link_status;
550
-	bool in_ifs_mode;
551
-	enum e1000_serdes_link_state serdes_link_state;
552
-	bool serdes_has_link;
553
-	bool tx_pkt_filtering;
554
-};
555
-
556
-struct e1000_phy_info {
557
-	struct e1000_phy_operations ops;
558
-	enum e1000_phy_type type;
559
-
560
-	enum e1000_1000t_rx_status local_rx;
561
-	enum e1000_1000t_rx_status remote_rx;
562
-	enum e1000_ms_type ms_type;
563
-	enum e1000_ms_type original_ms_type;
564
-	enum e1000_rev_polarity cable_polarity;
565
-	enum e1000_smart_speed smart_speed;
566
-
567
-	u32 addr;
568
-	u32 id;
569
-	u32 reset_delay_us; /* in usec */
570
-	u32 revision;
571
-
572
-	enum e1000_media_type media_type;
573
-
574
-	u16 autoneg_advertised;
575
-	u16 autoneg_mask;
576
-	u16 cable_length;
577
-	u16 max_cable_length;
578
-	u16 min_cable_length;
579
-
580
-	u8 mdix;
581
-
582
-	bool disable_polarity_correction;
583
-	bool is_mdix;
584
-	bool polarity_correction;
585
-	bool reset_disable;
586
-	bool speed_downgraded;
587
-	bool autoneg_wait_to_complete;
588
-};
589
-
590
-struct e1000_nvm_info {
591
-	struct e1000_nvm_operations ops;
592
-	enum e1000_nvm_type type;
593
-	enum e1000_nvm_override override;
594
-
595
-	u32 flash_bank_size;
596
-	u32 flash_base_addr;
597
-
598
-	u16 word_size;
599
-	u16 delay_usec;
600
-	u16 address_bits;
601
-	u16 opcode_bits;
602
-	u16 page_size;
603
-};
604
-
605
-struct e1000_bus_info {
606
-	enum e1000_bus_type type;
607
-	enum e1000_bus_speed speed;
608
-	enum e1000_bus_width width;
609
-
610
-	u16 func;
611
-	u16 pci_cmd_word;
612
-};
613
-
614
-struct e1000_fc_info {
615
-	u32 high_water;          /* Flow control high-water mark */
616
-	u32 low_water;           /* Flow control low-water mark */
617
-	u16 pause_time;          /* Flow control pause timer */
618
-	bool send_xon;           /* Flow control send XON */
619
-	bool strict_ieee;        /* Strict IEEE mode */
620
-	enum e1000_fc_mode current_mode; /* FC mode in effect */
621
-	enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
622
-};
623
-
624
-struct e1000_mbx_operations {
625
-	s32 (*init_params)(struct e1000_hw *hw);
626
-	s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
627
-	s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
628
-	s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
629
-	s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
630
-	s32 (*check_for_msg)(struct e1000_hw *, u16);
631
-	s32 (*check_for_ack)(struct e1000_hw *, u16);
632
-	s32 (*check_for_rst)(struct e1000_hw *, u16);
633
-};
634
-
635
-struct e1000_mbx_stats {
636
-	u32 msgs_tx;
637
-	u32 msgs_rx;
638
-
639
-	u32 acks;
640
-	u32 reqs;
641
-	u32 rsts;
642
-};
643
-
644
-struct e1000_mbx_info {
645
-	struct e1000_mbx_operations ops;
646
-	struct e1000_mbx_stats stats;
647
-	u32 timeout;
648
-	u32 usec_delay;
649
-	u16 size;
650
-};
651
-
652
-struct e1000_dev_spec_82575 {
653
-	bool sgmii_active;
654
-	bool global_device_reset;
655
-};
656
-
657
-struct e1000_dev_spec_vf {
658
-	u32	vf_number;
659
-	u32	v2p_mailbox;
660
-};
661
-
662
-
663
-struct e1000_hw {
664
-	void *back;
665
-
666
-	u8 __iomem *hw_addr;
667
-	u8 __iomem *flash_address;
668
-	unsigned long io_base;
669
-
670
-	struct e1000_mac_info  mac;
671
-	struct e1000_fc_info   fc;
672
-	struct e1000_phy_info  phy;
673
-	struct e1000_nvm_info  nvm;
674
-	struct e1000_bus_info  bus;
675
-	struct e1000_mbx_info mbx;
676
-	struct e1000_host_mng_dhcp_cookie mng_cookie;
677
-
678
-	union {
679
-		struct e1000_dev_spec_82575	_82575;
680
-		struct e1000_dev_spec_vf	vf;
681
-	} dev_spec;
682
-
683
-	u16 device_id;
684
-	u16 subsystem_vendor_id;
685
-	u16 subsystem_device_id;
686
-	u16 vendor_id;
687
-
688
-	u8  revision_id;
689
-};
690
-
691
-#include "igb_82575.h"
692
-
693
-/* These functions must be implemented by drivers */
694
-s32  igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
695
-s32  igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
696
-
697
-#endif /* _IGB_HW_H_ */

+ 0
- 1991
src/drivers/net/igb/igb_mac.c
Разлика између датотеке није приказан због своје велике величине
Прегледај датотеку


+ 0
- 82
src/drivers/net/igb/igb_mac.h Прегледај датотеку

@@ -1,82 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel(R) Gigabit Ethernet Linux driver
4
-  Copyright(c) 2007-2009 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
-
26
-*******************************************************************************/
27
-
28
-FILE_LICENCE ( GPL2_ONLY );
29
-
30
-#ifndef _IGB_MAC_H_
31
-#define _IGB_MAC_H_
32
-
33
-/*
34
- * Functions that should not be called directly from drivers but can be used
35
- * by other files in this 'shared code'
36
- */
37
-void igb_init_mac_ops_generic(struct e1000_hw *hw);
38
-s32  igb_blink_led_generic(struct e1000_hw *hw);
39
-s32  igb_check_for_copper_link_generic(struct e1000_hw *hw);
40
-s32  igb_check_for_fiber_link_generic(struct e1000_hw *hw);
41
-s32  igb_check_for_serdes_link_generic(struct e1000_hw *hw);
42
-s32  igb_cleanup_led_generic(struct e1000_hw *hw);
43
-s32  igb_config_fc_after_link_up_generic(struct e1000_hw *hw);
44
-s32  igb_disable_pcie_master_generic(struct e1000_hw *hw);
45
-s32  igb_force_mac_fc_generic(struct e1000_hw *hw);
46
-s32  igb_get_auto_rd_done_generic(struct e1000_hw *hw);
47
-s32  igb_get_bus_info_pcie_generic(struct e1000_hw *hw);
48
-void igb_set_lan_id_single_port(struct e1000_hw *hw);
49
-s32  igb_get_hw_semaphore_generic(struct e1000_hw *hw);
50
-s32  igb_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
51
-                                               u16 *duplex);
52
-s32  igb_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
53
-                                                     u16 *speed, u16 *duplex);
54
-s32  igb_id_led_init_generic(struct e1000_hw *hw);
55
-s32  igb_led_on_generic(struct e1000_hw *hw);
56
-s32  igb_led_off_generic(struct e1000_hw *hw);
57
-void igb_update_mc_addr_list_generic(struct e1000_hw *hw,
58
-	                               u8 *mc_addr_list, u32 mc_addr_count);
59
-s32  igb_set_fc_watermarks_generic(struct e1000_hw *hw);
60
-s32  igb_setup_fiber_serdes_link_generic(struct e1000_hw *hw);
61
-s32  igb_setup_led_generic(struct e1000_hw *hw);
62
-s32  igb_setup_link_generic(struct e1000_hw *hw);
63
-s32  igb_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
64
-                                       u32 offset, u8 data);
65
-
66
-u32  igb_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr);
67
-
68
-void igb_clear_hw_cntrs_base_generic(struct e1000_hw *hw);
69
-void igb_clear_vfta_generic(struct e1000_hw *hw);
70
-void igb_config_collision_dist_generic(struct e1000_hw *hw);
71
-void igb_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count);
72
-void igb_mta_set_generic(struct e1000_hw *hw, u32 hash_value);
73
-void igb_pcix_mmrbc_workaround_generic(struct e1000_hw *hw);
74
-void igb_put_hw_semaphore_generic(struct e1000_hw *hw);
75
-void igb_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
76
-s32  igb_check_alt_mac_addr_generic(struct e1000_hw *hw);
77
-void igb_reset_adaptive_generic(struct e1000_hw *hw);
78
-void igb_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop);
79
-void igb_update_adaptive_generic(struct e1000_hw *hw);
80
-void igb_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
81
-
82
-#endif /* _IGB_MAC_H_ */

+ 0
- 1010
src/drivers/net/igb/igb_main.c
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Прегледај датотеку


+ 0
- 388
src/drivers/net/igb/igb_manage.c Прегледај датотеку

@@ -1,388 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel(R) Gigabit Ethernet Linux driver
4
-  Copyright(c) 2007-2009 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
-
26
-*******************************************************************************/
27
-
28
-FILE_LICENCE ( GPL2_ONLY );
29
-
30
-#include "igb.h"
31
-
32
-#if 0
33
-
34
-static u8 e1000_calculate_checksum(u8 *buffer, u32 length);
35
-
36
-/**
37
- *  e1000_calculate_checksum - Calculate checksum for buffer
38
- *  @buffer: pointer to EEPROM
39
- *  @length: size of EEPROM to calculate a checksum for
40
- *
41
- *  Calculates the checksum for some buffer on a specified length.  The
42
- *  checksum calculated is returned.
43
- **/
44
-static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
45
-{
46
-	u32 i;
47
-	u8  sum = 0;
48
-
49
-	DEBUGFUNC("igb_calculate_checksum");
50
-
51
-	if (!buffer)
52
-		return 0;
53
-
54
-	for (i = 0; i < length; i++)
55
-		sum += buffer[i];
56
-
57
-	return (u8) (0 - sum);
58
-}
59
-
60
-/**
61
- *  e1000_mng_enable_host_if_generic - Checks host interface is enabled
62
- *  @hw: pointer to the HW structure
63
- *
64
- *  Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
65
- *
66
- *  This function checks whether the HOST IF is enabled for command operation
67
- *  and also checks whether the previous command is completed.  It busy waits
68
- *  in case of previous command is not completed.
69
- **/
70
-s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw)
71
-{
72
-	u32 hicr;
73
-	s32 ret_val = E1000_SUCCESS;
74
-	u8  i;
75
-
76
-	DEBUGFUNC("igb_mng_enable_host_if_generic");
77
-
78
-	/* Check that the host interface is enabled. */
79
-	hicr = E1000_READ_REG(hw, E1000_HICR);
80
-	if ((hicr & E1000_HICR_EN) == 0) {
81
-		DEBUGOUT("E1000_HOST_EN bit disabled.\n");
82
-		ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
83
-		goto out;
84
-	}
85
-	/* check the previous command is completed */
86
-	for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
87
-		hicr = E1000_READ_REG(hw, E1000_HICR);
88
-		if (!(hicr & E1000_HICR_C))
89
-			break;
90
-		msec_delay_irq(1);
91
-	}
92
-
93
-	if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
94
-		DEBUGOUT("Previous command timeout failed .\n");
95
-		ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
96
-		goto out;
97
-	}
98
-
99
-out:
100
-	return ret_val;
101
-}
102
-
103
-/**
104
- *  e1000_check_mng_mode_generic - Generic check management mode
105
- *  @hw: pointer to the HW structure
106
- *
107
- *  Reads the firmware semaphore register and returns true (>0) if
108
- *  manageability is enabled, else false (0).
109
- **/
110
-bool e1000_check_mng_mode_generic(struct e1000_hw *hw)
111
-{
112
-	u32 fwsm;
113
-
114
-	DEBUGFUNC("igb_check_mng_mode_generic");
115
-
116
-	fwsm = E1000_READ_REG(hw, E1000_FWSM);
117
-
118
-	return (fwsm & E1000_FWSM_MODE_MASK) ==
119
-	        (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
120
-}
121
-
122
-/**
123
- *  e1000_enable_tx_pkt_filtering_generic - Enable packet filtering on TX
124
- *  @hw: pointer to the HW structure
125
- *
126
- *  Enables packet filtering on transmit packets if manageability is enabled
127
- *  and host interface is enabled.
128
- **/
129
-bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw)
130
-{
131
-	struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
132
-	u32 *buffer = (u32 *)&hw->mng_cookie;
133
-	u32 offset;
134
-	s32 ret_val, hdr_csum, csum;
135
-	u8 i, len;
136
-	bool tx_filter = true;
137
-
138
-	DEBUGFUNC("igb_enable_tx_pkt_filtering_generic");
139
-
140
-	/* No manageability, no filtering */
141
-	if (!hw->mac.ops.check_mng_mode(hw)) {
142
-		tx_filter = false;
143
-		goto out;
144
-	}
145
-
146
-	/*
147
-	 * If we can't read from the host interface for whatever
148
-	 * reason, disable filtering.
149
-	 */
150
-	ret_val = hw->mac.ops.mng_enable_host_if(hw);
151
-	if (ret_val != E1000_SUCCESS) {
152
-		tx_filter = false;
153
-		goto out;
154
-	}
155
-
156
-	/* Read in the header.  Length and offset are in dwords. */
157
-	len    = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
158
-	offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
159
-	for (i = 0; i < len; i++) {
160
-		*(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw,
161
-		                                           E1000_HOST_IF,
162
-		                                           offset + i);
163
-	}
164
-	hdr_csum = hdr->checksum;
165
-	hdr->checksum = 0;
166
-	csum = e1000_calculate_checksum((u8 *)hdr,
167
-	                                E1000_MNG_DHCP_COOKIE_LENGTH);
168
-	/*
169
-	 * If either the checksums or signature don't match, then
170
-	 * the cookie area isn't considered valid, in which case we
171
-	 * take the safe route of assuming Tx filtering is enabled.
172
-	 */
173
-	if (hdr_csum != csum)
174
-		goto out;
175
-	if (hdr->signature != E1000_IAMT_SIGNATURE)
176
-		goto out;
177
-
178
-	/* Cookie area is valid, make the final check for filtering. */
179
-	if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))
180
-		tx_filter = false;
181
-
182
-out:
183
-	hw->mac.tx_pkt_filtering = tx_filter;
184
-	return tx_filter;
185
-}
186
-
187
-/**
188
- *  e1000_mng_write_dhcp_info_generic - Writes DHCP info to host interface
189
- *  @hw: pointer to the HW structure
190
- *  @buffer: pointer to the host interface
191
- *  @length: size of the buffer
192
- *
193
- *  Writes the DHCP information to the host interface.
194
- **/
195
-s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, u8 *buffer,
196
-                                      u16 length)
197
-{
198
-	struct e1000_host_mng_command_header hdr;
199
-	s32 ret_val;
200
-	u32 hicr;
201
-
202
-	DEBUGFUNC("igb_mng_write_dhcp_info_generic");
203
-
204
-	hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
205
-	hdr.command_length = length;
206
-	hdr.reserved1 = 0;
207
-	hdr.reserved2 = 0;
208
-	hdr.checksum = 0;
209
-
210
-	/* Enable the host interface */
211
-	ret_val = hw->mac.ops.mng_enable_host_if(hw);
212
-	if (ret_val)
213
-		goto out;
214
-
215
-	/* Populate the host interface with the contents of "buffer". */
216
-	ret_val = hw->mac.ops.mng_host_if_write(hw, buffer, length,
217
-	                                  sizeof(hdr), &(hdr.checksum));
218
-	if (ret_val)
219
-		goto out;
220
-
221
-	/* Write the manageability command header */
222
-	ret_val = hw->mac.ops.mng_write_cmd_header(hw, &hdr);
223
-	if (ret_val)
224
-		goto out;
225
-
226
-	/* Tell the ARC a new command is pending. */
227
-	hicr = E1000_READ_REG(hw, E1000_HICR);
228
-	E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
229
-
230
-out:
231
-	return ret_val;
232
-}
233
-
234
-/**
235
- *  e1000_mng_write_cmd_header_generic - Writes manageability command header
236
- *  @hw: pointer to the HW structure
237
- *  @hdr: pointer to the host interface command header
238
- *
239
- *  Writes the command header after does the checksum calculation.
240
- **/
241
-s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
242
-                                    struct e1000_host_mng_command_header *hdr)
243
-{
244
-	u16 i, length = sizeof(struct e1000_host_mng_command_header);
245
-
246
-	DEBUGFUNC("igb_mng_write_cmd_header_generic");
247
-
248
-	/* Write the whole command header structure with new checksum. */
249
-
250
-	hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
251
-
252
-	length >>= 2;
253
-	/* Write the relevant command block into the ram area. */
254
-	for (i = 0; i < length; i++) {
255
-		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
256
-		                            *((u32 *) hdr + i));
257
-		E1000_WRITE_FLUSH(hw);
258
-	}
259
-
260
-	return E1000_SUCCESS;
261
-}
262
-
263
-/**
264
- *  e1000_mng_host_if_write_generic - Write to the manageability host interface
265
- *  @hw: pointer to the HW structure
266
- *  @buffer: pointer to the host interface buffer
267
- *  @length: size of the buffer
268
- *  @offset: location in the buffer to write to
269
- *  @sum: sum of the data (not checksum)
270
- *
271
- *  This function writes the buffer content at the offset given on the host if.
272
- *  It also does alignment considerations to do the writes in most efficient
273
- *  way.  Also fills up the sum of the buffer in *buffer parameter.
274
- **/
275
-s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
276
-                                    u16 length, u16 offset, u8 *sum)
277
-{
278
-	u8 *tmp;
279
-	u8 *bufptr = buffer;
280
-	u32 data = 0;
281
-	s32 ret_val = E1000_SUCCESS;
282
-	u16 remaining, i, j, prev_bytes;
283
-
284
-	DEBUGFUNC("igb_mng_host_if_write_generic");
285
-
286
-	/* sum = only sum of the data and it is not checksum */
287
-
288
-	if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
289
-		ret_val = -E1000_ERR_PARAM;
290
-		goto out;
291
-	}
292
-
293
-	tmp = (u8 *)&data;
294
-	prev_bytes = offset & 0x3;
295
-	offset >>= 2;
296
-
297
-	if (prev_bytes) {
298
-		data = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset);
299
-		for (j = prev_bytes; j < sizeof(u32); j++) {
300
-			*(tmp + j) = *bufptr++;
301
-			*sum += *(tmp + j);
302
-		}
303
-		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset, data);
304
-		length -= j - prev_bytes;
305
-		offset++;
306
-	}
307
-
308
-	remaining = length & 0x3;
309
-	length -= remaining;
310
-
311
-	/* Calculate length in DWORDs */
312
-	length >>= 2;
313
-
314
-	/*
315
-	 * The device driver writes the relevant command block into the
316
-	 * ram area.
317
-	 */
318
-	for (i = 0; i < length; i++) {
319
-		for (j = 0; j < sizeof(u32); j++) {
320
-			*(tmp + j) = *bufptr++;
321
-			*sum += *(tmp + j);
322
-		}
323
-
324
-		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
325
-		                            data);
326
-	}
327
-	if (remaining) {
328
-		for (j = 0; j < sizeof(u32); j++) {
329
-			if (j < remaining)
330
-				*(tmp + j) = *bufptr++;
331
-			else
332
-				*(tmp + j) = 0;
333
-
334
-			*sum += *(tmp + j);
335
-		}
336
-		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i, data);
337
-	}
338
-
339
-out:
340
-	return ret_val;
341
-}
342
-
343
-/**
344
- *  e1000_enable_mng_pass_thru - Enable processing of ARP's
345
- *  @hw: pointer to the HW structure
346
- *
347
- *  Verifies the hardware needs to allow ARPs to be processed by the host.
348
- **/
349
-bool e1000_enable_mng_pass_thru(struct e1000_hw *hw)
350
-{
351
-	u32 manc;
352
-	u32 fwsm, factps;
353
-	bool ret_val = false;
354
-
355
-	DEBUGFUNC("igb_enable_mng_pass_thru");
356
-
357
-	if (!hw->mac.asf_firmware_present)
358
-		goto out;
359
-
360
-	manc = E1000_READ_REG(hw, E1000_MANC);
361
-
362
-	if (!(manc & E1000_MANC_RCV_TCO_EN) ||
363
-	    !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
364
-		goto out;
365
-
366
-	if (hw->mac.arc_subsystem_valid) {
367
-		fwsm = E1000_READ_REG(hw, E1000_FWSM);
368
-		factps = E1000_READ_REG(hw, E1000_FACTPS);
369
-
370
-		if (!(factps & E1000_FACTPS_MNGCG) &&
371
-		    ((fwsm & E1000_FWSM_MODE_MASK) ==
372
-		     (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
373
-			ret_val = true;
374
-			goto out;
375
-		}
376
-	} else {
377
-		if ((manc & E1000_MANC_SMBUS_EN) &&
378
-		    !(manc & E1000_MANC_ASF_EN)) {
379
-			ret_val = true;
380
-			goto out;
381
-		}
382
-	}
383
-
384
-out:
385
-	return ret_val;
386
-}
387
-
388
-#endif

+ 0
- 83
src/drivers/net/igb/igb_manage.h Прегледај датотеку

@@ -1,83 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel(R) Gigabit Ethernet Linux driver
4
-  Copyright(c) 2007-2009 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
-
26
-*******************************************************************************/
27
-
28
-FILE_LICENCE ( GPL2_ONLY );
29
-
30
-#ifndef _IGB_MANAGE_H_
31
-#define _IGB_MANAGE_H_
32
-
33
-bool e1000_check_mng_mode_generic(struct e1000_hw *hw);
34
-bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw);
35
-s32  e1000_mng_enable_host_if_generic(struct e1000_hw *hw);
36
-s32  e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
37
-                                     u16 length, u16 offset, u8 *sum);
38
-s32  e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
39
-                                    struct e1000_host_mng_command_header *hdr);
40
-s32  e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw,
41
-                                       u8 *buffer, u16 length);
42
-bool e1000_enable_mng_pass_thru(struct e1000_hw *hw);
43
-
44
-enum e1000_mng_mode {
45
-	e1000_mng_mode_none = 0,
46
-	e1000_mng_mode_asf,
47
-	e1000_mng_mode_pt,
48
-	e1000_mng_mode_ipmi,
49
-	e1000_mng_mode_host_if_only
50
-};
51
-
52
-#define E1000_FACTPS_MNGCG    0x20000000
53
-
54
-#define E1000_FWSM_MODE_MASK  0xE
55
-#define E1000_FWSM_MODE_SHIFT 1
56
-
57
-#define E1000_MNG_IAMT_MODE                  0x3
58
-#define E1000_MNG_DHCP_COOKIE_LENGTH         0x10
59
-#define E1000_MNG_DHCP_COOKIE_OFFSET         0x6F0
60
-#define E1000_MNG_DHCP_COMMAND_TIMEOUT       10
61
-#define E1000_MNG_DHCP_TX_PAYLOAD_CMD        64
62
-#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
63
-#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN    0x2
64
-
65
-#define E1000_VFTA_ENTRY_SHIFT               5
66
-#define E1000_VFTA_ENTRY_MASK                0x7F
67
-#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK      0x1F
68
-
69
-#define E1000_HI_MAX_BLOCK_BYTE_LENGTH       1792 /* Num of bytes in range */
70
-#define E1000_HI_MAX_BLOCK_DWORD_LENGTH      448 /* Num of dwords in range */
71
-#define E1000_HI_COMMAND_TIMEOUT             500 /* Process HI command limit */
72
-
73
-#define E1000_HICR_EN              0x01  /* Enable bit - RO */
74
-/* Driver sets this bit when done to put command in RAM */
75
-#define E1000_HICR_C               0x02
76
-#define E1000_HICR_SV              0x04  /* Status Validity */
77
-#define E1000_HICR_FW_RESET_ENABLE 0x40
78
-#define E1000_HICR_FW_RESET        0x80
79
-
80
-/* Intel(R) Active Management Technology signature */
81
-#define E1000_IAMT_SIGNATURE  0x544D4149
82
-
83
-#endif /* _IGB_MANAGE_H_ */

+ 0
- 627
src/drivers/net/igb/igb_nvm.c Прегледај датотеку

@@ -1,627 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel(R) Gigabit Ethernet Linux driver
4
-  Copyright(c) 2007-2009 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
-
26
-*******************************************************************************/
27
-
28
-FILE_LICENCE ( GPL2_ONLY );
29
-
30
-#include "igb.h"
31
-
32
-static void igb_stop_nvm(struct e1000_hw *hw);
33
-static void igb_reload_nvm_generic(struct e1000_hw *hw);
34
-
35
-/**
36
- *  igb_init_nvm_ops_generic - Initialize NVM function pointers
37
- *  @hw: pointer to the HW structure
38
- *
39
- *  Setups up the function pointers to no-op functions
40
- **/
41
-void igb_init_nvm_ops_generic(struct e1000_hw *hw)
42
-{
43
-	struct e1000_nvm_info *nvm = &hw->nvm;
44
-	DEBUGFUNC("igb_init_nvm_ops_generic");
45
-
46
-	/* Initialize function pointers */
47
-	nvm->ops.reload = igb_reload_nvm_generic;
48
-}
49
-
50
-/**
51
- *  igb_raise_eec_clk - Raise EEPROM clock
52
- *  @hw: pointer to the HW structure
53
- *  @eecd: pointer to the EEPROM
54
- *
55
- *  Enable/Raise the EEPROM clock bit.
56
- **/
57
-static void igb_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
58
-{
59
-	*eecd = *eecd | E1000_EECD_SK;
60
-	E1000_WRITE_REG(hw, E1000_EECD, *eecd);
61
-	E1000_WRITE_FLUSH(hw);
62
-	usec_delay(hw->nvm.delay_usec);
63
-}
64
-
65
-/**
66
- *  igb_lower_eec_clk - Lower EEPROM clock
67
- *  @hw: pointer to the HW structure
68
- *  @eecd: pointer to the EEPROM
69
- *
70
- *  Clear/Lower the EEPROM clock bit.
71
- **/
72
-static void igb_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
73
-{
74
-	*eecd = *eecd & ~E1000_EECD_SK;
75
-	E1000_WRITE_REG(hw, E1000_EECD, *eecd);
76
-	E1000_WRITE_FLUSH(hw);
77
-	usec_delay(hw->nvm.delay_usec);
78
-}
79
-
80
-/**
81
- *  igb_shift_out_eec_bits - Shift data bits our to the EEPROM
82
- *  @hw: pointer to the HW structure
83
- *  @data: data to send to the EEPROM
84
- *  @count: number of bits to shift out
85
- *
86
- *  We need to shift 'count' bits out to the EEPROM.  So, the value in the
87
- *  "data" parameter will be shifted out to the EEPROM one bit at a time.
88
- *  In order to do this, "data" must be broken down into bits.
89
- **/
90
-static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
91
-{
92
-	struct e1000_nvm_info *nvm = &hw->nvm;
93
-	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
94
-	u32 mask;
95
-
96
-	DEBUGFUNC("igb_shift_out_eec_bits");
97
-
98
-	mask = 0x01 << (count - 1);
99
-	if (nvm->type == e1000_nvm_eeprom_spi)
100
-		eecd |= E1000_EECD_DO;
101
-
102
-	do {
103
-		eecd &= ~E1000_EECD_DI;
104
-
105
-		if (data & mask)
106
-			eecd |= E1000_EECD_DI;
107
-
108
-		E1000_WRITE_REG(hw, E1000_EECD, eecd);
109
-		E1000_WRITE_FLUSH(hw);
110
-
111
-		usec_delay(nvm->delay_usec);
112
-
113
-		igb_raise_eec_clk(hw, &eecd);
114
-		igb_lower_eec_clk(hw, &eecd);
115
-
116
-		mask >>= 1;
117
-	} while (mask);
118
-
119
-	eecd &= ~E1000_EECD_DI;
120
-	E1000_WRITE_REG(hw, E1000_EECD, eecd);
121
-}
122
-
123
-/**
124
- *  igb_shift_in_eec_bits - Shift data bits in from the EEPROM
125
- *  @hw: pointer to the HW structure
126
- *  @count: number of bits to shift in
127
- *
128
- *  In order to read a register from the EEPROM, we need to shift 'count' bits
129
- *  in from the EEPROM.  Bits are "shifted in" by raising the clock input to
130
- *  the EEPROM (setting the SK bit), and then reading the value of the data out
131
- *  "DO" bit.  During this "shifting in" process the data in "DI" bit should
132
- *  always be clear.
133
- **/
134
-static u16 igb_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
135
-{
136
-	u32 eecd;
137
-	u32 i;
138
-	u16 data;
139
-
140
-	DEBUGFUNC("igb_shift_in_eec_bits");
141
-
142
-	eecd = E1000_READ_REG(hw, E1000_EECD);
143
-
144
-	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
145
-	data = 0;
146
-
147
-	for (i = 0; i < count; i++) {
148
-		data <<= 1;
149
-		igb_raise_eec_clk(hw, &eecd);
150
-
151
-		eecd = E1000_READ_REG(hw, E1000_EECD);
152
-
153
-		eecd &= ~E1000_EECD_DI;
154
-		if (eecd & E1000_EECD_DO)
155
-			data |= 1;
156
-
157
-		igb_lower_eec_clk(hw, &eecd);
158
-	}
159
-
160
-	return data;
161
-}
162
-
163
-/**
164
- *  igb_poll_eerd_eewr_done - Poll for EEPROM read/write completion
165
- *  @hw: pointer to the HW structure
166
- *  @ee_reg: EEPROM flag for polling
167
- *
168
- *  Polls the EEPROM status bit for either read or write completion based
169
- *  upon the value of 'ee_reg'.
170
- **/
171
-s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
172
-{
173
-	u32 attempts = 100000;
174
-	u32 i, reg = 0;
175
-	s32 ret_val = -E1000_ERR_NVM;
176
-
177
-	DEBUGFUNC("igb_poll_eerd_eewr_done");
178
-
179
-	for (i = 0; i < attempts; i++) {
180
-		if (ee_reg == E1000_NVM_POLL_READ)
181
-			reg = E1000_READ_REG(hw, E1000_EERD);
182
-		else
183
-			reg = E1000_READ_REG(hw, E1000_EEWR);
184
-
185
-		if (reg & E1000_NVM_RW_REG_DONE) {
186
-			ret_val = E1000_SUCCESS;
187
-			break;
188
-		}
189
-
190
-		usec_delay(5);
191
-	}
192
-
193
-	return ret_val;
194
-}
195
-
196
-/**
197
- *  igb_acquire_nvm_generic - Generic request for access to EEPROM
198
- *  @hw: pointer to the HW structure
199
- *
200
- *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
201
- *  Return successful if access grant bit set, else clear the request for
202
- *  EEPROM access and return -E1000_ERR_NVM (-1).
203
- **/
204
-s32 igb_acquire_nvm_generic(struct e1000_hw *hw)
205
-{
206
-	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
207
-	s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
208
-	s32 ret_val = E1000_SUCCESS;
209
-
210
-	DEBUGFUNC("igb_acquire_nvm_generic");
211
-
212
-	E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
213
-	eecd = E1000_READ_REG(hw, E1000_EECD);
214
-
215
-	while (timeout) {
216
-		if (eecd & E1000_EECD_GNT)
217
-			break;
218
-		usec_delay(5);
219
-		eecd = E1000_READ_REG(hw, E1000_EECD);
220
-		timeout--;
221
-	}
222
-
223
-	if (!timeout) {
224
-		eecd &= ~E1000_EECD_REQ;
225
-		E1000_WRITE_REG(hw, E1000_EECD, eecd);
226
-		DEBUGOUT("Could not acquire NVM grant\n");
227
-		ret_val = -E1000_ERR_NVM;
228
-	}
229
-
230
-	return ret_val;
231
-}
232
-
233
-/**
234
- *  igb_standby_nvm - Return EEPROM to standby state
235
- *  @hw: pointer to the HW structure
236
- *
237
- *  Return the EEPROM to a standby state.
238
- **/
239
-static void igb_standby_nvm(struct e1000_hw *hw)
240
-{
241
-	struct e1000_nvm_info *nvm = &hw->nvm;
242
-	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
243
-
244
-	DEBUGFUNC("igb_standby_nvm");
245
-
246
-	if (nvm->type == e1000_nvm_eeprom_spi) {
247
-		/* Toggle CS to flush commands */
248
-		eecd |= E1000_EECD_CS;
249
-		E1000_WRITE_REG(hw, E1000_EECD, eecd);
250
-		E1000_WRITE_FLUSH(hw);
251
-		usec_delay(nvm->delay_usec);
252
-		eecd &= ~E1000_EECD_CS;
253
-		E1000_WRITE_REG(hw, E1000_EECD, eecd);
254
-		E1000_WRITE_FLUSH(hw);
255
-		usec_delay(nvm->delay_usec);
256
-	}
257
-}
258
-
259
-/**
260
- *  igb_stop_nvm - Terminate EEPROM command
261
- *  @hw: pointer to the HW structure
262
- *
263
- *  Terminates the current command by inverting the EEPROM's chip select pin.
264
- **/
265
-static void igb_stop_nvm(struct e1000_hw *hw)
266
-{
267
-	u32 eecd;
268
-
269
-	DEBUGFUNC("igb_stop_nvm");
270
-
271
-	eecd = E1000_READ_REG(hw, E1000_EECD);
272
-	if (hw->nvm.type == e1000_nvm_eeprom_spi) {
273
-		/* Pull CS high */
274
-		eecd |= E1000_EECD_CS;
275
-		igb_lower_eec_clk(hw, &eecd);
276
-	}
277
-}
278
-
279
-/**
280
- *  igb_release_nvm_generic - Release exclusive access to EEPROM
281
- *  @hw: pointer to the HW structure
282
- *
283
- *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
284
- **/
285
-void igb_release_nvm_generic(struct e1000_hw *hw)
286
-{
287
-	u32 eecd;
288
-
289
-	DEBUGFUNC("igb_release_nvm_generic");
290
-
291
-	igb_stop_nvm(hw);
292
-
293
-	eecd = E1000_READ_REG(hw, E1000_EECD);
294
-	eecd &= ~E1000_EECD_REQ;
295
-	E1000_WRITE_REG(hw, E1000_EECD, eecd);
296
-}
297
-
298
-/**
299
- *  igb_ready_nvm_eeprom - Prepares EEPROM for read/write
300
- *  @hw: pointer to the HW structure
301
- *
302
- *  Setups the EEPROM for reading and writing.
303
- **/
304
-static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw)
305
-{
306
-	struct e1000_nvm_info *nvm = &hw->nvm;
307
-	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
308
-	s32 ret_val = E1000_SUCCESS;
309
-	u16 timeout = 0;
310
-	u8 spi_stat_reg;
311
-
312
-	DEBUGFUNC("igb_ready_nvm_eeprom");
313
-
314
-	if (nvm->type == e1000_nvm_eeprom_spi) {
315
-		/* Clear SK and CS */
316
-		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
317
-		E1000_WRITE_REG(hw, E1000_EECD, eecd);
318
-		usec_delay(1);
319
-		timeout = NVM_MAX_RETRY_SPI;
320
-
321
-		/*
322
-		 * Read "Status Register" repeatedly until the LSB is cleared.
323
-		 * The EEPROM will signal that the command has been completed
324
-		 * by clearing bit 0 of the internal status register.  If it's
325
-		 * not cleared within 'timeout', then error out.
326
-		 */
327
-		while (timeout) {
328
-			igb_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
329
-			                         hw->nvm.opcode_bits);
330
-			spi_stat_reg = (u8)igb_shift_in_eec_bits(hw, 8);
331
-			if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
332
-				break;
333
-
334
-			usec_delay(5);
335
-			igb_standby_nvm(hw);
336
-			timeout--;
337
-		}
338
-
339
-		if (!timeout) {
340
-			DEBUGOUT("SPI NVM Status error\n");
341
-			ret_val = -E1000_ERR_NVM;
342
-			goto out;
343
-		}
344
-	}
345
-
346
-out:
347
-	return ret_val;
348
-}
349
-
350
-/**
351
- *  igb_read_nvm_eerd - Reads EEPROM using EERD register
352
- *  @hw: pointer to the HW structure
353
- *  @offset: offset of word in the EEPROM to read
354
- *  @words: number of words to read
355
- *  @data: word read from the EEPROM
356
- *
357
- *  Reads a 16 bit word from the EEPROM using the EERD register.
358
- **/
359
-s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
360
-{
361
-	struct e1000_nvm_info *nvm = &hw->nvm;
362
-	u32 i, eerd = 0;
363
-	s32 ret_val = E1000_SUCCESS;
364
-
365
-	DEBUGFUNC("igb_read_nvm_eerd");
366
-
367
-	/*
368
-	 * A check for invalid values:  offset too large, too many words,
369
-	 * too many words for the offset, and not enough words.
370
-	 */
371
-	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
372
-	    (words == 0)) {
373
-		DEBUGOUT("nvm parameter(s) out of bounds\n");
374
-		ret_val = -E1000_ERR_NVM;
375
-		goto out;
376
-	}
377
-
378
-	for (i = 0; i < words; i++) {
379
-		eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
380
-		       E1000_NVM_RW_REG_START;
381
-
382
-		E1000_WRITE_REG(hw, E1000_EERD, eerd);
383
-		ret_val = igb_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
384
-		if (ret_val)
385
-			break;
386
-
387
-		data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
388
-		           E1000_NVM_RW_REG_DATA);
389
-	}
390
-
391
-out:
392
-	return ret_val;
393
-}
394
-
395
-/**
396
- *  igb_write_nvm_spi - Write to EEPROM using SPI
397
- *  @hw: pointer to the HW structure
398
- *  @offset: offset within the EEPROM to be written to
399
- *  @words: number of words to write
400
- *  @data: 16 bit word(s) to be written to the EEPROM
401
- *
402
- *  Writes data to EEPROM at offset using SPI interface.
403
- *
404
- *  If e1000_update_nvm_checksum is not called after this function , the
405
- *  EEPROM will most likely contain an invalid checksum.
406
- **/
407
-s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
408
-{
409
-	struct e1000_nvm_info *nvm = &hw->nvm;
410
-	s32 ret_val;
411
-	u16 widx = 0;
412
-
413
-	DEBUGFUNC("igb_write_nvm_spi");
414
-
415
-	/*
416
-	 * A check for invalid values:  offset too large, too many words,
417
-	 * and not enough words.
418
-	 */
419
-	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
420
-	    (words == 0)) {
421
-		DEBUGOUT("nvm parameter(s) out of bounds\n");
422
-		ret_val = -E1000_ERR_NVM;
423
-		goto out;
424
-	}
425
-
426
-	ret_val = nvm->ops.acquire(hw);
427
-	if (ret_val)
428
-		goto out;
429
-
430
-	while (widx < words) {
431
-		u8 write_opcode = NVM_WRITE_OPCODE_SPI;
432
-
433
-		ret_val = igb_ready_nvm_eeprom(hw);
434
-		if (ret_val)
435
-			goto release;
436
-
437
-		igb_standby_nvm(hw);
438
-
439
-		/* Send the WRITE ENABLE command (8 bit opcode) */
440
-		igb_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
441
-		                         nvm->opcode_bits);
442
-
443
-		igb_standby_nvm(hw);
444
-
445
-		/*
446
-		 * Some SPI eeproms use the 8th address bit embedded in the
447
-		 * opcode
448
-		 */
449
-		if ((nvm->address_bits == 8) && (offset >= 128))
450
-			write_opcode |= NVM_A8_OPCODE_SPI;
451
-
452
-		/* Send the Write command (8-bit opcode + addr) */
453
-		igb_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
454
-		igb_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
455
-		                         nvm->address_bits);
456
-
457
-		/* Loop to allow for up to whole page write of eeprom */
458
-		while (widx < words) {
459
-			u16 word_out = data[widx];
460
-			word_out = (word_out >> 8) | (word_out << 8);
461
-			igb_shift_out_eec_bits(hw, word_out, 16);
462
-			widx++;
463
-
464
-			if ((((offset + widx) * 2) % nvm->page_size) == 0) {
465
-				igb_standby_nvm(hw);
466
-				break;
467
-			}
468
-		}
469
-	}
470
-
471
-	msec_delay(10);
472
-release:
473
-	nvm->ops.release(hw);
474
-
475
-out:
476
-	return ret_val;
477
-}
478
-
479
-/**
480
- *  igb_read_pba_num_generic - Read device part number
481
- *  @hw: pointer to the HW structure
482
- *  @pba_num: pointer to device part number
483
- *
484
- *  Reads the product board assembly (PBA) number from the EEPROM and stores
485
- *  the value in pba_num.
486
- **/
487
-s32 igb_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
488
-{
489
-	s32  ret_val;
490
-	u16 nvm_data;
491
-
492
-	DEBUGFUNC("igb_read_pba_num_generic");
493
-
494
-	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
495
-	if (ret_val) {
496
-		DEBUGOUT("NVM Read Error\n");
497
-		goto out;
498
-	}
499
-	*pba_num = (u32)(nvm_data << 16);
500
-
501
-	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
502
-	if (ret_val) {
503
-		DEBUGOUT("NVM Read Error\n");
504
-		goto out;
505
-	}
506
-	*pba_num |= nvm_data;
507
-
508
-out:
509
-	return ret_val;
510
-}
511
-
512
-/**
513
- *  igb_read_mac_addr_generic - Read device MAC address
514
- *  @hw: pointer to the HW structure
515
- *
516
- *  Reads the device MAC address from the EEPROM and stores the value.
517
- *  Since devices with two ports use the same EEPROM, we increment the
518
- *  last bit in the MAC address for the second port.
519
- **/
520
-s32 igb_read_mac_addr_generic(struct e1000_hw *hw)
521
-{
522
-	u32 rar_high;
523
-	u32 rar_low;
524
-	u16 i;
525
-
526
-	rar_high = E1000_READ_REG(hw, E1000_RAH(0));
527
-	rar_low = E1000_READ_REG(hw, E1000_RAL(0));
528
-
529
-	for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
530
-		hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
531
-
532
-	for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
533
-		hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
534
-
535
-	for (i = 0; i < ETH_ADDR_LEN; i++)
536
-		hw->mac.addr[i] = hw->mac.perm_addr[i];
537
-
538
-	return E1000_SUCCESS;
539
-}
540
-
541
-/**
542
- *  igb_validate_nvm_checksum_generic - Validate EEPROM checksum
543
- *  @hw: pointer to the HW structure
544
- *
545
- *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
546
- *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
547
- **/
548
-s32 igb_validate_nvm_checksum_generic(struct e1000_hw *hw)
549
-{
550
-	s32 ret_val = E1000_SUCCESS;
551
-	u16 checksum = 0;
552
-	u16 i, nvm_data;
553
-
554
-	DEBUGFUNC("igb_validate_nvm_checksum_generic");
555
-
556
-	for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
557
-		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
558
-		if (ret_val) {
559
-			DEBUGOUT("NVM Read Error\n");
560
-			goto out;
561
-		}
562
-		checksum += nvm_data;
563
-	}
564
-
565
-	if (checksum != (u16) NVM_SUM) {
566
-		DEBUGOUT("NVM Checksum Invalid\n");
567
-		ret_val = -E1000_ERR_NVM;
568
-		goto out;
569
-	}
570
-
571
-out:
572
-	return ret_val;
573
-}
574
-
575
-/**
576
- *  igb_update_nvm_checksum_generic - Update EEPROM checksum
577
- *  @hw: pointer to the HW structure
578
- *
579
- *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
580
- *  up to the checksum.  Then calculates the EEPROM checksum and writes the
581
- *  value to the EEPROM.
582
- **/
583
-s32 igb_update_nvm_checksum_generic(struct e1000_hw *hw)
584
-{
585
-	s32  ret_val;
586
-	u16 checksum = 0;
587
-	u16 i, nvm_data;
588
-
589
-	DEBUGFUNC("igb_update_nvm_checksum");
590
-
591
-	for (i = 0; i < NVM_CHECKSUM_REG; i++) {
592
-		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
593
-		if (ret_val) {
594
-			DEBUGOUT("NVM Read Error while updating checksum.\n");
595
-			goto out;
596
-		}
597
-		checksum += nvm_data;
598
-	}
599
-	checksum = (u16) NVM_SUM - checksum;
600
-	ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
601
-	if (ret_val) {
602
-		DEBUGOUT("NVM Write Error while updating checksum.\n");
603
-        }
604
-out:
605
-	return ret_val;
606
-}
607
-
608
-/**
609
- *  igb_reload_nvm_generic - Reloads EEPROM
610
- *  @hw: pointer to the HW structure
611
- *
612
- *  Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
613
- *  extended control register.
614
- **/
615
-static void igb_reload_nvm_generic(struct e1000_hw *hw)
616
-{
617
-	u32 ctrl_ext;
618
-
619
-	DEBUGFUNC("igb_reload_nvm_generic");
620
-
621
-	usec_delay(10);
622
-	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
623
-	ctrl_ext |= E1000_CTRL_EXT_EE_RST;
624
-	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
625
-	E1000_WRITE_FLUSH(hw);
626
-}
627
-

+ 0
- 52
src/drivers/net/igb/igb_nvm.h Прегледај датотеку

@@ -1,52 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel(R) Gigabit Ethernet Linux driver
4
-  Copyright(c) 2007-2009 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
-
26
-*******************************************************************************/
27
-
28
-FILE_LICENCE ( GPL2_ONLY );
29
-
30
-#ifndef _IGB_NVM_H_
31
-#define _IGB_NVM_H_
32
-
33
-void igb_init_nvm_ops_generic(struct e1000_hw *hw);
34
-s32  igb_acquire_nvm_generic(struct e1000_hw *hw);
35
-
36
-s32  igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
37
-s32  igb_read_mac_addr_generic(struct e1000_hw *hw);
38
-s32  igb_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num);
39
-s32  igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words,
40
-                         u16 *data);
41
-s32  igb_valid_led_default_generic(struct e1000_hw *hw, u16 *data);
42
-s32  igb_validate_nvm_checksum_generic(struct e1000_hw *hw);
43
-s32  igb_write_nvm_eewr(struct e1000_hw *hw, u16 offset,
44
-                          u16 words, u16 *data);
45
-s32  igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words,
46
-                         u16 *data);
47
-s32  igb_update_nvm_checksum_generic(struct e1000_hw *hw);
48
-void igb_release_nvm_generic(struct e1000_hw *hw);
49
-
50
-#define E1000_STM_OPCODE  0xDB00
51
-
52
-#endif /* _IGB_NVM_H_ */

+ 0
- 124
src/drivers/net/igb/igb_osdep.h Прегледај датотеку

@@ -1,124 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel(R) Gigabit Ethernet Linux driver
4
-  Copyright(c) 2007-2009 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
-
26
-*******************************************************************************/
27
-
28
-FILE_LICENCE ( GPL2_ONLY );
29
-
30
-/* glue for the OS independent part of e1000
31
- * includes register access macros
32
- */
33
-
34
-#ifndef _IGB_OSDEP_H_
35
-#define _IGB_OSDEP_H_
36
-
37
-/* Begin OS Dependencies */
38
-
39
-#define u8         unsigned char
40
-#define bool       boolean_t
41
-#define dma_addr_t unsigned long
42
-#define __le16     uint16_t
43
-#define __le32     uint32_t
44
-#define __le64     uint64_t
45
-
46
-#define __iomem
47
-#define __devinit
48
-
49
-#define msleep(x) mdelay(x)
50
-
51
-#define ETH_FCS_LEN 4
52
-
53
-typedef int spinlock_t;
54
-typedef enum {
55
-    false = 0,
56
-    true = 1
57
-} boolean_t;
58
-
59
-#define TRUE  1
60
-#define FALSE 0
61
-
62
-#define usec_delay(x) udelay(x)
63
-#define msec_delay(x) mdelay(x)
64
-#define msec_delay_irq(x) mdelay(x)
65
-
66
-/* End OS Dependencies */
67
-
68
-#define PCI_COMMAND_REGISTER   PCI_COMMAND
69
-#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
70
-#define ETH_ADDR_LEN           ETH_ALEN
71
-
72
-#define DEBUGOUT(S) if (0) { printf(S); }
73
-#define DEBUGOUT1(S, A...) if (0) { printf(S, A); }
74
-
75
-#define DEBUGFUNC(F) DEBUGOUT(F "\n")
76
-#define DEBUGOUT2 DEBUGOUT1
77
-#define DEBUGOUT3 DEBUGOUT2
78
-#define DEBUGOUT7 DEBUGOUT3
79
-
80
-#define E1000_REGISTER(a, reg) (reg)
81
-
82
-#define E1000_WRITE_REG(a, reg, value) do {  \
83
-                writel((value), ((a)->hw_addr + E1000_REGISTER(a, reg))); } while (0)
84
-
85
-#define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_REGISTER(a, reg)))
86
-
87
-#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) do { \
88
-          writel((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 2))); } while (0);
89
-
90
-#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
91
-    readl((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 2)))
92
-
93
-#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
94
-#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
95
-
96
-#define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
97
-    writew((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 1))))
98
-
99
-#define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
100
-    readw((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 1)))
101
-
102
-#define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
103
-    writeb((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + (offset))))
104
-
105
-#define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
106
-    readb((a)->hw_addr + E1000_REGISTER(a, reg) + (offset)))
107
-
108
-#define E1000_WRITE_REG_IO(a, reg, offset) do { \
109
-    outl(reg, ((a)->io_base));                  \
110
-    outl(offset, ((a)->io_base + 4));      } while (0)
111
-
112
-#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS)
113
-
114
-#define E1000_WRITE_FLASH_REG(a, reg, value) ( \
115
-    writel((value), ((a)->flash_address + reg)))
116
-
117
-#define E1000_WRITE_FLASH_REG16(a, reg, value) ( \
118
-    writew((value), ((a)->flash_address + reg)))
119
-
120
-#define E1000_READ_FLASH_REG(a, reg) (readl((a)->flash_address + reg))
121
-
122
-#define E1000_READ_FLASH_REG16(a, reg) (readw((a)->flash_address + reg))
123
-
124
-#endif /* _IGB_OSDEP_H_ */

+ 0
- 2470
src/drivers/net/igb/igb_phy.c
Разлика између датотеке није приказан због своје велике величине
Прегледај датотеку


+ 0
- 171
src/drivers/net/igb/igb_phy.h Прегледај датотеку

@@ -1,171 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel(R) Gigabit Ethernet Linux driver
4
-  Copyright(c) 2007-2009 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
-
26
-*******************************************************************************/
27
-
28
-FILE_LICENCE ( GPL2_ONLY );
29
-
30
-#ifndef _IGB_PHY_H_
31
-#define _IGB_PHY_H_
32
-
33
-void igb_init_phy_ops_generic(struct e1000_hw *hw);
34
-s32  igb_check_downshift_generic(struct e1000_hw *hw);
35
-s32  igb_check_polarity_m88(struct e1000_hw *hw);
36
-s32  igb_check_polarity_igp(struct e1000_hw *hw);
37
-s32  igb_check_polarity_ife(struct e1000_hw *hw);
38
-s32  igb_check_reset_block_generic(struct e1000_hw *hw);
39
-s32  igb_copper_link_autoneg(struct e1000_hw *hw);
40
-s32  igb_copper_link_setup_igp(struct e1000_hw *hw);
41
-s32  igb_copper_link_setup_m88(struct e1000_hw *hw);
42
-#if 0
43
-s32  igb_phy_force_speed_duplex_igp(struct e1000_hw *hw);
44
-s32  igb_phy_force_speed_duplex_m88(struct e1000_hw *hw);
45
-s32  igb_phy_force_speed_duplex_ife(struct e1000_hw *hw);
46
-#endif
47
-#if 0
48
-s32  igb_get_cable_length_m88(struct e1000_hw *hw);
49
-s32  igb_get_cable_length_igp_2(struct e1000_hw *hw);
50
-#endif
51
-s32  igb_get_cfg_done_generic(struct e1000_hw *hw);
52
-s32  igb_get_phy_id(struct e1000_hw *hw);
53
-s32  igb_get_phy_info_igp(struct e1000_hw *hw);
54
-s32  igb_get_phy_info_m88(struct e1000_hw *hw);
55
-s32  igb_phy_sw_reset_generic(struct e1000_hw *hw);
56
-#if 0
57
-void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
58
-#endif
59
-s32  igb_phy_hw_reset_generic(struct e1000_hw *hw);
60
-s32  igb_phy_reset_dsp_generic(struct e1000_hw *hw);
61
-s32  igb_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);
62
-s32  igb_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);
63
-s32  igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
64
-s32  igb_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);
65
-s32  igb_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
66
-s32  igb_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active);
67
-s32  igb_setup_copper_link_generic(struct e1000_hw *hw);
68
-s32  igb_wait_autoneg_generic(struct e1000_hw *hw);
69
-s32  igb_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);
70
-s32  igb_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data);
71
-s32  igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
72
-s32  igb_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);
73
-s32  igb_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
74
-s32  igb_phy_reset_dsp(struct e1000_hw *hw);
75
-s32  igb_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
76
-                                u32 usec_interval, bool *success);
77
-s32  igb_phy_init_script_igp3(struct e1000_hw *hw);
78
-enum e1000_phy_type igb_get_phy_type_from_id(u32 phy_id);
79
-s32  igb_determine_phy_address(struct e1000_hw *hw);
80
-void igb_power_up_phy_copper(struct e1000_hw *hw);
81
-void igb_power_down_phy_copper(struct e1000_hw *hw);
82
-s32  igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
83
-s32  igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
84
-s32  igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
85
-s32  igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
86
-
87
-#define E1000_MAX_PHY_ADDR                4
88
-
89
-/* IGP01E1000 Specific Registers */
90
-#define IGP01E1000_PHY_PORT_CONFIG        0x10 /* Port Config */
91
-#define IGP01E1000_PHY_PORT_STATUS        0x11 /* Status */
92
-#define IGP01E1000_PHY_PORT_CTRL          0x12 /* Control */
93
-#define IGP01E1000_PHY_LINK_HEALTH        0x13 /* PHY Link Health */
94
-#define IGP01E1000_GMII_FIFO              0x14 /* GMII FIFO */
95
-#define IGP01E1000_PHY_CHANNEL_QUALITY    0x15 /* PHY Channel Quality */
96
-#define IGP02E1000_PHY_POWER_MGMT         0x19 /* Power Management */
97
-#define IGP01E1000_PHY_PAGE_SELECT        0x1F /* Page Select */
98
-#define BM_PHY_PAGE_SELECT                22   /* Page Select for BM */
99
-#define IGP_PAGE_SHIFT                    5
100
-#define PHY_REG_MASK                      0x1F
101
-
102
-#define IGP01E1000_PHY_PCS_INIT_REG       0x00B4
103
-#define IGP01E1000_PHY_POLARITY_MASK      0x0078
104
-
105
-#define IGP01E1000_PSCR_AUTO_MDIX         0x1000
106
-#define IGP01E1000_PSCR_FORCE_MDI_MDIX    0x2000 /* 0=MDI, 1=MDIX */
107
-
108
-#define IGP01E1000_PSCFR_SMART_SPEED      0x0080
109
-
110
-/* Enable flexible speed on link-up */
111
-#define IGP01E1000_GMII_FLEX_SPD          0x0010
112
-#define IGP01E1000_GMII_SPD               0x0020 /* Enable SPD */
113
-
114
-#define IGP02E1000_PM_SPD                 0x0001 /* Smart Power Down */
115
-#define IGP02E1000_PM_D0_LPLU             0x0002 /* For D0a states */
116
-#define IGP02E1000_PM_D3_LPLU             0x0004 /* For all other states */
117
-
118
-#define IGP01E1000_PLHR_SS_DOWNGRADE      0x8000
119
-
120
-#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
121
-#define IGP01E1000_PSSR_MDIX              0x0800
122
-#define IGP01E1000_PSSR_SPEED_MASK        0xC000
123
-#define IGP01E1000_PSSR_SPEED_1000MBPS    0xC000
124
-
125
-#define IGP02E1000_PHY_CHANNEL_NUM        4
126
-#define IGP02E1000_PHY_AGC_A              0x11B1
127
-#define IGP02E1000_PHY_AGC_B              0x12B1
128
-#define IGP02E1000_PHY_AGC_C              0x14B1
129
-#define IGP02E1000_PHY_AGC_D              0x18B1
130
-
131
-#define IGP02E1000_AGC_LENGTH_SHIFT       9   /* Course - 15:13, Fine - 12:9 */
132
-#define IGP02E1000_AGC_LENGTH_MASK        0x7F
133
-#define IGP02E1000_AGC_RANGE              15
134
-
135
-#define IGP03E1000_PHY_MISC_CTRL          0x1B
136
-#define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET  0x1000 /* Manually Set Duplex */
137
-
138
-#define E1000_CABLE_LENGTH_UNDEFINED      0xFF
139
-
140
-#define E1000_KMRNCTRLSTA_OFFSET          0x001F0000
141
-#define E1000_KMRNCTRLSTA_OFFSET_SHIFT    16
142
-#define E1000_KMRNCTRLSTA_REN             0x00200000
143
-#define E1000_KMRNCTRLSTA_DIAG_OFFSET     0x3    /* Kumeran Diagnostic */
144
-#define E1000_KMRNCTRLSTA_TIMEOUTS        0x4    /* Kumeran Timeouts */
145
-#define E1000_KMRNCTRLSTA_INBAND_PARAM    0x9    /* Kumeran InBand Parameters */
146
-#define E1000_KMRNCTRLSTA_DIAG_NELPBK     0x1000 /* Nearend Loopback mode */
147
-
148
-#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
149
-#define IFE_PHY_SPECIAL_CONTROL     0x11 /* 100BaseTx PHY Special Control */
150
-#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
151
-#define IFE_PHY_MDIX_CONTROL        0x1C /* MDI/MDI-X Control */
152
-
153
-/* IFE PHY Extended Status Control */
154
-#define IFE_PESC_POLARITY_REVERSED    0x0100
155
-
156
-/* IFE PHY Special Control */
157
-#define IFE_PSC_AUTO_POLARITY_DISABLE      0x0010
158
-#define IFE_PSC_FORCE_POLARITY             0x0020
159
-#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
160
-
161
-/* IFE PHY Special Control and LED Control */
162
-#define IFE_PSCL_PROBE_MODE            0x0020
163
-#define IFE_PSCL_PROBE_LEDS_OFF        0x0006 /* Force LEDs 0 and 2 off */
164
-#define IFE_PSCL_PROBE_LEDS_ON         0x0007 /* Force LEDs 0 and 2 on */
165
-
166
-/* IFE PHY MDIX Control */
167
-#define IFE_PMC_MDIX_STATUS      0x0020 /* 1=MDI-X, 0=MDI */
168
-#define IFE_PMC_FORCE_MDIX       0x0040 /* 1=force MDI-X, 0=force MDI */
169
-#define IFE_PMC_AUTO_MDIX        0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
170
-
171
-#endif /* _IGB_PHY_H_ */

+ 0
- 486
src/drivers/net/igb/igb_regs.h Прегледај датотеку

@@ -1,486 +0,0 @@
1
-/*******************************************************************************
2
-
3
-  Intel(R) Gigabit Ethernet Linux driver
4
-  Copyright(c) 2007-2009 Intel Corporation.
5
-
6
-  This program is free software; you can redistribute it and/or modify it
7
-  under the terms and conditions of the GNU General Public License,
8
-  version 2, as published by the Free Software Foundation.
9
-
10
-  This program is distributed in the hope it will be useful, but WITHOUT
11
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
-  more details.
14
-
15
-  You should have received a copy of the GNU General Public License along with
16
-  this program; if not, write to the Free Software Foundation, Inc.,
17
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
-
19
-  The full GNU General Public License is included in this distribution in
20
-  the file called "COPYING".
21
-
22
-  Contact Information:
23
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
-
26
-*******************************************************************************/
27
-
28
-FILE_LICENCE ( GPL2_ONLY );
29
-
30
-#ifndef _IGB_REGS_H_
31
-#define _IGB_REGS_H_
32
-
33
-#define E1000_CTRL     0x00000  /* Device Control - RW */
34
-#define E1000_CTRL_DUP 0x00004  /* Device Control Duplicate (Shadow) - RW */
35
-#define E1000_STATUS   0x00008  /* Device Status - RO */
36
-#define E1000_EECD     0x00010  /* EEPROM/Flash Control - RW */
37
-#define E1000_EERD     0x00014  /* EEPROM Read - RW */
38
-#define E1000_CTRL_EXT 0x00018  /* Extended Device Control - RW */
39
-#define E1000_FLA      0x0001C  /* Flash Access - RW */
40
-#define E1000_MDIC     0x00020  /* MDI Control - RW */
41
-#define E1000_SCTL     0x00024  /* SerDes Control - RW */
42
-#define E1000_FCAL     0x00028  /* Flow Control Address Low - RW */
43
-#define E1000_FCAH     0x0002C  /* Flow Control Address High -RW */
44
-#define E1000_FEXT     0x0002C  /* Future Extended - RW */
45
-#define E1000_FEXTNVM  0x00028  /* Future Extended NVM - RW */
46
-#define E1000_FCT      0x00030  /* Flow Control Type - RW */
47
-#define E1000_CONNSW   0x00034  /* Copper/Fiber switch control - RW */
48
-#define E1000_VET      0x00038  /* VLAN Ether Type - RW */
49
-#define E1000_ICR      0x000C0  /* Interrupt Cause Read - R/clr */
50
-#define E1000_ITR      0x000C4  /* Interrupt Throttling Rate - RW */
51
-#define E1000_ICS      0x000C8  /* Interrupt Cause Set - WO */
52
-#define E1000_IMS      0x000D0  /* Interrupt Mask Set - RW */
53
-#define E1000_IMC      0x000D8  /* Interrupt Mask Clear - WO */
54
-#define E1000_IAM      0x000E0  /* Interrupt Acknowledge Auto Mask */
55
-#define E1000_RCTL     0x00100  /* Rx Control - RW */
56
-#define E1000_FCTTV    0x00170  /* Flow Control Transmit Timer Value - RW */
57
-#define E1000_TXCW     0x00178  /* Tx Configuration Word - RW */
58
-#define E1000_RXCW     0x00180  /* Rx Configuration Word - RO */
59
-#define E1000_EICR     0x01580  /* Ext. Interrupt Cause Read - R/clr */
60
-#define E1000_EITR(_n) (0x01680 + (0x4 * (_n)))
61
-#define E1000_EICS     0x01520  /* Ext. Interrupt Cause Set - W0 */
62
-#define E1000_EIMS     0x01524  /* Ext. Interrupt Mask Set/Read - RW */
63
-#define E1000_EIMC     0x01528  /* Ext. Interrupt Mask Clear - WO */
64
-#define E1000_EIAC     0x0152C  /* Ext. Interrupt Auto Clear - RW */
65
-#define E1000_EIAM     0x01530  /* Ext. Interrupt Ack Auto Clear Mask - RW */
66
-#define E1000_GPIE     0x01514  /* General Purpose Interrupt Enable - RW */
67
-#define E1000_IVAR0    0x01700  /* Interrupt Vector Allocation (array) - RW */
68
-#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
69
-#define E1000_TCTL     0x00400  /* Tx Control - RW */
70
-#define E1000_TCTL_EXT 0x00404  /* Extended Tx Control - RW */
71
-#define E1000_TIPG     0x00410  /* Tx Inter-packet gap -RW */
72
-#define E1000_TBT      0x00448  /* Tx Burst Timer - RW */
73
-#define E1000_AIT      0x00458  /* Adaptive Interframe Spacing Throttle - RW */
74
-#define E1000_LEDCTL   0x00E00  /* LED Control - RW */
75
-#define E1000_EXTCNF_CTRL  0x00F00  /* Extended Configuration Control */
76
-#define E1000_EXTCNF_SIZE  0x00F08  /* Extended Configuration Size */
77
-#define E1000_PHY_CTRL     0x00F10  /* PHY Control Register in CSR */
78
-#define E1000_PBA      0x01000  /* Packet Buffer Allocation - RW */
79
-#define E1000_PBS      0x01008  /* Packet Buffer Size */
80
-#define E1000_EEMNGCTL 0x01010  /* MNG EEprom Control */
81
-#define E1000_EEARBC   0x01024  /* EEPROM Auto Read Bus Control */
82
-#define E1000_FLASHT   0x01028  /* FLASH Timer Register */
83
-#define E1000_EEWR     0x0102C  /* EEPROM Write Register - RW */
84
-#define E1000_FLSWCTL  0x01030  /* FLASH control register */
85
-#define E1000_FLSWDATA 0x01034  /* FLASH data register */
86
-#define E1000_FLSWCNT  0x01038  /* FLASH Access Counter */
87
-#define E1000_FLOP     0x0103C  /* FLASH Opcode Register */
88
-#define E1000_I2CCMD   0x01028  /* SFPI2C Command Register - RW */
89
-#define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */
90
-#define E1000_WDSTP    0x01040  /* Watchdog Setup - RW */
91
-#define E1000_SWDSTS   0x01044  /* SW Device Status - RW */
92
-#define E1000_FRTIMER  0x01048  /* Free Running Timer - RW */
93
-#define E1000_TCPTIMER 0x0104C  /* TCP Timer - RW */
94
-#define E1000_VPDDIAG  0x01060  /* VPD Diagnostic - RO */
95
-#define E1000_ICR_V2   0x01500  /* Interrupt Cause - new location - RC */
96
-#define E1000_ICS_V2   0x01504  /* Interrupt Cause Set - new location - WO */
97
-#define E1000_IMS_V2   0x01508  /* Interrupt Mask Set/Read - new location - RW */
98
-#define E1000_IMC_V2   0x0150C  /* Interrupt Mask Clear - new location - WO */
99
-#define E1000_IAM_V2   0x01510  /* Interrupt Ack Auto Mask - new location - RW */
100
-#define E1000_ERT      0x02008  /* Early Rx Threshold - RW */
101
-#define E1000_FCRTL    0x02160  /* Flow Control Receive Threshold Low - RW */
102
-#define E1000_FCRTH    0x02168  /* Flow Control Receive Threshold High - RW */
103
-#define E1000_PSRCTL   0x02170  /* Packet Split Receive Control - RW */
104
-#define E1000_RDFPCQ(_n)  (0x02430 + (0x4 * (_n)))
105
-#define E1000_PBRTH    0x02458  /* PB Rx Arbitration Threshold - RW */
106
-#define E1000_FCRTV    0x02460  /* Flow Control Refresh Timer Value - RW */
107
-/* Split and Replication Rx Control - RW */
108
-#define E1000_RDPUMB   0x025CC  /* DMA Rx Descriptor uC Mailbox - RW */
109
-#define E1000_RDPUAD   0x025D0  /* DMA Rx Descriptor uC Addr Command - RW */
110
-#define E1000_RDPUWD   0x025D4  /* DMA Rx Descriptor uC Data Write - RW */
111
-#define E1000_RDPURD   0x025D8  /* DMA Rx Descriptor uC Data Read - RW */
112
-#define E1000_RDPUCTL  0x025DC  /* DMA Rx Descriptor uC Control - RW */
113
-#define E1000_PBDIAG   0x02458  /* Packet Buffer Diagnostic - RW */
114
-#define E1000_RXPBS    0x02404  /* Rx Packet Buffer Size - RW */
115
-#define E1000_RDTR     0x02820  /* Rx Delay Timer - RW */
116
-#define E1000_RADV     0x0282C  /* Rx Interrupt Absolute Delay Timer - RW */
117
-/*
118
- * Convenience macros
119
- *
120
- * Note: "_n" is the queue number of the register to be written to.
121
- *
122
- * Example usage:
123
- * E1000_RDBAL_REG(current_rx_queue)
124
- */
125
-#define E1000_RDBAL(_n)      ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \
126
-                                         (0x0C000 + ((_n) * 0x40)))
127
-#define E1000_RDBAH(_n)      ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \
128
-                                         (0x0C004 + ((_n) * 0x40)))
129
-#define E1000_RDLEN(_n)      ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \
130
-                                         (0x0C008 + ((_n) * 0x40)))
131
-#define E1000_SRRCTL(_n)     ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
132
-                                         (0x0C00C + ((_n) * 0x40)))
133
-#define E1000_RDH(_n)        ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \
134
-                                         (0x0C010 + ((_n) * 0x40)))
135
-#define E1000_RXCTL(_n)      ((_n) < 4 ? (0x02814 + ((_n) * 0x100)) : \
136
-                                         (0x0C014 + ((_n) * 0x40)))
137
-#define E1000_DCA_RXCTRL(_n) E1000_RXCTL(_n)
138
-#define E1000_RDT(_n)        ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \
139
-                                         (0x0C018 + ((_n) * 0x40)))
140
-#define E1000_RXDCTL(_n)     ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \
141
-                                         (0x0C028 + ((_n) * 0x40)))
142
-#define E1000_RQDPC(_n)      ((_n) < 4 ? (0x02830 + ((_n) * 0x100)) : \
143
-                                         (0x0C030 + ((_n) * 0x40)))
144
-#define E1000_TDBAL(_n)      ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \
145
-                                         (0x0E000 + ((_n) * 0x40)))
146
-#define E1000_TDBAH(_n)      ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \
147
-                                         (0x0E004 + ((_n) * 0x40)))
148
-#define E1000_TDLEN(_n)      ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \
149
-                                         (0x0E008 + ((_n) * 0x40)))
150
-#define E1000_TDH(_n)        ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \
151
-                                         (0x0E010 + ((_n) * 0x40)))
152
-#define E1000_TXCTL(_n)      ((_n) < 4 ? (0x03814 + ((_n) * 0x100)) : \
153
-                                         (0x0E014 + ((_n) * 0x40)))
154
-#define E1000_DCA_TXCTRL(_n) E1000_TXCTL(_n)
155
-#define E1000_TDT(_n)        ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \
156
-                                         (0x0E018 + ((_n) * 0x40)))
157
-#define E1000_TXDCTL(_n)     ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \
158
-                                         (0x0E028 + ((_n) * 0x40)))
159
-#define E1000_TDWBAL(_n)     ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : \
160
-                                         (0x0E038 + ((_n) * 0x40)))
161
-#define E1000_TDWBAH(_n)     ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : \
162
-                                         (0x0E03C + ((_n) * 0x40)))
163
-#define E1000_TARC(_n)                   (0x03840 + ((_n) * 0x100))
164
-#define E1000_RSRPD    0x02C00  /* Rx Small Packet Detect - RW */
165
-#define E1000_RAID     0x02C08  /* Receive Ack Interrupt Delay - RW */
166
-#define E1000_TXDMAC   0x03000  /* Tx DMA Control - RW */
167
-#define E1000_KABGTXD  0x03004  /* AFE Band Gap Transmit Ref Data */
168
-#define E1000_PSRTYPE(_i)       (0x05480 + ((_i) * 4))
169
-#define E1000_RAL(_i)  (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
170
-                                       (0x054E0 + ((_i - 16) * 8)))
171
-#define E1000_RAH(_i)  (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
172
-                                       (0x054E4 + ((_i - 16) * 8)))
173
-#define E1000_IP4AT_REG(_i)     (0x05840 + ((_i) * 8))
174
-#define E1000_IP6AT_REG(_i)     (0x05880 + ((_i) * 4))
175
-#define E1000_WUPM_REG(_i)      (0x05A00 + ((_i) * 4))
176
-#define E1000_FFMT_REG(_i)      (0x09000 + ((_i) * 8))
177
-#define E1000_FFVT_REG(_i)      (0x09800 + ((_i) * 8))
178
-#define E1000_FFLT_REG(_i)      (0x05F00 + ((_i) * 8))
179
-#define E1000_PBSLAC   0x03100  /* Packet Buffer Slave Access Control */
180
-#define E1000_PBSLAD(_n)  (0x03110 + (0x4 * (_n)))  /* Packet Buffer DWORD (_n) */
181
-#define E1000_TXPBS    0x03404  /* Tx Packet Buffer Size - RW */
182
-#define E1000_TDFH     0x03410  /* Tx Data FIFO Head - RW */
183
-#define E1000_TDFT     0x03418  /* Tx Data FIFO Tail - RW */
184
-#define E1000_TDFHS    0x03420  /* Tx Data FIFO Head Saved - RW */
185
-#define E1000_TDFTS    0x03428  /* Tx Data FIFO Tail Saved - RW */
186
-#define E1000_TDFPC    0x03430  /* Tx Data FIFO Packet Count - RW */
187
-#define E1000_TDPUMB   0x0357C  /* DMA Tx Descriptor uC Mail Box - RW */
188
-#define E1000_TDPUAD   0x03580  /* DMA Tx Descriptor uC Addr Command - RW */
189
-#define E1000_TDPUWD   0x03584  /* DMA Tx Descriptor uC Data Write - RW */
190
-#define E1000_TDPURD   0x03588  /* DMA Tx Descriptor uC Data  Read  - RW */
191
-#define E1000_TDPUCTL  0x0358C  /* DMA Tx Descriptor uC Control - RW */
192
-#define E1000_DTXCTL   0x03590  /* DMA Tx Control - RW */
193
-#define E1000_DTXTCPFLGL 0x0359C /* DMA Tx Control flag low - RW */
194
-#define E1000_DTXTCPFLGH 0x035A0 /* DMA Tx Control flag high - RW */
195
-#define E1000_DTXMXSZRQ  0x03540 /* DMA Tx Max Total Allow Size Requests - RW */
196
-#define E1000_TIDV     0x03820  /* Tx Interrupt Delay Value - RW */
197
-#define E1000_TADV     0x0382C  /* Tx Interrupt Absolute Delay Val - RW */
198
-#define E1000_TSPMT    0x03830  /* TCP Segmentation PAD & Min Threshold - RW */
199
-#define E1000_CRCERRS  0x04000  /* CRC Error Count - R/clr */
200
-#define E1000_ALGNERRC 0x04004  /* Alignment Error Count - R/clr */
201
-#define E1000_SYMERRS  0x04008  /* Symbol Error Count - R/clr */
202
-#define E1000_RXERRC   0x0400C  /* Receive Error Count - R/clr */
203
-#define E1000_MPC      0x04010  /* Missed Packet Count - R/clr */
204
-#define E1000_SCC      0x04014  /* Single Collision Count - R/clr */
205
-#define E1000_ECOL     0x04018  /* Excessive Collision Count - R/clr */
206
-#define E1000_MCC      0x0401C  /* Multiple Collision Count - R/clr */
207
-#define E1000_LATECOL  0x04020  /* Late Collision Count - R/clr */
208
-#define E1000_COLC     0x04028  /* Collision Count - R/clr */
209
-#define E1000_DC       0x04030  /* Defer Count - R/clr */
210
-#define E1000_TNCRS    0x04034  /* Tx-No CRS - R/clr */
211
-#define E1000_SEC      0x04038  /* Sequence Error Count - R/clr */
212
-#define E1000_CEXTERR  0x0403C  /* Carrier Extension Error Count - R/clr */
213
-#define E1000_RLEC     0x04040  /* Receive Length Error Count - R/clr */
214
-#define E1000_XONRXC   0x04048  /* XON Rx Count - R/clr */
215
-#define E1000_XONTXC   0x0404C  /* XON Tx Count - R/clr */
216
-#define E1000_XOFFRXC  0x04050  /* XOFF Rx Count - R/clr */
217
-#define E1000_XOFFTXC  0x04054  /* XOFF Tx Count - R/clr */
218
-#define E1000_FCRUC    0x04058  /* Flow Control Rx Unsupported Count- R/clr */
219
-#define E1000_PRC64    0x0405C  /* Packets Rx (64 bytes) - R/clr */
220
-#define E1000_PRC127   0x04060  /* Packets Rx (65-127 bytes) - R/clr */
221
-#define E1000_PRC255   0x04064  /* Packets Rx (128-255 bytes) - R/clr */
222
-#define E1000_PRC511   0x04068  /* Packets Rx (255-511 bytes) - R/clr */
223
-#define E1000_PRC1023  0x0406C  /* Packets Rx (512-1023 bytes) - R/clr */
224
-#define E1000_PRC1522  0x04070  /* Packets Rx (1024-1522 bytes) - R/clr */
225
-#define E1000_GPRC     0x04074  /* Good Packets Rx Count - R/clr */
226
-#define E1000_BPRC     0x04078  /* Broadcast Packets Rx Count - R/clr */
227
-#define E1000_MPRC     0x0407C  /* Multicast Packets Rx Count - R/clr */
228
-#define E1000_GPTC     0x04080  /* Good Packets Tx Count - R/clr */
229
-#define E1000_GORCL    0x04088  /* Good Octets Rx Count Low - R/clr */
230
-#define E1000_GORCH    0x0408C  /* Good Octets Rx Count High - R/clr */
231
-#define E1000_GOTCL    0x04090  /* Good Octets Tx Count Low - R/clr */
232
-#define E1000_GOTCH    0x04094  /* Good Octets Tx Count High - R/clr */
233
-#define E1000_RNBC     0x040A0  /* Rx No Buffers Count - R/clr */
234
-#define E1000_RUC      0x040A4  /* Rx Undersize Count - R/clr */
235
-#define E1000_RFC      0x040A8  /* Rx Fragment Count - R/clr */
236
-#define E1000_ROC      0x040AC  /* Rx Oversize Count - R/clr */
237
-#define E1000_RJC      0x040B0  /* Rx Jabber Count - R/clr */
238
-#define E1000_MGTPRC   0x040B4  /* Management Packets Rx Count - R/clr */
239
-#define E1000_MGTPDC   0x040B8  /* Management Packets Dropped Count - R/clr */
240
-#define E1000_MGTPTC   0x040BC  /* Management Packets Tx Count - R/clr */
241
-#define E1000_TORL     0x040C0  /* Total Octets Rx Low - R/clr */
242
-#define E1000_TORH     0x040C4  /* Total Octets Rx High - R/clr */
243
-#define E1000_TOTL     0x040C8  /* Total Octets Tx Low - R/clr */
244
-#define E1000_TOTH     0x040CC  /* Total Octets Tx High - R/clr */
245
-#define E1000_TPR      0x040D0  /* Total Packets Rx - R/clr */
246
-#define E1000_TPT      0x040D4  /* Total Packets Tx - R/clr */
247
-#define E1000_PTC64    0x040D8  /* Packets Tx (64 bytes) - R/clr */
248
-#define E1000_PTC127   0x040DC  /* Packets Tx (65-127 bytes) - R/clr */
249
-#define E1000_PTC255   0x040E0  /* Packets Tx (128-255 bytes) - R/clr */
250
-#define E1000_PTC511   0x040E4  /* Packets Tx (256-511 bytes) - R/clr */
251
-#define E1000_PTC1023  0x040E8  /* Packets Tx (512-1023 bytes) - R/clr */
252
-#define E1000_PTC1522  0x040EC  /* Packets Tx (1024-1522 Bytes) - R/clr */
253
-#define E1000_MPTC     0x040F0  /* Multicast Packets Tx Count - R/clr */
254
-#define E1000_BPTC     0x040F4  /* Broadcast Packets Tx Count - R/clr */
255
-#define E1000_TSCTC    0x040F8  /* TCP Segmentation Context Tx - R/clr */
256
-#define E1000_TSCTFC   0x040FC  /* TCP Segmentation Context Tx Fail - R/clr */
257
-#define E1000_IAC      0x04100  /* Interrupt Assertion Count */
258
-#define E1000_ICRXPTC  0x04104  /* Interrupt Cause Rx Pkt Timer Expire Count */
259
-#define E1000_ICRXATC  0x04108  /* Interrupt Cause Rx Abs Timer Expire Count */
260
-#define E1000_ICTXPTC  0x0410C  /* Interrupt Cause Tx Pkt Timer Expire Count */
261
-#define E1000_ICTXATC  0x04110  /* Interrupt Cause Tx Abs Timer Expire Count */
262
-#define E1000_ICTXQEC  0x04118  /* Interrupt Cause Tx Queue Empty Count */
263
-#define E1000_ICTXQMTC 0x0411C  /* Interrupt Cause Tx Queue Min Thresh Count */
264
-#define E1000_ICRXDMTC 0x04120  /* Interrupt Cause Rx Desc Min Thresh Count */
265
-#define E1000_ICRXOC   0x04124  /* Interrupt Cause Receiver Overrun Count */
266
-
267
-#define E1000_LSECTXUT        0x04300  /* LinkSec Tx Untagged Packet Count - OutPktsUntagged */
268
-#define E1000_LSECTXPKTE      0x04304  /* LinkSec Encrypted Tx Packets Count - OutPktsEncrypted */
269
-#define E1000_LSECTXPKTP      0x04308  /* LinkSec Protected Tx Packet Count - OutPktsProtected */
270
-#define E1000_LSECTXOCTE      0x0430C  /* LinkSec Encrypted Tx Octets Count - OutOctetsEncrypted */
271
-#define E1000_LSECTXOCTP      0x04310  /* LinkSec Protected Tx Octets Count - OutOctetsProtected */
272
-#define E1000_LSECRXUT        0x04314  /* LinkSec Untagged non-Strict Rx Packet Count - InPktsUntagged/InPktsNoTag */
273
-#define E1000_LSECRXOCTD      0x0431C  /* LinkSec Rx Octets Decrypted Count - InOctetsDecrypted */
274
-#define E1000_LSECRXOCTV      0x04320  /* LinkSec Rx Octets Validated - InOctetsValidated */
275
-#define E1000_LSECRXBAD       0x04324  /* LinkSec Rx Bad Tag - InPktsBadTag */
276
-#define E1000_LSECRXNOSCI     0x04328  /* LinkSec Rx Packet No SCI Count - InPktsNoSci */
277
-#define E1000_LSECRXUNSCI     0x0432C  /* LinkSec Rx Packet Unknown SCI Count - InPktsUnknownSci */
278
-#define E1000_LSECRXUNCH      0x04330  /* LinkSec Rx Unchecked Packets Count - InPktsUnchecked */
279
-#define E1000_LSECRXDELAY     0x04340  /* LinkSec Rx Delayed Packet Count - InPktsDelayed */
280
-#define E1000_LSECRXLATE      0x04350  /* LinkSec Rx Late Packets Count - InPktsLate */
281
-#define E1000_LSECRXOK(_n)    (0x04360 + (0x04 * (_n))) /* LinkSec Rx Packet OK Count - InPktsOk */
282
-#define E1000_LSECRXINV(_n)   (0x04380 + (0x04 * (_n))) /* LinkSec Rx Invalid Count - InPktsInvalid */
283
-#define E1000_LSECRXNV(_n)    (0x043A0 + (0x04 * (_n))) /* LinkSec Rx Not Valid Count - InPktsNotValid */
284
-#define E1000_LSECRXUNSA      0x043C0  /* LinkSec Rx Unused SA Count - InPktsUnusedSa */
285
-#define E1000_LSECRXNUSA      0x043D0  /* LinkSec Rx Not Using SA Count - InPktsNotUsingSa */
286
-#define E1000_LSECTXCAP       0x0B000  /* LinkSec Tx Capabilities Register - RO */
287
-#define E1000_LSECRXCAP       0x0B300  /* LinkSec Rx Capabilities Register - RO */
288
-#define E1000_LSECTXCTRL      0x0B004  /* LinkSec Tx Control - RW */
289
-#define E1000_LSECRXCTRL      0x0B304  /* LinkSec Rx Control - RW */
290
-#define E1000_LSECTXSCL       0x0B008  /* LinkSec Tx SCI Low - RW */
291
-#define E1000_LSECTXSCH       0x0B00C  /* LinkSec Tx SCI High - RW */
292
-#define E1000_LSECTXSA        0x0B010  /* LinkSec Tx SA0 - RW */
293
-#define E1000_LSECTXPN0       0x0B018  /* LinkSec Tx SA PN 0 - RW */
294
-#define E1000_LSECTXPN1       0x0B01C  /* LinkSec Tx SA PN 1 - RW */
295
-#define E1000_LSECRXSCL       0x0B3D0  /* LinkSec Rx SCI Low - RW */
296
-#define E1000_LSECRXSCH       0x0B3E0  /* LinkSec Rx SCI High - RW */
297
-#define E1000_LSECTXKEY0(_n)  (0x0B020 + (0x04 * (_n))) /* LinkSec Tx 128-bit Key 0 - WO */
298
-#define E1000_LSECTXKEY1(_n)  (0x0B030 + (0x04 * (_n))) /* LinkSec Tx 128-bit Key 1 - WO */
299
-#define E1000_LSECRXSA(_n)    (0x0B310 + (0x04 * (_n))) /* LinkSec Rx SAs - RW */
300
-#define E1000_LSECRXPN(_n)    (0x0B330 + (0x04 * (_n))) /* LinkSec Rx SAs - RW */
301
-/*
302
- * LinkSec Rx Keys  - where _n is the SA no. and _m the 4 dwords of the 128 bit
303
- * key - RW.
304
- */
305
-#define E1000_LSECRXKEY(_n, _m) (0x0B350 + (0x10 * (_n)) + (0x04 * (_m)))
306
-
307
-#define E1000_SSVPC             0x041A0  /* Switch Security Violation Packet Count */
308
-#define E1000_IPSCTRL           0xB430   /* IpSec Control Register */
309
-#define E1000_IPSRXCMD          0x0B408  /* IPSec Rx Command Register - RW */
310
-#define E1000_IPSRXIDX          0x0B400  /* IPSec Rx Index - RW */
311
-#define E1000_IPSRXIPADDR(_n)   (0x0B420+ (0x04 * (_n)))  /* IPSec Rx IPv4/v6 Address - RW */
312
-#define E1000_IPSRXKEY(_n)      (0x0B410 + (0x04 * (_n))) /* IPSec Rx 128-bit Key - RW */
313
-#define E1000_IPSRXSALT         0x0B404  /* IPSec Rx Salt - RW */
314
-#define E1000_IPSRXSPI          0x0B40C  /* IPSec Rx SPI - RW */
315
-#define E1000_IPSTXKEY(_n)      (0x0B460 + (0x04 * (_n))) /* IPSec Tx 128-bit Key - RW */
316
-#define E1000_IPSTXSALT         0x0B454  /* IPSec Tx Salt - RW */
317
-#define E1000_IPSTXIDX          0x0B450  /* IPSec Tx SA IDX - RW */
318
-#define E1000_PCS_CFG0    0x04200  /* PCS Configuration 0 - RW */
319
-#define E1000_PCS_LCTL    0x04208  /* PCS Link Control - RW */
320
-#define E1000_PCS_LSTAT   0x0420C  /* PCS Link Status - RO */
321
-#define E1000_CBTMPC      0x0402C  /* Circuit Breaker Tx Packet Count */
322
-#define E1000_HTDPMC      0x0403C  /* Host Transmit Discarded Packets */
323
-#define E1000_CBRDPC      0x04044  /* Circuit Breaker Rx Dropped Count */
324
-#define E1000_CBRMPC      0x040FC  /* Circuit Breaker Rx Packet Count */
325
-#define E1000_RPTHC       0x04104  /* Rx Packets To Host */
326
-#define E1000_HGPTC       0x04118  /* Host Good Packets Tx Count */
327
-#define E1000_HTCBDPC     0x04124  /* Host Tx Circuit Breaker Dropped Count */
328
-#define E1000_HGORCL      0x04128  /* Host Good Octets Received Count Low */
329
-#define E1000_HGORCH      0x0412C  /* Host Good Octets Received Count High */
330
-#define E1000_HGOTCL      0x04130  /* Host Good Octets Transmit Count Low */
331
-#define E1000_HGOTCH      0x04134  /* Host Good Octets Transmit Count High */
332
-#define E1000_LENERRS     0x04138  /* Length Errors Count */
333
-#define E1000_SCVPC       0x04228  /* SerDes/SGMII Code Violation Pkt Count */
334
-#define E1000_HRMPC       0x0A018  /* Header Redirection Missed Packet Count */
335
-#define E1000_PCS_ANADV   0x04218  /* AN advertisement - RW */
336
-#define E1000_PCS_LPAB    0x0421C  /* Link Partner Ability - RW */
337
-#define E1000_PCS_NPTX    0x04220  /* AN Next Page Transmit - RW */
338
-#define E1000_PCS_LPABNP  0x04224  /* Link Partner Ability Next Page - RW */
339
-#define E1000_1GSTAT_RCV  0x04228  /* 1GSTAT Code Violation Packet Count - RW */
340
-#define E1000_RXCSUM   0x05000  /* Rx Checksum Control - RW */
341
-#define E1000_RLPML    0x05004  /* Rx Long Packet Max Length */
342
-#define E1000_RFCTL    0x05008  /* Receive Filter Control*/
343
-#define E1000_MTA      0x05200  /* Multicast Table Array - RW Array */
344
-#define E1000_RA       0x05400  /* Receive Address - RW Array */
345
-#define E1000_RA2      0x054E0  /* 2nd half of receive address array - RW Array */
346
-#define E1000_VFTA     0x05600  /* VLAN Filter Table Array - RW Array */
347
-#define E1000_VT_CTL   0x0581C  /* VMDq Control - RW */
348
-#define E1000_VFQA0    0x0B000  /* VLAN Filter Queue Array 0 - RW Array */
349
-#define E1000_VFQA1    0x0B200  /* VLAN Filter Queue Array 1 - RW Array */
350
-#define E1000_WUC      0x05800  /* Wakeup Control - RW */
351
-#define E1000_WUFC     0x05808  /* Wakeup Filter Control - RW */
352
-#define E1000_WUS      0x05810  /* Wakeup Status - RO */
353
-#define E1000_MANC     0x05820  /* Management Control - RW */
354
-#define E1000_IPAV     0x05838  /* IP Address Valid - RW */
355
-#define E1000_IP4AT    0x05840  /* IPv4 Address Table - RW Array */
356
-#define E1000_IP6AT    0x05880  /* IPv6 Address Table - RW Array */
357
-#define E1000_WUPL     0x05900  /* Wakeup Packet Length - RW */
358
-#define E1000_WUPM     0x05A00  /* Wakeup Packet Memory - RO A */
359
-#define E1000_PBACL    0x05B68  /* MSIx PBA Clear - Read/Write 1's to clear */
360
-#define E1000_FFLT     0x05F00  /* Flexible Filter Length Table - RW Array */
361
-#define E1000_HOST_IF  0x08800  /* Host Interface */
362
-#define E1000_FFMT     0x09000  /* Flexible Filter Mask Table - RW Array */
363
-#define E1000_FFVT     0x09800  /* Flexible Filter Value Table - RW Array */
364
-#define E1000_FHFT(_n)  (0x09000 + (_n * 0x100)) /* Flexible Host Filter Table */
365
-#define E1000_FHFT_EXT(_n) (0x09A00 + (_n * 0x100)) /* Ext Flexible Host Filter Table */
366
-
367
-
368
-#define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */
369
-#define E1000_MDPHYA      0x0003C /* PHY address - RW */
370
-#define E1000_MANC2H      0x05860 /* Management Control To Host - RW */
371
-#define E1000_SW_FW_SYNC  0x05B5C /* Software-Firmware Synchronization - RW */
372
-#define E1000_CCMCTL      0x05B48 /* CCM Control Register */
373
-#define E1000_GIOCTL      0x05B44 /* GIO Analog Control Register */
374
-#define E1000_SCCTL       0x05B4C /* PCIc PLL Configuration Register */
375
-#define E1000_GCR         0x05B00 /* PCI-Ex Control */
376
-#define E1000_GCR2        0x05B64 /* PCI-Ex Control #2 */
377
-#define E1000_GSCL_1    0x05B10 /* PCI-Ex Statistic Control #1 */
378
-#define E1000_GSCL_2    0x05B14 /* PCI-Ex Statistic Control #2 */
379
-#define E1000_GSCL_3    0x05B18 /* PCI-Ex Statistic Control #3 */
380
-#define E1000_GSCL_4    0x05B1C /* PCI-Ex Statistic Control #4 */
381
-#define E1000_FACTPS    0x05B30 /* Function Active and Power State to MNG */
382
-#define E1000_SWSM      0x05B50 /* SW Semaphore */
383
-#define E1000_FWSM      0x05B54 /* FW Semaphore */
384
-#define E1000_SWSM2     0x05B58 /* Driver-only SW semaphore (not used by BOOT agents) */
385
-#define E1000_DCA_ID    0x05B70 /* DCA Requester ID Information - RO */
386
-#define E1000_DCA_CTRL  0x05B74 /* DCA Control - RW */
387
-#define E1000_FFLT_DBG  0x05F04 /* Debug Register */
388
-#define E1000_HICR      0x08F00 /* Host Interface Control */
389
-
390
-/* RSS registers */
391
-#define E1000_CPUVEC    0x02C10 /* CPU Vector Register - RW */
392
-#define E1000_MRQC      0x05818 /* Multiple Receive Control - RW */
393
-#define E1000_IMIR(_i)      (0x05A80 + ((_i) * 4))  /* Immediate Interrupt */
394
-#define E1000_IMIREXT(_i)   (0x05AA0 + ((_i) * 4))  /* Immediate Interrupt Ext*/
395
-#define E1000_IMIRVP    0x05AC0 /* Immediate Interrupt Rx VLAN Priority - RW */
396
-#define E1000_MSIXBM(_i)    (0x01600 + ((_i) * 4)) /* MSI-X Allocation Register
397
-                                                    * (_i) - RW */
398
-#define E1000_MSIXTADD(_i)  (0x0C000 + ((_i) * 0x10)) /* MSI-X Table entry addr
399
-                                                       * low reg - RW */
400
-#define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10)) /* MSI-X Table entry addr
401
-                                                       * upper reg - RW */
402
-#define E1000_MSIXTMSG(_i)  (0x0C008 + ((_i) * 0x10)) /* MSI-X Table entry
403
-                                                       * message reg - RW */
404
-#define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10)) /* MSI-X Table entry
405
-                                                       * vector ctrl reg - RW */
406
-#define E1000_MSIXPBA    0x0E000 /* MSI-X Pending bit array */
407
-#define E1000_RETA(_i)  (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */
408
-#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */
409
-#define E1000_RSSIM     0x05864 /* RSS Interrupt Mask */
410
-#define E1000_RSSIR     0x05868 /* RSS Interrupt Request */
411
-/* VT Registers */
412
-#define E1000_SWPBS     0x03004 /* Switch Packet Buffer Size - RW */
413
-#define E1000_MBVFICR   0x00C80 /* Mailbox VF Cause - RWC */
414
-#define E1000_MBVFIMR   0x00C84 /* Mailbox VF int Mask - RW */
415
-#define E1000_VFLRE     0x00C88 /* VF Register Events - RWC */
416
-#define E1000_VFRE      0x00C8C /* VF Receive Enables */
417
-#define E1000_VFTE      0x00C90 /* VF Transmit Enables */
418
-#define E1000_QDE       0x02408 /* Queue Drop Enable - RW */
419
-#define E1000_DTXSWC    0x03500 /* DMA Tx Switch Control - RW */
420
-#define E1000_RPLOLR    0x05AF0 /* Replication Offload - RW */
421
-#define E1000_UTA       0x0A000 /* Unicast Table Array - RW */
422
-#define E1000_IOVTCL    0x05BBC /* IOV Control Register */
423
-#define E1000_VMRCTL    0X05D80 /* Virtual Mirror Rule Control */
424
-/* These act per VF so an array friendly macro is used */
425
-#define E1000_V2PMAILBOX(_n)   (0x00C40 + (4 * (_n)))
426
-#define E1000_P2VMAILBOX(_n)   (0x00C00 + (4 * (_n)))
427
-#define E1000_VMBMEM(_n)       (0x00800 + (64 * (_n)))
428
-#define E1000_VFVMBMEM(_n)     (0x00800 + (_n))
429
-#define E1000_VMOLR(_n)        (0x05AD0 + (4 * (_n)))
430
-#define E1000_VLVF(_n)         (0x05D00 + (4 * (_n))) /* VLAN Virtual Machine
431
-                                                       * Filter - RW */
432
-/* Time Sync */
433
-#define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */
434
-#define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */
435
-#define E1000_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */
436
-#define E1000_RXSTMPL    0x0B624 /* Rx timestamp Low - RO */
437
-#define E1000_RXSTMPH    0x0B628 /* Rx timestamp High - RO */
438
-#define E1000_RXSATRL    0x0B62C /* Rx timestamp attribute low - RO */
439
-#define E1000_RXSATRH    0x0B630 /* Rx timestamp attribute high - RO */
440
-#define E1000_TXSTMPL    0x0B618 /* Tx timestamp value Low - RO */
441
-#define E1000_TXSTMPH    0x0B61C /* Tx timestamp value High - RO */
442
-#define E1000_SYSTIML    0x0B600 /* System time register Low - RO */
443
-#define E1000_SYSTIMH    0x0B604 /* System time register High - RO */
444
-#define E1000_TIMINCA    0x0B608 /* Increment attributes register - RW */
445
-
446
-/* Filtering Registers */
447
-#define E1000_SAQF(_n)  (0x05980 + (4 * (_n))) /* Source Address Queue Fltr */
448
-#define E1000_DAQF(_n)  (0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */
449
-#define E1000_SPQF(_n)  (0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */
450
-#define E1000_FTQF(_n)  (0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */
451
-#define E1000_TTQF(_n)  (0x059E0 + (4 * (_n))) /* 2-tuple Queue Fltr */
452
-#define E1000_SYNQF(_n) (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */
453
-#define E1000_ETQF(_n)  (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */
454
-
455
-#define E1000_RTTDCS            0x3600  /* Reedtown Tx Desc plane control and status */
456
-#define E1000_RTTPCS            0x3474  /* Reedtown Tx Packet Plane control and status */
457
-#define E1000_RTRPCS            0x2474  /* Rx packet plane control and status */
458
-#define E1000_RTRUP2TC          0x05AC4 /* Rx User Priority to Traffic Class */
459
-#define E1000_RTTUP2TC          0x0418  /* Transmit User Priority to Traffic Class */
460
-#define E1000_RTTDTCRC(_n)      (0x3610 + ((_n) * 4)) /* Tx Desc plane TC Rate-scheduler config */
461
-#define E1000_RTTPTCRC(_n)      (0x3480 + ((_n) * 4)) /* Tx Packet plane TC Rate-Scheduler Config */
462
-#define E1000_RTRPTCRC(_n)      (0x2480 + ((_n) * 4)) /* Rx Packet plane TC Rate-Scheduler Config */
463
-#define E1000_RTTDTCRS(_n)      (0x3630 + ((_n) * 4)) /* Tx Desc Plane TC Rate-Scheduler Status */
464
-#define E1000_RTTDTCRM(_n)      (0x3650 + ((_n) * 4)) /* Tx Desc Plane TC Rate-Scheduler MMW */
465
-#define E1000_RTTPTCRS(_n)      (0x34A0 + ((_n) * 4)) /* Tx Packet plane TC Rate-Scheduler Status */
466
-#define E1000_RTTPTCRM(_n)      (0x34C0 + ((_n) * 4)) /* Tx Packet plane TC Rate-scheduler MMW */
467
-#define E1000_RTRPTCRS(_n)      (0x24A0 + ((_n) * 4)) /* Rx Packet plane TC Rate-Scheduler Status */
468
-#define E1000_RTRPTCRM(_n)      (0x24C0 + ((_n) * 4)) /* Rx Packet plane TC Rate-Scheduler MMW */
469
-#define E1000_RTTDVMRM(_n)      (0x3670 + ((_n) * 4)) /* Tx Desc plane VM Rate-Scheduler MMW*/
470
-#define E1000_RTTBCNRM(_n)      (0x3690 + ((_n) * 4)) /* Tx BCN Rate-Scheduler MMW */
471
-#define E1000_RTTDQSEL          0x3604  /* Tx Desc Plane Queue Select */
472
-#define E1000_RTTDVMRC          0x3608  /* Tx Desc Plane VM Rate-Scheduler Config */
473
-#define E1000_RTTDVMRS          0x360C  /* Tx Desc Plane VM Rate-Scheduler Status */
474
-#define E1000_RTTBCNRC          0x36B0  /* Tx BCN Rate-Scheduler Config */
475
-#define E1000_RTTBCNRS          0x36B4  /* Tx BCN Rate-Scheduler Status */
476
-#define E1000_RTTBCNCR          0xB200  /* Tx BCN Control Register */
477
-#define E1000_RTTBCNTG          0x35A4  /* Tx BCN Tagging */
478
-#define E1000_RTTBCNCP          0xB208  /* Tx BCN Congestion point */
479
-#define E1000_RTRBCNCR          0xB20C  /* Rx BCN Control Register */
480
-#define E1000_RTTBCNRD          0x36B8  /* Tx BCN Rate Drift */
481
-#define E1000_PFCTOP            0x1080  /* Priority Flow Control Type and Opcode */
482
-#define E1000_RTTBCNIDX         0xB204  /* Tx BCN Congestion Point */
483
-#define E1000_RTTBCNACH         0x0B214 /* Tx BCN Control High */
484
-#define E1000_RTTBCNACL         0x0B210 /* Tx BCN Control Low */
485
-
486
-#endif /* _IGB_REGS_H_ */

+ 946
- 0
src/drivers/net/intel.c Прегледај датотеку

@@ -0,0 +1,946 @@
1
+/*
2
+ * Copyright (C) 2012 Michael Brown <mbrown@fensystems.co.uk>.
3
+ *
4
+ * This program is free software; you can redistribute it and/or
5
+ * modify it under the terms of the GNU General Public License as
6
+ * published by the Free Software Foundation; either version 2 of the
7
+ * License, or (at your option) any later version.
8
+ *
9
+ * This program is distributed in the hope that it will be useful, but
10
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
11
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
12
+ * General Public License for more details.
13
+ *
14
+ * You should have received a copy of the GNU General Public License
15
+ * along with this program; if not, write to the Free Software
16
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17
+ * 02110-1301, USA.
18
+ */
19
+
20
+FILE_LICENCE ( GPL2_OR_LATER );
21
+
22
+#include <stdint.h>
23
+#include <string.h>
24
+#include <unistd.h>
25
+#include <errno.h>
26
+#include <byteswap.h>
27
+#include <ipxe/netdevice.h>
28
+#include <ipxe/ethernet.h>
29
+#include <ipxe/if_ether.h>
30
+#include <ipxe/iobuf.h>
31
+#include <ipxe/malloc.h>
32
+#include <ipxe/pci.h>
33
+#include "intel.h"
34
+
35
+/** @file
36
+ *
37
+ * Intel 10/100/1000 network card driver
38
+ *
39
+ */
40
+
41
+/******************************************************************************
42
+ *
43
+ * EEPROM interface
44
+ *
45
+ ******************************************************************************
46
+ */
47
+
48
+/**
49
+ * Read data from EEPROM
50
+ *
51
+ * @v nvs		NVS device
52
+ * @v address		Address from which to read
53
+ * @v data		Data buffer
54
+ * @v len		Length of data buffer
55
+ * @ret rc		Return status code
56
+ */
57
+static int intel_read_eeprom ( struct nvs_device *nvs, unsigned int address,
58
+			       void *data, size_t len ) {
59
+	struct intel_nic *intel =
60
+		container_of ( nvs, struct intel_nic, eeprom );
61
+	unsigned int i;
62
+	uint32_t value;
63
+	uint16_t *data_word = data;
64
+
65
+	/* Sanity check.  We advertise a blocksize of one word, so
66
+	 * should only ever receive single-word requests.
67
+	 */
68
+	assert ( len == sizeof ( *data_word ) );
69
+
70
+	/* Initiate read */
71
+	writel ( ( INTEL_EERD_START | ( address << intel->eerd_addr_shift ) ),
72
+		 intel->regs + INTEL_EERD );
73
+
74
+	/* Wait for read to complete */
75
+	for ( i = 0 ; i < INTEL_EEPROM_MAX_WAIT_MS ; i++ ) {
76
+
77
+		/* If read is not complete, delay 1ms and retry */
78
+		value = readl ( intel->regs + INTEL_EERD );
79
+		if ( ! ( value & intel->eerd_done ) ) {
80
+			mdelay ( 1 );
81
+			continue;
82
+		}
83
+
84
+		/* Extract data */
85
+		*data_word = cpu_to_le16 ( INTEL_EERD_DATA ( value ) );
86
+		return 0;
87
+	}
88
+
89
+	DBGC ( intel, "INTEL %p timed out waiting for EEPROM read\n", intel );
90
+	return -ETIMEDOUT;
91
+}
92
+
93
+/**
94
+ * Write data to EEPROM
95
+ *
96
+ * @v nvs		NVS device
97
+ * @v address		Address to which to write
98
+ * @v data		Data buffer
99
+ * @v len		Length of data buffer
100
+ * @ret rc		Return status code
101
+ */
102
+static int intel_write_eeprom ( struct nvs_device *nvs,
103
+				unsigned int address __unused,
104
+				const void *data __unused,
105
+				size_t len __unused ) {
106
+	struct intel_nic *intel =
107
+		container_of ( nvs, struct intel_nic, eeprom );
108
+
109
+	DBGC ( intel, "INTEL %p EEPROM write not supported\n", intel );
110
+	return -ENOTSUP;
111
+}
112
+
113
+/**
114
+ * Initialise EEPROM
115
+ *
116
+ * @v intel		Intel device
117
+ * @ret rc		Return status code
118
+ */
119
+static int intel_init_eeprom ( struct intel_nic *intel ) {
120
+	unsigned int i;
121
+	uint32_t value;
122
+
123
+	/* The NIC automatically detects the type of attached EEPROM.
124
+	 * The EERD register provides access to only a single word at
125
+	 * a time, so we pretend to have a single-word block size.
126
+	 *
127
+	 * The EEPROM size may be larger than the minimum size, but
128
+	 * this doesn't matter to us since we access only the first
129
+	 * few words.
130
+	 */
131
+	intel->eeprom.word_len_log2 = INTEL_EEPROM_WORD_LEN_LOG2;
132
+	intel->eeprom.size = INTEL_EEPROM_MIN_SIZE_WORDS;
133
+	intel->eeprom.block_size = 1;
134
+	intel->eeprom.read = intel_read_eeprom;
135
+	intel->eeprom.write = intel_write_eeprom;
136
+
137
+	/* The layout of the EERD register was changed at some point
138
+	 * to accommodate larger EEPROMs.  Read from address zero (for
139
+	 * which the request layouts are compatible) to determine
140
+	 * which type of register we have.
141
+	 */
142
+	writel ( INTEL_EERD_START, intel->regs + INTEL_EERD );
143
+	for ( i = 0 ; i < INTEL_EEPROM_MAX_WAIT_MS ; i++ ) {
144
+		value = readl ( intel->regs + INTEL_EERD );
145
+		if ( value & INTEL_EERD_DONE_LARGE ) {
146
+			DBGC ( intel, "INTEL %p has large-format EERD\n",
147
+			       intel );
148
+			intel->eerd_done = INTEL_EERD_DONE_LARGE;
149
+			intel->eerd_addr_shift = INTEL_EERD_ADDR_SHIFT_LARGE;
150
+			return 0;
151
+		}
152
+		if ( value & INTEL_EERD_DONE_SMALL ) {
153
+			DBGC ( intel, "INTEL %p has small-format EERD\n",
154
+			       intel );
155
+			intel->eerd_done = INTEL_EERD_DONE_SMALL;
156
+			intel->eerd_addr_shift = INTEL_EERD_ADDR_SHIFT_SMALL;
157
+			return 0;
158
+		}
159
+		mdelay ( 1 );
160
+	}
161
+
162
+	DBGC ( intel, "INTEL %p timed out waiting for initial EEPROM read "
163
+	       "(value %08x)\n", intel, value );
164
+	return -ETIMEDOUT;
165
+}
166
+
167
+/******************************************************************************
168
+ *
169
+ * MAC address
170
+ *
171
+ ******************************************************************************
172
+ */
173
+
174
+/**
175
+ * Fetch initial MAC address from EEPROM
176
+ *
177
+ * @v intel		Intel device
178
+ * @v hw_addr		Hardware address to fill in
179
+ * @ret rc		Return status code
180
+ */
181
+static int intel_fetch_mac_eeprom ( struct intel_nic *intel,
182
+				    uint8_t *hw_addr ) {
183
+	int rc;
184
+
185
+	/* Initialise EEPROM */
186
+	if ( ( rc = intel_init_eeprom ( intel ) ) != 0 )
187
+		return rc;
188
+
189
+	/* Read base MAC address from EEPROM */
190
+	if ( ( rc = nvs_read ( &intel->eeprom, INTEL_EEPROM_MAC,
191
+			       hw_addr, ETH_ALEN ) ) != 0 ) {
192
+		DBGC ( intel, "INTEL %p could not read EEPROM base MAC "
193
+		       "address: %s\n", intel, strerror ( rc ) );
194
+		return rc;
195
+	}
196
+
197
+	/* Adjust MAC address for multi-port devices */
198
+	hw_addr[ETH_ALEN-1] ^= intel->port;
199
+
200
+	DBGC ( intel, "INTEL %p has EEPROM MAC address %s (port %d)\n",
201
+	       intel, eth_ntoa ( hw_addr ), intel->port );
202
+	return 0;
203
+}
204
+
205
+/**
206
+ * Fetch initial MAC address
207
+ *
208
+ * @v intel		Intel device
209
+ * @v hw_addr		Hardware address to fill in
210
+ * @ret rc		Return status code
211
+ */
212
+static int intel_fetch_mac ( struct intel_nic *intel, uint8_t *hw_addr ) {
213
+	union intel_receive_address mac;
214
+	int rc;
215
+
216
+	/* Read current address from RAL0/RAH0 */
217
+	mac.reg.low = cpu_to_le32 ( readl ( intel->regs + INTEL_RAL0 ) );
218
+	mac.reg.high = cpu_to_le32 ( readl ( intel->regs + INTEL_RAH0 ) );
219
+	DBGC ( intel, "INTEL %p has autoloaded MAC address %s\n",
220
+	       intel, eth_ntoa ( mac.raw ) );
221
+
222
+	/* Try to read address from EEPROM */
223
+	if ( ( rc = intel_fetch_mac_eeprom ( intel, hw_addr ) ) == 0 )
224
+		return 0;
225
+
226
+	/* Use current address if valid */
227
+	if ( is_valid_ether_addr ( mac.raw ) ) {
228
+		memcpy ( hw_addr, mac.raw, ETH_ALEN );
229
+		return 0;
230
+	}
231
+
232
+	DBGC ( intel, "INTEL %p has no MAC address to use\n", intel );
233
+	return -ENOENT;
234
+}
235
+
236
+/******************************************************************************
237
+ *
238
+ * Diagnostics
239
+ *
240
+ ******************************************************************************
241
+ */
242
+
243
+/**
244
+ * Dump diagnostic information
245
+ *
246
+ * @v intel		Intel device
247
+ */
248
+static void __attribute__ (( unused )) intel_diag ( struct intel_nic *intel ) {
249
+
250
+	DBGC ( intel, "INTEL %p TDH=%04x TDT=%04x RDH=%04x RDT=%04x\n", intel,
251
+	       readl ( intel->regs + INTEL_TDH ),
252
+	       readl ( intel->regs + INTEL_TDT ),
253
+	       readl ( intel->regs + INTEL_RDH ),
254
+	       readl ( intel->regs + INTEL_RDT ) );
255
+}
256
+
257
+/******************************************************************************
258
+ *
259
+ * Device reset
260
+ *
261
+ ******************************************************************************
262
+ */
263
+
264
+/**
265
+ * Reset hardware
266
+ *
267
+ * @v intel		Intel device
268
+ * @ret rc		Return status code
269
+ */
270
+static int intel_reset ( struct intel_nic *intel ) {
271
+	uint32_t pbs;
272
+	uint32_t ctrl;
273
+	uint32_t status;
274
+
275
+	/* Force RX and TX packet buffer allocation, to work around an
276
+	 * errata in ICH devices.
277
+	 */
278
+	pbs = readl ( intel->regs + INTEL_PBS );
279
+	if ( ( pbs == 0x14 ) || ( pbs == 0x18 ) ) {
280
+		DBGC ( intel, "INTEL %p WARNING: applying ICH PBS/PBA errata\n",
281
+		       intel );
282
+		writel ( 0x08, intel->regs + INTEL_PBA );
283
+		writel ( 0x10, intel->regs + INTEL_PBS );
284
+	}
285
+
286
+	/* Always reset MAC.  Required to reset the TX and RX rings. */
287
+	ctrl = readl ( intel->regs + INTEL_CTRL );
288
+	writel ( ( ctrl | INTEL_CTRL_RST ), intel->regs + INTEL_CTRL );
289
+	mdelay ( INTEL_RESET_DELAY_MS );
290
+
291
+	/* Set a sensible default configuration */
292
+	ctrl |= ( INTEL_CTRL_SLU | INTEL_CTRL_ASDE );
293
+	ctrl &= ~( INTEL_CTRL_LRST | INTEL_CTRL_FRCSPD | INTEL_CTRL_FRCDPLX );
294
+	writel ( ctrl, intel->regs + INTEL_CTRL );
295
+	mdelay ( INTEL_RESET_DELAY_MS );
296
+
297
+	/* If link is already up, do not attempt to reset the PHY.  On
298
+	 * some models (notably ICH), performing a PHY reset seems to
299
+	 * drop the link speed to 10Mbps.
300
+	 */
301
+	status = readl ( intel->regs + INTEL_STATUS );
302
+	if ( status & INTEL_STATUS_LU ) {
303
+		DBGC ( intel, "INTEL %p MAC reset (ctrl %08x)\n",
304
+		       intel, ctrl );
305
+		return 0;
306
+	}
307
+
308
+	/* Reset PHY and MAC simultaneously */
309
+	writel ( ( ctrl | INTEL_CTRL_RST | INTEL_CTRL_PHY_RST ),
310
+		 intel->regs + INTEL_CTRL );
311
+	mdelay ( INTEL_RESET_DELAY_MS );
312
+
313
+	/* PHY reset is not self-clearing on all models */
314
+	writel ( ctrl, intel->regs + INTEL_CTRL );
315
+	mdelay ( INTEL_RESET_DELAY_MS );
316
+
317
+	DBGC ( intel, "INTEL %p MAC+PHY reset (ctrl %08x)\n", intel, ctrl );
318
+	return 0;
319
+}
320
+
321
+/******************************************************************************
322
+ *
323
+ * Link state
324
+ *
325
+ ******************************************************************************
326
+ */
327
+
328
+/**
329
+ * Check link state
330
+ *
331
+ * @v netdev		Network device
332
+ */
333
+static void intel_check_link ( struct net_device *netdev ) {
334
+	struct intel_nic *intel = netdev->priv;
335
+	uint32_t status;
336
+
337
+	/* Read link status */
338
+	status = readl ( intel->regs + INTEL_STATUS );
339
+	DBGC ( intel, "INTEL %p link status is %08x\n", intel, status );
340
+
341
+	/* Update network device */
342
+	if ( status & INTEL_STATUS_LU ) {
343
+		netdev_link_up ( netdev );
344
+	} else {
345
+		netdev_link_down ( netdev );
346
+	}
347
+}
348
+
349
+/******************************************************************************
350
+ *
351
+ * Network device interface
352
+ *
353
+ ******************************************************************************
354
+ */
355
+
356
+/**
357
+ * Create descriptor ring
358
+ *
359
+ * @v intel		Intel device
360
+ * @v ring		Descriptor ring
361
+ * @ret rc		Return status code
362
+ */
363
+static int intel_create_ring ( struct intel_nic *intel,
364
+			       struct intel_ring *ring ) {
365
+	physaddr_t address;
366
+
367
+	/* Allocate descriptor ring.  Align ring on its own size to
368
+	 * prevent any possible page-crossing errors due to hardware
369
+	 * errata.
370
+	 */
371
+	ring->desc = malloc_dma ( ring->len, ring->len );
372
+	if ( ! ring->desc )
373
+		return -ENOMEM;
374
+
375
+	/* Initialise descriptor ring */
376
+	memset ( ring->desc, 0, ring->len );
377
+
378
+	/* Program ring address */
379
+	address = virt_to_bus ( ring->desc );
380
+	writel ( ( address & 0xffffffffUL ),
381
+		 ( intel->regs + ring->reg + INTEL_xDBAL ) );
382
+	if ( sizeof ( physaddr_t ) > sizeof ( uint32_t ) ) {
383
+		writel ( ( ( ( uint64_t ) address ) >> 32 ),
384
+			 ( intel->regs + ring->reg + INTEL_xDBAH ) );
385
+	} else {
386
+		writel ( 0, intel->regs + ring->reg + INTEL_xDBAH );
387
+	}
388
+
389
+	/* Program ring length */
390
+	writel ( ring->len, ( intel->regs + ring->reg + INTEL_xDLEN ) );
391
+
392
+	/* Reset head and tail pointers */
393
+	writel ( 0, ( intel->regs + ring->reg + INTEL_xDH ) );
394
+	writel ( 0, ( intel->regs + ring->reg + INTEL_xDT ) );
395
+
396
+	DBGC ( intel, "INTEL %p ring %05x is at [%08llx,%08llx)\n",
397
+	       intel, ring->reg, ( ( unsigned long long ) address ),
398
+	       ( ( unsigned long long ) address + ring->len ) );
399
+
400
+	return 0;
401
+}
402
+
403
+/**
404
+ * Destroy descriptor ring
405
+ *
406
+ * @v intel		Intel device
407
+ * @v ring		Descriptor ring
408
+ */
409
+static void intel_destroy_ring ( struct intel_nic *intel,
410
+				 struct intel_ring *ring ) {
411
+
412
+	/* Clear ring length */
413
+	writel ( 0, ( intel->regs + ring->reg + INTEL_xDLEN ) );
414
+
415
+	/* Clear ring address */
416
+	writel ( 0, ( intel->regs + ring->reg + INTEL_xDBAL ) );
417
+	writel ( 0, ( intel->regs + ring->reg + INTEL_xDBAH ) );
418
+
419
+	/* Free descriptor ring */
420
+	free_dma ( ring->desc, ring->len );
421
+	ring->desc = NULL;
422
+	ring->prod = 0;
423
+	ring->cons = 0;
424
+}
425
+
426
+/**
427
+ * Refill receive descriptor ring
428
+ *
429
+ * @v intel		Intel device
430
+ */
431
+static void intel_refill_rx ( struct intel_nic *intel ) {
432
+	struct intel_descriptor *rx;
433
+	struct io_buffer *iobuf;
434
+	unsigned int rx_idx;
435
+	unsigned int rx_tail;
436
+	physaddr_t address;
437
+
438
+	while ( ( intel->rx.prod - intel->rx.cons ) < INTEL_RX_FILL ) {
439
+
440
+		/* Allocate I/O buffer */
441
+		iobuf = alloc_iob ( INTEL_RX_MAX_LEN );
442
+		if ( ! iobuf ) {
443
+			/* Wait for next refill */
444
+			return;
445
+		}
446
+
447
+		/* Get next receive descriptor */
448
+		rx_idx = ( intel->rx.prod++ % INTEL_NUM_RX_DESC );
449
+		rx_tail = ( intel->rx.prod % INTEL_NUM_RX_DESC );
450
+		rx = &intel->rx.desc[rx_idx];
451
+
452
+		/* Populate receive descriptor */
453
+		address = virt_to_bus ( iobuf->data );
454
+		rx->address = cpu_to_le64 ( address );
455
+		rx->length = 0;
456
+		rx->status = 0;
457
+		rx->errors = 0;
458
+		wmb();
459
+
460
+		/* Record I/O buffer */
461
+		assert ( intel->rx_iobuf[rx_idx] == NULL );
462
+		intel->rx_iobuf[rx_idx] = iobuf;
463
+
464
+		/* Push descriptor to card */
465
+		writel ( rx_tail, intel->regs + INTEL_RDT );
466
+
467
+		DBGC2 ( intel, "INTEL %p RX %d is [%llx,%llx)\n", intel, rx_idx,
468
+			( ( unsigned long long ) address ),
469
+			( ( unsigned long long ) address + INTEL_RX_MAX_LEN ) );
470
+	}
471
+}
472
+
473
+/**
474
+ * Open network device
475
+ *
476
+ * @v netdev		Network device
477
+ * @ret rc		Return status code
478
+ */
479
+static int intel_open ( struct net_device *netdev ) {
480
+	struct intel_nic *intel = netdev->priv;
481
+	union intel_receive_address mac;
482
+	uint32_t tctl;
483
+	uint32_t rctl;
484
+	int rc;
485
+
486
+	/* Create transmit descriptor ring */
487
+	if ( ( rc = intel_create_ring ( intel, &intel->tx ) ) != 0 )
488
+		goto err_create_tx;
489
+
490
+	/* Create receive descriptor ring */
491
+	if ( ( rc = intel_create_ring ( intel, &intel->rx ) ) != 0 )
492
+		goto err_create_rx;
493
+
494
+	/* Fill receive ring */
495
+	intel_refill_rx ( intel );
496
+
497
+	/* Program MAC address */
498
+	memset ( &mac, 0, sizeof ( mac ) );
499
+	memcpy ( mac.raw, netdev->ll_addr, sizeof ( mac.raw ) );
500
+	writel ( le32_to_cpu ( mac.reg.low ), intel->regs + INTEL_RAL0 );
501
+	writel ( ( le32_to_cpu ( mac.reg.high ) | INTEL_RAH0_AV ),
502
+		 intel->regs + INTEL_RAH0 );
503
+
504
+	/* Enable transmitter  */
505
+	tctl = readl ( intel->regs + INTEL_TCTL );
506
+	tctl &= ~( INTEL_TCTL_CT_MASK | INTEL_TCTL_COLD_MASK );
507
+	tctl |= ( INTEL_TCTL_EN | INTEL_TCTL_PSP | INTEL_TCTL_CT_DEFAULT |
508
+		  INTEL_TCTL_COLD_DEFAULT );
509
+	writel ( tctl, intel->regs + INTEL_TCTL );
510
+
511
+	/* Enable receiver */
512
+	rctl = readl ( intel->regs + INTEL_RCTL );
513
+	rctl &= ~( INTEL_RCTL_BSIZE_BSEX_MASK );
514
+	rctl |= ( INTEL_RCTL_EN | INTEL_RCTL_UPE | INTEL_RCTL_MPE |
515
+		  INTEL_RCTL_BAM | INTEL_RCTL_BSIZE_2048 | INTEL_RCTL_SECRC );
516
+	writel ( rctl, intel->regs + INTEL_RCTL );
517
+
518
+	/* Update link state */
519
+	intel_check_link ( netdev );
520
+
521
+	return 0;
522
+
523
+	intel_destroy_ring ( intel, &intel->rx );
524
+ err_create_rx:
525
+	intel_destroy_ring ( intel, &intel->tx );
526
+ err_create_tx:
527
+	return rc;
528
+}
529
+
530
+/**
531
+ * Close network device
532
+ *
533
+ * @v netdev		Network device
534
+ */
535
+static void intel_close ( struct net_device *netdev ) {
536
+	struct intel_nic *intel = netdev->priv;
537
+	unsigned int i;
538
+
539
+	/* Disable receiver */
540
+	writel ( 0, intel->regs + INTEL_RCTL );
541
+
542
+	/* Disable transmitter  */
543
+	writel ( 0, intel->regs + INTEL_TCTL );
544
+
545
+	/* Destroy receive descriptor ring */
546
+	intel_destroy_ring ( intel, &intel->rx );
547
+
548
+	/* Discard any unused receive buffers */
549
+	for ( i = 0 ; i < INTEL_NUM_RX_DESC ; i++ ) {
550
+		if ( intel->rx_iobuf[i] )
551
+			free_iob ( intel->rx_iobuf[i] );
552
+		intel->rx_iobuf[i] = NULL;
553
+	}
554
+
555
+	/* Destroy transmit descriptor ring */
556
+	intel_destroy_ring ( intel, &intel->tx );
557
+
558
+	/* Reset the NIC, to flush the transmit and receive FIFOs */
559
+	intel_reset ( intel );
560
+}
561
+
562
+/**
563
+ * Transmit packet
564
+ *
565
+ * @v netdev		Network device
566
+ * @v iobuf		I/O buffer
567
+ * @ret rc		Return status code
568
+ */
569
+static int intel_transmit ( struct net_device *netdev,
570
+			       struct io_buffer *iobuf ) {
571
+	struct intel_nic *intel = netdev->priv;
572
+	struct intel_descriptor *tx;
573
+	unsigned int tx_idx;
574
+	unsigned int tx_tail;
575
+	physaddr_t address;
576
+
577
+	/* Get next transmit descriptor */
578
+	if ( ( intel->tx.prod - intel->tx.cons ) >= INTEL_NUM_TX_DESC ) {
579
+		DBGC ( intel, "INTEL %p out of transmit descriptors\n", intel );
580
+		return -ENOBUFS;
581
+	}
582
+	tx_idx = ( intel->tx.prod++ % INTEL_NUM_TX_DESC );
583
+	tx_tail = ( intel->tx.prod % INTEL_NUM_TX_DESC );
584
+	tx = &intel->tx.desc[tx_idx];
585
+
586
+	/* Populate transmit descriptor */
587
+	address = virt_to_bus ( iobuf->data );
588
+	tx->address = cpu_to_le64 ( address );
589
+	tx->length = cpu_to_le16 ( iob_len ( iobuf ) );
590
+	tx->command = ( INTEL_DESC_CMD_RS | INTEL_DESC_CMD_IFCS |
591
+			INTEL_DESC_CMD_EOP );
592
+	tx->status = 0;
593
+	wmb();
594
+
595
+	/* Notify card that there are packets ready to transmit */
596
+	writel ( tx_tail, intel->regs + INTEL_TDT );
597
+
598
+	DBGC2 ( intel, "INTEL %p TX %d is [%llx,%llx)\n", intel, tx_idx,
599
+		( ( unsigned long long ) address ),
600
+		( ( unsigned long long ) address + iob_len ( iobuf ) ) );
601
+
602
+	return 0;
603
+}
604
+
605
+/**
606
+ * Poll for completed packets
607
+ *
608
+ * @v netdev		Network device
609
+ */
610
+static void intel_poll_tx ( struct net_device *netdev ) {
611
+	struct intel_nic *intel = netdev->priv;
612
+	struct intel_descriptor *tx;
613
+	unsigned int tx_idx;
614
+
615
+	/* Check for completed packets */
616
+	while ( intel->tx.cons != intel->tx.prod ) {
617
+
618
+		/* Get next transmit descriptor */
619
+		tx_idx = ( intel->tx.cons % INTEL_NUM_TX_DESC );
620
+		tx = &intel->tx.desc[tx_idx];
621
+
622
+		/* Stop if descriptor is still in use */
623
+		if ( ! ( tx->status & INTEL_DESC_STATUS_DD ) )
624
+			return;
625
+
626
+		DBGC2 ( intel, "INTEL %p TX %d complete\n", intel, tx_idx );
627
+
628
+		/* Complete TX descriptor */
629
+		netdev_tx_complete_next ( netdev );
630
+		intel->tx.cons++;
631
+	}
632
+}
633
+
634
+/**
635
+ * Poll for received packets
636
+ *
637
+ * @v netdev		Network device
638
+ */
639
+static void intel_poll_rx ( struct net_device *netdev ) {
640
+	struct intel_nic *intel = netdev->priv;
641
+	struct intel_descriptor *rx;
642
+	struct io_buffer *iobuf;
643
+	unsigned int rx_idx;
644
+	size_t len;
645
+
646
+	/* Check for received packets */
647
+	while ( intel->rx.cons != intel->rx.prod ) {
648
+
649
+		/* Get next receive descriptor */
650
+		rx_idx = ( intel->rx.cons % INTEL_NUM_RX_DESC );
651
+		rx = &intel->rx.desc[rx_idx];
652
+
653
+		/* Stop if descriptor is still in use */
654
+		if ( ! ( rx->status & INTEL_DESC_STATUS_DD ) )
655
+			return;
656
+
657
+		/* Populate I/O buffer */
658
+		iobuf = intel->rx_iobuf[rx_idx];
659
+		intel->rx_iobuf[rx_idx] = NULL;
660
+		len = le16_to_cpu ( rx->length );
661
+		iob_put ( iobuf, len );
662
+
663
+		/* Hand off to network stack */
664
+		if ( rx->errors ) {
665
+			DBGC ( intel, "INTEL %p RX %d error (length %zd, "
666
+			       "errors %02x)\n",
667
+			       intel, rx_idx, len, rx->errors );
668
+			netdev_rx_err ( netdev, iobuf, -EIO );
669
+		} else {
670
+			DBGC2 ( intel, "INTEL %p RX %d complete (length %zd)\n",
671
+				intel, rx_idx, len );
672
+			netdev_rx ( netdev, iobuf );
673
+		}
674
+		intel->rx.cons++;
675
+	}
676
+}
677
+
678
+/**
679
+ * Poll for completed and received packets
680
+ *
681
+ * @v netdev		Network device
682
+ */
683
+static void intel_poll ( struct net_device *netdev ) {
684
+	struct intel_nic *intel = netdev->priv;
685
+	uint32_t icr;
686
+
687
+	/* Check for and acknowledge interrupts */
688
+	icr = readl ( intel->regs + INTEL_ICR );
689
+	if ( ! icr )
690
+		return;
691
+
692
+	/* Poll for TX completions, if applicable */
693
+	if ( icr & INTEL_IRQ_TXDW )
694
+		intel_poll_tx ( netdev );
695
+
696
+	/* Poll for RX completionsm, if applicable */
697
+	if ( icr & INTEL_IRQ_RXT0 )
698
+		intel_poll_rx ( netdev );
699
+
700
+	/* Check link state, if applicable */
701
+	if ( icr & INTEL_IRQ_LSC )
702
+		intel_check_link ( netdev );
703
+
704
+	/* Refill RX ring */
705
+	intel_refill_rx ( intel );
706
+}
707
+
708
+/**
709
+ * Enable or disable interrupts
710
+ *
711
+ * @v netdev		Network device
712
+ * @v enable		Interrupts should be enabled
713
+ */
714
+static void intel_irq ( struct net_device *netdev, int enable ) {
715
+	struct intel_nic *intel = netdev->priv;
716
+	uint32_t mask;
717
+
718
+	mask = ( INTEL_IRQ_TXDW | INTEL_IRQ_LSC | INTEL_IRQ_RXT0 );
719
+	if ( enable ) {
720
+		writel ( mask, intel->regs + INTEL_IMS );
721
+	} else {
722
+		writel ( mask, intel->regs + INTEL_IMC );
723
+	}
724
+}
725
+
726
+/** Intel network device operations */
727
+static struct net_device_operations intel_operations = {
728
+	.open		= intel_open,
729
+	.close		= intel_close,
730
+	.transmit	= intel_transmit,
731
+	.poll		= intel_poll,
732
+	.irq		= intel_irq,
733
+};
734
+
735
+/******************************************************************************
736
+ *
737
+ * PCI interface
738
+ *
739
+ ******************************************************************************
740
+ */
741
+
742
+/**
743
+ * Probe PCI device
744
+ *
745
+ * @v pci		PCI device
746
+ * @ret rc		Return status code
747
+ */
748
+static int intel_probe ( struct pci_device *pci ) {
749
+	struct net_device *netdev;
750
+	struct intel_nic *intel;
751
+	int rc;
752
+
753
+	/* Allocate and initialise net device */
754
+	netdev = alloc_etherdev ( sizeof ( *intel ) );
755
+	if ( ! netdev ) {
756
+		rc = -ENOMEM;
757
+		goto err_alloc;
758
+	}
759
+	netdev_init ( netdev, &intel_operations );
760
+	intel = netdev->priv;
761
+	pci_set_drvdata ( pci, netdev );
762
+	netdev->dev = &pci->dev;
763
+	memset ( intel, 0, sizeof ( *intel ) );
764
+	intel->port = PCI_FUNC ( pci->busdevfn );
765
+	intel_init_ring ( &intel->tx, INTEL_NUM_TX_DESC, INTEL_TD );
766
+	intel_init_ring ( &intel->rx, INTEL_NUM_RX_DESC, INTEL_RD );
767
+
768
+	/* Fix up PCI device */
769
+	adjust_pci_device ( pci );
770
+
771
+	/* Map registers */
772
+	intel->regs = ioremap ( pci->membase, INTEL_BAR_SIZE );
773
+
774
+	/* Reset the NIC */
775
+	if ( ( rc = intel_reset ( intel ) ) != 0 )
776
+		goto err_reset;
777
+
778
+	/* Fetch MAC address */
779
+	if ( ( rc = intel_fetch_mac ( intel, netdev->hw_addr ) ) != 0 )
780
+		goto err_fetch_mac;
781
+
782
+	/* Register network device */
783
+	if ( ( rc = register_netdev ( netdev ) ) != 0 )
784
+		goto err_register_netdev;
785
+
786
+	/* Set initial link state */
787
+	intel_check_link ( netdev );
788
+
789
+	return 0;
790
+
791
+	unregister_netdev ( netdev );
792
+ err_register_netdev:
793
+ err_fetch_mac:
794
+	intel_reset ( intel );
795
+ err_reset:
796
+	netdev_nullify ( netdev );
797
+	netdev_put ( netdev );
798
+ err_alloc:
799
+	return rc;
800
+}
801
+
802
+/**
803
+ * Remove PCI device
804
+ *
805
+ * @v pci		PCI device
806
+ */
807
+static void intel_remove ( struct pci_device *pci ) {
808
+	struct net_device *netdev = pci_get_drvdata ( pci );
809
+	struct intel_nic *intel = netdev->priv;
810
+
811
+	/* Unregister network device */
812
+	unregister_netdev ( netdev );
813
+
814
+	/* Reset the NIC */
815
+	intel_reset ( intel );
816
+
817
+	/* Free network device */
818
+	netdev_nullify ( netdev );
819
+	netdev_put ( netdev );
820
+}
821
+
822
+/** Intel PCI device IDs */
823
+static struct pci_device_id intel_nics[] = {
824
+	PCI_ROM ( 0x8086, 0x0438, "dh8900cc", "DH8900CC", 0 ),
825
+	PCI_ROM ( 0x8086, 0x043a, "dh8900cc-f", "DH8900CC Fiber", 0 ),
826
+	PCI_ROM ( 0x8086, 0x043c, "dh8900cc-b", "DH8900CC Backplane", 0 ),
827
+	PCI_ROM ( 0x8086, 0x0440, "dh8900cc-s", "DH8900CC SFP", 0 ),
828
+	PCI_ROM ( 0x8086, 0x1000, "82542-f", "82542 (Fiber)", 0 ),
829
+	PCI_ROM ( 0x8086, 0x1001, "82543gc-f", "82543GC (Fiber)", 0 ),
830
+	PCI_ROM ( 0x8086, 0x1004, "82543gc", "82543GC (Copper)", 0 ),
831
+	PCI_ROM ( 0x8086, 0x1008, "82544ei", "82544EI (Copper)", 0 ),
832
+	PCI_ROM ( 0x8086, 0x1009, "82544ei-f", "82544EI (Fiber)", 0 ),
833
+	PCI_ROM ( 0x8086, 0x100c, "82544gc", "82544GC (Copper)", 0 ),
834
+	PCI_ROM ( 0x8086, 0x100d, "82544gc-l", "82544GC (LOM)", 0 ),
835
+	PCI_ROM ( 0x8086, 0x100e, "82540em", "82540EM", 0 ),
836
+	PCI_ROM ( 0x8086, 0x100f, "82545em", "82545EM (Copper)", 0 ),
837
+	PCI_ROM ( 0x8086, 0x1010, "82546eb", "82546EB (Copper)", 0 ),
838
+	PCI_ROM ( 0x8086, 0x1011, "82545em-f", "82545EM (Fiber)", 0 ),
839
+	PCI_ROM ( 0x8086, 0x1012, "82546eb-f", "82546EB (Fiber)", 0 ),
840
+	PCI_ROM ( 0x8086, 0x1013, "82541ei", "82541EI", 0 ),
841
+	PCI_ROM ( 0x8086, 0x1014, "82541er", "82541ER", 0 ),
842
+	PCI_ROM ( 0x8086, 0x1015, "82540em-l", "82540EM (LOM)", 0 ),
843
+	PCI_ROM ( 0x8086, 0x1016, "82540ep-m", "82540EP (Mobile)", 0 ),
844
+	PCI_ROM ( 0x8086, 0x1017, "82540ep", "82540EP", 0 ),
845
+	PCI_ROM ( 0x8086, 0x1018, "82541ei", "82541EI", 0 ),
846
+	PCI_ROM ( 0x8086, 0x1019, "82547ei", "82547EI", 0 ),
847
+	PCI_ROM ( 0x8086, 0x101a, "82547ei-m", "82547EI (Mobile)", 0 ),
848
+	PCI_ROM ( 0x8086, 0x101d, "82546eb", "82546EB", 0 ),
849
+	PCI_ROM ( 0x8086, 0x101e, "82540ep-m", "82540EP (Mobile)", 0 ),
850
+	PCI_ROM ( 0x8086, 0x1026, "82545gm", "82545GM", 0 ),
851
+	PCI_ROM ( 0x8086, 0x1027, "82545gm-1", "82545GM", 0 ),
852
+	PCI_ROM ( 0x8086, 0x1028, "82545gm-2", "82545GM", 0 ),
853
+	PCI_ROM ( 0x8086, 0x1049, "82566mm", "82566MM", 0 ),
854
+	PCI_ROM ( 0x8086, 0x104a, "82566dm", "82566DM", 0 ),
855
+	PCI_ROM ( 0x8086, 0x104b, "82566dc", "82566DC", 0 ),
856
+	PCI_ROM ( 0x8086, 0x104c, "82562v", "82562V 10/100", 0 ),
857
+	PCI_ROM ( 0x8086, 0x104d, "82566mc", "82566MC", 0 ),
858
+	PCI_ROM ( 0x8086, 0x105e, "82571eb", "82571EB", 0 ),
859
+	PCI_ROM ( 0x8086, 0x105f, "82571eb-1", "82571EB", 0 ),
860
+	PCI_ROM ( 0x8086, 0x1060, "82571eb-2", "82571EB", 0 ),
861
+	PCI_ROM ( 0x8086, 0x1075, "82547gi", "82547GI", 0 ),
862
+	PCI_ROM ( 0x8086, 0x1076, "82541gi", "82541GI", 0 ),
863
+	PCI_ROM ( 0x8086, 0x1077, "82541gi-1", "82541GI", 0 ),
864
+	PCI_ROM ( 0x8086, 0x1078, "82541er", "82541ER", 0 ),
865
+	PCI_ROM ( 0x8086, 0x1079, "82546gb", "82546GB", 0 ),
866
+	PCI_ROM ( 0x8086, 0x107a, "82546gb-1", "82546GB", 0 ),
867
+	PCI_ROM ( 0x8086, 0x107b, "82546gb-2", "82546GB", 0 ),
868
+	PCI_ROM ( 0x8086, 0x107c, "82541pi", "82541PI", 0 ),
869
+	PCI_ROM ( 0x8086, 0x107d, "82572ei", "82572EI (Copper)", 0 ),
870
+	PCI_ROM ( 0x8086, 0x107e, "82572ei-f", "82572EI (Fiber)", 0 ),
871
+	PCI_ROM ( 0x8086, 0x107f, "82572ei", "82572EI", 0 ),
872
+	PCI_ROM ( 0x8086, 0x108a, "82546gb-3", "82546GB", 0 ),
873
+	PCI_ROM ( 0x8086, 0x108b, "82573v", "82573V (Copper)", 0 ),
874
+	PCI_ROM ( 0x8086, 0x108c, "82573e", "82573E (Copper)", 0 ),
875
+	PCI_ROM ( 0x8086, 0x1096, "80003es2lan", "80003ES2LAN (Copper)", 0 ),
876
+	PCI_ROM ( 0x8086, 0x1098, "80003es2lan-s", "80003ES2LAN (Serdes)", 0 ),
877
+	PCI_ROM ( 0x8086, 0x1099, "82546gb-4", "82546GB (Copper)", 0 ),
878
+	PCI_ROM ( 0x8086, 0x109a, "82573l", "82573L", 0 ),
879
+	PCI_ROM ( 0x8086, 0x10a4, "82571eb", "82571EB", 0 ),
880
+	PCI_ROM ( 0x8086, 0x10a5, "82571eb", "82571EB (Fiber)", 0 ),
881
+	PCI_ROM ( 0x8086, 0x10a7, "82575eb", "82575EB", 0 ),
882
+	PCI_ROM ( 0x8086, 0x10a9, "82575eb", "82575EB Backplane", 0 ),
883
+	PCI_ROM ( 0x8086, 0x10b5, "82546gb", "82546GB (Copper)", 0 ),
884
+	PCI_ROM ( 0x8086, 0x10b9, "82572ei", "82572EI (Copper)", 0 ),
885
+	PCI_ROM ( 0x8086, 0x10ba, "80003es2lan", "80003ES2LAN (Copper)", 0 ),
886
+	PCI_ROM ( 0x8086, 0x10bb, "80003es2lan", "80003ES2LAN (Serdes)", 0 ),
887
+	PCI_ROM ( 0x8086, 0x10bc, "82571eb", "82571EB (Copper)", 0 ),
888
+	PCI_ROM ( 0x8086, 0x10bd, "82566dm-2", "82566DM-2", 0 ),
889
+	PCI_ROM ( 0x8086, 0x10bf, "82567lf", "82567LF", 0 ),
890
+	PCI_ROM ( 0x8086, 0x10c0, "82562v-2", "82562V-2 10/100", 0 ),
891
+	PCI_ROM ( 0x8086, 0x10c2, "82562g-2", "82562G-2 10/100", 0 ),
892
+	PCI_ROM ( 0x8086, 0x10c3, "82562gt-2", "82562GT-2 10/100", 0 ),
893
+	PCI_ROM ( 0x8086, 0x10c4, "82562gt", "82562GT 10/100", 0 ),
894
+	PCI_ROM ( 0x8086, 0x10c5, "82562g", "82562G 10/100", 0 ),
895
+	PCI_ROM ( 0x8086, 0x10c9, "82576", "82576", 0 ),
896
+	PCI_ROM ( 0x8086, 0x10cb, "82567v", "82567V", 0 ),
897
+	PCI_ROM ( 0x8086, 0x10cc, "82567lm-2", "82567LM-2", 0 ),
898
+	PCI_ROM ( 0x8086, 0x10cd, "82567lf-2", "82567LF-2", 0 ),
899
+	PCI_ROM ( 0x8086, 0x10ce, "82567v-2", "82567V-2", 0 ),
900
+	PCI_ROM ( 0x8086, 0x10d3, "82574l", "82574L", 0 ),
901
+	PCI_ROM ( 0x8086, 0x10d5, "82571pt", "82571PT PT Quad", 0 ),
902
+	PCI_ROM ( 0x8086, 0x10d6, "82575gb", "82575GB", 0 ),
903
+	PCI_ROM ( 0x8086, 0x10d9, "82571eb-d", "82571EB Dual Mezzanine", 0 ),
904
+	PCI_ROM ( 0x8086, 0x10da, "82571eb-q", "82571EB Quad Mezzanine", 0 ),
905
+	PCI_ROM ( 0x8086, 0x10de, "82567lm-3", "82567LM-3", 0 ),
906
+	PCI_ROM ( 0x8086, 0x10df, "82567lf-3", "82567LF-3", 0 ),
907
+	PCI_ROM ( 0x8086, 0x10e5, "82567lm-4", "82567LM-4", 0 ),
908
+	PCI_ROM ( 0x8086, 0x10e6, "82576", "82576", 0 ),
909
+	PCI_ROM ( 0x8086, 0x10e7, "82576-2", "82576", 0 ),
910
+	PCI_ROM ( 0x8086, 0x10e8, "82576-3", "82576", 0 ),
911
+	PCI_ROM ( 0x8086, 0x10ea, "82577lm", "82577LM", 0 ),
912
+	PCI_ROM ( 0x8086, 0x10eb, "82577lc", "82577LC", 0 ),
913
+	PCI_ROM ( 0x8086, 0x10ef, "82578dm", "82578DM", 0 ),
914
+	PCI_ROM ( 0x8086, 0x10f0, "82578dc", "82578DC", 0 ),
915
+	PCI_ROM ( 0x8086, 0x10f5, "82567lm", "82567LM", 0 ),
916
+	PCI_ROM ( 0x8086, 0x10f6, "82574l", "82574L", 0 ),
917
+	PCI_ROM ( 0x8086, 0x1501, "82567v-3", "82567V-3", 0 ),
918
+	PCI_ROM ( 0x8086, 0x1502, "82579lm", "82579LM", 0 ),
919
+	PCI_ROM ( 0x8086, 0x1503, "82579v", "82579V", 0 ),
920
+	PCI_ROM ( 0x8086, 0x150a, "82576ns", "82576NS", 0 ),
921
+	PCI_ROM ( 0x8086, 0x150c, "82583v", "82583V", 0 ),
922
+	PCI_ROM ( 0x8086, 0x150d, "82576-4", "82576 Backplane", 0 ),
923
+	PCI_ROM ( 0x8086, 0x150e, "82580", "82580", 0 ),
924
+	PCI_ROM ( 0x8086, 0x150f, "82580-f", "82580 Fiber", 0 ),
925
+	PCI_ROM ( 0x8086, 0x1510, "82580-b", "82580 Backplane", 0 ),
926
+	PCI_ROM ( 0x8086, 0x1511, "82580-s", "82580 SFP", 0 ),
927
+	PCI_ROM ( 0x8086, 0x1516, "82580-2", "82580", 0 ),
928
+	PCI_ROM ( 0x8086, 0x1518, "82576ns", "82576NS SerDes", 0 ),
929
+	PCI_ROM ( 0x8086, 0x1521, "i350", "I350", 0 ),
930
+	PCI_ROM ( 0x8086, 0x1522, "i350-f", "I350 Fiber", 0 ),
931
+	PCI_ROM ( 0x8086, 0x1523, "i350-b", "I350 Backplane", 0 ),
932
+	PCI_ROM ( 0x8086, 0x1524, "i350-2", "I350", 0 ),
933
+	PCI_ROM ( 0x8086, 0x1525, "82567v-4", "82567V-4", 0 ),
934
+	PCI_ROM ( 0x8086, 0x1526, "82576-5", "82576", 0 ),
935
+	PCI_ROM ( 0x8086, 0x1527, "82580-f2", "82580 Fiber", 0 ),
936
+	PCI_ROM ( 0x8086, 0x294c, "82566dc-2", "82566DC-2", 0 ),
937
+	PCI_ROM ( 0x8086, 0x2e6e, "cemedia", "CE Media Processor", 0 ),
938
+};
939
+
940
+/** Intel PCI driver */
941
+struct pci_driver intel_driver __pci_driver = {
942
+	.ids = intel_nics,
943
+	.id_count = ( sizeof ( intel_nics ) / sizeof ( intel_nics[0] ) ),
944
+	.probe = intel_probe,
945
+	.remove = intel_remove,
946
+};

+ 252
- 0
src/drivers/net/intel.h Прегледај датотеку

@@ -0,0 +1,252 @@
1
+#ifndef _INTEL_H
2
+#define _INTEL_H
3
+
4
+/** @file
5
+ *
6
+ * Intel 10/100/1000 network card driver
7
+ *
8
+ */
9
+
10
+FILE_LICENCE ( GPL2_OR_LATER );
11
+
12
+#include <stdint.h>
13
+#include <ipxe/if_ether.h>
14
+#include <ipxe/nvs.h>
15
+
16
+/** Intel BAR size */
17
+#define INTEL_BAR_SIZE ( 128 * 1024 )
18
+
19
+/** A packet descriptor */
20
+struct intel_descriptor {
21
+	/** Buffer address */
22
+	uint64_t address;
23
+	/** Length */
24
+	uint16_t length;
25
+	/** Reserved */
26
+	uint8_t reserved_a;
27
+	/** Command */
28
+	uint8_t command;
29
+	/** Status */
30
+	uint8_t status;
31
+	/** Errors */
32
+	uint8_t errors;
33
+	/** Reserved */
34
+	uint16_t reserved_b;
35
+} __attribute__ (( packed ));
36
+
37
+/** Packet descriptor command bits */
38
+enum intel_descriptor_command {
39
+	/** Report status */
40
+	INTEL_DESC_CMD_RS = 0x08,
41
+	/** Insert frame checksum (CRC) */
42
+	INTEL_DESC_CMD_IFCS = 0x02,
43
+	/** End of packet */
44
+	INTEL_DESC_CMD_EOP = 0x01,
45
+};
46
+
47
+/** Packet descriptor status bits */
48
+enum intel_descriptor_status {
49
+	/** Descriptor done */
50
+	INTEL_DESC_STATUS_DD = 0x01,
51
+};
52
+
53
+/** Device Control Register */
54
+#define INTEL_CTRL 0x00000UL
55
+#define INTEL_CTRL_LRST		0x00000008UL	/**< Link reset */
56
+#define INTEL_CTRL_ASDE		0x00000020UL	/**< Auto-speed detection */
57
+#define INTEL_CTRL_SLU		0x00000040UL	/**< Set link up */
58
+#define INTEL_CTRL_FRCSPD	0x00000800UL	/**< Force speed */
59
+#define INTEL_CTRL_FRCDPLX	0x00001000UL	/**< Force duplex */
60
+#define INTEL_CTRL_RST		0x04000000UL	/**< Device reset */
61
+#define INTEL_CTRL_PHY_RST	0x80000000UL	/**< PHY reset */
62
+
63
+/** Time to delay for device reset, in milliseconds */
64
+#define INTEL_RESET_DELAY_MS 20
65
+
66
+/** Device Status Register */
67
+#define INTEL_STATUS 0x00008UL
68
+#define INTEL_STATUS_LU		0x00000002UL	/**< Link up */
69
+
70
+/** EEPROM Read Register */
71
+#define INTEL_EERD 0x00014UL
72
+#define INTEL_EERD_START	0x00000001UL	/**< Start read */
73
+#define INTEL_EERD_DONE_SMALL	0x00000010UL	/**< Read done (small EERD) */
74
+#define INTEL_EERD_DONE_LARGE	0x00000002UL	/**< Read done (large EERD) */
75
+#define INTEL_EERD_ADDR_SHIFT_SMALL 8		/**< Address shift (small) */
76
+#define INTEL_EERD_ADDR_SHIFT_LARGE 2		/**< Address shift (large) */
77
+#define INTEL_EERD_DATA(value)	( (value) >> 16 ) /**< Read data */
78
+
79
+/** Maximum time to wait for EEPROM read, in milliseconds */
80
+#define INTEL_EEPROM_MAX_WAIT_MS 100
81
+
82
+/** EEPROM word length */
83
+#define INTEL_EEPROM_WORD_LEN_LOG2 1
84
+
85
+/** Minimum EEPROM size, in words */
86
+#define INTEL_EEPROM_MIN_SIZE_WORDS 64
87
+
88
+/** Offset of MAC address within EEPROM */
89
+#define INTEL_EEPROM_MAC 0x00
90
+
91
+/** Interrupt Cause Read Register */
92
+#define INTEL_ICR 0x000c0UL
93
+#define INTEL_IRQ_TXDW		0x00000001UL	/**< Transmit descriptor done */
94
+#define INTEL_IRQ_LSC		0x00000004UL	/**< Link status change */
95
+#define INTEL_IRQ_RXT0		0x00000080UL	/**< Receive timer */
96
+
97
+/** Interrupt Mask Set/Read Register */
98
+#define INTEL_IMS 0x000d0UL
99
+
100
+/** Interrupt Mask Clear Register */
101
+#define INTEL_IMC 0x000d8UL
102
+
103
+/** Receive Control Register */
104
+#define INTEL_RCTL 0x00100UL
105
+#define INTEL_RCTL_EN		0x00000002UL	/**< Receive enable */
106
+#define INTEL_RCTL_UPE		0x00000008UL	/**< Unicast promiscuous mode */
107
+#define INTEL_RCTL_MPE		0x00000010UL	/**< Multicast promiscuous */
108
+#define INTEL_RCTL_BAM		0x00008000UL	/**< Broadcast accept mode */
109
+#define INTEL_RCTL_BSIZE_BSEX(bsex,bsize) \
110
+	( ( (bsize) << 16 ) | ( (bsex) << 25 ) ) /**< Buffer size */
111
+#define INTEL_RCTL_BSIZE_2048	INTEL_RCTL_BSIZE_BSEX ( 0, 0 )
112
+#define INTEL_RCTL_BSIZE_BSEX_MASK INTEL_RCTL_BSIZE_BSEX ( 1, 3 )
113
+#define INTEL_RCTL_SECRC	0x04000000UL	/**< Strip CRC */
114
+
115
+/** Transmit Control Register */
116
+#define INTEL_TCTL 0x00400UL
117
+#define INTEL_TCTL_EN		0x00000002UL	/**< Transmit enable */
118
+#define INTEL_TCTL_PSP		0x00000008UL	/**< Pad short packets */
119
+#define INTEL_TCTL_CT(x)	( (x) << 4 )	/**< Collision threshold */
120
+#define INTEL_TCTL_CT_DEFAULT	INTEL_TCTL_CT ( 0x0f )
121
+#define INTEL_TCTL_CT_MASK	INTEL_TCTL_CT ( 0xff )
122
+#define INTEL_TCTL_COLD(x)	( (x) << 12 )	/**< Collision distance */
123
+#define INTEL_TCTL_COLD_DEFAULT	INTEL_TCTL_COLD ( 0x040 )
124
+#define INTEL_TCTL_COLD_MASK	INTEL_TCTL_COLD ( 0x3ff )
125
+
126
+/** Packet Buffer Allocation */
127
+#define INTEL_PBA 0x01000UL
128
+
129
+/** Packet Buffer Size */
130
+#define INTEL_PBS 0x01008UL
131
+
132
+/** Receive Descriptor register block */
133
+#define INTEL_RD 0x02800UL
134
+
135
+/** Number of receive descriptors
136
+ *
137
+ * Minimum value is 8, since the descriptor ring length must be a
138
+ * multiple of 128.
139
+ */
140
+#define INTEL_NUM_RX_DESC 8
141
+
142
+/** Receive descriptor ring fill level */
143
+#define INTEL_RX_FILL 4
144
+
145
+/** Receive buffer length */
146
+#define INTEL_RX_MAX_LEN 2048
147
+
148
+/** Transmit Descriptor register block */
149
+#define INTEL_TD 0x03800UL
150
+
151
+/** Number of transmit descriptors
152
+ *
153
+ * Descriptor ring length must be a multiple of 16.  ICH8/9/10
154
+ * requires a minimum of 16 TX descriptors.
155
+ */
156
+#define INTEL_NUM_TX_DESC 16
157
+
158
+/** Receive/Transmit Descriptor Base Address Low (offset) */
159
+#define INTEL_xDBAL 0x00
160
+
161
+/** Receive/Transmit Descriptor Base Address High (offset) */
162
+#define INTEL_xDBAH 0x04
163
+
164
+/** Receive/Transmit Descriptor Length (offset) */
165
+#define INTEL_xDLEN 0x08
166
+
167
+/** Receive/Transmit Descriptor Head (offset) */
168
+#define INTEL_xDH 0x10
169
+
170
+/** Receive/Transmit Descriptor Tail (offset) */
171
+#define INTEL_xDT 0x18
172
+
173
+/** Receive Descriptor Head */
174
+#define INTEL_RDH ( INTEL_RD + INTEL_xDH )
175
+
176
+/** Receive Descriptor Tail */
177
+#define INTEL_RDT ( INTEL_RD + INTEL_xDT )
178
+
179
+/** Transmit Descriptor Head */
180
+#define INTEL_TDH ( INTEL_TD + INTEL_xDH )
181
+
182
+/** Transmit Descriptor Tail */
183
+#define INTEL_TDT ( INTEL_TD + INTEL_xDT )
184
+
185
+/** Receive Address Low */
186
+#define INTEL_RAL0 0x05400UL
187
+
188
+/** Receive Address High */
189
+#define INTEL_RAH0 0x05404UL
190
+#define INTEL_RAH0_AV		0x80000000UL	/**< Address valid */
191
+
192
+/** Receive address */
193
+union intel_receive_address {
194
+	struct {
195
+		uint32_t low;
196
+		uint32_t high;
197
+	} __attribute__ (( packed )) reg;
198
+	uint8_t raw[ETH_ALEN];
199
+};
200
+
201
+/** An Intel descriptor ring */
202
+struct intel_ring {
203
+	/** Descriptors */
204
+	struct intel_descriptor *desc;
205
+	/** Producer index */
206
+	unsigned int prod;
207
+	/** Consumer index */
208
+	unsigned int cons;
209
+
210
+	/** Register block */
211
+	unsigned int reg;
212
+	/** Length (in bytes) */
213
+	size_t len;
214
+};
215
+
216
+/**
217
+ * Initialise descriptor ring
218
+ *
219
+ * @v ring		Descriptor ring
220
+ * @v count		Number of descriptors
221
+ * @v reg		Descriptor register block
222
+ */
223
+static inline __attribute__ (( always_inline)) void
224
+intel_init_ring ( struct intel_ring *ring, unsigned int count,
225
+		  unsigned int reg ) {
226
+	ring->len = ( count * sizeof ( ring->desc[0] ) );
227
+	ring->reg = reg;
228
+}
229
+
230
+/** An Intel network card */
231
+struct intel_nic {
232
+	/** Registers */
233
+	void *regs;
234
+	/** Port number (for multi-port devices) */
235
+	unsigned int port;
236
+
237
+	/** EEPROM */
238
+	struct nvs_device eeprom;
239
+	/** EEPROM done flag */
240
+	uint32_t eerd_done;
241
+	/** EEPROM address shift */
242
+	unsigned int eerd_addr_shift;
243
+
244
+	/** Transmit descriptor ring */
245
+	struct intel_ring tx;
246
+	/** Receive descriptor ring */
247
+	struct intel_ring rx;
248
+	/** Receive I/O buffers */
249
+	struct io_buffer *rx_iobuf[INTEL_NUM_RX_DESC];
250
+};
251
+
252
+#endif /* _INTEL_H */

+ 1
- 0
src/include/ipxe/errfile.h Прегледај датотеку

@@ -144,6 +144,7 @@ FILE_LICENCE ( GPL2_OR_LATER );
144 144
 #define ERRFILE_mii		     ( ERRFILE_DRIVER | 0x00620000 )
145 145
 #define ERRFILE_realtek		     ( ERRFILE_DRIVER | 0x00630000 )
146 146
 #define ERRFILE_skeleton	     ( ERRFILE_DRIVER | 0x00640000 )
147
+#define ERRFILE_intel		     ( ERRFILE_DRIVER | 0x00650000 )
147 148
 
148 149
 #define ERRFILE_scsi		     ( ERRFILE_DRIVER | 0x00700000 )
149 150
 #define ERRFILE_arbel		     ( ERRFILE_DRIVER | 0x00710000 )

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