[smsc95xx] Enable LEDs

The LED pins are configured by default as GPIO inputs.  While it is
conceivable that a board might actually use these pins as GPIOs, no
such board is known to exist.

The Linux smsc95xx driver configures these pins unconditionally as LED
outputs.  Assume that it is safe to do likewise.

Signed-off-by: Michael Brown <mcb30@ipxe.org>

src/drivers/net/smsc95xx.c

@@ -687,6 +687,7 @@ static int smsc95xx_dump_statistics ( struct smsc95xx_device *smsc95xx ) {
  */
 static int smsc95xx_reset ( struct smsc95xx_device *smsc95xx ) {
 	uint32_t hw_cfg;
+	uint32_t led_gpio_cfg;
 	int rc;
 
 	/* Reset device */
@@ -706,6 +707,17 @@ static int smsc95xx_reset ( struct smsc95xx_device *smsc95xx ) {
 		return -ETIMEDOUT;
 	}
 
+	/* Configure LEDs */
+	led_gpio_cfg = ( SMSC95XX_LED_GPIO_CFG_GPCTL2_NSPD_LED |
+			 SMSC95XX_LED_GPIO_CFG_GPCTL1_NLNKA_LED |
+			 SMSC95XX_LED_GPIO_CFG_GPCTL0_NFDX_LED );
+	if ( ( rc = smsc95xx_writel ( smsc95xx, SMSC95XX_LED_GPIO_CFG,
+				      led_gpio_cfg ) ) != 0 ) {
+		DBGC ( smsc95xx, "SMSC95XX %p could not configure LEDs: %s\n",
+		       smsc95xx, strerror ( rc ) );
+		/* Ignore error and continue */
+	}
+
 	return 0;
 }
 

src/drivers/net/smsc95xx.h

@@ -43,6 +43,18 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
 #define SMSC95XX_HW_CFG_BIR		0x00001000UL	/**< Bulk IN use NAK */
 #define SMSC95XX_HW_CFG_LRST		0x00000008UL	/**< Soft lite reset */
 
+/** LED GPIO configuration register */
+#define SMSC95XX_LED_GPIO_CFG 0x024
+#define SMSC95XX_LED_GPIO_CFG_GPCTL2(x)	( (x) << 24 )	/**< GPIO 2 control */
+#define SMSC95XX_LED_GPIO_CFG_GPCTL2_NSPD_LED \
+	SMSC95XX_LED_GPIO_CFG_GPCTL2 ( 1 )		/**< Link speed LED */
+#define SMSC95XX_LED_GPIO_CFG_GPCTL1(x)	( (x) << 20 )	/**< GPIO 1 control */
+#define SMSC95XX_LED_GPIO_CFG_GPCTL1_NLNKA_LED \
+	SMSC95XX_LED_GPIO_CFG_GPCTL1 ( 1 )		/**< Activity LED */
+#define SMSC95XX_LED_GPIO_CFG_GPCTL0(x)	( (x) << 16 )	/**< GPIO 0 control */
+#define SMSC95XX_LED_GPIO_CFG_GPCTL0_NFDX_LED \
+	SMSC95XX_LED_GPIO_CFG_GPCTL0 ( 1 )		/**< Full-duplex LED */
+
 /** EEPROM command register */
 #define SMSC95XX_E2P_CMD 0x030
 #define SMSC95XX_E2P_CMD_EPC_BSY	0x80000000UL	/**< EPC busy */