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[intel] Profile common virtual machine operations

Operations which are negligible on physical hardware (such as issuing
a posted write to the transmit ring tail register) may involve
substantial amounts of processing within the hypervisor if running in
a virtual machine.

Signed-off-by: Michael Brown <mcb30@ipxe.org>
tags/v1.20.1
Michael Brown 11 years ago
parent
commit
8a3dcefc0c
1 changed files with 19 additions and 0 deletions
  1. 19
    0
      src/drivers/net/intel.c

+ 19
- 0
src/drivers/net/intel.c View File

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 #include <ipxe/iobuf.h>
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 #include <ipxe/iobuf.h>
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 #include <ipxe/malloc.h>
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 #include <ipxe/malloc.h>
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 #include <ipxe/pci.h>
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 #include <ipxe/pci.h>
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+#include <ipxe/profile.h>
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 #include "intel.h"
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 #include "intel.h"
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35
 
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 /** @file
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 /** @file
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  *
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  *
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  */
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  */
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+/** VM transmit profiler */
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+static struct profiler intel_vm_tx_profiler __profiler =
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+	{ .name = "intel.vm_tx" };
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+
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+/** VM receive refill profiler */
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+static struct profiler intel_vm_refill_profiler __profiler =
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+	{ .name = "intel.vm_refill" };
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+
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+/** VM poll profiler */
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+static struct profiler intel_vm_poll_profiler __profiler =
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+	{ .name = "intel.vm_poll" };
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+
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 /******************************************************************************
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 /******************************************************************************
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  *
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  *
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  * EEPROM interface
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  * EEPROM interface
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 		intel->rx_iobuf[rx_idx] = iobuf;
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 		intel->rx_iobuf[rx_idx] = iobuf;
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 		/* Push descriptor to card */
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 		/* Push descriptor to card */
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+		profile_start ( &intel_vm_refill_profiler );
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 		writel ( rx_tail, intel->regs + intel->rx.reg + INTEL_xDT );
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 		writel ( rx_tail, intel->regs + intel->rx.reg + INTEL_xDT );
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+		profile_stop ( &intel_vm_refill_profiler );
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 		DBGC2 ( intel, "INTEL %p RX %d is [%llx,%llx)\n", intel, rx_idx,
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 		DBGC2 ( intel, "INTEL %p RX %d is [%llx,%llx)\n", intel, rx_idx,
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 			( ( unsigned long long ) address ),
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 			( ( unsigned long long ) address ),
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 	wmb();
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 	wmb();
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 	/* Notify card that there are packets ready to transmit */
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 	/* Notify card that there are packets ready to transmit */
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+	profile_start ( &intel_vm_tx_profiler );
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 	writel ( tx_tail, intel->regs + intel->tx.reg + INTEL_xDT );
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 	writel ( tx_tail, intel->regs + intel->tx.reg + INTEL_xDT );
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+	profile_stop ( &intel_vm_tx_profiler );
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 	DBGC2 ( intel, "INTEL %p TX %d is [%llx,%llx)\n", intel, tx_idx,
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 	DBGC2 ( intel, "INTEL %p TX %d is [%llx,%llx)\n", intel, tx_idx,
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 		( ( unsigned long long ) address ),
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 		( ( unsigned long long ) address ),
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 	uint32_t icr;
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 	uint32_t icr;
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 	/* Check for and acknowledge interrupts */
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 	/* Check for and acknowledge interrupts */
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+	profile_start ( &intel_vm_poll_profiler );
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 	icr = readl ( intel->regs + INTEL_ICR );
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 	icr = readl ( intel->regs + INTEL_ICR );
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+	profile_stop ( &intel_vm_poll_profiler );
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 	if ( ! icr )
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 	if ( ! icr )
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 		return;
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 		return;
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728
 

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