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@@ -11,10 +11,15 @@
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11
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11
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*
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12
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12
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*/
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13
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13
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14
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+#include "errno.h"
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15
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+#include "byteswap.h"
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14
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16
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#include "etherboot.h"
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15
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17
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#include "ipxe/io.h"
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16
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-#include "ipxe/virtio-ring.h"
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18
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+#include "ipxe/iomap.h"
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19
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+#include "ipxe/pci.h"
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20
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+#include "ipxe/reboot.h"
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17
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21
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#include "ipxe/virtio-pci.h"
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22
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+#include "ipxe/virtio-ring.h"
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18
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23
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19
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24
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int vp_find_vq(unsigned int ioaddr, int queue_index,
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20
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25
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struct vring_virtqueue *vq)
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@@ -30,19 +35,19 @@ int vp_find_vq(unsigned int ioaddr, int queue_index,
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30
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35
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31
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36
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num = inw(ioaddr + VIRTIO_PCI_QUEUE_NUM);
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32
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37
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if (!num) {
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33
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- printf("ERROR: queue size is 0\n");
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38
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+ DBG("VIRTIO-PCI ERROR: queue size is 0\n");
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34
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39
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return -1;
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35
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40
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}
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36
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41
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37
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42
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if (num > MAX_QUEUE_NUM) {
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38
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- printf("ERROR: queue size %d > %d\n", num, MAX_QUEUE_NUM);
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43
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+ DBG("VIRTIO-PCI ERROR: queue size %d > %d\n", num, MAX_QUEUE_NUM);
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39
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44
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return -1;
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40
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45
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}
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41
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46
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42
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47
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/* check if the queue is already active */
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43
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48
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44
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49
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if (inl(ioaddr + VIRTIO_PCI_QUEUE_PFN)) {
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45
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- printf("ERROR: queue already active\n");
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50
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+ DBG("VIRTIO-PCI ERROR: queue already active\n");
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46
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51
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return -1;
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47
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52
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}
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48
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53
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@@ -62,3 +67,343 @@ int vp_find_vq(unsigned int ioaddr, int queue_index,
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62
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67
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63
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68
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return num;
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64
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69
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}
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70
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+
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71
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+#define CFG_POS(vdev, field) \
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72
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+ (vdev->cfg_cap_pos + offsetof(struct virtio_pci_cfg_cap, field))
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73
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+
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74
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+static void prep_pci_cfg_cap(struct virtio_pci_modern_device *vdev,
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75
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+ struct virtio_pci_region *region,
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76
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+ size_t offset, u32 length)
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77
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+{
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78
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+ pci_write_config_byte(vdev->pci, CFG_POS(vdev, cap.bar), region->bar);
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79
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+ pci_write_config_dword(vdev->pci, CFG_POS(vdev, cap.length), length);
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80
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+ pci_write_config_dword(vdev->pci, CFG_POS(vdev, cap.offset),
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81
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+ (intptr_t)(region->base + offset));
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82
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+}
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83
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+
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84
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+void vpm_iowrite8(struct virtio_pci_modern_device *vdev,
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85
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+ struct virtio_pci_region *region, u8 data, size_t offset)
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86
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+{
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87
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+ switch (region->flags & VIRTIO_PCI_REGION_TYPE_MASK) {
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88
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+ case VIRTIO_PCI_REGION_MEMORY:
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89
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+ writeb(data, region->base + offset);
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90
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+ break;
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91
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+ case VIRTIO_PCI_REGION_PORT:
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92
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+ outb(data, region->base + offset);
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93
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+ break;
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94
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+ case VIRTIO_PCI_REGION_PCI_CONFIG:
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95
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+ prep_pci_cfg_cap(vdev, region, offset, 1);
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96
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+ pci_write_config_byte(vdev->pci, CFG_POS(vdev, pci_cfg_data), data);
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97
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+ break;
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98
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+ default:
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99
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+ assert(0);
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100
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+ break;
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101
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+ }
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102
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+}
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103
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+
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104
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+void vpm_iowrite16(struct virtio_pci_modern_device *vdev,
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105
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+ struct virtio_pci_region *region, u16 data, size_t offset)
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106
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+{
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107
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+ data = cpu_to_le16(data);
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108
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+ switch (region->flags & VIRTIO_PCI_REGION_TYPE_MASK) {
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109
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+ case VIRTIO_PCI_REGION_MEMORY:
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110
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+ writew(data, region->base + offset);
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111
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+ break;
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112
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+ case VIRTIO_PCI_REGION_PORT:
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113
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+ outw(data, region->base + offset);
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114
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+ break;
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115
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+ case VIRTIO_PCI_REGION_PCI_CONFIG:
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116
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+ prep_pci_cfg_cap(vdev, region, offset, 2);
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117
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+ pci_write_config_word(vdev->pci, CFG_POS(vdev, pci_cfg_data), data);
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118
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+ break;
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119
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+ default:
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|
120
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+ assert(0);
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121
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+ break;
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|
122
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+ }
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123
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+}
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|
124
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+
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|
125
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+void vpm_iowrite32(struct virtio_pci_modern_device *vdev,
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126
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+ struct virtio_pci_region *region, u32 data, size_t offset)
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127
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+{
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128
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+ data = cpu_to_le32(data);
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|
129
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+ switch (region->flags & VIRTIO_PCI_REGION_TYPE_MASK) {
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130
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+ case VIRTIO_PCI_REGION_MEMORY:
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131
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+ writel(data, region->base + offset);
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132
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+ break;
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133
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+ case VIRTIO_PCI_REGION_PORT:
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134
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+ outl(data, region->base + offset);
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|
135
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+ break;
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136
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+ case VIRTIO_PCI_REGION_PCI_CONFIG:
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137
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+ prep_pci_cfg_cap(vdev, region, offset, 4);
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138
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+ pci_write_config_dword(vdev->pci, CFG_POS(vdev, pci_cfg_data), data);
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139
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+ break;
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140
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+ default:
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141
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+ assert(0);
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|
142
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+ break;
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|
143
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+ }
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|
144
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+}
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|
145
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+
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|
146
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+u8 vpm_ioread8(struct virtio_pci_modern_device *vdev,
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|
147
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+ struct virtio_pci_region *region, size_t offset)
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|
148
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+{
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|
149
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+ uint8_t data;
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|
150
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+ switch (region->flags & VIRTIO_PCI_REGION_TYPE_MASK) {
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151
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+ case VIRTIO_PCI_REGION_MEMORY:
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|
152
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+ data = readb(region->base + offset);
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|
153
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+ break;
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|
154
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+ case VIRTIO_PCI_REGION_PORT:
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155
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+ data = inb(region->base + offset);
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|
156
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+ break;
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157
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+ case VIRTIO_PCI_REGION_PCI_CONFIG:
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158
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+ prep_pci_cfg_cap(vdev, region, offset, 1);
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|
159
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+ pci_read_config_byte(vdev->pci, CFG_POS(vdev, pci_cfg_data), &data);
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|
160
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+ break;
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|
161
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+ default:
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|
162
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+ assert(0);
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|
163
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+ data = 0;
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|
164
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+ break;
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|
165
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+ }
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|
166
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+ return data;
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|
167
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+}
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|
168
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+
|
|
169
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+u16 vpm_ioread16(struct virtio_pci_modern_device *vdev,
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170
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+ struct virtio_pci_region *region, size_t offset)
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171
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+{
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172
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+ uint16_t data;
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173
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+ switch (region->flags & VIRTIO_PCI_REGION_TYPE_MASK) {
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174
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+ case VIRTIO_PCI_REGION_MEMORY:
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175
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+ data = readw(region->base + offset);
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176
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+ break;
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177
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+ case VIRTIO_PCI_REGION_PORT:
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178
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+ data = inw(region->base + offset);
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179
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+ break;
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180
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+ case VIRTIO_PCI_REGION_PCI_CONFIG:
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181
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+ prep_pci_cfg_cap(vdev, region, offset, 2);
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182
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+ pci_read_config_word(vdev->pci, CFG_POS(vdev, pci_cfg_data), &data);
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183
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+ break;
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184
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+ default:
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185
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+ assert(0);
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186
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+ data = 0;
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|
187
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+ break;
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|
188
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+ }
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|
189
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+ return le16_to_cpu(data);
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|
190
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+}
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|
191
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+
|
|
192
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+u32 vpm_ioread32(struct virtio_pci_modern_device *vdev,
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193
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+ struct virtio_pci_region *region, size_t offset)
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|
194
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+{
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|
195
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+ uint32_t data;
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196
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+ switch (region->flags & VIRTIO_PCI_REGION_TYPE_MASK) {
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197
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+ case VIRTIO_PCI_REGION_MEMORY:
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|
198
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+ data = readw(region->base + offset);
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|
199
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+ break;
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|
200
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+ case VIRTIO_PCI_REGION_PORT:
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201
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+ data = inw(region->base + offset);
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202
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+ break;
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203
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+ case VIRTIO_PCI_REGION_PCI_CONFIG:
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204
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+ prep_pci_cfg_cap(vdev, region, offset, 4);
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205
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+ pci_read_config_dword(vdev->pci, CFG_POS(vdev, pci_cfg_data), &data);
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|
206
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+ break;
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|
207
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+ default:
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|
208
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+ assert(0);
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|
209
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+ data = 0;
|
|
210
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+ break;
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|
211
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+ }
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|
212
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+ return le32_to_cpu(data);
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|
213
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+}
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|
214
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+
|
|
215
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+int virtio_pci_find_capability(struct pci_device *pci, uint8_t cfg_type)
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216
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+{
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|
217
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+ int pos;
|
|
218
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+ uint8_t type, bar;
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|
219
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+
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|
220
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+ for (pos = pci_find_capability(pci, PCI_CAP_ID_VNDR);
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|
221
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+ pos > 0;
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222
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+ pos = pci_find_next_capability(pci, pos, PCI_CAP_ID_VNDR)) {
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|
223
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+
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|
224
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+ pci_read_config_byte(pci, pos + offsetof(struct virtio_pci_cap,
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|
225
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+ cfg_type), &type);
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226
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+ pci_read_config_byte(pci, pos + offsetof(struct virtio_pci_cap,
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|
227
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+ bar), &bar);
|
|
228
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+
|
|
229
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+ /* Ignore structures with reserved BAR values */
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|
230
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+ if (bar > 0x5) {
|
|
231
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+ continue;
|
|
232
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+ }
|
|
233
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+
|
|
234
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+ if (type == cfg_type) {
|
|
235
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+ return pos;
|
|
236
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+ }
|
|
237
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+ }
|
|
238
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+ return 0;
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239
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+}
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|
240
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+
|
|
241
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+int virtio_pci_map_capability(struct pci_device *pci, int cap, size_t minlen,
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242
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+ u32 align, u32 start, u32 size,
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243
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+ struct virtio_pci_region *region)
|
|
244
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+{
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|
245
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+ u8 bar;
|
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246
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+ u32 offset, length, base_raw;
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247
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+ unsigned long base;
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248
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+
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249
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+ pci_read_config_byte(pci, cap + offsetof(struct virtio_pci_cap, bar), &bar);
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250
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+ pci_read_config_dword(pci, cap + offsetof(struct virtio_pci_cap, offset),
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251
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+ &offset);
|
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252
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+ pci_read_config_dword(pci, cap + offsetof(struct virtio_pci_cap, length),
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253
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+ &length);
|
|
254
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+
|
|
255
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+ if (length <= start) {
|
|
256
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+ DBG("VIRTIO-PCI bad capability len %u (>%u expected)\n", length, start);
|
|
257
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+ return -EINVAL;
|
|
258
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+ }
|
|
259
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+ if (length - start < minlen) {
|
|
260
|
+ DBG("VIRTIO-PCI bad capability len %u (>=%zu expected)\n", length, minlen);
|
|
261
|
+ return -EINVAL;
|
|
262
|
+ }
|
|
263
|
+ length -= start;
|
|
264
|
+ if (start + offset < offset) {
|
|
265
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+ DBG("VIRTIO-PCI map wrap-around %u+%u\n", start, offset);
|
|
266
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+ return -EINVAL;
|
|
267
|
+ }
|
|
268
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+ offset += start;
|
|
269
|
+ if (offset & (align - 1)) {
|
|
270
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+ DBG("VIRTIO-PCI offset %u not aligned to %u\n", offset, align);
|
|
271
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+ return -EINVAL;
|
|
272
|
+ }
|
|
273
|
+ if (length > size) {
|
|
274
|
+ length = size;
|
|
275
|
+ }
|
|
276
|
+
|
|
277
|
+ if (minlen + offset < minlen ||
|
|
278
|
+ minlen + offset > pci_bar_size(pci, PCI_BASE_ADDRESS(bar))) {
|
|
279
|
+ DBG("VIRTIO-PCI map virtio %zu@%u out of range on bar %i length %lu\n",
|
|
280
|
+ minlen, offset,
|
|
281
|
+ bar, (unsigned long)pci_bar_size(pci, PCI_BASE_ADDRESS(bar)));
|
|
282
|
+ return -EINVAL;
|
|
283
|
+ }
|
|
284
|
+
|
|
285
|
+ region->base = NULL;
|
|
286
|
+ region->length = length;
|
|
287
|
+ region->bar = bar;
|
|
288
|
+
|
|
289
|
+ base = pci_bar_start(pci, PCI_BASE_ADDRESS(bar));
|
|
290
|
+ if (base) {
|
|
291
|
+ pci_read_config_dword(pci, PCI_BASE_ADDRESS(bar), &base_raw);
|
|
292
|
+
|
|
293
|
+ if (base_raw & PCI_BASE_ADDRESS_SPACE_IO) {
|
|
294
|
+ /* Region accessed using port I/O */
|
|
295
|
+ region->base = (void *)(base + offset);
|
|
296
|
+ region->flags = VIRTIO_PCI_REGION_PORT;
|
|
297
|
+ } else {
|
|
298
|
+ /* Region mapped into memory space */
|
|
299
|
+ region->base = ioremap(base + offset, length);
|
|
300
|
+ region->flags = VIRTIO_PCI_REGION_MEMORY;
|
|
301
|
+ }
|
|
302
|
+ }
|
|
303
|
+ if (!region->base) {
|
|
304
|
+ /* Region accessed via PCI config space window */
|
|
305
|
+ region->base = (void *)(intptr_t)offset;
|
|
306
|
+ region->flags = VIRTIO_PCI_REGION_PCI_CONFIG;
|
|
307
|
+ }
|
|
308
|
+ return 0;
|
|
309
|
+}
|
|
310
|
+
|
|
311
|
+void virtio_pci_unmap_capability(struct virtio_pci_region *region)
|
|
312
|
+{
|
|
313
|
+ unsigned region_type = region->flags & VIRTIO_PCI_REGION_TYPE_MASK;
|
|
314
|
+ if (region_type == VIRTIO_PCI_REGION_MEMORY) {
|
|
315
|
+ iounmap(region->base);
|
|
316
|
+ }
|
|
317
|
+}
|
|
318
|
+
|
|
319
|
+void vpm_notify(struct virtio_pci_modern_device *vdev,
|
|
320
|
+ struct vring_virtqueue *vq)
|
|
321
|
+{
|
|
322
|
+ vpm_iowrite16(vdev, &vq->notification, (u16)vq->queue_index, 0);
|
|
323
|
+}
|
|
324
|
+
|
|
325
|
+int vpm_find_vqs(struct virtio_pci_modern_device *vdev,
|
|
326
|
+ unsigned nvqs, struct vring_virtqueue *vqs)
|
|
327
|
+{
|
|
328
|
+ unsigned i;
|
|
329
|
+ struct vring_virtqueue *vq;
|
|
330
|
+ u16 size, off;
|
|
331
|
+ u32 notify_offset_multiplier;
|
|
332
|
+ int err;
|
|
333
|
+
|
|
334
|
+ if (nvqs > vpm_ioread16(vdev, &vdev->common, COMMON_OFFSET(num_queues))) {
|
|
335
|
+ return -ENOENT;
|
|
336
|
+ }
|
|
337
|
+
|
|
338
|
+ /* Read notify_off_multiplier from config space. */
|
|
339
|
+ pci_read_config_dword(vdev->pci,
|
|
340
|
+ vdev->notify_cap_pos + offsetof(struct virtio_pci_notify_cap,
|
|
341
|
+ notify_off_multiplier),
|
|
342
|
+ ¬ify_offset_multiplier);
|
|
343
|
+
|
|
344
|
+ for (i = 0; i < nvqs; i++) {
|
|
345
|
+ /* Select the queue we're interested in */
|
|
346
|
+ vpm_iowrite16(vdev, &vdev->common, (u16)i, COMMON_OFFSET(queue_select));
|
|
347
|
+
|
|
348
|
+ /* Check if queue is either not available or already active. */
|
|
349
|
+ size = vpm_ioread16(vdev, &vdev->common, COMMON_OFFSET(queue_size));
|
|
350
|
+ /* QEMU has a bug where queues don't revert to inactive on device
|
|
351
|
+ * reset. Skip checking the queue_enable field until it is fixed.
|
|
352
|
+ */
|
|
353
|
+ if (!size /*|| vpm_ioread16(vdev, &vdev->common.queue_enable)*/)
|
|
354
|
+ return -ENOENT;
|
|
355
|
+
|
|
356
|
+ if (size & (size - 1)) {
|
|
357
|
+ DBG("VIRTIO-PCI %p: bad queue size %u", vdev, size);
|
|
358
|
+ return -EINVAL;
|
|
359
|
+ }
|
|
360
|
+
|
|
361
|
+ vq = &vqs[i];
|
|
362
|
+ vq->queue_index = i;
|
|
363
|
+
|
|
364
|
+ /* get offset of notification word for this vq */
|
|
365
|
+ off = vpm_ioread16(vdev, &vdev->common, COMMON_OFFSET(queue_notify_off));
|
|
366
|
+ vq->vring.num = size;
|
|
367
|
+
|
|
368
|
+ vring_init(&vq->vring, size, (unsigned char *)vq->queue);
|
|
369
|
+
|
|
370
|
+ /* activate the queue */
|
|
371
|
+ vpm_iowrite16(vdev, &vdev->common, size, COMMON_OFFSET(queue_size));
|
|
372
|
+
|
|
373
|
+ vpm_iowrite64(vdev, &vdev->common, virt_to_phys(vq->vring.desc),
|
|
374
|
+ COMMON_OFFSET(queue_desc_lo),
|
|
375
|
+ COMMON_OFFSET(queue_desc_hi));
|
|
376
|
+ vpm_iowrite64(vdev, &vdev->common, virt_to_phys(vq->vring.avail),
|
|
377
|
+ COMMON_OFFSET(queue_avail_lo),
|
|
378
|
+ COMMON_OFFSET(queue_avail_hi));
|
|
379
|
+ vpm_iowrite64(vdev, &vdev->common, virt_to_phys(vq->vring.used),
|
|
380
|
+ COMMON_OFFSET(queue_used_lo),
|
|
381
|
+ COMMON_OFFSET(queue_used_hi));
|
|
382
|
+
|
|
383
|
+ err = virtio_pci_map_capability(vdev->pci,
|
|
384
|
+ vdev->notify_cap_pos, 2, 2,
|
|
385
|
+ off * notify_offset_multiplier, 2,
|
|
386
|
+ &vq->notification);
|
|
387
|
+ if (err) {
|
|
388
|
+ goto err_map_notify;
|
|
389
|
+ }
|
|
390
|
+ }
|
|
391
|
+
|
|
392
|
+ /* Select and activate all queues. Has to be done last: once we do
|
|
393
|
+ * this, there's no way to go back except reset.
|
|
394
|
+ */
|
|
395
|
+ for (i = 0; i < nvqs; i++) {
|
|
396
|
+ vq = &vqs[i];
|
|
397
|
+ vpm_iowrite16(vdev, &vdev->common, (u16)vq->queue_index,
|
|
398
|
+ COMMON_OFFSET(queue_select));
|
|
399
|
+ vpm_iowrite16(vdev, &vdev->common, 1, COMMON_OFFSET(queue_enable));
|
|
400
|
+ }
|
|
401
|
+ return 0;
|
|
402
|
+
|
|
403
|
+err_map_notify:
|
|
404
|
+ /* Undo the virtio_pci_map_capability calls. */
|
|
405
|
+ while (i-- > 0) {
|
|
406
|
+ virtio_pci_unmap_capability(&vqs[i].notification);
|
|
407
|
+ }
|
|
408
|
+ return err;
|
|
409
|
+}
|