[ath5k] Save proper cacheline size when fixing PCI configuration

Some BIOSes set the PCI cacheline size to zero for the card; the ath5k
driver fixes it to a reasonable in PCI config space, but failed to
correct the internal value it had already read. This resulted in
divide-by-zero errors when cacheline-aligning various data structures.

Fix by setting the internal cachelsz to a sane value at the same time
as we write that value to PCI config space.

Signed-off-by: Marty Connor <mdc@etherboot.org>

src/drivers/net/ath5k/ath5k.c

@@ -306,7 +306,8 @@ static int ath5k_probe(struct pci_device *pdev,
 		 * DMA to work so force a reasonable value here if it
 		 * comes up zero.
 		 */
-		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 16);
+		csz = 16;
+		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
 	}
 	/*
 	 * The default setting of latency timer yields poor results,