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+/*
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+ * Copyright (c) 2008 Stefan Hajnoczi <stefanha@gmail.com>
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+ * Copyright (c) 2008 Pantelis Koukousoulas <pktoss@gmail.com>
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of the
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+ * License, or any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful, but
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+ * WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+ * General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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+ *
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+ * This driver is a port of the b44 linux driver version 1.01
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+ *
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+ * Copyright (c) 2002 David S. Miller <davem@redhat.com>
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+ * Copyright (c) Pekka Pietikainen <pp@ee.oulu.fi>
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+ * Copyright (C) 2006 Broadcom Corporation.
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+ *
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+ * Some ssb bits copied from version 2.0 of the b44 driver
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+ * Copyright (c) Michael Buesch
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+ *
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+ * Copyright (c) a lot of people too. Please respect their work.
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+ */
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+
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+#include <errno.h>
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32
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+#include <assert.h>
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+#include <stdio.h>
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34
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+#include <unistd.h>
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35
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+#include <byteswap.h>
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+#include <gpxe/io.h>
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37
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+#include <mii.h>
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+#include <gpxe/iobuf.h>
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39
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+#include <gpxe/malloc.h>
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+#include <gpxe/pci.h>
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+#include <gpxe/netdevice.h>
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+#include <gpxe/ethernet.h>
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+#include <gpxe/if_ether.h>
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+#include <gpxe/memmap.h>
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45
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+#include "b44.h"
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+
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+
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+static inline int ring_next(int index)
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+{
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+ /* B44_RING_SIZE is a power of 2 :) */
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+ return (index + 1) & (B44_RING_SIZE - 1);
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+}
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+
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+
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+/* Memory-mapped I/O wrappers */
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+
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+static inline u32 br32(const struct b44_private *bp, u32 reg)
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+{
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+ return readl(bp->regs + reg);
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+}
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+
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+
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+static inline void bw32(const struct b44_private *bp, u32 reg, u32 val)
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+{
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+ writel(val, bp->regs + reg);
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+}
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+
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+
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+static inline void bflush(const struct b44_private *bp, u32 reg, u32 timeout)
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+{
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+ readl(bp->regs + reg);
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+ udelay(timeout);
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+}
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+
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+
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+#define VIRT_TO_B44(addr) ( virt_to_bus(addr) + SB_PCI_DMA )
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+
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+
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+/**
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+ * Return non-zero if the installed RAM is within
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+ * the limit given and zero if it is outside.
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+ * Hopefully will be removed soon.
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+ */
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+int phys_ram_within_limit(u64 limit)
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+{
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+ struct memory_map memmap;
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+ struct memory_region *highest = NULL;
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+ get_memmap(&memmap);
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+
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+ highest = &memmap.regions[memmap.count - 1];
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+
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+ return (highest->end < limit);
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+}
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+
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+
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+/**
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+ * Ring cells waiting to be processed are between 'tx_cur' and 'pending'
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+ * indexes in the ring.
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+ */
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+static u32 pending_tx_index(struct b44_private *bp)
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+{
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+ u32 pending = br32(bp, B44_DMATX_STAT);
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+ pending &= DMATX_STAT_CDMASK;
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+
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+ pending /= sizeof(struct dma_desc);
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+ return pending & (B44_RING_SIZE - 1);
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+}
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+
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+
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+/**
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+ * Ring cells waiting to be processed are between 'rx_cur' and 'pending'
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+ * indexes in the ring.
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+ */
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+static u32 pending_rx_index(struct b44_private *bp)
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+{
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+ u32 pending = br32(bp, B44_DMARX_STAT);
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+ pending &= DMARX_STAT_CDMASK;
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+
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+ pending /= sizeof(struct dma_desc);
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+ return pending & (B44_RING_SIZE - 1);
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+}
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+
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+
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+/**
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+ * Wait until the given bit is set/cleared.
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+ */
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+static int b44_wait_bit(struct b44_private *bp, unsigned long reg, u32 bit,
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+ unsigned long timeout, const int clear)
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+{
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+ unsigned long i;
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+
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+ for (i = 0; i < timeout; i++) {
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+ u32 val = br32(bp, reg);
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+
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+ if (clear && !(val & bit))
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+ break;
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+
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+ if (!clear && (val & bit))
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+ break;
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+
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+ udelay(10);
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+ }
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+ if (i == timeout) {
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+ return -ENODEV;
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+ }
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+ return 0;
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+}
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+
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+
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+/*
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+ * Sonics Silicon Backplane support. SSB is a mini-bus interconnecting
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+ * so-called IP Cores. One of those cores implements the Fast Ethernet
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+ * functionality and another one the PCI engine.
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+ *
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+ * You need to switch to the core you want to talk to before actually
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+ * sending commands.
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+ *
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+ * See: http://bcm-v4.sipsolutions.net/Backplane for (reverse-engineered)
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+ * specs.
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+ */
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+
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+static inline u32 ssb_get_core_rev(struct b44_private *bp)
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+{
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+ return (br32(bp, B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
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+}
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+
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+
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+static inline int ssb_is_core_up(struct b44_private *bp)
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+{
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+ return ((br32(bp, B44_SBTMSLOW) & (SSB_CORE_DOWN | SBTMSLOW_CLOCK))
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+ == SBTMSLOW_CLOCK);
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+}
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+
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+
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+static u32 ssb_pci_setup(struct b44_private *bp, u32 cores)
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+{
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+ u32 bar_orig, pci_rev, val;
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+
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+ pci_read_config_dword(bp->pci, SSB_BAR0_WIN, &bar_orig);
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+ pci_write_config_dword(bp->pci, SSB_BAR0_WIN,
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+ BCM4400_PCI_CORE_ADDR);
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+ pci_rev = ssb_get_core_rev(bp);
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+
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+ val = br32(bp, B44_SBINTVEC);
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+ val |= cores;
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+ bw32(bp, B44_SBINTVEC, val);
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+
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+ val = br32(bp, SSB_PCI_TRANS_2);
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+ val |= SSB_PCI_PREF | SSB_PCI_BURST;
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+ bw32(bp, SSB_PCI_TRANS_2, val);
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+
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+ pci_write_config_dword(bp->pci, SSB_BAR0_WIN, bar_orig);
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+
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+ return pci_rev;
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+}
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+
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+
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+static void ssb_core_disable(struct b44_private *bp)
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+{
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+ if (br32(bp, B44_SBTMSLOW) & SBTMSLOW_RESET)
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+ return;
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+
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+ bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
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+ b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0);
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+ b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1);
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+
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+ bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
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+ SSB_CORE_DOWN));
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+ bflush(bp, B44_SBTMSLOW, 1);
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+
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+ bw32(bp, B44_SBTMSLOW, SSB_CORE_DOWN);
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+ bflush(bp, B44_SBTMSLOW, 1);
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+}
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+
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+
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+static void ssb_core_reset(struct b44_private *bp)
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+{
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+ u32 val;
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+ const u32 mask = (SBTMSLOW_CLOCK | SBTMSLOW_FGC | SBTMSLOW_RESET);
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+
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+ ssb_core_disable(bp);
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+
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+ bw32(bp, B44_SBTMSLOW, mask);
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+ bflush(bp, B44_SBTMSLOW, 1);
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+
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+ /* Clear SERR if set, this is a hw bug workaround. */
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+ if (br32(bp, B44_SBTMSHIGH) & SBTMSHIGH_SERR)
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+ bw32(bp, B44_SBTMSHIGH, 0);
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+
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+ val = br32(bp, B44_SBIMSTATE);
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+ if (val & (SBIMSTATE_BAD)) {
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+ bw32(bp, B44_SBIMSTATE, val & ~SBIMSTATE_BAD);
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+ }
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+
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+ bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
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+ bflush(bp, B44_SBTMSLOW, 1);
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+
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+ bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK));
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+ bflush(bp, B44_SBTMSLOW, 1);
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+}
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+
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+
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+/*
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+ * Driver helper functions
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+ */
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+
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+/*
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+ * Chip reset provides power to the b44 MAC & PCI cores, which
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+ * is necessary for MAC register access. We only do a partial
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+ * reset in case of transmit/receive errors (ISTAT_ERRORS) to
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+ * avoid the chip being hung for an unnecessary long time in
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+ * this case.
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+ *
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+ * Called-by: b44_close, b44_halt, b44_inithw(b44_open), b44_probe
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+ */
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256
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+static void b44_chip_reset(struct b44_private *bp, int reset_kind)
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+{
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+ if (ssb_is_core_up(bp)) {
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+ bw32(bp, B44_RCV_LAZY, 0);
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+
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+ bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
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+
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263
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+ b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 200, 1);
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+
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265
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+ bw32(bp, B44_DMATX_CTRL, 0);
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+
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267
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+ bp->tx_dirty = bp->tx_cur = 0;
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+
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269
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+ if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK)
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+ b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
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+ 100, 0);
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+
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273
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+ bw32(bp, B44_DMARX_CTRL, 0);
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+
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+ bp->rx_cur = 0;
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276
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+ } else {
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277
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+ ssb_pci_setup(bp, SBINTVEC_ENET0);
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278
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+ }
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279
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+
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280
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+ ssb_core_reset(bp);
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281
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+
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282
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+ /* Don't enable PHY if we are only doing a partial reset. */
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283
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+ if (reset_kind == B44_CHIP_RESET_PARTIAL)
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284
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+ return;
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285
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+
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286
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+ /* Make PHY accessible. */
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287
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+ bw32(bp, B44_MDIO_CTRL,
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288
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+ (MDIO_CTRL_PREAMBLE | (0x0d & MDIO_CTRL_MAXF_MASK)));
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289
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+ bflush(bp, B44_MDIO_CTRL, 1);
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290
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+
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291
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+ /* Enable internal or external PHY */
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292
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+ if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
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293
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+ bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
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294
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+ bflush(bp, B44_ENET_CTRL, 1);
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295
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+ } else {
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296
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+ u32 val = br32(bp, B44_DEVCTRL);
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297
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+ if (val & DEVCTRL_EPR) {
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298
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+ bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
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299
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+ bflush(bp, B44_DEVCTRL, 100);
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300
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+ }
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301
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+ }
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302
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+}
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303
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+
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304
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+
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305
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+/**
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306
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+ * called by b44_poll in the error path
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307
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+ */
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308
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+static void b44_halt(struct b44_private *bp)
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309
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+{
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310
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+ /* disable ints */
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311
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+ bw32(bp, B44_IMASK, 0);
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312
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+ bflush(bp, B44_IMASK, 1);
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313
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+
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314
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+ DBG("b44: powering down PHY\n");
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315
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+ bw32(bp, B44_MAC_CTRL, MAC_CTRL_PHY_PDOWN);
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316
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+
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317
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+ /*
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318
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+ * Now reset the chip, but without enabling
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319
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+ * the MAC&PHY part of it.
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320
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+ * This has to be done _after_ we shut down the PHY
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321
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+ */
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322
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+ b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
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323
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+}
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324
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+
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325
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+
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326
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+
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327
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+/*
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328
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+ * Called at device open time to get the chip ready for
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329
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+ * packet processing.
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330
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+ *
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331
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+ * Called-by: b44_open
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332
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+ */
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333
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+static void b44_init_hw(struct b44_private *bp, int reset_kind)
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334
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+{
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335
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+ u32 val;
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336
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+#define CTRL_MASK (DMARX_CTRL_ENABLE | (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT))
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337
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+
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338
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+ b44_chip_reset(bp, B44_CHIP_RESET_FULL);
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339
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+ if (reset_kind == B44_FULL_RESET) {
|
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340
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+ b44_phy_reset(bp);
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341
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+ }
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342
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+
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343
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+ /* Enable CRC32, set proper LED modes and power on PHY */
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344
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+ bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
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345
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+ bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
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346
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+
|
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347
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+ /* This sets the MAC address too. */
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348
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+ b44_set_rx_mode(bp->netdev);
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|
349
|
+
|
|
350
|
+ /* MTU + eth header + possible VLAN tag + struct rx_header */
|
|
351
|
+ bw32(bp, B44_RXMAXLEN, B44_MAX_MTU + ETH_HLEN + 8 + RX_HEADER_LEN);
|
|
352
|
+ bw32(bp, B44_TXMAXLEN, B44_MAX_MTU + ETH_HLEN + 8 + RX_HEADER_LEN);
|
|
353
|
+
|
|
354
|
+ bw32(bp, B44_TX_HIWMARK, TX_HIWMARK_DEFLT);
|
|
355
|
+ if (reset_kind == B44_PARTIAL_RESET) {
|
|
356
|
+ bw32(bp, B44_DMARX_CTRL, CTRL_MASK);
|
|
357
|
+ } else {
|
|
358
|
+ bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
|
|
359
|
+ bw32(bp, B44_DMATX_ADDR, VIRT_TO_B44(bp->tx));
|
|
360
|
+
|
|
361
|
+ bw32(bp, B44_DMARX_CTRL, CTRL_MASK);
|
|
362
|
+ bw32(bp, B44_DMARX_ADDR, VIRT_TO_B44(bp->rx));
|
|
363
|
+ bw32(bp, B44_DMARX_PTR, B44_RX_RING_LEN_BYTES);
|
|
364
|
+
|
|
365
|
+ bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
|
|
366
|
+ }
|
|
367
|
+
|
|
368
|
+ val = br32(bp, B44_ENET_CTRL);
|
|
369
|
+ bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
|
|
370
|
+#undef CTRL_MASK
|
|
371
|
+}
|
|
372
|
+
|
|
373
|
+
|
|
374
|
+/*** Management of ring descriptors ***/
|
|
375
|
+
|
|
376
|
+
|
|
377
|
+static void b44_populate_rx_descriptor(struct b44_private *bp, u32 idx)
|
|
378
|
+{
|
|
379
|
+ struct rx_header *rh;
|
|
380
|
+ u32 ctrl, addr;
|
|
381
|
+
|
|
382
|
+ rh = bp->rx_iobuf[idx]->data;
|
|
383
|
+ rh->len = 0;
|
|
384
|
+ rh->flags = 0;
|
|
385
|
+ ctrl = DESC_CTRL_LEN & (RX_PKT_BUF_SZ - RX_PKT_OFFSET);
|
|
386
|
+ if (idx == B44_RING_LAST) {
|
|
387
|
+ ctrl |= DESC_CTRL_EOT;
|
|
388
|
+ }
|
|
389
|
+ addr = VIRT_TO_B44(bp->rx_iobuf[idx]->data);
|
|
390
|
+
|
|
391
|
+ bp->rx[idx].ctrl = cpu_to_le32(ctrl);
|
|
392
|
+ bp->rx[idx].addr = cpu_to_le32(addr);
|
|
393
|
+ bw32(bp, B44_DMARX_PTR, idx * sizeof(struct dma_desc));
|
|
394
|
+}
|
|
395
|
+
|
|
396
|
+
|
|
397
|
+/*
|
|
398
|
+ * Refill RX ring descriptors with buffers. This is needed
|
|
399
|
+ * because during rx we are passing ownership of descriptor
|
|
400
|
+ * buffers to the network stack.
|
|
401
|
+ */
|
|
402
|
+static void b44_rx_refill(struct b44_private *bp, u32 pending)
|
|
403
|
+{
|
|
404
|
+ u32 i;
|
|
405
|
+
|
|
406
|
+ // skip pending
|
|
407
|
+ for (i = pending + 1; i != bp->rx_cur; i = ring_next(i)) {
|
|
408
|
+ if (bp->rx_iobuf[i] != NULL)
|
|
409
|
+ continue;
|
|
410
|
+
|
|
411
|
+ bp->rx_iobuf[i] = alloc_iob(RX_PKT_BUF_SZ);
|
|
412
|
+ if (!bp->rx_iobuf[i]) {
|
|
413
|
+ DBG("Refill rx ring failed!!\n");
|
|
414
|
+ break;
|
|
415
|
+ }
|
|
416
|
+
|
|
417
|
+ b44_populate_rx_descriptor(bp, i);
|
|
418
|
+ }
|
|
419
|
+}
|
|
420
|
+
|
|
421
|
+
|
|
422
|
+static void b44_free_rx_ring(struct b44_private *bp)
|
|
423
|
+{
|
|
424
|
+ u32 i;
|
|
425
|
+
|
|
426
|
+ if (bp->rx) {
|
|
427
|
+ for (i = 0; i < B44_RING_SIZE; i++) {
|
|
428
|
+ free_iob(bp->rx_iobuf[i]);
|
|
429
|
+ bp->rx_iobuf[i] = NULL;
|
|
430
|
+ }
|
|
431
|
+ free_dma(bp->rx, B44_RX_RING_LEN_BYTES);
|
|
432
|
+ bp->rx = NULL;
|
|
433
|
+ }
|
|
434
|
+}
|
|
435
|
+
|
|
436
|
+
|
|
437
|
+static int b44_init_rx_ring(struct b44_private *bp)
|
|
438
|
+{
|
|
439
|
+ b44_free_rx_ring(bp);
|
|
440
|
+
|
|
441
|
+ bp->rx = malloc_dma(B44_RX_RING_LEN_BYTES, B44_DMA_ALIGNMENT);
|
|
442
|
+ if (!bp->rx)
|
|
443
|
+ return -ENOMEM;
|
|
444
|
+
|
|
445
|
+ memset(bp->rx_iobuf, 0, sizeof(bp->rx_iobuf));
|
|
446
|
+
|
|
447
|
+ bp->rx_iobuf[0] = alloc_iob(RX_PKT_BUF_SZ);
|
|
448
|
+ b44_populate_rx_descriptor(bp, 0);
|
|
449
|
+ b44_rx_refill(bp, 0);
|
|
450
|
+
|
|
451
|
+ DBG("Init RX rings: rx=0x%08lx\n", VIRT_TO_B44(bp->rx));
|
|
452
|
+ return 0;
|
|
453
|
+}
|
|
454
|
+
|
|
455
|
+
|
|
456
|
+static void b44_free_tx_ring(struct b44_private *bp)
|
|
457
|
+{
|
|
458
|
+ if (bp->tx) {
|
|
459
|
+ free_dma(bp->tx, B44_TX_RING_LEN_BYTES);
|
|
460
|
+ bp->tx = NULL;
|
|
461
|
+ }
|
|
462
|
+}
|
|
463
|
+
|
|
464
|
+
|
|
465
|
+static int b44_init_tx_ring(struct b44_private *bp)
|
|
466
|
+{
|
|
467
|
+ b44_free_tx_ring(bp);
|
|
468
|
+
|
|
469
|
+ bp->tx = malloc_dma(B44_TX_RING_LEN_BYTES, B44_DMA_ALIGNMENT);
|
|
470
|
+ if (!bp->tx)
|
|
471
|
+ return -ENOMEM;
|
|
472
|
+
|
|
473
|
+ memset(bp->tx, 0, B44_TX_RING_LEN_BYTES);
|
|
474
|
+ memset(bp->tx_iobuf, 0, sizeof(bp->tx_iobuf));
|
|
475
|
+
|
|
476
|
+ DBG("Init TX rings: tx=0x%08lx\n", VIRT_TO_B44(bp->tx));
|
|
477
|
+ return 0;
|
|
478
|
+}
|
|
479
|
+
|
|
480
|
+
|
|
481
|
+/*** Interaction with the PHY ***/
|
|
482
|
+
|
|
483
|
+
|
|
484
|
+static int b44_phy_read(struct b44_private *bp, int reg, u32 * val)
|
|
485
|
+{
|
|
486
|
+ int err;
|
|
487
|
+
|
|
488
|
+ u32 arg1 = (MDIO_OP_READ << MDIO_DATA_OP_SHIFT);
|
|
489
|
+ u32 arg2 = (bp->phy_addr << MDIO_DATA_PMD_SHIFT);
|
|
490
|
+ u32 arg3 = (reg << MDIO_DATA_RA_SHIFT);
|
|
491
|
+ u32 arg4 = (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT);
|
|
492
|
+ u32 argv = arg1 | arg2 | arg3 | arg4;
|
|
493
|
+
|
|
494
|
+ bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
|
|
495
|
+ bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START | argv));
|
|
496
|
+ err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
|
|
497
|
+ *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
|
|
498
|
+
|
|
499
|
+ return err;
|
|
500
|
+}
|
|
501
|
+
|
|
502
|
+
|
|
503
|
+static int b44_phy_write(struct b44_private *bp, int reg, u32 val)
|
|
504
|
+{
|
|
505
|
+ u32 arg1 = (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT);
|
|
506
|
+ u32 arg2 = (bp->phy_addr << MDIO_DATA_PMD_SHIFT);
|
|
507
|
+ u32 arg3 = (reg << MDIO_DATA_RA_SHIFT);
|
|
508
|
+ u32 arg4 = (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT);
|
|
509
|
+ u32 arg5 = (val & MDIO_DATA_DATA);
|
|
510
|
+ u32 argv = arg1 | arg2 | arg3 | arg4 | arg5;
|
|
511
|
+
|
|
512
|
+
|
|
513
|
+ bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
|
|
514
|
+ bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START | argv));
|
|
515
|
+ return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
|
|
516
|
+}
|
|
517
|
+
|
|
518
|
+
|
|
519
|
+static int b44_phy_reset(struct b44_private *bp)
|
|
520
|
+{
|
|
521
|
+ u32 val;
|
|
522
|
+ int err;
|
|
523
|
+
|
|
524
|
+ err = b44_phy_write(bp, MII_BMCR, BMCR_RESET);
|
|
525
|
+ if (err)
|
|
526
|
+ return err;
|
|
527
|
+
|
|
528
|
+ udelay(100);
|
|
529
|
+ err = b44_phy_read(bp, MII_BMCR, &val);
|
|
530
|
+ if (!err) {
|
|
531
|
+ if (val & BMCR_RESET) {
|
|
532
|
+ return -ENODEV;
|
|
533
|
+ }
|
|
534
|
+ }
|
|
535
|
+
|
|
536
|
+ return 0;
|
|
537
|
+}
|
|
538
|
+
|
|
539
|
+
|
|
540
|
+/*
|
|
541
|
+ * The BCM44xx CAM (Content Addressable Memory) stores the MAC
|
|
542
|
+ * and PHY address.
|
|
543
|
+ */
|
|
544
|
+static void b44_cam_write(struct b44_private *bp, unsigned char *data,
|
|
545
|
+ int index)
|
|
546
|
+{
|
|
547
|
+ u32 val;
|
|
548
|
+
|
|
549
|
+ val = ((u32) data[2]) << 24;
|
|
550
|
+ val |= ((u32) data[3]) << 16;
|
|
551
|
+ val |= ((u32) data[4]) << 8;
|
|
552
|
+ val |= ((u32) data[5]) << 0;
|
|
553
|
+ bw32(bp, B44_CAM_DATA_LO, val);
|
|
554
|
+
|
|
555
|
+
|
|
556
|
+ val = (CAM_DATA_HI_VALID |
|
|
557
|
+ (((u32) data[0]) << 8) | (((u32) data[1]) << 0));
|
|
558
|
+
|
|
559
|
+ bw32(bp, B44_CAM_DATA_HI, val);
|
|
560
|
+
|
|
561
|
+ val = CAM_CTRL_WRITE | (index << CAM_CTRL_INDEX_SHIFT);
|
|
562
|
+ bw32(bp, B44_CAM_CTRL, val);
|
|
563
|
+
|
|
564
|
+ b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
|
|
565
|
+}
|
|
566
|
+
|
|
567
|
+
|
|
568
|
+static void b44_set_mac_addr(struct b44_private *bp)
|
|
569
|
+{
|
|
570
|
+ u32 val;
|
|
571
|
+ bw32(bp, B44_CAM_CTRL, 0);
|
|
572
|
+ b44_cam_write(bp, bp->netdev->ll_addr, 0);
|
|
573
|
+ val = br32(bp, B44_CAM_CTRL);
|
|
574
|
+ bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
|
|
575
|
+}
|
|
576
|
+
|
|
577
|
+
|
|
578
|
+/* Read 128-bytes of EEPROM. */
|
|
579
|
+static void b44_read_eeprom(struct b44_private *bp, u8 * data)
|
|
580
|
+{
|
|
581
|
+ long i;
|
|
582
|
+ u16 *ptr = (u16 *) data;
|
|
583
|
+
|
|
584
|
+ for (i = 0; i < 128; i += 2)
|
|
585
|
+ ptr[i / 2] = cpu_to_le16(readw(bp->regs + 4096 + i));
|
|
586
|
+}
|
|
587
|
+
|
|
588
|
+
|
|
589
|
+static void b44_load_mac_and_phy_addr(struct b44_private *bp)
|
|
590
|
+{
|
|
591
|
+ u8 eeprom[128];
|
|
592
|
+
|
|
593
|
+ /* Load MAC address, note byteswapping */
|
|
594
|
+ b44_read_eeprom(bp, &eeprom[0]);
|
|
595
|
+ bp->netdev->ll_addr[0] = eeprom[79];
|
|
596
|
+ bp->netdev->ll_addr[1] = eeprom[78];
|
|
597
|
+ bp->netdev->ll_addr[2] = eeprom[81];
|
|
598
|
+ bp->netdev->ll_addr[3] = eeprom[80];
|
|
599
|
+ bp->netdev->ll_addr[4] = eeprom[83];
|
|
600
|
+ bp->netdev->ll_addr[5] = eeprom[82];
|
|
601
|
+
|
|
602
|
+ /* Load PHY address */
|
|
603
|
+ bp->phy_addr = eeprom[90] & 0x1f;
|
|
604
|
+}
|
|
605
|
+
|
|
606
|
+
|
|
607
|
+static void b44_set_rx_mode(struct net_device *netdev)
|
|
608
|
+{
|
|
609
|
+ struct b44_private *bp = netdev_priv(netdev);
|
|
610
|
+ unsigned char zero[6] = { 0, 0, 0, 0, 0, 0 };
|
|
611
|
+ u32 val;
|
|
612
|
+ int i;
|
|
613
|
+
|
|
614
|
+ val = br32(bp, B44_RXCONFIG);
|
|
615
|
+ val &= ~RXCONFIG_PROMISC;
|
|
616
|
+ val |= RXCONFIG_ALLMULTI;
|
|
617
|
+
|
|
618
|
+ b44_set_mac_addr(bp);
|
|
619
|
+
|
|
620
|
+ for (i = 1; i < 64; i++)
|
|
621
|
+ b44_cam_write(bp, zero, i);
|
|
622
|
+
|
|
623
|
+ bw32(bp, B44_RXCONFIG, val);
|
|
624
|
+ val = br32(bp, B44_CAM_CTRL);
|
|
625
|
+ bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
|
|
626
|
+}
|
|
627
|
+
|
|
628
|
+
|
|
629
|
+/*** Implementation of gPXE driver callbacks ***/
|
|
630
|
+
|
|
631
|
+/**
|
|
632
|
+ * Probe device
|
|
633
|
+ *
|
|
634
|
+ * @v pci PCI device
|
|
635
|
+ * @v id Matching entry in ID table
|
|
636
|
+ * @ret rc Return status code
|
|
637
|
+ */
|
|
638
|
+static int b44_probe(struct pci_device *pci, const struct pci_device_id *id)
|
|
639
|
+{
|
|
640
|
+ struct net_device *netdev;
|
|
641
|
+ struct b44_private *bp;
|
|
642
|
+ int rc;
|
|
643
|
+
|
|
644
|
+ /*
|
|
645
|
+ * Bail out if more than 1GB of physical RAM is installed.
|
|
646
|
+ * This limitation will be removed later when dma mapping
|
|
647
|
+ * is merged into mainline.
|
|
648
|
+ */
|
|
649
|
+ if (!phys_ram_within_limit(B44_30BIT_DMA_MASK)) {
|
|
650
|
+ DBG("Sorry, this version of the driver does not\n"
|
|
651
|
+ "support systems with more than 1GB of RAM.\n");
|
|
652
|
+ return -ENOMEM;
|
|
653
|
+ }
|
|
654
|
+
|
|
655
|
+ /* Set up netdev */
|
|
656
|
+ netdev = alloc_etherdev(sizeof(*bp));
|
|
657
|
+ if (!netdev)
|
|
658
|
+ return -ENOMEM;
|
|
659
|
+
|
|
660
|
+ netdev_init(netdev, &b44_operations);
|
|
661
|
+ pci_set_drvdata(pci, netdev);
|
|
662
|
+ netdev->dev = &pci->dev;
|
|
663
|
+
|
|
664
|
+ /* Set up private data */
|
|
665
|
+ bp = netdev_priv(netdev);
|
|
666
|
+ memset(bp, 0, sizeof(*bp));
|
|
667
|
+ bp->netdev = netdev;
|
|
668
|
+ bp->pci = pci;
|
|
669
|
+
|
|
670
|
+ /* Map device registers */
|
|
671
|
+ bp->regs = ioremap(pci->membase, B44_REGS_SIZE);
|
|
672
|
+ if (!bp->regs) {
|
|
673
|
+ netdev_put(netdev);
|
|
674
|
+ return -ENOMEM;
|
|
675
|
+ }
|
|
676
|
+
|
|
677
|
+ /* Enable PCI bus mastering */
|
|
678
|
+ adjust_pci_device(pci);
|
|
679
|
+
|
|
680
|
+ b44_load_mac_and_phy_addr(bp);
|
|
681
|
+
|
|
682
|
+ /* Link management currently not implemented */
|
|
683
|
+ netdev_link_up(netdev);
|
|
684
|
+
|
|
685
|
+ rc = register_netdev(netdev);
|
|
686
|
+ if (rc != 0) {
|
|
687
|
+ iounmap(bp->regs);
|
|
688
|
+ netdev_put(netdev);
|
|
689
|
+ return rc;
|
|
690
|
+ }
|
|
691
|
+
|
|
692
|
+ b44_chip_reset(bp, B44_CHIP_RESET_FULL);
|
|
693
|
+
|
|
694
|
+ DBG("b44 %s (%04x:%04x) regs=%p MAC=%s\n", id->name, id->vendor,
|
|
695
|
+ id->device, bp->regs, eth_ntoa(netdev->ll_addr));
|
|
696
|
+
|
|
697
|
+ return 0;
|
|
698
|
+}
|
|
699
|
+
|
|
700
|
+
|
|
701
|
+/**
|
|
702
|
+ * Remove device
|
|
703
|
+ *
|
|
704
|
+ * @v pci PCI device
|
|
705
|
+ */
|
|
706
|
+static void b44_remove(struct pci_device *pci)
|
|
707
|
+{
|
|
708
|
+ struct net_device *netdev = pci_get_drvdata(pci);
|
|
709
|
+ struct b44_private *bp = netdev_priv(netdev);
|
|
710
|
+
|
|
711
|
+ ssb_core_disable(bp);
|
|
712
|
+ unregister_netdev(netdev);
|
|
713
|
+ iounmap(bp->regs);
|
|
714
|
+ netdev_nullify(netdev);
|
|
715
|
+ netdev_put(netdev);
|
|
716
|
+}
|
|
717
|
+
|
|
718
|
+
|
|
719
|
+/** Enable or disable interrupts
|
|
720
|
+ *
|
|
721
|
+ * @v netdev Network device
|
|
722
|
+ * @v enable Interrupts should be enabled
|
|
723
|
+ */
|
|
724
|
+static void b44_irq(struct net_device *netdev, int enable)
|
|
725
|
+{
|
|
726
|
+ struct b44_private *bp = netdev_priv(netdev);
|
|
727
|
+
|
|
728
|
+ /* Interrupt mask specifies which events generate interrupts */
|
|
729
|
+ bw32(bp, B44_IMASK, enable ? IMASK_DEF : IMASK_DISABLE);
|
|
730
|
+}
|
|
731
|
+
|
|
732
|
+
|
|
733
|
+/** Open network device
|
|
734
|
+ *
|
|
735
|
+ * @v netdev Network device
|
|
736
|
+ * @ret rc Return status code
|
|
737
|
+ */
|
|
738
|
+static int b44_open(struct net_device *netdev)
|
|
739
|
+{
|
|
740
|
+ struct b44_private *bp = netdev_priv(netdev);
|
|
741
|
+ int rc;
|
|
742
|
+
|
|
743
|
+ rc = b44_init_tx_ring(bp);
|
|
744
|
+ if (rc != 0)
|
|
745
|
+ return rc;
|
|
746
|
+
|
|
747
|
+ rc = b44_init_rx_ring(bp);
|
|
748
|
+ if (rc != 0)
|
|
749
|
+ return rc;
|
|
750
|
+
|
|
751
|
+ b44_init_hw(bp, B44_FULL_RESET);
|
|
752
|
+
|
|
753
|
+ /* Disable interrupts */
|
|
754
|
+ b44_irq(netdev, 0);
|
|
755
|
+
|
|
756
|
+ return 0;
|
|
757
|
+}
|
|
758
|
+
|
|
759
|
+
|
|
760
|
+/** Close network device
|
|
761
|
+ *
|
|
762
|
+ * @v netdev Network device
|
|
763
|
+ */
|
|
764
|
+static void b44_close(struct net_device *netdev)
|
|
765
|
+{
|
|
766
|
+ struct b44_private *bp = netdev_priv(netdev);
|
|
767
|
+
|
|
768
|
+ b44_chip_reset(bp, B44_FULL_RESET);
|
|
769
|
+ b44_free_tx_ring(bp);
|
|
770
|
+ b44_free_rx_ring(bp);
|
|
771
|
+}
|
|
772
|
+
|
|
773
|
+
|
|
774
|
+/** Transmit packet
|
|
775
|
+ *
|
|
776
|
+ * @v netdev Network device
|
|
777
|
+ * @v iobuf I/O buffer
|
|
778
|
+ * @ret rc Return status code
|
|
779
|
+ */
|
|
780
|
+static int b44_transmit(struct net_device *netdev, struct io_buffer *iobuf)
|
|
781
|
+{
|
|
782
|
+ struct b44_private *bp = netdev_priv(netdev);
|
|
783
|
+ u32 cur = bp->tx_cur;
|
|
784
|
+ u32 ctrl;
|
|
785
|
+
|
|
786
|
+ /* Check for TX ring overflow */
|
|
787
|
+ if (bp->tx[cur].ctrl) {
|
|
788
|
+ DBG("tx overflow\n");
|
|
789
|
+ return -ENOBUFS;
|
|
790
|
+ }
|
|
791
|
+
|
|
792
|
+ /* Will call netdev_tx_complete() on the iobuf later */
|
|
793
|
+ bp->tx_iobuf[cur] = iobuf;
|
|
794
|
+
|
|
795
|
+ /* Set up TX descriptor */
|
|
796
|
+ ctrl = (iob_len(iobuf) & DESC_CTRL_LEN) |
|
|
797
|
+ DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
|
|
798
|
+
|
|
799
|
+ if (cur == B44_RING_LAST)
|
|
800
|
+ ctrl |= DESC_CTRL_EOT;
|
|
801
|
+
|
|
802
|
+ bp->tx[cur].ctrl = cpu_to_le32(ctrl);
|
|
803
|
+ bp->tx[cur].addr = cpu_to_le32(VIRT_TO_B44(iobuf->data));
|
|
804
|
+
|
|
805
|
+ /* Update next available descriptor index */
|
|
806
|
+ cur = ring_next(cur);
|
|
807
|
+ bp->tx_cur = cur;
|
|
808
|
+ wmb();
|
|
809
|
+
|
|
810
|
+ /* Tell card that a new TX descriptor is ready */
|
|
811
|
+ bw32(bp, B44_DMATX_PTR, cur * sizeof(struct dma_desc));
|
|
812
|
+ return 0;
|
|
813
|
+}
|
|
814
|
+
|
|
815
|
+
|
|
816
|
+/** Recycles sent TX descriptors and notifies network stack
|
|
817
|
+ *
|
|
818
|
+ * @v bp Driver state
|
|
819
|
+ */
|
|
820
|
+static void b44_tx_complete(struct b44_private *bp)
|
|
821
|
+{
|
|
822
|
+ u32 cur, i;
|
|
823
|
+
|
|
824
|
+ cur = pending_tx_index(bp);
|
|
825
|
+
|
|
826
|
+ for (i = bp->tx_dirty; i != cur; i = ring_next(i)) {
|
|
827
|
+ /* Free finished frame */
|
|
828
|
+ netdev_tx_complete(bp->netdev, bp->tx_iobuf[i]);
|
|
829
|
+ bp->tx_iobuf[i] = NULL;
|
|
830
|
+
|
|
831
|
+ /* Clear TX descriptor */
|
|
832
|
+ bp->tx[i].ctrl = 0;
|
|
833
|
+ bp->tx[i].addr = 0;
|
|
834
|
+ }
|
|
835
|
+ bp->tx_dirty = cur;
|
|
836
|
+}
|
|
837
|
+
|
|
838
|
+
|
|
839
|
+static void b44_process_rx_packets(struct b44_private *bp)
|
|
840
|
+{
|
|
841
|
+ struct io_buffer *iob; /* received data */
|
|
842
|
+ struct rx_header *rh;
|
|
843
|
+ u32 pending, i;
|
|
844
|
+ u16 len;
|
|
845
|
+
|
|
846
|
+ pending = pending_rx_index(bp);
|
|
847
|
+
|
|
848
|
+ for (i = bp->rx_cur; i != pending; i = ring_next(i)) {
|
|
849
|
+ iob = bp->rx_iobuf[i];
|
|
850
|
+ if (iob == NULL)
|
|
851
|
+ break;
|
|
852
|
+
|
|
853
|
+ rh = iob->data;
|
|
854
|
+ len = le16_to_cpu(rh->len);
|
|
855
|
+
|
|
856
|
+ /*
|
|
857
|
+ * Guard against incompletely written RX descriptors.
|
|
858
|
+ * Without this, things can get really slow!
|
|
859
|
+ */
|
|
860
|
+ if (len == 0)
|
|
861
|
+ break;
|
|
862
|
+
|
|
863
|
+ /* Discard CRC that is generated by the card */
|
|
864
|
+ len -= 4;
|
|
865
|
+
|
|
866
|
+ /* Check for invalid packets and errors */
|
|
867
|
+ if (len > RX_PKT_BUF_SZ - RX_PKT_OFFSET ||
|
|
868
|
+ (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
|
|
869
|
+ DBG("rx error len=%d flags=%04x\n", len,
|
|
870
|
+ cpu_to_le16(rh->flags));
|
|
871
|
+ rh->len = 0;
|
|
872
|
+ rh->flags = 0;
|
|
873
|
+ netdev_rx_err(bp->netdev, iob, -EINVAL);
|
|
874
|
+ continue;
|
|
875
|
+ }
|
|
876
|
+
|
|
877
|
+ /* Clear RX descriptor */
|
|
878
|
+ rh->len = 0;
|
|
879
|
+ rh->flags = 0;
|
|
880
|
+ bp->rx_iobuf[i] = NULL;
|
|
881
|
+
|
|
882
|
+ /* Hand off the IO buffer to the network stack */
|
|
883
|
+ iob_reserve(iob, RX_PKT_OFFSET);
|
|
884
|
+ iob_put(iob, len);
|
|
885
|
+ netdev_rx(bp->netdev, iob);
|
|
886
|
+ }
|
|
887
|
+ bp->rx_cur = i;
|
|
888
|
+ b44_rx_refill(bp, pending_rx_index(bp));
|
|
889
|
+}
|
|
890
|
+
|
|
891
|
+
|
|
892
|
+/** Poll for completed and received packets
|
|
893
|
+ *
|
|
894
|
+ * @v netdev Network device
|
|
895
|
+ */
|
|
896
|
+static void b44_poll(struct net_device *netdev)
|
|
897
|
+{
|
|
898
|
+ struct b44_private *bp = netdev_priv(netdev);
|
|
899
|
+ u32 istat;
|
|
900
|
+
|
|
901
|
+ /* Interrupt status */
|
|
902
|
+ istat = br32(bp, B44_ISTAT);
|
|
903
|
+ istat &= IMASK_DEF; /* only the events we care about */
|
|
904
|
+
|
|
905
|
+ if (!istat)
|
|
906
|
+ return;
|
|
907
|
+ if (istat & ISTAT_TX)
|
|
908
|
+ b44_tx_complete(bp);
|
|
909
|
+ if (istat & ISTAT_RX)
|
|
910
|
+ b44_process_rx_packets(bp);
|
|
911
|
+ if (istat & ISTAT_ERRORS) {
|
|
912
|
+ DBG("b44 error istat=0x%08x\n", istat);
|
|
913
|
+
|
|
914
|
+ /* Reset B44 core partially to avoid long waits */
|
|
915
|
+ b44_irq(bp->netdev, 0);
|
|
916
|
+ b44_halt(bp);
|
|
917
|
+ b44_init_tx_ring(bp);
|
|
918
|
+ b44_init_rx_ring(bp);
|
|
919
|
+ b44_init_hw(bp, B44_FULL_RESET_SKIP_PHY);
|
|
920
|
+ }
|
|
921
|
+
|
|
922
|
+ /* Acknowledge interrupt */
|
|
923
|
+ bw32(bp, B44_ISTAT, 0);
|
|
924
|
+ bflush(bp, B44_ISTAT, 1);
|
|
925
|
+}
|
|
926
|
+
|
|
927
|
+
|
|
928
|
+static struct net_device_operations b44_operations = {
|
|
929
|
+ .open = b44_open,
|
|
930
|
+ .close = b44_close,
|
|
931
|
+ .transmit = b44_transmit,
|
|
932
|
+ .poll = b44_poll,
|
|
933
|
+ .irq = b44_irq,
|
|
934
|
+};
|
|
935
|
+
|
|
936
|
+
|
|
937
|
+static struct pci_device_id b44_nics[] = {
|
|
938
|
+ PCI_ROM(0x14e4, 0x4401, "BCM4401", "BCM4401"),
|
|
939
|
+ PCI_ROM(0x14e4, 0x170c, "BCM4401-B0", "BCM4401-B0"),
|
|
940
|
+ PCI_ROM(0x14e4, 0x4402, "BCM4401-B1", "BCM4401-B1"),
|
|
941
|
+};
|
|
942
|
+
|
|
943
|
+
|
|
944
|
+struct pci_driver b44_driver __pci_driver = {
|
|
945
|
+ .ids = b44_nics,
|
|
946
|
+ .id_count = sizeof b44_nics / sizeof b44_nics[0],
|
|
947
|
+ .probe = b44_probe,
|
|
948
|
+ .remove = b44_remove,
|
|
949
|
+};
|