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[ath] Fix building with GCC 6

Signed-off-by: Michael Brown <mcb30@ipxe.org>
tags/v1.20.1
Michael Brown 8 years ago
parent
commit
63037bdce4

+ 0
- 2
src/drivers/net/ath/ath.h View File

@@ -101,8 +101,6 @@ static inline u32 get_unaligned_le32(const void *p)
101 101
  */
102 102
 #define	ATH_KEYMAX	        128     /* max key cache size we handle */
103 103
 
104
-static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
105
-
106 104
 struct ath_ani {
107 105
 	int caldone;
108 106
 	unsigned int longcal_timer;

+ 0
- 40
src/drivers/net/ath/ath5k/ath5k.c View File

@@ -85,46 +85,6 @@ static struct pci_device_id ath5k_nics[] = {
85 85
 	PCI_ROM(0x168c, 0x001d, "ath2417", "Atheros 2417 Nala", AR5K_AR5212),
86 86
 };
87 87
 
88
-/* Known SREVs */
89
-static const struct ath5k_srev_name srev_names[] = {
90
-	{ "5210",	AR5K_VERSION_MAC,	AR5K_SREV_AR5210 },
91
-	{ "5311",	AR5K_VERSION_MAC,	AR5K_SREV_AR5311 },
92
-	{ "5311A",	AR5K_VERSION_MAC,	AR5K_SREV_AR5311A },
93
-	{ "5311B",	AR5K_VERSION_MAC,	AR5K_SREV_AR5311B },
94
-	{ "5211",	AR5K_VERSION_MAC,	AR5K_SREV_AR5211 },
95
-	{ "5212",	AR5K_VERSION_MAC,	AR5K_SREV_AR5212 },
96
-	{ "5213",	AR5K_VERSION_MAC,	AR5K_SREV_AR5213 },
97
-	{ "5213A",	AR5K_VERSION_MAC,	AR5K_SREV_AR5213A },
98
-	{ "2413",	AR5K_VERSION_MAC,	AR5K_SREV_AR2413 },
99
-	{ "2414",	AR5K_VERSION_MAC,	AR5K_SREV_AR2414 },
100
-	{ "5424",	AR5K_VERSION_MAC,	AR5K_SREV_AR5424 },
101
-	{ "5413",	AR5K_VERSION_MAC,	AR5K_SREV_AR5413 },
102
-	{ "5414",	AR5K_VERSION_MAC,	AR5K_SREV_AR5414 },
103
-	{ "2415",	AR5K_VERSION_MAC,	AR5K_SREV_AR2415 },
104
-	{ "5416",	AR5K_VERSION_MAC,	AR5K_SREV_AR5416 },
105
-	{ "5418",	AR5K_VERSION_MAC,	AR5K_SREV_AR5418 },
106
-	{ "2425",	AR5K_VERSION_MAC,	AR5K_SREV_AR2425 },
107
-	{ "2417",	AR5K_VERSION_MAC,	AR5K_SREV_AR2417 },
108
-	{ "xxxxx",	AR5K_VERSION_MAC,	AR5K_SREV_UNKNOWN },
109
-	{ "5110",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_5110 },
110
-	{ "5111",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_5111 },
111
-	{ "5111A",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_5111A },
112
-	{ "2111",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_2111 },
113
-	{ "5112",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_5112 },
114
-	{ "5112A",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_5112A },
115
-	{ "5112B",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_5112B },
116
-	{ "2112",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_2112 },
117
-	{ "2112A",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_2112A },
118
-	{ "2112B",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_2112B },
119
-	{ "2413",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_2413 },
120
-	{ "5413",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_5413 },
121
-	{ "2316",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_2316 },
122
-	{ "2317",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_2317 },
123
-	{ "5424",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_5424 },
124
-	{ "5133",	AR5K_VERSION_RAD,	AR5K_SREV_RAD_5133 },
125
-	{ "xxxxx",	AR5K_VERSION_RAD,	AR5K_SREV_UNKNOWN },
126
-};
127
-
128 88
 #define ATH5K_SPMBL_NO   1
129 89
 #define ATH5K_SPMBL_YES  2
130 90
 #define ATH5K_SPMBL_BOTH 3

+ 3
- 3
src/drivers/net/ath/ath5k/ath5k_phy.c View File

@@ -1219,12 +1219,12 @@ static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1219 1219
 
1220 1220
 	/* Update radio registers */
1221 1221
 	ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
1222
-		AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
1222
+		AR5K_REG_SM(-1U, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
1223 1223
 
1224 1224
 	ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
1225 1225
 			AR5K_PHY_AGCCOARSE_LO)) |
1226
-		AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
1227
-		AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
1226
+		AR5K_REG_SM(-1U, AR5K_PHY_AGCCOARSE_HI) |
1227
+		AR5K_REG_SM(-127U, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
1228 1228
 
1229 1229
 	ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
1230 1230
 			AR5K_PHY_ADCSAT_THR)) |

+ 0
- 8
src/drivers/net/ath/ath5k/ath5k_reset.c View File

@@ -134,14 +134,6 @@ static int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
134 134
 	return 0;
135 135
 }
136 136
 
137
-
138
-/*
139
- * index into rates for control rates, we can set it up like this because
140
- * this is only used for AR5212 and we know it supports G mode
141
- */
142
-static const unsigned int control_rates[] =
143
-	{ 0, 1, 1, 1, 4, 4, 6, 6, 8, 8, 8, 8 };
144
-
145 137
 /**
146 138
  * ath5k_hw_write_rate_duration - fill rate code to duration table
147 139
  *

+ 36
- 36
src/drivers/net/ath/ath9k/ar9002_initvals.h View File

@@ -16,7 +16,7 @@
16 16
 
17 17
 FILE_LICENCE ( BSD2 );
18 18
 
19
-static const u32 ar9280Modes_9280_2[][6] = {
19
+static __unused const u32 ar9280Modes_9280_2[][6] = {
20 20
 	{0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0},
21 21
 	{0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0},
22 22
 	{0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180},
@@ -65,7 +65,7 @@ static const u32 ar9280Modes_9280_2[][6] = {
65 65
 	{0x00007894, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000},
66 66
 };
67 67
 
68
-static const u32 ar9280Common_9280_2[][2] = {
68
+static __unused const u32 ar9280Common_9280_2[][2] = {
69 69
 	/* Addr      allmodes  */
70 70
 	{0x0000000c, 0x00000000},
71 71
 	{0x00000030, 0x00020015},
@@ -409,7 +409,7 @@ static const u32 ar9280Common_9280_2[][2] = {
409 409
 	{0x00007898, 0x2a850160},
410 410
 };
411 411
 
412
-static const u32 ar9280Modes_fast_clock_9280_2[][3] = {
412
+static __unused const u32 ar9280Modes_fast_clock_9280_2[][3] = {
413 413
 	/* Addr      5G_HT20     5G_HT40   */
414 414
 	{0x00001030, 0x00000268, 0x000004d0},
415 415
 	{0x00001070, 0x0000018c, 0x00000318},
@@ -426,7 +426,7 @@ static const u32 ar9280Modes_fast_clock_9280_2[][3] = {
426 426
 	{0x00009918, 0x0000000b, 0x00000016},
427 427
 };
428 428
 
429
-static const u32 ar9280Modes_backoff_23db_rxgain_9280_2[][6] = {
429
+static __unused const u32 ar9280Modes_backoff_23db_rxgain_9280_2[][6] = {
430 430
 	{0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290},
431 431
 	{0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300},
432 432
 	{0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304},
@@ -559,7 +559,7 @@ static const u32 ar9280Modes_backoff_23db_rxgain_9280_2[][6] = {
559 559
 	{0x0000a848, 0x00001066, 0x00001066, 0x00001055, 0x00001055, 0x00001055},
560 560
 };
561 561
 
562
-static const u32 ar9280Modes_original_rxgain_9280_2[][6] = {
562
+static __unused const u32 ar9280Modes_original_rxgain_9280_2[][6] = {
563 563
 	{0x00009a00, 0x00008184, 0x00008184, 0x00008000, 0x00008000, 0x00008000},
564 564
 	{0x00009a04, 0x00008188, 0x00008188, 0x00008000, 0x00008000, 0x00008000},
565 565
 	{0x00009a08, 0x0000818c, 0x0000818c, 0x00008000, 0x00008000, 0x00008000},
@@ -692,7 +692,7 @@ static const u32 ar9280Modes_original_rxgain_9280_2[][6] = {
692 692
 	{0x0000a848, 0x00001066, 0x00001066, 0x00001063, 0x00001063, 0x00001063},
693 693
 };
694 694
 
695
-static const u32 ar9280Modes_backoff_13db_rxgain_9280_2[][6] = {
695
+static __unused const u32 ar9280Modes_backoff_13db_rxgain_9280_2[][6] = {
696 696
 	{0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290},
697 697
 	{0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300},
698 698
 	{0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304},
@@ -825,7 +825,7 @@ static const u32 ar9280Modes_backoff_13db_rxgain_9280_2[][6] = {
825 825
 	{0x0000a848, 0x00001066, 0x00001066, 0x0000105a, 0x0000105a, 0x0000105a},
826 826
 };
827 827
 
828
-static const u32 ar9280Modes_high_power_tx_gain_9280_2[][6] = {
828
+static __unused const u32 ar9280Modes_high_power_tx_gain_9280_2[][6] = {
829 829
 	{0x0000a274, 0x0a19e652, 0x0a19e652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652},
830 830
 	{0x0000a27c, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce},
831 831
 	{0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
@@ -859,7 +859,7 @@ static const u32 ar9280Modes_high_power_tx_gain_9280_2[][6] = {
859 859
 	{0x00007844, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480},
860 860
 };
861 861
 
862
-static const u32 ar9280Modes_original_tx_gain_9280_2[][6] = {
862
+static __unused const u32 ar9280Modes_original_tx_gain_9280_2[][6] = {
863 863
 	{0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652},
864 864
 	{0x0000a27c, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce},
865 865
 	{0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
@@ -893,7 +893,7 @@ static const u32 ar9280Modes_original_tx_gain_9280_2[][6] = {
893 893
 	{0x00007844, 0x92592480, 0x92592480, 0x92592480, 0x92592480, 0x92592480},
894 894
 };
895 895
 
896
-static const u32 ar9280PciePhy_clkreq_off_L1_9280[][2] = {
896
+static __unused const u32 ar9280PciePhy_clkreq_off_L1_9280[][2] = {
897 897
 	/* Addr      allmodes  */
898 898
 	{0x00004040, 0x9248fd00},
899 899
 	{0x00004040, 0x24924924},
@@ -907,7 +907,7 @@ static const u32 ar9280PciePhy_clkreq_off_L1_9280[][2] = {
907 907
 	{0x00004044, 0x00000000},
908 908
 };
909 909
 
910
-static const u32 ar9280PciePhy_clkreq_always_on_L1_9280[][2] = {
910
+static __unused const u32 ar9280PciePhy_clkreq_always_on_L1_9280[][2] = {
911 911
 	/* Addr      allmodes  */
912 912
 	{0x00004040, 0x9248fd00},
913 913
 	{0x00004040, 0x24924924},
@@ -921,7 +921,7 @@ static const u32 ar9280PciePhy_clkreq_always_on_L1_9280[][2] = {
921 921
 	{0x00004044, 0x00000000},
922 922
 };
923 923
 
924
-static const u32 ar9285PciePhy_clkreq_always_on_L1_9285[][2] = {
924
+static __unused const u32 ar9285PciePhy_clkreq_always_on_L1_9285[][2] = {
925 925
 	/* Addr      allmodes  */
926 926
 	{0x00004040, 0x9248fd00},
927 927
 	{0x00004040, 0x24924924},
@@ -935,7 +935,7 @@ static const u32 ar9285PciePhy_clkreq_always_on_L1_9285[][2] = {
935 935
 	{0x00004044, 0x00000000},
936 936
 };
937 937
 
938
-static const u32 ar9285PciePhy_clkreq_off_L1_9285[][2] = {
938
+static __unused const u32 ar9285PciePhy_clkreq_off_L1_9285[][2] = {
939 939
 	/* Addr      allmodes  */
940 940
 	{0x00004040, 0x9248fd00},
941 941
 	{0x00004040, 0x24924924},
@@ -949,7 +949,7 @@ static const u32 ar9285PciePhy_clkreq_off_L1_9285[][2] = {
949 949
 	{0x00004044, 0x00000000},
950 950
 };
951 951
 
952
-static const u32 ar9285Modes_9285_1_2[][6] = {
952
+static __unused const u32 ar9285Modes_9285_1_2[][6] = {
953 953
 	{0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0},
954 954
 	{0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0},
955 955
 	{0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180},
@@ -1254,7 +1254,7 @@ static const u32 ar9285Modes_9285_1_2[][6] = {
1254 1254
 	{0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e},
1255 1255
 };
1256 1256
 
1257
-static const u32 ar9285Common_9285_1_2[][2] = {
1257
+static __unused const u32 ar9285Common_9285_1_2[][2] = {
1258 1258
 	/* Addr      allmodes  */
1259 1259
 	{0x0000000c, 0x00000000},
1260 1260
 	{0x00000030, 0x00020045},
@@ -1574,7 +1574,7 @@ static const u32 ar9285Common_9285_1_2[][2] = {
1574 1574
 	{0x00007870, 0x10142c00},
1575 1575
 };
1576 1576
 
1577
-static const u32 ar9285Modes_high_power_tx_gain_9285_1_2[][6] = {
1577
+static __unused const u32 ar9285Modes_high_power_tx_gain_9285_1_2[][6] = {
1578 1578
 	{0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1579 1579
 	{0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200, 0x00000000},
1580 1580
 	{0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201, 0x00000000},
@@ -1614,7 +1614,7 @@ static const u32 ar9285Modes_high_power_tx_gain_9285_1_2[][6] = {
1614 1614
 	{0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7},
1615 1615
 };
1616 1616
 
1617
-static const u32 ar9285Modes_original_tx_gain_9285_1_2[][6] = {
1617
+static __unused const u32 ar9285Modes_original_tx_gain_9285_1_2[][6] = {
1618 1618
 	{0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1619 1619
 	{0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000},
1620 1620
 	{0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000},
@@ -1654,7 +1654,7 @@ static const u32 ar9285Modes_original_tx_gain_9285_1_2[][6] = {
1654 1654
 	{0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c},
1655 1655
 };
1656 1656
 
1657
-static const u32 ar9285Modes_XE2_0_normal_power[][6] = {
1657
+static __unused const u32 ar9285Modes_XE2_0_normal_power[][6] = {
1658 1658
 	{0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1659 1659
 	{0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000},
1660 1660
 	{0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000},
@@ -1694,7 +1694,7 @@ static const u32 ar9285Modes_XE2_0_normal_power[][6] = {
1694 1694
 	{0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c},
1695 1695
 };
1696 1696
 
1697
-static const u32 ar9285Modes_XE2_0_high_power[][6] = {
1697
+static __unused const u32 ar9285Modes_XE2_0_high_power[][6] = {
1698 1698
 	{0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1699 1699
 	{0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200, 0x00000000},
1700 1700
 	{0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201, 0x00000000},
@@ -1734,7 +1734,7 @@ static const u32 ar9285Modes_XE2_0_high_power[][6] = {
1734 1734
 	{0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7},
1735 1735
 };
1736 1736
 
1737
-static const u32 ar9285PciePhy_clkreq_always_on_L1_9285_1_2[][2] = {
1737
+static __unused const u32 ar9285PciePhy_clkreq_always_on_L1_9285_1_2[][2] = {
1738 1738
 	/* Addr      allmodes  */
1739 1739
 	{0x00004040, 0x9248fd00},
1740 1740
 	{0x00004040, 0x24924924},
@@ -1748,7 +1748,7 @@ static const u32 ar9285PciePhy_clkreq_always_on_L1_9285_1_2[][2] = {
1748 1748
 	{0x00004044, 0x00000000},
1749 1749
 };
1750 1750
 
1751
-static const u32 ar9285PciePhy_clkreq_off_L1_9285_1_2[][2] = {
1751
+static __unused const u32 ar9285PciePhy_clkreq_off_L1_9285_1_2[][2] = {
1752 1752
 	/* Addr      allmodes  */
1753 1753
 	{0x00004040, 0x9248fd00},
1754 1754
 	{0x00004040, 0x24924924},
@@ -1762,7 +1762,7 @@ static const u32 ar9285PciePhy_clkreq_off_L1_9285_1_2[][2] = {
1762 1762
 	{0x00004044, 0x00000000},
1763 1763
 };
1764 1764
 
1765
-static const u32 ar9287Modes_9287_1_1[][6] = {
1765
+static __unused const u32 ar9287Modes_9287_1_1[][6] = {
1766 1766
 	{0x00001030, 0x00000000, 0x00000000, 0x000002c0, 0x00000160, 0x000001e0},
1767 1767
 	{0x00001070, 0x00000000, 0x00000000, 0x00000318, 0x0000018c, 0x000001e0},
1768 1768
 	{0x000010b0, 0x00000000, 0x00000000, 0x00007c70, 0x00003e38, 0x00001180},
@@ -1808,7 +1808,7 @@ static const u32 ar9287Modes_9287_1_1[][6] = {
1808 1808
 	{0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
1809 1809
 };
1810 1810
 
1811
-static const u32 ar9287Common_9287_1_1[][2] = {
1811
+static __unused const u32 ar9287Common_9287_1_1[][2] = {
1812 1812
 	/* Addr      allmodes  */
1813 1813
 	{0x0000000c, 0x00000000},
1814 1814
 	{0x00000030, 0x00020015},
@@ -2177,21 +2177,21 @@ static const u32 ar9287Common_9287_1_1[][2] = {
2177 2177
 	{0x000078b8, 0x2a850160},
2178 2178
 };
2179 2179
 
2180
-static const u32 ar9287Common_normal_cck_fir_coeff_9287_1_1[][2] = {
2180
+static __unused const u32 ar9287Common_normal_cck_fir_coeff_9287_1_1[][2] = {
2181 2181
 	/* Addr      allmodes  */
2182 2182
 	{0x0000a1f4, 0x00fffeff},
2183 2183
 	{0x0000a1f8, 0x00f5f9ff},
2184 2184
 	{0x0000a1fc, 0xb79f6427},
2185 2185
 };
2186 2186
 
2187
-static const u32 ar9287Common_japan_2484_cck_fir_coeff_9287_1_1[][2] = {
2187
+static __unused const u32 ar9287Common_japan_2484_cck_fir_coeff_9287_1_1[][2] = {
2188 2188
 	/* Addr      allmodes  */
2189 2189
 	{0x0000a1f4, 0x00000000},
2190 2190
 	{0x0000a1f8, 0xefff0301},
2191 2191
 	{0x0000a1fc, 0xca9228ee},
2192 2192
 };
2193 2193
 
2194
-static const u32 ar9287Modes_tx_gain_9287_1_1[][6] = {
2194
+static __unused const u32 ar9287Modes_tx_gain_9287_1_1[][6] = {
2195 2195
 	{0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
2196 2196
 	{0x0000a304, 0x00000000, 0x00000000, 0x00004002, 0x00004002, 0x00004002},
2197 2197
 	{0x0000a308, 0x00000000, 0x00000000, 0x00008004, 0x00008004, 0x00008004},
@@ -2239,7 +2239,7 @@ static const u32 ar9287Modes_tx_gain_9287_1_1[][6] = {
2239 2239
 	{0x0000a274, 0x0a180000, 0x0a180000, 0x0a1aa000, 0x0a1aa000, 0x0a1aa000},
2240 2240
 };
2241 2241
 
2242
-static const u32 ar9287Modes_rx_gain_9287_1_1[][6] = {
2242
+static __unused const u32 ar9287Modes_rx_gain_9287_1_1[][6] = {
2243 2243
 	{0x00009a00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120},
2244 2244
 	{0x00009a04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124},
2245 2245
 	{0x00009a08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128},
@@ -2500,7 +2500,7 @@ static const u32 ar9287Modes_rx_gain_9287_1_1[][6] = {
2500 2500
 	{0x0000a848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067},
2501 2501
 };
2502 2502
 
2503
-static const u32 ar9287PciePhy_clkreq_always_on_L1_9287_1_1[][2] = {
2503
+static __unused const u32 ar9287PciePhy_clkreq_always_on_L1_9287_1_1[][2] = {
2504 2504
 	/* Addr      allmodes  */
2505 2505
 	{0x00004040, 0x9248fd00},
2506 2506
 	{0x00004040, 0x24924924},
@@ -2514,7 +2514,7 @@ static const u32 ar9287PciePhy_clkreq_always_on_L1_9287_1_1[][2] = {
2514 2514
 	{0x00004044, 0x00000000},
2515 2515
 };
2516 2516
 
2517
-static const u32 ar9287PciePhy_clkreq_off_L1_9287_1_1[][2] = {
2517
+static __unused const u32 ar9287PciePhy_clkreq_off_L1_9287_1_1[][2] = {
2518 2518
 	/* Addr      allmodes  */
2519 2519
 	{0x00004040, 0x9248fd00},
2520 2520
 	{0x00004040, 0x24924924},
@@ -2528,7 +2528,7 @@ static const u32 ar9287PciePhy_clkreq_off_L1_9287_1_1[][2] = {
2528 2528
 	{0x00004044, 0x00000000},
2529 2529
 };
2530 2530
 
2531
-static const u32 ar9271Modes_9271[][6] = {
2531
+static __unused const u32 ar9271Modes_9271[][6] = {
2532 2532
 	{0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0},
2533 2533
 	{0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0},
2534 2534
 	{0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180},
@@ -2834,7 +2834,7 @@ static const u32 ar9271Modes_9271[][6] = {
2834 2834
 	{0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e},
2835 2835
 };
2836 2836
 
2837
-static const u32 ar9271Common_9271[][2] = {
2837
+static __unused const u32 ar9271Common_9271[][2] = {
2838 2838
 	/* Addr      allmodes  */
2839 2839
 	{0x0000000c, 0x00000000},
2840 2840
 	{0x00000030, 0x00020045},
@@ -3163,26 +3163,26 @@ static const u32 ar9271Common_9271[][2] = {
3163 3163
 	{0x0000d384, 0xf3307ff0},
3164 3164
 };
3165 3165
 
3166
-static const u32 ar9271Common_normal_cck_fir_coeff_9271[][2] = {
3166
+static __unused const u32 ar9271Common_normal_cck_fir_coeff_9271[][2] = {
3167 3167
 	/* Addr      allmodes  */
3168 3168
 	{0x0000a1f4, 0x00fffeff},
3169 3169
 	{0x0000a1f8, 0x00f5f9ff},
3170 3170
 	{0x0000a1fc, 0xb79f6427},
3171 3171
 };
3172 3172
 
3173
-static const u32 ar9271Common_japan_2484_cck_fir_coeff_9271[][2] = {
3173
+static __unused const u32 ar9271Common_japan_2484_cck_fir_coeff_9271[][2] = {
3174 3174
 	/* Addr      allmodes  */
3175 3175
 	{0x0000a1f4, 0x00000000},
3176 3176
 	{0x0000a1f8, 0xefff0301},
3177 3177
 	{0x0000a1fc, 0xca9228ee},
3178 3178
 };
3179 3179
 
3180
-static const u32 ar9271Modes_9271_1_0_only[][6] = {
3180
+static __unused const u32 ar9271Modes_9271_1_0_only[][6] = {
3181 3181
 	{0x00009910, 0x30002311, 0x30002311, 0x30002311, 0x30002311, 0x30002311},
3182 3182
 	{0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001},
3183 3183
 };
3184 3184
 
3185
-static const u32 ar9271Modes_9271_ANI_reg[][6] = {
3185
+static __unused const u32 ar9271Modes_9271_ANI_reg[][6] = {
3186 3186
 	{0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2},
3187 3187
 	{0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e},
3188 3188
 	{0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e},
@@ -3193,7 +3193,7 @@ static const u32 ar9271Modes_9271_ANI_reg[][6] = {
3193 3193
 	{0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
3194 3194
 };
3195 3195
 
3196
-static const u32 ar9271Modes_normal_power_tx_gain_9271[][6] = {
3196
+static __unused const u32 ar9271Modes_normal_power_tx_gain_9271[][6] = {
3197 3197
 	{0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
3198 3198
 	{0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000},
3199 3199
 	{0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000},
@@ -3229,7 +3229,7 @@ static const u32 ar9271Modes_normal_power_tx_gain_9271[][6] = {
3229 3229
 	{0x0000a3e0, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd},
3230 3230
 };
3231 3231
 
3232
-static const u32 ar9271Modes_high_power_tx_gain_9271[][6] = {
3232
+static __unused const u32 ar9271Modes_high_power_tx_gain_9271[][6] = {
3233 3233
 	{0x0000a300, 0x00000000, 0x00000000, 0x00010000, 0x00010000, 0x00000000},
3234 3234
 	{0x0000a304, 0x00000000, 0x00000000, 0x00016200, 0x00016200, 0x00000000},
3235 3235
 	{0x0000a308, 0x00000000, 0x00000000, 0x00018201, 0x00018201, 0x00000000},

+ 20
- 20
src/drivers/net/ath/ath9k/ar9003_2p2_initvals.h View File

@@ -19,7 +19,7 @@
19 19
 
20 20
 /* AR9003 2.2 */
21 21
 
22
-static const u32 ar9300_2p2_radio_postamble[][5] = {
22
+static __unused const u32 ar9300_2p2_radio_postamble[][5] = {
23 23
 	/* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
24 24
 	{0x0001609c, 0x0dd08f29, 0x0dd08f29, 0x0b283f31, 0x0b283f31},
25 25
 	{0x000160ac, 0xa4653c00, 0xa4653c00, 0x24652800, 0x24652800},
@@ -32,7 +32,7 @@ static const u32 ar9300_2p2_radio_postamble[][5] = {
32 32
 	{0x00016940, 0x10804008, 0x10804008, 0x50804008, 0x50804008},
33 33
 };
34 34
 
35
-static const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p2[][5] = {
35
+static __unused const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p2[][5] = {
36 36
 	/* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
37 37
 	{0x0000a2dc, 0x00033800, 0x00033800, 0x03aaa352, 0x03aaa352},
38 38
 	{0x0000a2e0, 0x0003c000, 0x0003c000, 0x03ccc584, 0x03ccc584},
@@ -138,7 +138,7 @@ static const u32 ar9300Modes_lowest_ob_db_tx_gain_table_2p2[][5] = {
138 138
 	{0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
139 139
 };
140 140
 
141
-static const u32 ar9300Modes_fast_clock_2p2[][3] = {
141
+static __unused const u32 ar9300Modes_fast_clock_2p2[][3] = {
142 142
 	/* Addr      5G_HT20     5G_HT40   */
143 143
 	{0x00001030, 0x00000268, 0x000004d0},
144 144
 	{0x00001070, 0x0000018c, 0x00000318},
@@ -151,7 +151,7 @@ static const u32 ar9300Modes_fast_clock_2p2[][3] = {
151 151
 	{0x0000a254, 0x00000898, 0x00001130},
152 152
 };
153 153
 
154
-static const u32 ar9300_2p2_radio_core[][2] = {
154
+static __unused const u32 ar9300_2p2_radio_core[][2] = {
155 155
 	/* Addr      allmodes  */
156 156
 	{0x00016000, 0x36db6db6},
157 157
 	{0x00016004, 0x6db6db40},
@@ -295,7 +295,7 @@ static const u32 ar9300_2p2_radio_core[][2] = {
295 295
 	{0x00016bd4, 0x00000000},
296 296
 };
297 297
 
298
-static const u32 ar9300Common_rx_gain_table_merlin_2p2[][2] = {
298
+static __unused const u32 ar9300Common_rx_gain_table_merlin_2p2[][2] = {
299 299
 	/* Addr      allmodes  */
300 300
 	{0x0000a000, 0x02000101},
301 301
 	{0x0000a004, 0x02000102},
@@ -555,7 +555,7 @@ static const u32 ar9300Common_rx_gain_table_merlin_2p2[][2] = {
555 555
 	{0x0000b1fc, 0x00000776},
556 556
 };
557 557
 
558
-static const u32 ar9300_2p2_mac_postamble[][5] = {
558
+static __unused const u32 ar9300_2p2_mac_postamble[][5] = {
559 559
 	/* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
560 560
 	{0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
561 561
 	{0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
@@ -567,12 +567,12 @@ static const u32 ar9300_2p2_mac_postamble[][5] = {
567 567
 	{0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
568 568
 };
569 569
 
570
-static const u32 ar9300_2p2_soc_postamble[][5] = {
570
+static __unused const u32 ar9300_2p2_soc_postamble[][5] = {
571 571
 	/* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
572 572
 	{0x00007010, 0x00000023, 0x00000023, 0x00000023, 0x00000023},
573 573
 };
574 574
 
575
-static const u32 ar9200_merlin_2p2_radio_core[][2] = {
575
+static __unused const u32 ar9200_merlin_2p2_radio_core[][2] = {
576 576
 	/* Addr      allmodes  */
577 577
 	{0x00007800, 0x00040000},
578 578
 	{0x00007804, 0xdb005012},
@@ -614,7 +614,7 @@ static const u32 ar9200_merlin_2p2_radio_core[][2] = {
614 614
 	{0x00007894, 0x5a108000},
615 615
 };
616 616
 
617
-static const u32 ar9300_2p2_baseband_postamble[][5] = {
617
+static __unused const u32 ar9300_2p2_baseband_postamble[][5] = {
618 618
 	/* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
619 619
 	{0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
620 620
 	{0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
@@ -670,7 +670,7 @@ static const u32 ar9300_2p2_baseband_postamble[][5] = {
670 670
 	{0x0000c284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
671 671
 };
672 672
 
673
-static const u32 ar9300_2p2_baseband_core[][2] = {
673
+static __unused const u32 ar9300_2p2_baseband_core[][2] = {
674 674
 	/* Addr      allmodes  */
675 675
 	{0x00009800, 0xafe68e30},
676 676
 	{0x00009804, 0xfd14e000},
@@ -833,7 +833,7 @@ static const u32 ar9300_2p2_baseband_core[][2] = {
833 833
 	{0x0000c420, 0x00000000},
834 834
 };
835 835
 
836
-static const u32 ar9300Modes_high_power_tx_gain_table_2p2[][5] = {
836
+static __unused const u32 ar9300Modes_high_power_tx_gain_table_2p2[][5] = {
837 837
 	/* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
838 838
 	{0x0000a2dc, 0x0380c7fc, 0x0380c7fc, 0x03aaa352, 0x03aaa352},
839 839
 	{0x0000a2e0, 0x0000f800, 0x0000f800, 0x03ccc584, 0x03ccc584},
@@ -939,7 +939,7 @@ static const u32 ar9300Modes_high_power_tx_gain_table_2p2[][5] = {
939 939
 	{0x00016868, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c, 0x6eb6db6c},
940 940
 };
941 941
 
942
-static const u32 ar9300Modes_high_ob_db_tx_gain_table_2p2[][5] = {
942
+static __unused const u32 ar9300Modes_high_ob_db_tx_gain_table_2p2[][5] = {
943 943
 	/* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
944 944
 	{0x0000a2dc, 0x01feee00, 0x01feee00, 0x03aaa352, 0x03aaa352},
945 945
 	{0x0000a2e0, 0x0000f000, 0x0000f000, 0x03ccc584, 0x03ccc584},
@@ -1045,7 +1045,7 @@ static const u32 ar9300Modes_high_ob_db_tx_gain_table_2p2[][5] = {
1045 1045
 	{0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
1046 1046
 };
1047 1047
 
1048
-static const u32 ar9300Common_rx_gain_table_2p2[][2] = {
1048
+static __unused const u32 ar9300Common_rx_gain_table_2p2[][2] = {
1049 1049
 	/* Addr      allmodes  */
1050 1050
 	{0x0000a000, 0x00010000},
1051 1051
 	{0x0000a004, 0x00030002},
@@ -1305,7 +1305,7 @@ static const u32 ar9300Common_rx_gain_table_2p2[][2] = {
1305 1305
 	{0x0000b1fc, 0x00000196},
1306 1306
 };
1307 1307
 
1308
-static const u32 ar9300Modes_low_ob_db_tx_gain_table_2p2[][5] = {
1308
+static __unused const u32 ar9300Modes_low_ob_db_tx_gain_table_2p2[][5] = {
1309 1309
 	/* Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20   */
1310 1310
 	{0x0000a2dc, 0x00033800, 0x00033800, 0x03aaa352, 0x03aaa352},
1311 1311
 	{0x0000a2e0, 0x0003c000, 0x0003c000, 0x03ccc584, 0x03ccc584},
@@ -1411,7 +1411,7 @@ static const u32 ar9300Modes_low_ob_db_tx_gain_table_2p2[][5] = {
1411 1411
 	{0x00016868, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c, 0x6db6db6c},
1412 1412
 };
1413 1413
 
1414
-static const u32 ar9300_2p2_mac_core[][2] = {
1414
+static __unused const u32 ar9300_2p2_mac_core[][2] = {
1415 1415
 	/* Addr      allmodes  */
1416 1416
 	{0x00000008, 0x00000000},
1417 1417
 	{0x00000030, 0x00020085},
@@ -1570,7 +1570,7 @@ static const u32 ar9300_2p2_mac_core[][2] = {
1570 1570
 	{0x000083d0, 0x000301ff},
1571 1571
 };
1572 1572
 
1573
-static const u32 ar9300Common_wo_xlna_rx_gain_table_2p2[][2] = {
1573
+static __unused const u32 ar9300Common_wo_xlna_rx_gain_table_2p2[][2] = {
1574 1574
 	/* Addr      allmodes  */
1575 1575
 	{0x0000a000, 0x00010000},
1576 1576
 	{0x0000a004, 0x00030002},
@@ -1830,7 +1830,7 @@ static const u32 ar9300Common_wo_xlna_rx_gain_table_2p2[][2] = {
1830 1830
 	{0x0000b1fc, 0x00000196},
1831 1831
 };
1832 1832
 
1833
-static const u32 ar9300_2p2_soc_preamble[][2] = {
1833
+static __unused const u32 ar9300_2p2_soc_preamble[][2] = {
1834 1834
 	/* Addr      allmodes  */
1835 1835
 	{0x000040a4, 0x00a0c1c9},
1836 1836
 	{0x00007008, 0x00000000},
@@ -1840,21 +1840,21 @@ static const u32 ar9300_2p2_soc_preamble[][2] = {
1840 1840
 	{0x00007048, 0x00000008},
1841 1841
 };
1842 1842
 
1843
-static const u32 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2[][2] = {
1843
+static __unused const u32 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2[][2] = {
1844 1844
 	/* Addr      allmodes  */
1845 1845
 	{0x00004040, 0x0821265e},
1846 1846
 	{0x00004040, 0x0008003b},
1847 1847
 	{0x00004044, 0x00000000},
1848 1848
 };
1849 1849
 
1850
-static const u32 ar9300PciePhy_clkreq_enable_L1_2p2[][2] = {
1850
+static __unused const u32 ar9300PciePhy_clkreq_enable_L1_2p2[][2] = {
1851 1851
 	/* Addr      allmodes  */
1852 1852
 	{0x00004040, 0x08253e5e},
1853 1853
 	{0x00004040, 0x0008003b},
1854 1854
 	{0x00004044, 0x00000000},
1855 1855
 };
1856 1856
 
1857
-static const u32 ar9300PciePhy_clkreq_disable_L1_2p2[][2] = {
1857
+static __unused const u32 ar9300PciePhy_clkreq_disable_L1_2p2[][2] = {
1858 1858
 	/* Addr      allmodes  */
1859 1859
 	{0x00004040, 0x08213e5e},
1860 1860
 	{0x00004040, 0x0008003b},

+ 18
- 18
src/drivers/net/ath/ath9k/ar9340_initvals.h View File

@@ -17,7 +17,7 @@
17 17
 #ifndef INITVALS_9340_H
18 18
 #define INITVALS_9340_H
19 19
 
20
-static const u32 ar9340_1p0_radio_postamble[][5] = {
20
+static __unused const u32 ar9340_1p0_radio_postamble[][5] = {
21 21
 	/*  Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
22 22
 	{0x000160ac, 0xa4646800, 0xa4646800, 0xa4646800, 0xa4646800},
23 23
 	{0x0001610c, 0x08000000, 0x08000000, 0x00000000, 0x00000000},
@@ -26,7 +26,7 @@ static const u32 ar9340_1p0_radio_postamble[][5] = {
26 26
 	{0x00016540, 0x10804000, 0x10804000, 0x50804000, 0x50804000},
27 27
 };
28 28
 
29
-static const u32 ar9340Modes_lowest_ob_db_tx_gain_table_1p0[][5] = {
29
+static __unused const u32 ar9340Modes_lowest_ob_db_tx_gain_table_1p0[][5] = {
30 30
 	/*   Addr     5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
31 31
 	{0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
32 32
 	{0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
@@ -99,7 +99,7 @@ static const u32 ar9340Modes_lowest_ob_db_tx_gain_table_1p0[][5] = {
99 99
 	{0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
100 100
 };
101 101
 
102
-static const u32 ar9340Modes_fast_clock_1p0[][3] = {
102
+static __unused const u32 ar9340Modes_fast_clock_1p0[][3] = {
103 103
 	/*  Addr      5G_HT20     5G_HT40  */
104 104
 	{0x00001030, 0x00000268, 0x000004d0},
105 105
 	{0x00001070, 0x0000018c, 0x00000318},
@@ -112,7 +112,7 @@ static const u32 ar9340Modes_fast_clock_1p0[][3] = {
112 112
 	{0x0000a254, 0x00000898, 0x00001130},
113 113
 };
114 114
 
115
-static const u32 ar9340_1p0_radio_core[][2] = {
115
+static __unused const u32 ar9340_1p0_radio_core[][2] = {
116 116
 	/*  Addr     allmodes  */
117 117
 	{0x00016000, 0x36db6db6},
118 118
 	{0x00016004, 0x6db6db40},
@@ -218,13 +218,13 @@ static const u32 ar9340_1p0_radio_core[][2] = {
218 218
 	{0x000167d4, 0x00000000},
219 219
 };
220 220
 
221
-static const u32 ar9340_1p0_radio_core_40M[][2] = {
221
+static __unused const u32 ar9340_1p0_radio_core_40M[][2] = {
222 222
 	{0x0001609c, 0x02566f3a},
223 223
 	{0x000160ac, 0xa4647c00},
224 224
 	{0x000160b0, 0x01885f5a},
225 225
 };
226 226
 
227
-static const u32 ar9340_1p0_mac_postamble[][5] = {
227
+static __unused const u32 ar9340_1p0_mac_postamble[][5] = {
228 228
 	/* Addr       5G_HT20     5G_HT40     2G_HT40    2G_HT20  */
229 229
 	{0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
230 230
 	{0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
@@ -236,12 +236,12 @@ static const u32 ar9340_1p0_mac_postamble[][5] = {
236 236
 	{0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
237 237
 };
238 238
 
239
-static const u32 ar9340_1p0_soc_postamble[][5] = {
239
+static __unused const u32 ar9340_1p0_soc_postamble[][5] = {
240 240
 	/*   Addr     5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
241 241
 	{0x00007010, 0x00000023, 0x00000023, 0x00000023, 0x00000023},
242 242
 };
243 243
 
244
-static const u32 ar9340_1p0_baseband_postamble[][5] = {
244
+static __unused const u32 ar9340_1p0_baseband_postamble[][5] = {
245 245
 	/*  Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
246 246
 	{0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
247 247
 	{0x00009820, 0x206a022e, 0x206a022e, 0x206a022e, 0x206a022e},
@@ -288,7 +288,7 @@ static const u32 ar9340_1p0_baseband_postamble[][5] = {
288 288
 	{0x0000b284, 0x00000000, 0x00000000, 0x00000150, 0x00000150},
289 289
 };
290 290
 
291
-static const u32 ar9340_1p0_baseband_core[][2] = {
291
+static __unused const u32 ar9340_1p0_baseband_core[][2] = {
292 292
 	/*  Addr     allmodes  */
293 293
 	{0x00009800, 0xafe68e30},
294 294
 	{0x00009804, 0xfd14e000},
@@ -464,7 +464,7 @@ static const u32 ar9340_1p0_baseband_core[][2] = {
464 464
 	{0x0000b420, 0x00000000},
465 465
 };
466 466
 
467
-static const u32 ar9340Modes_high_power_tx_gain_table_1p0[][5] = {
467
+static __unused const u32 ar9340Modes_high_power_tx_gain_table_1p0[][5] = {
468 468
 	/*  Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
469 469
 	{0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
470 470
 	{0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
@@ -537,7 +537,7 @@ static const u32 ar9340Modes_high_power_tx_gain_table_1p0[][5] = {
537 537
 	{0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
538 538
 };
539 539
 
540
-static const u32 ar9340Modes_high_ob_db_tx_gain_table_1p0[][5] = {
540
+static __unused const u32 ar9340Modes_high_ob_db_tx_gain_table_1p0[][5] = {
541 541
 	/*  Addr       5G_HT20    5G_HT40     2G_HT40     2G_HT20  */
542 542
 	{0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
543 543
 	{0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
@@ -609,7 +609,7 @@ static const u32 ar9340Modes_high_ob_db_tx_gain_table_1p0[][5] = {
609 609
 	{0x00016444, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4, 0x03b6d2e4},
610 610
 	{0x00016448, 0x8e481266, 0x8e481266, 0x8e481266, 0x8e481266},
611 611
 };
612
-static const u32 ar9340Modes_ub124_tx_gain_table_1p0[][5] = {
612
+static __unused const u32 ar9340Modes_ub124_tx_gain_table_1p0[][5] = {
613 613
 	/*  Addr      5G_HT20      5G_HT40     2G_HT40    2G_HT20  */
614 614
 	{0x0000a410, 0x000050d8, 0x000050d8, 0x000050d9, 0x000050d9},
615 615
 	{0x0000a500, 0x00002220, 0x00002220, 0x00000000, 0x00000000},
@@ -683,7 +683,7 @@ static const u32 ar9340Modes_ub124_tx_gain_table_1p0[][5] = {
683 683
 };
684 684
 
685 685
 
686
-static const u32 ar9340Common_rx_gain_table_1p0[][2] = {
686
+static __unused const u32 ar9340Common_rx_gain_table_1p0[][2] = {
687 687
 	/*   Addr     allmodes */
688 688
 	{0x0000a000, 0x00010000},
689 689
 	{0x0000a004, 0x00030002},
@@ -943,7 +943,7 @@ static const u32 ar9340Common_rx_gain_table_1p0[][2] = {
943 943
 	{0x0000b1fc, 0x00000196},
944 944
 };
945 945
 
946
-static const u32 ar9340Modes_low_ob_db_tx_gain_table_1p0[][5] = {
946
+static __unused const u32 ar9340Modes_low_ob_db_tx_gain_table_1p0[][5] = {
947 947
 	/*  Addr      5G_HT20     5G_HT40     2G_HT40     2G_HT20  */
948 948
 	{0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
949 949
 	{0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
@@ -1016,7 +1016,7 @@ static const u32 ar9340Modes_low_ob_db_tx_gain_table_1p0[][5] = {
1016 1016
 	{0x00016448, 0x24925266, 0x24925266, 0x24925266, 0x24925266},
1017 1017
 };
1018 1018
 
1019
-static const u32 ar9340Modes_mixed_ob_db_tx_gain_table_1p0[][5] = {
1019
+static __unused const u32 ar9340Modes_mixed_ob_db_tx_gain_table_1p0[][5] = {
1020 1020
 	/*  Addr       5G_HT20     5G_HT40     2G_HT40    2G_HT20  */
1021 1021
 	{0x0000a410, 0x000050d9, 0x000050d9, 0x000050d9, 0x000050d9},
1022 1022
 	{0x0000a500, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
@@ -1089,7 +1089,7 @@ static const u32 ar9340Modes_mixed_ob_db_tx_gain_table_1p0[][5] = {
1089 1089
 	{0x00016448, 0x24927266, 0x24927266, 0x8e482266, 0x8e482266},
1090 1090
 };
1091 1091
 
1092
-static const u32 ar9340_1p0_mac_core[][2] = {
1092
+static __unused const u32 ar9340_1p0_mac_core[][2] = {
1093 1093
 	/*    Addr        allmodes        */
1094 1094
 	{0x00000008, 0x00000000},
1095 1095
 	{0x00000030, 0x00020085},
@@ -1253,7 +1253,7 @@ static const u32 ar9340_1p0_mac_core[][2] = {
1253 1253
 	{0x000083d0, 0x000301ff},
1254 1254
 };
1255 1255
 
1256
-static const u32 ar9340Common_wo_xlna_rx_gain_table_1p0[][2] = {
1256
+static __unused const u32 ar9340Common_wo_xlna_rx_gain_table_1p0[][2] = {
1257 1257
 	/*    Addr        allmodes        */
1258 1258
 	{0x0000a000, 0x00010000},
1259 1259
 	{0x0000a004, 0x00030002},
@@ -1513,7 +1513,7 @@ static const u32 ar9340Common_wo_xlna_rx_gain_table_1p0[][2] = {
1513 1513
 	{0x0000b1fc, 0x00000196},
1514 1514
 };
1515 1515
 
1516
-static const u32 ar9340_1p0_soc_preamble[][2] = {
1516
+static __unused const u32 ar9340_1p0_soc_preamble[][2] = {
1517 1517
 	/*    Addr        allmodes        */
1518 1518
 	{0x000040a4, 0x00a0c1c9},
1519 1519
 	{0x00007008, 0x00000000},

+ 22
- 22
src/drivers/net/ath/ath9k/ar9485_initvals.h View File

@@ -17,7 +17,7 @@
17 17
 #ifndef INITVALS_9485_H
18 18
 #define INITVALS_9485_H
19 19
 
20
-static const u32 ar9485_1_1_mac_core[][2] = {
20
+static __unused const u32 ar9485_1_1_mac_core[][2] = {
21 21
 	/*  Addr       allmodes */
22 22
 	{0x00000008, 0x00000000},
23 23
 	{0x00000030, 0x00020085},
@@ -179,7 +179,7 @@ static const u32 ar9485_1_1_mac_core[][2] = {
179 179
 	{0x000083d0, 0x000301ff},
180 180
 };
181 181
 
182
-static const u32 ar9485_1_1_baseband_core[][2] = {
182
+static __unused const u32 ar9485_1_1_baseband_core[][2] = {
183 183
 	/* Addr       allmodes */
184 184
 	{0x00009800, 0xafe68e30},
185 185
 	{0x00009804, 0xfd14e000},
@@ -316,7 +316,7 @@ static const u32 ar9485_1_1_baseband_core[][2] = {
316 316
 	{0x0000a7dc, 0x00000000},
317 317
 };
318 318
 
319
-static const u32 ar9485Common_1_1[][2] = {
319
+static __unused const u32 ar9485Common_1_1[][2] = {
320 320
 	/*  Addr      allmodes */
321 321
 	{0x00007010, 0x00000022},
322 322
 	{0x00007020, 0x00000000},
@@ -324,7 +324,7 @@ static const u32 ar9485Common_1_1[][2] = {
324 324
 	{0x00007038, 0x000004c2},
325 325
 };
326 326
 
327
-static const u32 ar9485_1_1_baseband_postamble[][5] = {
327
+static __unused const u32 ar9485_1_1_baseband_postamble[][5] = {
328 328
 	/* Addr       5G_HT20        5G_HT40       2G_HT40       2G_HT20 */
329 329
 	{0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8005, 0xd00a8005},
330 330
 	{0x00009820, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e},
@@ -369,7 +369,7 @@ static const u32 ar9485_1_1_baseband_postamble[][5] = {
369 369
 	{0x0000be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
370 370
 };
371 371
 
372
-static const u32 ar9485Modes_high_ob_db_tx_gain_1_1[][5] = {
372
+static __unused const u32 ar9485Modes_high_ob_db_tx_gain_1_1[][5] = {
373 373
 	/* Addr        5G_HT20       5G_HT40       2G_HT40       2G_HT20 */
374 374
 	{0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
375 375
 	{0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
@@ -442,7 +442,7 @@ static const u32 ar9485Modes_high_ob_db_tx_gain_1_1[][5] = {
442 442
 	{0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
443 443
 };
444 444
 
445
-static const u32 ar9485_modes_lowest_ob_db_tx_gain_1_1[][5] = {
445
+static __unused const u32 ar9485_modes_lowest_ob_db_tx_gain_1_1[][5] = {
446 446
 	/* Addr        5G_HT20       5G_HT40       2G_HT40       2G_HT20  */
447 447
 	{0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
448 448
 	{0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
@@ -515,7 +515,7 @@ static const u32 ar9485_modes_lowest_ob_db_tx_gain_1_1[][5] = {
515 515
 	{0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
516 516
 };
517 517
 
518
-static const u32 ar9485_1_1_radio_postamble[][2] = {
518
+static __unused const u32 ar9485_1_1_radio_postamble[][2] = {
519 519
 	/* Addr        allmodes */
520 520
 	{0x0001609c, 0x0b283f31},
521 521
 	{0x000160ac, 0x24611800},
@@ -524,7 +524,7 @@ static const u32 ar9485_1_1_radio_postamble[][2] = {
524 524
 	{0x00016140, 0x10804008},
525 525
 };
526 526
 
527
-static const u32 ar9485_1_1_mac_postamble[][5] = {
527
+static __unused const u32 ar9485_1_1_mac_postamble[][5] = {
528 528
 	/* Addr        5G_HT20       5G_HT40       2G_HT40       2G_HT20 */
529 529
 	{0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160},
530 530
 	{0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c},
@@ -536,7 +536,7 @@ static const u32 ar9485_1_1_mac_postamble[][5] = {
536 536
 	{0x00008318, 0x00003e80, 0x00007d00, 0x00006880, 0x00003440},
537 537
 };
538 538
 
539
-static const u32 ar9485_1_1_radio_core[][2] = {
539
+static __unused const u32 ar9485_1_1_radio_core[][2] = {
540 540
 	/* Addr        allmodes */
541 541
 	{0x00016000, 0x36db6db6},
542 542
 	{0x00016004, 0x6db6db40},
@@ -601,14 +601,14 @@ static const u32 ar9485_1_1_radio_core[][2] = {
601 601
 	{0x00016c44, 0x12000000},
602 602
 };
603 603
 
604
-static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = {
604
+static __unused const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = {
605 605
 	/* Addr        allmodes */
606 606
 	{0x00018c00, 0x10052e5e},
607 607
 	{0x00018c04, 0x000801d8},
608 608
 	{0x00018c08, 0x0000080c},
609 609
 };
610 610
 
611
-static const u32 ar9485Modes_high_power_tx_gain_1_1[][5] = {
611
+static __unused const u32 ar9485Modes_high_power_tx_gain_1_1[][5] = {
612 612
 	/* Addr        5G_HT20       5G_HT40       2G_HT40       2G_HT20 */
613 613
 	{0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
614 614
 	{0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
@@ -681,7 +681,7 @@ static const u32 ar9485Modes_high_power_tx_gain_1_1[][5] = {
681 681
 	{0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
682 682
 };
683 683
 
684
-static const u32 ar9485_1_1[][2] = {
684
+static __unused const u32 ar9485_1_1[][2] = {
685 685
 	/* Addr        allmodes */
686 686
 	{0x0000a580, 0x00000000},
687 687
 	{0x0000a584, 0x00000000},
@@ -701,7 +701,7 @@ static const u32 ar9485_1_1[][2] = {
701 701
 	{0x0000a5bc, 0x00000000},
702 702
 };
703 703
 
704
-static const u32 ar9485_modes_green_ob_db_tx_gain_1_1[][5] = {
704
+static __unused const u32 ar9485_modes_green_ob_db_tx_gain_1_1[][5] = {
705 705
 	/* Addr        5G_HT20       5G_HT40       2G_HT40       2G_HT20 */
706 706
 	{0x000098bc, 0x00000003, 0x00000003, 0x00000003, 0x00000003},
707 707
 	{0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
@@ -774,14 +774,14 @@ static const u32 ar9485_modes_green_ob_db_tx_gain_1_1[][5] = {
774 774
 	{0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
775 775
 };
776 776
 
777
-static const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
777
+static __unused const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
778 778
 	/* Addr        allmodes */
779 779
 	{0x00018c00, 0x10013e5e},
780 780
 	{0x00018c04, 0x000801d8},
781 781
 	{0x00018c08, 0x0000080c},
782 782
 };
783 783
 
784
-static const u32 ar9485_1_1_soc_preamble[][2] = {
784
+static __unused const u32 ar9485_1_1_soc_preamble[][2] = {
785 785
 	/* Addr        allmodes */
786 786
 	{0x00004014, 0xba280400},
787 787
 	{0x00004090, 0x00aa10aa},
@@ -793,14 +793,14 @@ static const u32 ar9485_1_1_soc_preamble[][2] = {
793 793
 	{0x00007048, 0x00000002},
794 794
 };
795 795
 
796
-static const u32 ar9485_1_1_baseband_core_txfir_coeff_japan_2484[][2] = {
796
+static __unused const u32 ar9485_1_1_baseband_core_txfir_coeff_japan_2484[][2] = {
797 797
 	/* Addr        allmodes */
798 798
 	{0x0000a398, 0x00000000},
799 799
 	{0x0000a39c, 0x6f7f0301},
800 800
 	{0x0000a3a0, 0xca9228ee},
801 801
 };
802 802
 
803
-static const u32 ar9485Modes_low_ob_db_tx_gain_1_1[][5] = {
803
+static __unused const u32 ar9485Modes_low_ob_db_tx_gain_1_1[][5] = {
804 804
 	/* Addr        5G_HT20       5G_HT40       2G_HT40       2G_HT20  */
805 805
 	{0x000098bc, 0x00000002, 0x00000002, 0x00000002, 0x00000002},
806 806
 	{0x0000a410, 0x000050d9, 0x000050d9, 0x000050d8, 0x000050d8},
@@ -873,21 +873,21 @@ static const u32 ar9485Modes_low_ob_db_tx_gain_1_1[][5] = {
873 873
 	{0x00016048, 0x6c924260, 0x6c924260, 0x6c924260, 0x6c924260},
874 874
 };
875 875
 
876
-static const u32 ar9485_fast_clock_1_1_baseband_postamble[][3] = {
876
+static __unused const u32 ar9485_fast_clock_1_1_baseband_postamble[][3] = {
877 877
 	/* Addr        5G_HT2        5G_HT40  */
878 878
 	{0x00009e00, 0x03721821, 0x03721821},
879 879
 	{0x0000a230, 0x0000400b, 0x00004016},
880 880
 	{0x0000a254, 0x00000898, 0x00001130},
881 881
 };
882 882
 
883
-static const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
883
+static __unused const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
884 884
 	/* Addr        allmodes  */
885 885
 	{0x00018c00, 0x10012e5e},
886 886
 	{0x00018c04, 0x000801d8},
887 887
 	{0x00018c08, 0x0000080c},
888 888
 };
889 889
 
890
-static const u32 ar9485_common_rx_gain_1_1[][2] = {
890
+static __unused const u32 ar9485_common_rx_gain_1_1[][2] = {
891 891
 	/* Addr        allmodes */
892 892
 	{0x0000a000, 0x00010000},
893 893
 	{0x0000a004, 0x00030002},
@@ -1019,14 +1019,14 @@ static const u32 ar9485_common_rx_gain_1_1[][2] = {
1019 1019
 	{0x0000a1fc, 0x00000296},
1020 1020
 };
1021 1021
 
1022
-static const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = {
1022
+static __unused const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = {
1023 1023
 	/* Addr        allmodes */
1024 1024
 	{0x00018c00, 0x10053e5e},
1025 1025
 	{0x00018c04, 0x000801d8},
1026 1026
 	{0x00018c08, 0x0000080c},
1027 1027
 };
1028 1028
 
1029
-static const u32 ar9485Common_wo_xlna_rx_gain_1_1[][2] = {
1029
+static __unused const u32 ar9485Common_wo_xlna_rx_gain_1_1[][2] = {
1030 1030
 	/* Addr        allmodes */
1031 1031
 	{0x0000a000, 0x00060005},
1032 1032
 	{0x0000a004, 0x00810080},

+ 2
- 1
src/drivers/net/ath/ath9k/ath9k_init.c View File

@@ -22,6 +22,7 @@ FILE_LICENCE ( BSD2 );
22 22
 #include <ipxe/malloc.h>
23 23
 #include <ipxe/pci_io.h>
24 24
 #include <ipxe/pci.h>
25
+#include <ipxe/ethernet.h>
25 26
 
26 27
 #include "ath9k.h"
27 28
 
@@ -349,7 +350,7 @@ static void ath9k_init_misc(struct ath_softc *sc)
349 350
 	ath9k_hw_set_diversity(sc->sc_ah, 1);
350 351
 	sc->rx.defant = ath9k_hw_getdefantenna(sc->sc_ah);
351 352
 
352
-	memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
353
+	memcpy(common->bssidmask, eth_broadcast, ETH_ALEN);
353 354
 }
354 355
 
355 356
 static int ath9k_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,

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