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@@ -16,7 +16,7 @@
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FILE_LICENCE ( BSD2 );
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-static const u32 ar9280Modes_9280_2[][6] = {
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19
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+static __unused const u32 ar9280Modes_9280_2[][6] = {
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20
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20
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{0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0},
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21
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21
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{0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0},
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22
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22
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{0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180},
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@@ -65,7 +65,7 @@ static const u32 ar9280Modes_9280_2[][6] = {
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65
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65
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{0x00007894, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000, 0x5a508000},
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66
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66
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};
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67
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67
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68
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-static const u32 ar9280Common_9280_2[][2] = {
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68
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+static __unused const u32 ar9280Common_9280_2[][2] = {
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69
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69
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/* Addr allmodes */
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70
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70
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{0x0000000c, 0x00000000},
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71
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71
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{0x00000030, 0x00020015},
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@@ -409,7 +409,7 @@ static const u32 ar9280Common_9280_2[][2] = {
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409
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409
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{0x00007898, 0x2a850160},
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410
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410
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};
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411
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411
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412
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-static const u32 ar9280Modes_fast_clock_9280_2[][3] = {
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412
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+static __unused const u32 ar9280Modes_fast_clock_9280_2[][3] = {
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413
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413
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/* Addr 5G_HT20 5G_HT40 */
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414
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414
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{0x00001030, 0x00000268, 0x000004d0},
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415
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415
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{0x00001070, 0x0000018c, 0x00000318},
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@@ -426,7 +426,7 @@ static const u32 ar9280Modes_fast_clock_9280_2[][3] = {
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426
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426
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{0x00009918, 0x0000000b, 0x00000016},
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427
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427
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};
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428
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428
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429
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-static const u32 ar9280Modes_backoff_23db_rxgain_9280_2[][6] = {
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429
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+static __unused const u32 ar9280Modes_backoff_23db_rxgain_9280_2[][6] = {
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430
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430
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{0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290},
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431
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431
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{0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300},
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432
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432
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{0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304},
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@@ -559,7 +559,7 @@ static const u32 ar9280Modes_backoff_23db_rxgain_9280_2[][6] = {
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559
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559
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{0x0000a848, 0x00001066, 0x00001066, 0x00001055, 0x00001055, 0x00001055},
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560
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560
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};
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561
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561
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562
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-static const u32 ar9280Modes_original_rxgain_9280_2[][6] = {
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562
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+static __unused const u32 ar9280Modes_original_rxgain_9280_2[][6] = {
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563
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563
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{0x00009a00, 0x00008184, 0x00008184, 0x00008000, 0x00008000, 0x00008000},
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564
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564
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{0x00009a04, 0x00008188, 0x00008188, 0x00008000, 0x00008000, 0x00008000},
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565
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565
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{0x00009a08, 0x0000818c, 0x0000818c, 0x00008000, 0x00008000, 0x00008000},
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@@ -692,7 +692,7 @@ static const u32 ar9280Modes_original_rxgain_9280_2[][6] = {
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692
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692
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{0x0000a848, 0x00001066, 0x00001066, 0x00001063, 0x00001063, 0x00001063},
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693
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693
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};
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694
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694
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695
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-static const u32 ar9280Modes_backoff_13db_rxgain_9280_2[][6] = {
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695
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+static __unused const u32 ar9280Modes_backoff_13db_rxgain_9280_2[][6] = {
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696
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696
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{0x00009a00, 0x00008184, 0x00008184, 0x00000290, 0x00000290, 0x00000290},
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697
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697
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{0x00009a04, 0x00008188, 0x00008188, 0x00000300, 0x00000300, 0x00000300},
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698
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698
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{0x00009a08, 0x0000818c, 0x0000818c, 0x00000304, 0x00000304, 0x00000304},
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@@ -825,7 +825,7 @@ static const u32 ar9280Modes_backoff_13db_rxgain_9280_2[][6] = {
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825
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825
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{0x0000a848, 0x00001066, 0x00001066, 0x0000105a, 0x0000105a, 0x0000105a},
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826
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826
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};
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827
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827
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828
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-static const u32 ar9280Modes_high_power_tx_gain_9280_2[][6] = {
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828
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+static __unused const u32 ar9280Modes_high_power_tx_gain_9280_2[][6] = {
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829
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829
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{0x0000a274, 0x0a19e652, 0x0a19e652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652},
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830
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830
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{0x0000a27c, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce, 0x050739ce},
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831
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831
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{0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
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@@ -859,7 +859,7 @@ static const u32 ar9280Modes_high_power_tx_gain_9280_2[][6] = {
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859
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859
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{0x00007844, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480, 0xf258a480},
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860
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860
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};
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861
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861
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862
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-static const u32 ar9280Modes_original_tx_gain_9280_2[][6] = {
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862
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+static __unused const u32 ar9280Modes_original_tx_gain_9280_2[][6] = {
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863
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863
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{0x0000a274, 0x0a19c652, 0x0a19c652, 0x0a1aa652, 0x0a1aa652, 0x0a1aa652},
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864
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864
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{0x0000a27c, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce, 0x050701ce},
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865
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865
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{0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
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@@ -893,7 +893,7 @@ static const u32 ar9280Modes_original_tx_gain_9280_2[][6] = {
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893
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893
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{0x00007844, 0x92592480, 0x92592480, 0x92592480, 0x92592480, 0x92592480},
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894
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894
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};
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895
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895
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896
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-static const u32 ar9280PciePhy_clkreq_off_L1_9280[][2] = {
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896
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+static __unused const u32 ar9280PciePhy_clkreq_off_L1_9280[][2] = {
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897
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897
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/* Addr allmodes */
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898
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898
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{0x00004040, 0x9248fd00},
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899
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899
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{0x00004040, 0x24924924},
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@@ -907,7 +907,7 @@ static const u32 ar9280PciePhy_clkreq_off_L1_9280[][2] = {
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907
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907
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{0x00004044, 0x00000000},
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908
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908
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};
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909
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909
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910
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-static const u32 ar9280PciePhy_clkreq_always_on_L1_9280[][2] = {
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910
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+static __unused const u32 ar9280PciePhy_clkreq_always_on_L1_9280[][2] = {
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911
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911
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/* Addr allmodes */
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912
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912
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{0x00004040, 0x9248fd00},
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913
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913
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{0x00004040, 0x24924924},
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@@ -921,7 +921,7 @@ static const u32 ar9280PciePhy_clkreq_always_on_L1_9280[][2] = {
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921
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921
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{0x00004044, 0x00000000},
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922
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922
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};
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923
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923
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924
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-static const u32 ar9285PciePhy_clkreq_always_on_L1_9285[][2] = {
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924
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+static __unused const u32 ar9285PciePhy_clkreq_always_on_L1_9285[][2] = {
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925
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925
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/* Addr allmodes */
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926
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926
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{0x00004040, 0x9248fd00},
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927
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927
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{0x00004040, 0x24924924},
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@@ -935,7 +935,7 @@ static const u32 ar9285PciePhy_clkreq_always_on_L1_9285[][2] = {
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935
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935
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{0x00004044, 0x00000000},
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936
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936
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};
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937
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937
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938
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-static const u32 ar9285PciePhy_clkreq_off_L1_9285[][2] = {
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938
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+static __unused const u32 ar9285PciePhy_clkreq_off_L1_9285[][2] = {
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939
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939
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/* Addr allmodes */
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940
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940
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{0x00004040, 0x9248fd00},
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941
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941
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{0x00004040, 0x24924924},
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@@ -949,7 +949,7 @@ static const u32 ar9285PciePhy_clkreq_off_L1_9285[][2] = {
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949
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949
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{0x00004044, 0x00000000},
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950
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950
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};
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951
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951
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952
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-static const u32 ar9285Modes_9285_1_2[][6] = {
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952
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+static __unused const u32 ar9285Modes_9285_1_2[][6] = {
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953
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953
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{0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0},
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954
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954
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{0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0},
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955
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955
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{0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180},
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@@ -1254,7 +1254,7 @@ static const u32 ar9285Modes_9285_1_2[][6] = {
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1254
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1254
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{0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e},
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1255
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1255
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};
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1256
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1256
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1257
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-static const u32 ar9285Common_9285_1_2[][2] = {
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1257
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+static __unused const u32 ar9285Common_9285_1_2[][2] = {
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1258
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1258
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/* Addr allmodes */
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1259
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1259
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{0x0000000c, 0x00000000},
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1260
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1260
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{0x00000030, 0x00020045},
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@@ -1574,7 +1574,7 @@ static const u32 ar9285Common_9285_1_2[][2] = {
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1574
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1574
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{0x00007870, 0x10142c00},
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1575
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1575
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};
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1576
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1576
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1577
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-static const u32 ar9285Modes_high_power_tx_gain_9285_1_2[][6] = {
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1577
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+static __unused const u32 ar9285Modes_high_power_tx_gain_9285_1_2[][6] = {
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1578
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1578
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{0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
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1579
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1579
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{0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200, 0x00000000},
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1580
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1580
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{0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201, 0x00000000},
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@@ -1614,7 +1614,7 @@ static const u32 ar9285Modes_high_power_tx_gain_9285_1_2[][6] = {
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1614
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1614
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{0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7},
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1615
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1615
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};
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1616
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1616
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1617
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-static const u32 ar9285Modes_original_tx_gain_9285_1_2[][6] = {
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1617
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+static __unused const u32 ar9285Modes_original_tx_gain_9285_1_2[][6] = {
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1618
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1618
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{0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
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1619
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1619
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{0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000},
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1620
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1620
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{0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000},
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@@ -1654,7 +1654,7 @@ static const u32 ar9285Modes_original_tx_gain_9285_1_2[][6] = {
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1654
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1654
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{0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c},
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1655
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1655
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};
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1656
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1656
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1657
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-static const u32 ar9285Modes_XE2_0_normal_power[][6] = {
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1657
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+static __unused const u32 ar9285Modes_XE2_0_normal_power[][6] = {
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1658
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1658
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{0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
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1659
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1659
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{0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000},
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1660
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1660
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{0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000},
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@@ -1694,7 +1694,7 @@ static const u32 ar9285Modes_XE2_0_normal_power[][6] = {
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1694
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1694
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{0x0000a3e0, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c, 0x0000039c},
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1695
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1695
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};
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1696
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1696
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1697
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-static const u32 ar9285Modes_XE2_0_high_power[][6] = {
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1697
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+static __unused const u32 ar9285Modes_XE2_0_high_power[][6] = {
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1698
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1698
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{0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
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1699
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1699
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{0x0000a304, 0x00000000, 0x00000000, 0x00006200, 0x00006200, 0x00000000},
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1700
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1700
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{0x0000a308, 0x00000000, 0x00000000, 0x00008201, 0x00008201, 0x00000000},
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@@ -1734,7 +1734,7 @@ static const u32 ar9285Modes_XE2_0_high_power[][6] = {
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1734
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1734
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{0x0000a3e0, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7, 0x000000e7},
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1735
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1735
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};
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1736
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1736
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1737
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-static const u32 ar9285PciePhy_clkreq_always_on_L1_9285_1_2[][2] = {
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1737
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+static __unused const u32 ar9285PciePhy_clkreq_always_on_L1_9285_1_2[][2] = {
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1738
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1738
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/* Addr allmodes */
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1739
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1739
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{0x00004040, 0x9248fd00},
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1740
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1740
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{0x00004040, 0x24924924},
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@@ -1748,7 +1748,7 @@ static const u32 ar9285PciePhy_clkreq_always_on_L1_9285_1_2[][2] = {
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1748
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1748
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{0x00004044, 0x00000000},
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1749
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1749
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};
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1750
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1750
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1751
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-static const u32 ar9285PciePhy_clkreq_off_L1_9285_1_2[][2] = {
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1751
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+static __unused const u32 ar9285PciePhy_clkreq_off_L1_9285_1_2[][2] = {
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1752
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1752
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/* Addr allmodes */
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1753
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1753
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{0x00004040, 0x9248fd00},
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1754
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1754
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{0x00004040, 0x24924924},
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@@ -1762,7 +1762,7 @@ static const u32 ar9285PciePhy_clkreq_off_L1_9285_1_2[][2] = {
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1762
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1762
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{0x00004044, 0x00000000},
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1763
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1763
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};
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1764
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1764
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1765
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-static const u32 ar9287Modes_9287_1_1[][6] = {
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1765
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+static __unused const u32 ar9287Modes_9287_1_1[][6] = {
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1766
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1766
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{0x00001030, 0x00000000, 0x00000000, 0x000002c0, 0x00000160, 0x000001e0},
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1767
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1767
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{0x00001070, 0x00000000, 0x00000000, 0x00000318, 0x0000018c, 0x000001e0},
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1768
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1768
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{0x000010b0, 0x00000000, 0x00000000, 0x00007c70, 0x00003e38, 0x00001180},
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@@ -1808,7 +1808,7 @@ static const u32 ar9287Modes_9287_1_1[][6] = {
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1808
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1808
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{0x0000a3d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
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1809
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1809
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};
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1810
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1810
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1811
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-static const u32 ar9287Common_9287_1_1[][2] = {
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1811
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+static __unused const u32 ar9287Common_9287_1_1[][2] = {
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1812
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1812
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/* Addr allmodes */
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1813
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1813
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{0x0000000c, 0x00000000},
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1814
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1814
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{0x00000030, 0x00020015},
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@@ -2177,21 +2177,21 @@ static const u32 ar9287Common_9287_1_1[][2] = {
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2177
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2177
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{0x000078b8, 0x2a850160},
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2178
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2178
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};
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2179
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2179
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2180
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-static const u32 ar9287Common_normal_cck_fir_coeff_9287_1_1[][2] = {
|
|
2180
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+static __unused const u32 ar9287Common_normal_cck_fir_coeff_9287_1_1[][2] = {
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2181
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2181
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/* Addr allmodes */
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2182
|
2182
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{0x0000a1f4, 0x00fffeff},
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2183
|
2183
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{0x0000a1f8, 0x00f5f9ff},
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2184
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2184
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{0x0000a1fc, 0xb79f6427},
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2185
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2185
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};
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2186
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2186
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2187
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-static const u32 ar9287Common_japan_2484_cck_fir_coeff_9287_1_1[][2] = {
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|
2187
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+static __unused const u32 ar9287Common_japan_2484_cck_fir_coeff_9287_1_1[][2] = {
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2188
|
2188
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/* Addr allmodes */
|
2189
|
2189
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{0x0000a1f4, 0x00000000},
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2190
|
2190
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{0x0000a1f8, 0xefff0301},
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2191
|
2191
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{0x0000a1fc, 0xca9228ee},
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2192
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2192
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};
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2193
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2193
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|
2194
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-static const u32 ar9287Modes_tx_gain_9287_1_1[][6] = {
|
|
2194
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+static __unused const u32 ar9287Modes_tx_gain_9287_1_1[][6] = {
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2195
|
2195
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{0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
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2196
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2196
|
{0x0000a304, 0x00000000, 0x00000000, 0x00004002, 0x00004002, 0x00004002},
|
2197
|
2197
|
{0x0000a308, 0x00000000, 0x00000000, 0x00008004, 0x00008004, 0x00008004},
|
|
@@ -2239,7 +2239,7 @@ static const u32 ar9287Modes_tx_gain_9287_1_1[][6] = {
|
2239
|
2239
|
{0x0000a274, 0x0a180000, 0x0a180000, 0x0a1aa000, 0x0a1aa000, 0x0a1aa000},
|
2240
|
2240
|
};
|
2241
|
2241
|
|
2242
|
|
-static const u32 ar9287Modes_rx_gain_9287_1_1[][6] = {
|
|
2242
|
+static __unused const u32 ar9287Modes_rx_gain_9287_1_1[][6] = {
|
2243
|
2243
|
{0x00009a00, 0x00000000, 0x00000000, 0x0000a120, 0x0000a120, 0x0000a120},
|
2244
|
2244
|
{0x00009a04, 0x00000000, 0x00000000, 0x0000a124, 0x0000a124, 0x0000a124},
|
2245
|
2245
|
{0x00009a08, 0x00000000, 0x00000000, 0x0000a128, 0x0000a128, 0x0000a128},
|
|
@@ -2500,7 +2500,7 @@ static const u32 ar9287Modes_rx_gain_9287_1_1[][6] = {
|
2500
|
2500
|
{0x0000a848, 0x00000000, 0x00000000, 0x00001067, 0x00001067, 0x00001067},
|
2501
|
2501
|
};
|
2502
|
2502
|
|
2503
|
|
-static const u32 ar9287PciePhy_clkreq_always_on_L1_9287_1_1[][2] = {
|
|
2503
|
+static __unused const u32 ar9287PciePhy_clkreq_always_on_L1_9287_1_1[][2] = {
|
2504
|
2504
|
/* Addr allmodes */
|
2505
|
2505
|
{0x00004040, 0x9248fd00},
|
2506
|
2506
|
{0x00004040, 0x24924924},
|
|
@@ -2514,7 +2514,7 @@ static const u32 ar9287PciePhy_clkreq_always_on_L1_9287_1_1[][2] = {
|
2514
|
2514
|
{0x00004044, 0x00000000},
|
2515
|
2515
|
};
|
2516
|
2516
|
|
2517
|
|
-static const u32 ar9287PciePhy_clkreq_off_L1_9287_1_1[][2] = {
|
|
2517
|
+static __unused const u32 ar9287PciePhy_clkreq_off_L1_9287_1_1[][2] = {
|
2518
|
2518
|
/* Addr allmodes */
|
2519
|
2519
|
{0x00004040, 0x9248fd00},
|
2520
|
2520
|
{0x00004040, 0x24924924},
|
|
@@ -2528,7 +2528,7 @@ static const u32 ar9287PciePhy_clkreq_off_L1_9287_1_1[][2] = {
|
2528
|
2528
|
{0x00004044, 0x00000000},
|
2529
|
2529
|
};
|
2530
|
2530
|
|
2531
|
|
-static const u32 ar9271Modes_9271[][6] = {
|
|
2531
|
+static __unused const u32 ar9271Modes_9271[][6] = {
|
2532
|
2532
|
{0x00001030, 0x00000230, 0x00000460, 0x000002c0, 0x00000160, 0x000001e0},
|
2533
|
2533
|
{0x00001070, 0x00000168, 0x000002d0, 0x00000318, 0x0000018c, 0x000001e0},
|
2534
|
2534
|
{0x000010b0, 0x00000e60, 0x00001cc0, 0x00007c70, 0x00003e38, 0x00001180},
|
|
@@ -2834,7 +2834,7 @@ static const u32 ar9271Modes_9271[][6] = {
|
2834
|
2834
|
{0x0000a358, 0x7999aa02, 0x7999aa02, 0x7999aa0e, 0x7999aa0e, 0x7999aa0e},
|
2835
|
2835
|
};
|
2836
|
2836
|
|
2837
|
|
-static const u32 ar9271Common_9271[][2] = {
|
|
2837
|
+static __unused const u32 ar9271Common_9271[][2] = {
|
2838
|
2838
|
/* Addr allmodes */
|
2839
|
2839
|
{0x0000000c, 0x00000000},
|
2840
|
2840
|
{0x00000030, 0x00020045},
|
|
@@ -3163,26 +3163,26 @@ static const u32 ar9271Common_9271[][2] = {
|
3163
|
3163
|
{0x0000d384, 0xf3307ff0},
|
3164
|
3164
|
};
|
3165
|
3165
|
|
3166
|
|
-static const u32 ar9271Common_normal_cck_fir_coeff_9271[][2] = {
|
|
3166
|
+static __unused const u32 ar9271Common_normal_cck_fir_coeff_9271[][2] = {
|
3167
|
3167
|
/* Addr allmodes */
|
3168
|
3168
|
{0x0000a1f4, 0x00fffeff},
|
3169
|
3169
|
{0x0000a1f8, 0x00f5f9ff},
|
3170
|
3170
|
{0x0000a1fc, 0xb79f6427},
|
3171
|
3171
|
};
|
3172
|
3172
|
|
3173
|
|
-static const u32 ar9271Common_japan_2484_cck_fir_coeff_9271[][2] = {
|
|
3173
|
+static __unused const u32 ar9271Common_japan_2484_cck_fir_coeff_9271[][2] = {
|
3174
|
3174
|
/* Addr allmodes */
|
3175
|
3175
|
{0x0000a1f4, 0x00000000},
|
3176
|
3176
|
{0x0000a1f8, 0xefff0301},
|
3177
|
3177
|
{0x0000a1fc, 0xca9228ee},
|
3178
|
3178
|
};
|
3179
|
3179
|
|
3180
|
|
-static const u32 ar9271Modes_9271_1_0_only[][6] = {
|
|
3180
|
+static __unused const u32 ar9271Modes_9271_1_0_only[][6] = {
|
3181
|
3181
|
{0x00009910, 0x30002311, 0x30002311, 0x30002311, 0x30002311, 0x30002311},
|
3182
|
3182
|
{0x00009828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001},
|
3183
|
3183
|
};
|
3184
|
3184
|
|
3185
|
|
-static const u32 ar9271Modes_9271_ANI_reg[][6] = {
|
|
3185
|
+static __unused const u32 ar9271Modes_9271_ANI_reg[][6] = {
|
3186
|
3186
|
{0x00009850, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2, 0x6d4000e2},
|
3187
|
3187
|
{0x0000985c, 0x3139605e, 0x3139605e, 0x3137605e, 0x3137605e, 0x3139605e},
|
3188
|
3188
|
{0x00009858, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e, 0x7ec84d2e},
|
|
@@ -3193,7 +3193,7 @@ static const u32 ar9271Modes_9271_ANI_reg[][6] = {
|
3193
|
3193
|
{0x000099c0, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
|
3194
|
3194
|
};
|
3195
|
3195
|
|
3196
|
|
-static const u32 ar9271Modes_normal_power_tx_gain_9271[][6] = {
|
|
3196
|
+static __unused const u32 ar9271Modes_normal_power_tx_gain_9271[][6] = {
|
3197
|
3197
|
{0x0000a300, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
3198
|
3198
|
{0x0000a304, 0x00000000, 0x00000000, 0x00009200, 0x00009200, 0x00000000},
|
3199
|
3199
|
{0x0000a308, 0x00000000, 0x00000000, 0x00010208, 0x00010208, 0x00000000},
|
|
@@ -3229,7 +3229,7 @@ static const u32 ar9271Modes_normal_power_tx_gain_9271[][6] = {
|
3229
|
3229
|
{0x0000a3e0, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd, 0x000003bd},
|
3230
|
3230
|
};
|
3231
|
3231
|
|
3232
|
|
-static const u32 ar9271Modes_high_power_tx_gain_9271[][6] = {
|
|
3232
|
+static __unused const u32 ar9271Modes_high_power_tx_gain_9271[][6] = {
|
3233
|
3233
|
{0x0000a300, 0x00000000, 0x00000000, 0x00010000, 0x00010000, 0x00000000},
|
3234
|
3234
|
{0x0000a304, 0x00000000, 0x00000000, 0x00016200, 0x00016200, 0x00000000},
|
3235
|
3235
|
{0x0000a308, 0x00000000, 0x00000000, 0x00018201, 0x00018201, 0x00000000},
|