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[igb] Add igb driver

This commit adds an igb (Intel GigaBit) driver based on Intel source
code available at:

    http://sourceforge.net/projects/e1000/

which is upstream source for the Linux kernel e1000 drivers, and
should support some PCIe e1000 variants.

Signed-off-by: Marty Connor <mdc@etherboot.org>
tags/v1.20.1
Marty Connor преди 14 години
родител
ревизия
5e829de055

+ 1
- 0
src/Makefile Целия файл

@@ -60,6 +60,7 @@ SRCDIRS		+= drivers/bus
60 60
 SRCDIRS		+= drivers/net
61 61
 SRCDIRS		+= drivers/net/e1000
62 62
 SRCDIRS		+= drivers/net/e1000e
63
+SRCDIRS		+= drivers/net/igb
63 64
 SRCDIRS		+= drivers/net/phantom
64 65
 SRCDIRS		+= drivers/net/rtl818x
65 66
 SRCDIRS		+= drivers/net/ath5k

+ 32
- 0
src/drivers/net/igb/igb.c Целия файл

@@ -0,0 +1,32 @@
1
+/*******************************************************************************
2
+
3
+  Intel PRO/1000 Linux driver
4
+  Copyright(c) 1999 - 2008 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  Linux NICS <linux.nics@intel.com>
24
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
+
27
+*******************************************************************************/
28
+
29
+FILE_LICENCE ( GPL2_ONLY );
30
+
31
+REQUIRE_OBJECT(igb_main);
32
+REQUIRE_OBJECT(igb_82575);

+ 324
- 0
src/drivers/net/igb/igb.h Целия файл

@@ -0,0 +1,324 @@
1
+/*******************************************************************************
2
+
3
+  Intel(R) Gigabit Ethernet Linux driver
4
+  Copyright(c) 2007-2009 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
+
26
+*******************************************************************************/
27
+
28
+FILE_LICENCE ( GPL2_ONLY );
29
+
30
+/* Linux PRO/1000 Ethernet Driver main header file */
31
+
32
+#ifndef _IGB_H_
33
+#define _IGB_H_
34
+
35
+#include "igb_api.h"
36
+
37
+extern int igb_probe ( struct pci_device *pdev, const struct pci_device_id *ent);
38
+extern void igb_remove ( struct pci_device *pdev );
39
+
40
+struct igb_adapter;
41
+
42
+/* Interrupt defines */
43
+#define IGB_START_ITR                    648 /* ~6000 ints/sec */
44
+
45
+/* Interrupt modes, as used by the IntMode paramter */
46
+#define IGB_INT_MODE_LEGACY                0
47
+#define IGB_INT_MODE_MSI                   1
48
+#define IGB_INT_MODE_MSIX                  2
49
+
50
+#define HW_PERF
51
+/* TX/RX descriptor defines */
52
+#define IGB_DEFAULT_TXD                  256
53
+#define IGB_MIN_TXD                       80
54
+#define IGB_MAX_TXD                     4096
55
+
56
+#define IGB_DEFAULT_RXD                  256
57
+#define IGB_MIN_RXD                       80
58
+#define IGB_MAX_RXD                     4096
59
+
60
+#define IGB_MIN_ITR_USECS                 10 /* 100k irq/sec */
61
+#define IGB_MAX_ITR_USECS               8191 /* 120  irq/sec */
62
+
63
+#define NON_Q_VECTORS                      1
64
+#define MAX_Q_VECTORS                      8
65
+
66
+/* Transmit and receive queues */
67
+#define IGB_MAX_RX_QUEUES                  (adapter->vfs_allocated_count ? 2 : \
68
+                                           (hw->mac.type > e1000_82575 ? 8 : 4))
69
+#define IGB_ABS_MAX_TX_QUEUES              8
70
+#define IGB_MAX_TX_QUEUES                  IGB_MAX_RX_QUEUES
71
+
72
+#define IGB_MAX_VF_MC_ENTRIES              30
73
+#define IGB_MAX_VF_FUNCTIONS               8
74
+#define IGB_MAX_VFTA_ENTRIES               128
75
+#define IGB_MAX_UTA_ENTRIES                128
76
+#define MAX_EMULATION_MAC_ADDRS            16
77
+#define OUI_LEN                            3
78
+
79
+struct vf_data_storage {
80
+	unsigned char vf_mac_addresses[ETH_ALEN];
81
+	u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
82
+	u16 num_vf_mc_hashes;
83
+	u16 default_vf_vlan_id;
84
+	u16 vlans_enabled;
85
+	unsigned char em_mac_addresses[MAX_EMULATION_MAC_ADDRS * ETH_ALEN];
86
+	u32 uta_table_copy[IGB_MAX_UTA_ENTRIES];
87
+	u32 flags;
88
+	unsigned long last_nack;
89
+};
90
+
91
+#define IGB_VF_FLAG_CTS            0x00000001 /* VF is clear to send data */
92
+#define IGB_VF_FLAG_UNI_PROMISC    0x00000002 /* VF has unicast promisc */
93
+#define IGB_VF_FLAG_MULTI_PROMISC  0x00000004 /* VF has multicast promisc */
94
+
95
+/* RX descriptor control thresholds.
96
+ * PTHRESH - MAC will consider prefetch if it has fewer than this number of
97
+ *           descriptors available in its onboard memory.
98
+ *           Setting this to 0 disables RX descriptor prefetch.
99
+ * HTHRESH - MAC will only prefetch if there are at least this many descriptors
100
+ *           available in host memory.
101
+ *           If PTHRESH is 0, this should also be 0.
102
+ * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
103
+ *           descriptors until either it has this many to write back, or the
104
+ *           ITR timer expires.
105
+ */
106
+#define IGB_RX_PTHRESH                    (hw->mac.type <= e1000_82576 ? 16 : 8)
107
+#define IGB_RX_HTHRESH                     8
108
+#define IGB_RX_WTHRESH                     1
109
+#define IGB_TX_PTHRESH                     8
110
+#define IGB_TX_HTHRESH                     1
111
+#define IGB_TX_WTHRESH                     ((hw->mac.type == e1000_82576 && \
112
+                                             adapter->msix_entries) ? 0 : 16)
113
+
114
+/* this is the size past which hardware will drop packets when setting LPE=0 */
115
+#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
116
+
117
+/* Supported Rx Buffer Sizes */
118
+#define IGB_RXBUFFER_128   128    /* Used for packet split */
119
+#define IGB_RXBUFFER_256   256    /* Used for packet split */
120
+#define IGB_RXBUFFER_512   512
121
+#define IGB_RXBUFFER_1024  1024
122
+#define IGB_RXBUFFER_2048  2048
123
+#define IGB_RXBUFFER_4096  4096
124
+#define IGB_RXBUFFER_8192  8192
125
+#define IGB_RXBUFFER_16384 16384
126
+
127
+/* Packet Buffer allocations */
128
+#define IGB_PBA_BYTES_SHIFT 0xA
129
+#define IGB_TX_HEAD_ADDR_SHIFT 7
130
+#define IGB_PBA_TX_MASK 0xFFFF0000
131
+
132
+#define IGB_FC_PAUSE_TIME 0x0680 /* 858 usec */
133
+
134
+/* How many Tx Descriptors do we need to call netif_wake_queue ? */
135
+#define IGB_TX_QUEUE_WAKE	32
136
+/* How many Rx Buffers do we bundle into one write to the hardware ? */
137
+#define IGB_RX_BUFFER_WRITE	16	/* Must be power of 2 */
138
+
139
+#define AUTO_ALL_MODES            0
140
+#define IGB_EEPROM_APME         0x0400
141
+
142
+#ifndef IGB_MASTER_SLAVE
143
+/* Switch to override PHY master/slave setting */
144
+#define IGB_MASTER_SLAVE	e1000_ms_hw_default
145
+#endif
146
+
147
+#define IGB_MNG_VLAN_NONE -1
148
+
149
+/* wrapper around a pointer to a socket buffer,
150
+ * so a DMA handle can be stored along with the buffer */
151
+struct igb_buffer {
152
+	struct sk_buff *skb;
153
+	dma_addr_t dma;
154
+	dma_addr_t page_dma;
155
+	union {
156
+		/* TX */
157
+		struct {
158
+			unsigned long time_stamp;
159
+			u16 length;
160
+			u16 next_to_watch;
161
+		};
162
+
163
+#ifndef CONFIG_IGB_DISABLE_PACKET_SPLIT
164
+		/* RX */
165
+		struct {
166
+			unsigned long page_offset;
167
+			struct page *page;
168
+		};
169
+#endif
170
+	};
171
+};
172
+
173
+struct igb_queue_stats {
174
+	u64 packets;
175
+	u64 bytes;
176
+};
177
+
178
+struct igb_q_vector {
179
+	struct igb_adapter *adapter; /* backlink */
180
+	struct igb_ring *rx_ring;
181
+	struct igb_ring *tx_ring;
182
+#if 0
183
+	struct napi_struct napi;
184
+#endif
185
+	u32 eims_value;
186
+	u16 cpu;
187
+
188
+	u16 itr_val;
189
+	u8 set_itr;
190
+	u8 itr_shift;
191
+	void __iomem *itr_register;
192
+
193
+#if 0
194
+	char name[IFNAMSIZ + 9];
195
+#endif
196
+#ifndef HAVE_NETDEV_NAPI_LIST
197
+	struct net_device poll_dev;
198
+#endif
199
+};
200
+
201
+struct igb_ring {
202
+	struct igb_q_vector *q_vector; /* backlink to q_vector */
203
+	struct pci_dev *pdev;          /* pci device for dma mapping */
204
+	dma_addr_t dma;                /* phys address of the ring */
205
+	void *desc;                    /* descriptor ring memory */
206
+	unsigned int size;             /* length of desc. ring in bytes */
207
+	u16 count;                     /* number of desc. in the ring */
208
+	u16 next_to_use;
209
+	u16 next_to_clean;
210
+	u8 queue_index;
211
+	u8 reg_idx;
212
+	void __iomem *head;
213
+	void __iomem *tail;
214
+	struct igb_buffer *buffer_info; /* array of buffer info structs */
215
+
216
+	unsigned int total_bytes;
217
+	unsigned int total_packets;
218
+
219
+	struct igb_queue_stats stats;
220
+
221
+	union {
222
+		/* TX */
223
+		struct {
224
+			unsigned int restart_queue;
225
+			u32 ctx_idx;
226
+			bool detect_tx_hung;
227
+		};
228
+		/* RX */
229
+		struct {
230
+			u64 hw_csum_err;
231
+			u64 hw_csum_good;
232
+			u32 rx_buffer_len;
233
+			u16 rx_ps_hdr_size;
234
+			bool rx_csum;
235
+#ifdef IGB_LRO
236
+			struct net_lro_mgr lro_mgr;
237
+			bool lro_used;
238
+#endif
239
+		};
240
+	};
241
+};
242
+
243
+
244
+#define IGB_ADVTXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
245
+
246
+#define IGB_DESC_UNUSED(R) \
247
+	((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
248
+	(R)->next_to_clean - (R)->next_to_use - 1)
249
+
250
+#define E1000_RX_DESC_ADV(R, i)	    \
251
+	(&(((union e1000_adv_rx_desc *)((R).desc))[i]))
252
+#define E1000_TX_DESC_ADV(R, i)	    \
253
+	(&(((union e1000_adv_tx_desc *)((R).desc))[i]))
254
+#define E1000_TX_CTXTDESC_ADV(R, i)	    \
255
+	(&(((struct e1000_adv_tx_context_desc *)((R).desc))[i]))
256
+#define E1000_GET_DESC(R, i, type)	(&(((struct type *)((R).desc))[i]))
257
+#define E1000_TX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_tx_desc)
258
+#define E1000_RX_DESC(R, i)		E1000_GET_DESC(R, i, e1000_rx_desc)
259
+
260
+#define MAX_MSIX_COUNT 10
261
+/* board specific private data structure */
262
+
263
+/* board specific private data structure */
264
+struct igb_adapter {
265
+
266
+	/* OS defined structs */
267
+	struct net_device *netdev;
268
+	struct pci_device *pdev;
269
+	struct net_device_stats net_stats;
270
+
271
+	/* structs defined in e1000_hw.h */
272
+	struct e1000_hw hw;
273
+
274
+	struct e1000_phy_info phy_info;
275
+
276
+        u32 min_frame_size;
277
+        u32 max_frame_size;
278
+
279
+	u32 wol;
280
+	u32 pba;
281
+	u32 max_hw_frame_size;
282
+
283
+	bool fc_autoneg;
284
+
285
+	unsigned int flags;
286
+	unsigned int flags2;
287
+
288
+#define NUM_TX_DESC	8
289
+#define NUM_RX_DESC	8
290
+
291
+	struct io_buffer *tx_iobuf[NUM_TX_DESC];
292
+	struct io_buffer *rx_iobuf[NUM_RX_DESC];
293
+
294
+	struct e1000_tx_desc *tx_base;
295
+	struct e1000_rx_desc *rx_base;
296
+
297
+	uint32_t tx_ring_size;
298
+	uint32_t rx_ring_size;
299
+
300
+	uint32_t tx_head;
301
+	uint32_t tx_tail;
302
+	uint32_t tx_fill_ctr;
303
+
304
+	uint32_t rx_curr;
305
+
306
+	uint32_t ioaddr;
307
+	uint32_t irqno;
308
+
309
+        uint32_t tx_int_delay;
310
+        uint32_t tx_abs_int_delay;
311
+        uint32_t txd_cmd;
312
+};
313
+
314
+#define IGB_FLAG_HAS_MSI           (1 << 0)
315
+#define IGB_FLAG_MSI_ENABLE        (1 << 1)
316
+#define IGB_FLAG_DCA_ENABLED       (1 << 3)
317
+#define IGB_FLAG_LLI_PUSH          (1 << 4)
318
+#define IGB_FLAG_IN_NETPOLL        (1 << 5)
319
+#define IGB_FLAG_QUAD_PORT_A       (1 << 6)
320
+#define IGB_FLAG_QUEUE_PAIRS       (1 << 7)
321
+
322
+#define IGB_82576_TSYNC_SHIFT 19
323
+
324
+#endif /* _IGB_H_ */

+ 1617
- 0
src/drivers/net/igb/igb_82575.c
Файловите разлики са ограничени, защото са твърде много
Целия файл


+ 442
- 0
src/drivers/net/igb/igb_82575.h Целия файл

@@ -0,0 +1,442 @@
1
+/*******************************************************************************
2
+
3
+  Intel(R) Gigabit Ethernet Linux driver
4
+  Copyright(c) 2007-2009 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
+
26
+*******************************************************************************/
27
+
28
+FILE_LICENCE ( GPL2_ONLY );
29
+
30
+#ifndef _IGB_82575_H_
31
+#define _IGB_82575_H_
32
+
33
+#define ID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \
34
+                                     (ID_LED_DEF1_DEF2 <<  8) | \
35
+                                     (ID_LED_DEF1_DEF2 <<  4) | \
36
+                                     (ID_LED_OFF1_ON2))
37
+/*
38
+ * Receive Address Register Count
39
+ * Number of high/low register pairs in the RAR.  The RAR (Receive Address
40
+ * Registers) holds the directed and multicast addresses that we monitor.
41
+ * These entries are also used for MAC-based filtering.
42
+ */
43
+/*
44
+ * For 82576, there are an additional set of RARs that begin at an offset
45
+ * separate from the first set of RARs.
46
+ */
47
+#define E1000_RAR_ENTRIES_82575   16
48
+#define E1000_RAR_ENTRIES_82576   24
49
+
50
+struct e1000_adv_data_desc {
51
+	__le64 buffer_addr;    /* Address of the descriptor's data buffer */
52
+	union {
53
+		u32 data;
54
+		struct {
55
+			u32 datalen :16; /* Data buffer length */
56
+			u32 rsvd    :4;
57
+			u32 dtyp    :4;  /* Descriptor type */
58
+			u32 dcmd    :8;  /* Descriptor command */
59
+		} config;
60
+	} lower;
61
+	union {
62
+		u32 data;
63
+		struct {
64
+			u32 status  :4;  /* Descriptor status */
65
+			u32 idx     :4;
66
+			u32 popts   :6;  /* Packet Options */
67
+			u32 paylen  :18; /* Payload length */
68
+		} options;
69
+	} upper;
70
+};
71
+
72
+#define E1000_TXD_DTYP_ADV_C    0x2  /* Advanced Context Descriptor */
73
+#define E1000_TXD_DTYP_ADV_D    0x3  /* Advanced Data Descriptor */
74
+#define E1000_ADV_TXD_CMD_DEXT  0x20 /* Descriptor extension (0 = legacy) */
75
+#define E1000_ADV_TUCMD_IPV4    0x2  /* IP Packet Type: 1=IPv4 */
76
+#define E1000_ADV_TUCMD_IPV6    0x0  /* IP Packet Type: 0=IPv6 */
77
+#define E1000_ADV_TUCMD_L4T_UDP 0x0  /* L4 Packet TYPE of UDP */
78
+#define E1000_ADV_TUCMD_L4T_TCP 0x4  /* L4 Packet TYPE of TCP */
79
+#define E1000_ADV_TUCMD_MKRREQ  0x10 /* Indicates markers are required */
80
+#define E1000_ADV_DCMD_EOP      0x1  /* End of Packet */
81
+#define E1000_ADV_DCMD_IFCS     0x2  /* Insert FCS (Ethernet CRC) */
82
+#define E1000_ADV_DCMD_RS       0x8  /* Report Status */
83
+#define E1000_ADV_DCMD_VLE      0x40 /* Add VLAN tag */
84
+#define E1000_ADV_DCMD_TSE      0x80 /* TCP Seg enable */
85
+/* Extended Device Control */
86
+#define E1000_CTRL_EXT_NSICR    0x00000001 /* Disable Intr Clear all on read */
87
+
88
+struct e1000_adv_context_desc {
89
+	union {
90
+		u32 ip_config;
91
+		struct {
92
+			u32 iplen    :9;
93
+			u32 maclen   :7;
94
+			u32 vlan_tag :16;
95
+		} fields;
96
+	} ip_setup;
97
+	u32 seq_num;
98
+	union {
99
+		u64 l4_config;
100
+		struct {
101
+			u32 mkrloc :9;
102
+			u32 tucmd  :11;
103
+			u32 dtyp   :4;
104
+			u32 adv    :8;
105
+			u32 rsvd   :4;
106
+			u32 idx    :4;
107
+			u32 l4len  :8;
108
+			u32 mss    :16;
109
+		} fields;
110
+	} l4_setup;
111
+};
112
+
113
+/* SRRCTL bit definitions */
114
+#define E1000_SRRCTL_BSIZEPKT_SHIFT                     10 /* Shift _right_ */
115
+#define E1000_SRRCTL_BSIZEHDRSIZE_MASK                  0x00000F00
116
+#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT                 2  /* Shift _left_ */
117
+#define E1000_SRRCTL_DESCTYPE_LEGACY                    0x00000000
118
+#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF                0x02000000
119
+#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT                 0x04000000
120
+#define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS          0x0A000000
121
+#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION           0x06000000
122
+#define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
123
+#define E1000_SRRCTL_DESCTYPE_MASK                      0x0E000000
124
+#define E1000_SRRCTL_DROP_EN                            0x80000000
125
+
126
+#define E1000_SRRCTL_BSIZEPKT_MASK      0x0000007F
127
+#define E1000_SRRCTL_BSIZEHDR_MASK      0x00003F00
128
+
129
+#define E1000_TX_HEAD_WB_ENABLE   0x1
130
+#define E1000_TX_SEQNUM_WB_ENABLE 0x2
131
+
132
+#define E1000_MRQC_ENABLE_RSS_4Q            0x00000002
133
+#define E1000_MRQC_ENABLE_VMDQ              0x00000003
134
+#define E1000_MRQC_ENABLE_VMDQ_RSS_2Q       0x00000005
135
+#define E1000_MRQC_RSS_FIELD_IPV4_UDP       0x00400000
136
+#define E1000_MRQC_RSS_FIELD_IPV6_UDP       0x00800000
137
+#define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX    0x01000000
138
+
139
+#define E1000_VMRCTL_MIRROR_PORT_SHIFT      8
140
+#define E1000_VMRCTL_MIRROR_DSTPORT_MASK    (7 << E1000_VMRCTL_MIRROR_PORT_SHIFT)
141
+#define E1000_VMRCTL_POOL_MIRROR_ENABLE     (1 << 0)
142
+#define E1000_VMRCTL_UPLINK_MIRROR_ENABLE   (1 << 1)
143
+#define E1000_VMRCTL_DOWNLINK_MIRROR_ENABLE (1 << 2)
144
+
145
+#define E1000_EICR_TX_QUEUE ( \
146
+    E1000_EICR_TX_QUEUE0 |    \
147
+    E1000_EICR_TX_QUEUE1 |    \
148
+    E1000_EICR_TX_QUEUE2 |    \
149
+    E1000_EICR_TX_QUEUE3)
150
+
151
+#define E1000_EICR_RX_QUEUE ( \
152
+    E1000_EICR_RX_QUEUE0 |    \
153
+    E1000_EICR_RX_QUEUE1 |    \
154
+    E1000_EICR_RX_QUEUE2 |    \
155
+    E1000_EICR_RX_QUEUE3)
156
+
157
+#define E1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE
158
+#define E1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE
159
+
160
+#define EIMS_ENABLE_MASK ( \
161
+    E1000_EIMS_RX_QUEUE  | \
162
+    E1000_EIMS_TX_QUEUE  | \
163
+    E1000_EIMS_TCP_TIMER | \
164
+    E1000_EIMS_OTHER)
165
+
166
+/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
167
+#define E1000_IMIR_PORT_IM_EN     0x00010000  /* TCP port enable */
168
+#define E1000_IMIR_PORT_BP        0x00020000  /* TCP port check bypass */
169
+#define E1000_IMIREXT_SIZE_BP     0x00001000  /* Packet size bypass */
170
+#define E1000_IMIREXT_CTRL_URG    0x00002000  /* Check URG bit in header */
171
+#define E1000_IMIREXT_CTRL_ACK    0x00004000  /* Check ACK bit in header */
172
+#define E1000_IMIREXT_CTRL_PSH    0x00008000  /* Check PSH bit in header */
173
+#define E1000_IMIREXT_CTRL_RST    0x00010000  /* Check RST bit in header */
174
+#define E1000_IMIREXT_CTRL_SYN    0x00020000  /* Check SYN bit in header */
175
+#define E1000_IMIREXT_CTRL_FIN    0x00040000  /* Check FIN bit in header */
176
+#define E1000_IMIREXT_CTRL_BP     0x00080000  /* Bypass check of ctrl bits */
177
+
178
+/* Receive Descriptor - Advanced */
179
+union e1000_adv_rx_desc {
180
+	struct {
181
+		__le64 pkt_addr;             /* Packet buffer address */
182
+		__le64 hdr_addr;             /* Header buffer address */
183
+	} read;
184
+	struct {
185
+		struct {
186
+			union {
187
+				__le32 data;
188
+				struct {
189
+					__le16 pkt_info; /*RSS type, Pkt type*/
190
+					__le16 hdr_info; /* Split Header,
191
+							  * header buffer len*/
192
+				} hs_rss;
193
+			} lo_dword;
194
+			union {
195
+				__le32 rss;          /* RSS Hash */
196
+				struct {
197
+					__le16 ip_id;    /* IP id */
198
+					__le16 csum;     /* Packet Checksum */
199
+				} csum_ip;
200
+			} hi_dword;
201
+		} lower;
202
+		struct {
203
+			__le32 status_error;     /* ext status/error */
204
+			__le16 length;           /* Packet length */
205
+			__le16 vlan;             /* VLAN tag */
206
+		} upper;
207
+	} wb;  /* writeback */
208
+};
209
+
210
+#define E1000_RXDADV_RSSTYPE_MASK        0x0000000F
211
+#define E1000_RXDADV_RSSTYPE_SHIFT       12
212
+#define E1000_RXDADV_HDRBUFLEN_MASK      0x7FE0
213
+#define E1000_RXDADV_HDRBUFLEN_SHIFT     5
214
+#define E1000_RXDADV_SPLITHEADER_EN      0x00001000
215
+#define E1000_RXDADV_SPH                 0x8000
216
+#define E1000_RXDADV_STAT_TS             0x10000 /* Pkt was time stamped */
217
+#define E1000_RXDADV_ERR_HBO             0x00800000
218
+
219
+/* RSS Hash results */
220
+#define E1000_RXDADV_RSSTYPE_NONE        0x00000000
221
+#define E1000_RXDADV_RSSTYPE_IPV4_TCP    0x00000001
222
+#define E1000_RXDADV_RSSTYPE_IPV4        0x00000002
223
+#define E1000_RXDADV_RSSTYPE_IPV6_TCP    0x00000003
224
+#define E1000_RXDADV_RSSTYPE_IPV6_EX     0x00000004
225
+#define E1000_RXDADV_RSSTYPE_IPV6        0x00000005
226
+#define E1000_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
227
+#define E1000_RXDADV_RSSTYPE_IPV4_UDP    0x00000007
228
+#define E1000_RXDADV_RSSTYPE_IPV6_UDP    0x00000008
229
+#define E1000_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
230
+
231
+/* RSS Packet Types as indicated in the receive descriptor */
232
+#define E1000_RXDADV_PKTTYPE_NONE        0x00000000
233
+#define E1000_RXDADV_PKTTYPE_IPV4        0x00000010 /* IPV4 hdr present */
234
+#define E1000_RXDADV_PKTTYPE_IPV4_EX     0x00000020 /* IPV4 hdr + extensions */
235
+#define E1000_RXDADV_PKTTYPE_IPV6        0x00000040 /* IPV6 hdr present */
236
+#define E1000_RXDADV_PKTTYPE_IPV6_EX     0x00000080 /* IPV6 hdr + extensions */
237
+#define E1000_RXDADV_PKTTYPE_TCP         0x00000100 /* TCP hdr present */
238
+#define E1000_RXDADV_PKTTYPE_UDP         0x00000200 /* UDP hdr present */
239
+#define E1000_RXDADV_PKTTYPE_SCTP        0x00000400 /* SCTP hdr present */
240
+#define E1000_RXDADV_PKTTYPE_NFS         0x00000800 /* NFS hdr present */
241
+
242
+#define E1000_RXDADV_PKTTYPE_IPSEC_ESP   0x00001000 /* IPSec ESP */
243
+#define E1000_RXDADV_PKTTYPE_IPSEC_AH    0x00002000 /* IPSec AH */
244
+#define E1000_RXDADV_PKTTYPE_LINKSEC     0x00004000 /* LinkSec Encap */
245
+#define E1000_RXDADV_PKTTYPE_ETQF        0x00008000 /* PKTTYPE is ETQF index */
246
+#define E1000_RXDADV_PKTTYPE_ETQF_MASK   0x00000070 /* ETQF has 8 indices */
247
+#define E1000_RXDADV_PKTTYPE_ETQF_SHIFT  4          /* Right-shift 4 bits */
248
+
249
+/* LinkSec results */
250
+/* Security Processing bit Indication */
251
+#define E1000_RXDADV_LNKSEC_STATUS_SECP         0x00020000
252
+#define E1000_RXDADV_LNKSEC_ERROR_BIT_MASK      0x18000000
253
+#define E1000_RXDADV_LNKSEC_ERROR_NO_SA_MATCH   0x08000000
254
+#define E1000_RXDADV_LNKSEC_ERROR_REPLAY_ERROR  0x10000000
255
+#define E1000_RXDADV_LNKSEC_ERROR_BAD_SIG       0x18000000
256
+
257
+#define E1000_RXDADV_IPSEC_STATUS_SECP          0x00020000
258
+#define E1000_RXDADV_IPSEC_ERROR_BIT_MASK       0x18000000
259
+#define E1000_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL       0x08000000
260
+#define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH         0x10000000
261
+#define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED  0x18000000
262
+
263
+/* Transmit Descriptor - Advanced */
264
+union e1000_adv_tx_desc {
265
+	struct {
266
+		__le64 buffer_addr;    /* Address of descriptor's data buf */
267
+		__le32 cmd_type_len;
268
+		__le32 olinfo_status;
269
+	} read;
270
+	struct {
271
+		__le64 rsvd;       /* Reserved */
272
+		__le32 nxtseq_seed;
273
+		__le32 status;
274
+	} wb;
275
+};
276
+
277
+/* Adv Transmit Descriptor Config Masks */
278
+#define E1000_ADVTXD_DTYP_CTXT    0x00200000 /* Advanced Context Descriptor */
279
+#define E1000_ADVTXD_DTYP_DATA    0x00300000 /* Advanced Data Descriptor */
280
+#define E1000_ADVTXD_DCMD_EOP     0x01000000 /* End of Packet */
281
+#define E1000_ADVTXD_DCMD_IFCS    0x02000000 /* Insert FCS (Ethernet CRC) */
282
+#define E1000_ADVTXD_DCMD_RS      0x08000000 /* Report Status */
283
+#define E1000_ADVTXD_DCMD_DDTYP_ISCSI  0x10000000 /* DDP hdr type or iSCSI */
284
+#define E1000_ADVTXD_DCMD_DEXT    0x20000000 /* Descriptor extension (1=Adv) */
285
+#define E1000_ADVTXD_DCMD_VLE     0x40000000 /* VLAN pkt enable */
286
+#define E1000_ADVTXD_DCMD_TSE     0x80000000 /* TCP Seg enable */
287
+#define E1000_ADVTXD_MAC_LINKSEC  0x00040000 /* Apply LinkSec on packet */
288
+#define E1000_ADVTXD_MAC_TSTAMP   0x00080000 /* IEEE1588 Timestamp packet */
289
+#define E1000_ADVTXD_STAT_SN_CRC  0x00000002 /* NXTSEQ/SEED present in WB */
290
+#define E1000_ADVTXD_IDX_SHIFT    4  /* Adv desc Index shift */
291
+#define E1000_ADVTXD_POPTS_ISCO_1ST  0x00000000 /* 1st TSO of iSCSI PDU */
292
+#define E1000_ADVTXD_POPTS_ISCO_MDL  0x00000800 /* Middle TSO of iSCSI PDU */
293
+#define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
294
+#define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU*/
295
+#define E1000_ADVTXD_POPTS_IPSEC     0x00000400 /* IPSec offload request */
296
+#define E1000_ADVTXD_PAYLEN_SHIFT    14 /* Adv desc PAYLEN shift */
297
+
298
+/* Context descriptors */
299
+struct e1000_adv_tx_context_desc {
300
+	__le32 vlan_macip_lens;
301
+	__le32 seqnum_seed;
302
+	__le32 type_tucmd_mlhl;
303
+	__le32 mss_l4len_idx;
304
+};
305
+
306
+#define E1000_ADVTXD_MACLEN_SHIFT    9  /* Adv ctxt desc mac len shift */
307
+#define E1000_ADVTXD_VLAN_SHIFT     16  /* Adv ctxt vlan tag shift */
308
+#define E1000_ADVTXD_TUCMD_IPV4    0x00000400  /* IP Packet Type: 1=IPv4 */
309
+#define E1000_ADVTXD_TUCMD_IPV6    0x00000000  /* IP Packet Type: 0=IPv6 */
310
+#define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000  /* L4 Packet TYPE of UDP */
311
+#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800  /* L4 Packet TYPE of TCP */
312
+#define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000  /* L4 Packet TYPE of SCTP */
313
+#define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP    0x00002000 /* IPSec Type ESP */
314
+/* IPSec Encrypt Enable for ESP */
315
+#define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN  0x00004000
316
+#define E1000_ADVTXD_TUCMD_MKRREQ  0x00002000 /* Req requires Markers and CRC */
317
+#define E1000_ADVTXD_L4LEN_SHIFT     8  /* Adv ctxt L4LEN shift */
318
+#define E1000_ADVTXD_MSS_SHIFT      16  /* Adv ctxt MSS shift */
319
+/* Adv ctxt IPSec SA IDX mask */
320
+#define E1000_ADVTXD_IPSEC_SA_INDEX_MASK     0x000000FF
321
+/* Adv ctxt IPSec ESP len mask */
322
+#define E1000_ADVTXD_IPSEC_ESP_LEN_MASK      0x000000FF
323
+
324
+/* Additional Transmit Descriptor Control definitions */
325
+#define E1000_TXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Tx Queue */
326
+#define E1000_TXDCTL_SWFLSH        0x04000000 /* Tx Desc. write-back flushing */
327
+/* Tx Queue Arbitration Priority 0=low, 1=high */
328
+#define E1000_TXDCTL_PRIORITY      0x08000000
329
+
330
+/* Additional Receive Descriptor Control definitions */
331
+#define E1000_RXDCTL_QUEUE_ENABLE  0x02000000 /* Enable specific Rx Queue */
332
+#define E1000_RXDCTL_SWFLSH        0x04000000 /* Rx Desc. write-back flushing */
333
+
334
+/* Direct Cache Access (DCA) definitions */
335
+#define E1000_DCA_CTRL_DCA_ENABLE  0x00000000 /* DCA Enable */
336
+#define E1000_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
337
+
338
+#define E1000_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
339
+#define E1000_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
340
+
341
+#define E1000_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
342
+#define E1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
343
+#define E1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
344
+#define E1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
345
+
346
+#define E1000_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
347
+#define E1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
348
+#define E1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
349
+
350
+#define E1000_DCA_TXCTRL_CPUID_MASK_82576 0xFF000000 /* Tx CPUID Mask */
351
+#define E1000_DCA_RXCTRL_CPUID_MASK_82576 0xFF000000 /* Rx CPUID Mask */
352
+#define E1000_DCA_TXCTRL_CPUID_SHIFT_82576 24 /* Tx CPUID */
353
+#define E1000_DCA_RXCTRL_CPUID_SHIFT_82576 24 /* Rx CPUID */
354
+
355
+/* Additional interrupt register bit definitions */
356
+#define E1000_ICR_LSECPNS       0x00000020          /* PN threshold - server */
357
+#define E1000_IMS_LSECPNS       E1000_ICR_LSECPNS   /* PN threshold - server */
358
+#define E1000_ICS_LSECPNS       E1000_ICR_LSECPNS   /* PN threshold - server */
359
+
360
+/* ETQF register bit definitions */
361
+#define E1000_ETQF_FILTER_ENABLE   (1 << 26)
362
+#define E1000_ETQF_IMM_INT         (1 << 29)
363
+#define E1000_ETQF_1588            (1 << 30)
364
+#define E1000_ETQF_QUEUE_ENABLE    (1 << 31)
365
+/*
366
+ * ETQF filter list: one static filter per filter consumer. This is
367
+ *                   to avoid filter collisions later. Add new filters
368
+ *                   here!!
369
+ *
370
+ * Current filters:
371
+ *    EAPOL 802.1x (0x888e): Filter 0
372
+ */
373
+#define E1000_ETQF_FILTER_EAPOL          0
374
+
375
+#define E1000_FTQF_VF_BP               0x00008000
376
+#define E1000_FTQF_1588_TIME_STAMP     0x08000000
377
+#define E1000_FTQF_MASK                0xF0000000
378
+#define E1000_FTQF_MASK_PROTO_BP       0x10000000
379
+#define E1000_FTQF_MASK_SOURCE_ADDR_BP 0x20000000
380
+#define E1000_FTQF_MASK_DEST_ADDR_BP   0x40000000
381
+#define E1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000
382
+
383
+#define E1000_NVM_APME_82575          0x0400
384
+#define MAX_NUM_VFS                   8
385
+
386
+#define E1000_DTXSWC_MAC_SPOOF_MASK   0x000000FF /* Per VF MAC spoof control */
387
+#define E1000_DTXSWC_VLAN_SPOOF_MASK  0x0000FF00 /* Per VF VLAN spoof control */
388
+#define E1000_DTXSWC_LLE_MASK         0x00FF0000 /* Per VF Local LB enables */
389
+#define E1000_DTXSWC_VLAN_SPOOF_SHIFT 8
390
+#define E1000_DTXSWC_LLE_SHIFT        16
391
+#define E1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31)  /* global VF LB enable */
392
+
393
+/* Easy defines for setting default pool, would normally be left a zero */
394
+#define E1000_VT_CTL_DEFAULT_POOL_SHIFT 7
395
+#define E1000_VT_CTL_DEFAULT_POOL_MASK  (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT)
396
+
397
+/* Other useful VMD_CTL register defines */
398
+#define E1000_VT_CTL_IGNORE_MAC         (1 << 28)
399
+#define E1000_VT_CTL_DISABLE_DEF_POOL   (1 << 29)
400
+#define E1000_VT_CTL_VM_REPL_EN         (1 << 30)
401
+
402
+/* Per VM Offload register setup */
403
+#define E1000_VMOLR_RLPML_MASK 0x00003FFF /* Long Packet Maximum Length mask */
404
+#define E1000_VMOLR_LPE        0x00010000 /* Accept Long packet */
405
+#define E1000_VMOLR_RSSE       0x00020000 /* Enable RSS */
406
+#define E1000_VMOLR_AUPE       0x01000000 /* Accept untagged packets */
407
+#define E1000_VMOLR_ROMPE      0x02000000 /* Accept overflow multicast */
408
+#define E1000_VMOLR_ROPE       0x04000000 /* Accept overflow unicast */
409
+#define E1000_VMOLR_BAM        0x08000000 /* Accept Broadcast packets */
410
+#define E1000_VMOLR_MPME       0x10000000 /* Multicast promiscuous mode */
411
+#define E1000_VMOLR_STRVLAN    0x40000000 /* Vlan stripping enable */
412
+#define E1000_VMOLR_STRCRC     0x80000000 /* CRC stripping enable */
413
+
414
+#define E1000_VLVF_ARRAY_SIZE     32
415
+#define E1000_VLVF_VLANID_MASK    0x00000FFF
416
+#define E1000_VLVF_POOLSEL_SHIFT  12
417
+#define E1000_VLVF_POOLSEL_MASK   (0xFF << E1000_VLVF_POOLSEL_SHIFT)
418
+#define E1000_VLVF_LVLAN          0x00100000
419
+#define E1000_VLVF_VLANID_ENABLE  0x80000000
420
+
421
+#define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
422
+
423
+#define E1000_IOVCTL 0x05BBC
424
+#define E1000_IOVCTL_REUSE_VFQ 0x00000001
425
+
426
+#define E1000_RPLOLR_STRVLAN   0x40000000
427
+#define E1000_RPLOLR_STRCRC    0x80000000
428
+
429
+#define E1000_DTXCTL_8023LL     0x0004
430
+#define E1000_DTXCTL_VLAN_ADDED 0x0008
431
+#define E1000_DTXCTL_OOS_ENABLE 0x0010
432
+#define E1000_DTXCTL_MDP_EN     0x0020
433
+#define E1000_DTXCTL_SPOOF_INT  0x0040
434
+
435
+#define ALL_QUEUES   0xFFFF
436
+
437
+/* RX packet buffer size defines */
438
+#define E1000_RXPBS_SIZE_MASK_82576  0x0000007F
439
+void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable);
440
+void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable);
441
+
442
+#endif /* _IGB_82575_H_ */

+ 1108
- 0
src/drivers/net/igb/igb_api.c
Файловите разлики са ограничени, защото са твърде много
Целия файл


+ 166
- 0
src/drivers/net/igb/igb_api.h Целия файл

@@ -0,0 +1,166 @@
1
+/*******************************************************************************
2
+
3
+  Intel(R) Gigabit Ethernet Linux driver
4
+  Copyright(c) 2007-2009 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
+
26
+*******************************************************************************/
27
+
28
+FILE_LICENCE ( GPL2_ONLY );
29
+
30
+#ifndef _IGB_API_H_
31
+#define _IGB_API_H_
32
+
33
+#include <stdint.h>
34
+#include <stdlib.h>
35
+#include <stdio.h>
36
+#include <string.h>
37
+#include <unistd.h>
38
+#include <gpxe/io.h>
39
+#include <errno.h>
40
+#include <byteswap.h>
41
+#include <gpxe/pci.h>
42
+#include <gpxe/malloc.h>
43
+#include <gpxe/if_ether.h>
44
+#include <gpxe/ethernet.h>
45
+#include <gpxe/iobuf.h>
46
+#include <gpxe/netdevice.h>
47
+
48
+#include "igb_hw.h"
49
+
50
+extern void    igb_init_function_pointers_82575(struct e1000_hw *hw) __attribute__((weak));
51
+extern void    igb_rx_fifo_flush_82575(struct e1000_hw *hw) __attribute__((weak));
52
+extern void    igb_init_function_pointers_vf(struct e1000_hw *hw) __attribute__((weak));
53
+extern void    igb_shutdown_fiber_serdes_link(struct e1000_hw *hw) __attribute__((weak));
54
+
55
+s32  igb_set_mac_type(struct e1000_hw *hw);
56
+s32  igb_setup_init_funcs(struct e1000_hw *hw, bool init_device);
57
+s32  igb_init_mac_params(struct e1000_hw *hw);
58
+s32  igb_init_nvm_params(struct e1000_hw *hw);
59
+s32  igb_init_phy_params(struct e1000_hw *hw);
60
+s32  igb_init_mbx_params(struct e1000_hw *hw);
61
+s32  igb_get_bus_info(struct e1000_hw *hw);
62
+void igb_clear_vfta(struct e1000_hw *hw);
63
+void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value);
64
+s32  igb_force_mac_fc(struct e1000_hw *hw);
65
+s32  igb_check_for_link(struct e1000_hw *hw);
66
+s32  igb_reset_hw(struct e1000_hw *hw);
67
+s32  igb_init_hw(struct e1000_hw *hw);
68
+s32  igb_setup_link(struct e1000_hw *hw);
69
+s32  igb_get_speed_and_duplex(struct e1000_hw *hw, u16 *speed,
70
+                                u16 *duplex);
71
+s32  igb_disable_pcie_master(struct e1000_hw *hw);
72
+void igb_config_collision_dist(struct e1000_hw *hw);
73
+void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index);
74
+void igb_mta_set(struct e1000_hw *hw, u32 hash_value);
75
+u32  igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr);
76
+void igb_update_mc_addr_list(struct e1000_hw *hw,
77
+                               u8 *mc_addr_list, u32 mc_addr_count);
78
+s32  igb_setup_led(struct e1000_hw *hw);
79
+s32  igb_cleanup_led(struct e1000_hw *hw);
80
+s32  igb_check_reset_block(struct e1000_hw *hw);
81
+s32  igb_blink_led(struct e1000_hw *hw);
82
+s32  igb_led_on(struct e1000_hw *hw);
83
+s32  igb_led_off(struct e1000_hw *hw);
84
+s32 igb_id_led_init(struct e1000_hw *hw);
85
+void igb_reset_adaptive(struct e1000_hw *hw);
86
+void igb_update_adaptive(struct e1000_hw *hw);
87
+#if 0
88
+s32  igb_get_cable_length(struct e1000_hw *hw);
89
+#endif
90
+s32  igb_validate_mdi_setting(struct e1000_hw *hw);
91
+s32  igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data);
92
+s32  igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data);
93
+s32  igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg,
94
+                               u32 offset, u8 data);
95
+s32  igb_get_phy_info(struct e1000_hw *hw);
96
+void igb_release_phy(struct e1000_hw *hw);
97
+s32  igb_acquire_phy(struct e1000_hw *hw);
98
+s32  igb_phy_hw_reset(struct e1000_hw *hw);
99
+s32  igb_phy_commit(struct e1000_hw *hw);
100
+void igb_power_up_phy(struct e1000_hw *hw);
101
+void igb_power_down_phy(struct e1000_hw *hw);
102
+s32  igb_read_mac_addr(struct e1000_hw *hw);
103
+s32  igb_read_pba_num(struct e1000_hw *hw, u32 *part_num);
104
+void igb_reload_nvm(struct e1000_hw *hw);
105
+s32  igb_update_nvm_checksum(struct e1000_hw *hw);
106
+s32  igb_validate_nvm_checksum(struct e1000_hw *hw);
107
+s32  igb_read_nvm(struct e1000_hw *hw, u16 offset, u16 words, u16 *data);
108
+s32  igb_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data);
109
+s32  igb_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data);
110
+s32  igb_write_nvm(struct e1000_hw *hw, u16 offset, u16 words,
111
+                     u16 *data);
112
+s32  igb_wait_autoneg(struct e1000_hw *hw);
113
+s32  igb_set_d3_lplu_state(struct e1000_hw *hw, bool active);
114
+s32  igb_set_d0_lplu_state(struct e1000_hw *hw, bool active);
115
+bool igb_check_mng_mode(struct e1000_hw *hw);
116
+bool igb_enable_tx_pkt_filtering(struct e1000_hw *hw);
117
+s32  igb_mng_enable_host_if(struct e1000_hw *hw);
118
+s32  igb_mng_host_if_write(struct e1000_hw *hw,
119
+                             u8 *buffer, u16 length, u16 offset, u8 *sum);
120
+s32  igb_mng_write_cmd_header(struct e1000_hw *hw,
121
+                                struct e1000_host_mng_command_header *hdr);
122
+s32  igb_mng_write_dhcp_info(struct e1000_hw * hw,
123
+                                    u8 *buffer, u16 length);
124
+
125
+/*
126
+ * TBI_ACCEPT macro definition:
127
+ *
128
+ * This macro requires:
129
+ *      adapter = a pointer to struct e1000_hw
130
+ *      status = the 8 bit status field of the Rx descriptor with EOP set
131
+ *      error = the 8 bit error field of the Rx descriptor with EOP set
132
+ *      length = the sum of all the length fields of the Rx descriptors that
133
+ *               make up the current frame
134
+ *      last_byte = the last byte of the frame DMAed by the hardware
135
+ *      max_frame_length = the maximum frame length we want to accept.
136
+ *      min_frame_length = the minimum frame length we want to accept.
137
+ *
138
+ * This macro is a conditional that should be used in the interrupt
139
+ * handler's Rx processing routine when RxErrors have been detected.
140
+ *
141
+ * Typical use:
142
+ *  ...
143
+ *  if (TBI_ACCEPT) {
144
+ *      accept_frame = true;
145
+ *      e1000_tbi_adjust_stats(adapter, MacAddress);
146
+ *      frame_length--;
147
+ *  } else {
148
+ *      accept_frame = false;
149
+ *  }
150
+ *  ...
151
+ */
152
+
153
+/* The carrier extension symbol, as received by the NIC. */
154
+#define CARRIER_EXTENSION   0x0F
155
+
156
+#define TBI_ACCEPT(a, status, errors, length, last_byte, min_frame_size, max_frame_size) \
157
+    (e1000_tbi_sbp_enabled_82543(a) && \
158
+     (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
159
+     ((last_byte) == CARRIER_EXTENSION) && \
160
+     (((status) & E1000_RXD_STAT_VP) ? \
161
+          (((length) > (min_frame_size - VLAN_TAG_SIZE)) && \
162
+           ((length) <= (max_frame_size + 1))) : \
163
+          (((length) > min_frame_size) && \
164
+           ((length) <= (max_frame_size + VLAN_TAG_SIZE + 1)))))
165
+
166
+#endif /* _IGB_API_H_ */

+ 1515
- 0
src/drivers/net/igb/igb_defines.h
Файловите разлики са ограничени, защото са твърде много
Целия файл


+ 697
- 0
src/drivers/net/igb/igb_hw.h Целия файл

@@ -0,0 +1,697 @@
1
+/*******************************************************************************
2
+
3
+  Intel(R) Gigabit Ethernet Linux driver
4
+  Copyright(c) 2007-2009 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
+
26
+*******************************************************************************/
27
+
28
+FILE_LICENCE ( GPL2_ONLY );
29
+
30
+#ifndef _IGB_HW_H_
31
+#define _IGB_HW_H_
32
+
33
+#include "igb_osdep.h"
34
+#include "igb_regs.h"
35
+#include "igb_defines.h"
36
+
37
+struct e1000_hw;
38
+
39
+#define E1000_DEV_ID_82576                    0x10C9
40
+#define E1000_DEV_ID_82576_FIBER              0x10E6
41
+#define E1000_DEV_ID_82576_SERDES             0x10E7
42
+#define E1000_DEV_ID_82576_QUAD_COPPER        0x10E8
43
+#define E1000_DEV_ID_82576_NS                 0x150A
44
+#define E1000_DEV_ID_82576_NS_SERDES          0x1518
45
+#define E1000_DEV_ID_82576_SERDES_QUAD        0x150D
46
+#define E1000_DEV_ID_82575EB_COPPER           0x10A7
47
+#define E1000_DEV_ID_82575EB_FIBER_SERDES     0x10A9
48
+#define E1000_DEV_ID_82575GB_QUAD_COPPER      0x10D6
49
+#define E1000_REVISION_0 0
50
+#define E1000_REVISION_1 1
51
+#define E1000_REVISION_2 2
52
+#define E1000_REVISION_3 3
53
+#define E1000_REVISION_4 4
54
+
55
+#define E1000_FUNC_0     0
56
+#define E1000_FUNC_1     1
57
+
58
+#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
59
+#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
60
+
61
+enum e1000_mac_type {
62
+	e1000_undefined = 0,
63
+	e1000_82575,
64
+	e1000_82576,
65
+	e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
66
+};
67
+
68
+enum e1000_media_type {
69
+	e1000_media_type_unknown = 0,
70
+	e1000_media_type_copper = 1,
71
+	e1000_media_type_fiber = 2,
72
+	e1000_media_type_internal_serdes = 3,
73
+	e1000_num_media_types
74
+};
75
+
76
+enum e1000_nvm_type {
77
+	e1000_nvm_unknown = 0,
78
+	e1000_nvm_none,
79
+	e1000_nvm_eeprom_spi,
80
+	e1000_nvm_flash_hw,
81
+	e1000_nvm_flash_sw
82
+};
83
+
84
+enum e1000_nvm_override {
85
+	e1000_nvm_override_none = 0,
86
+	e1000_nvm_override_spi_small,
87
+	e1000_nvm_override_spi_large,
88
+};
89
+
90
+enum e1000_phy_type {
91
+	e1000_phy_unknown = 0,
92
+	e1000_phy_none,
93
+	e1000_phy_m88,
94
+	e1000_phy_igp,
95
+	e1000_phy_igp_2,
96
+	e1000_phy_gg82563,
97
+	e1000_phy_igp_3,
98
+	e1000_phy_ife,
99
+	e1000_phy_vf,
100
+};
101
+
102
+enum e1000_bus_type {
103
+	e1000_bus_type_unknown = 0,
104
+	e1000_bus_type_pci,
105
+	e1000_bus_type_pcix,
106
+	e1000_bus_type_pci_express,
107
+	e1000_bus_type_reserved
108
+};
109
+
110
+enum e1000_bus_speed {
111
+	e1000_bus_speed_unknown = 0,
112
+	e1000_bus_speed_33,
113
+	e1000_bus_speed_66,
114
+	e1000_bus_speed_100,
115
+	e1000_bus_speed_120,
116
+	e1000_bus_speed_133,
117
+	e1000_bus_speed_2500,
118
+	e1000_bus_speed_5000,
119
+	e1000_bus_speed_reserved
120
+};
121
+
122
+enum e1000_bus_width {
123
+	e1000_bus_width_unknown = 0,
124
+	e1000_bus_width_pcie_x1,
125
+	e1000_bus_width_pcie_x2,
126
+	e1000_bus_width_pcie_x4 = 4,
127
+	e1000_bus_width_pcie_x8 = 8,
128
+	e1000_bus_width_32,
129
+	e1000_bus_width_64,
130
+	e1000_bus_width_reserved
131
+};
132
+
133
+enum e1000_1000t_rx_status {
134
+	e1000_1000t_rx_status_not_ok = 0,
135
+	e1000_1000t_rx_status_ok,
136
+	e1000_1000t_rx_status_undefined = 0xFF
137
+};
138
+
139
+enum e1000_rev_polarity {
140
+	e1000_rev_polarity_normal = 0,
141
+	e1000_rev_polarity_reversed,
142
+	e1000_rev_polarity_undefined = 0xFF
143
+};
144
+
145
+enum e1000_fc_mode {
146
+	e1000_fc_none = 0,
147
+	e1000_fc_rx_pause,
148
+	e1000_fc_tx_pause,
149
+	e1000_fc_full,
150
+	e1000_fc_default = 0xFF
151
+};
152
+
153
+enum e1000_ms_type {
154
+	e1000_ms_hw_default = 0,
155
+	e1000_ms_force_master,
156
+	e1000_ms_force_slave,
157
+	e1000_ms_auto
158
+};
159
+
160
+enum e1000_smart_speed {
161
+	e1000_smart_speed_default = 0,
162
+	e1000_smart_speed_on,
163
+	e1000_smart_speed_off
164
+};
165
+
166
+enum e1000_serdes_link_state {
167
+	e1000_serdes_link_down = 0,
168
+	e1000_serdes_link_autoneg_progress,
169
+	e1000_serdes_link_autoneg_complete,
170
+	e1000_serdes_link_forced_up
171
+};
172
+
173
+/* Receive Descriptor */
174
+struct e1000_rx_desc {
175
+	__le64 buffer_addr; /* Address of the descriptor's data buffer */
176
+	__le16 length;      /* Length of data DMAed into data buffer */
177
+	__le16 csum;        /* Packet checksum */
178
+	u8  status;         /* Descriptor status */
179
+	u8  errors;         /* Descriptor Errors */
180
+	__le16 special;
181
+};
182
+
183
+/* Receive Descriptor - Extended */
184
+union e1000_rx_desc_extended {
185
+	struct {
186
+		__le64 buffer_addr;
187
+		__le64 reserved;
188
+	} read;
189
+	struct {
190
+		struct {
191
+			__le32 mrq;           /* Multiple Rx Queues */
192
+			union {
193
+				__le32 rss;         /* RSS Hash */
194
+				struct {
195
+					__le16 ip_id;  /* IP id */
196
+					__le16 csum;   /* Packet Checksum */
197
+				} csum_ip;
198
+			} hi_dword;
199
+		} lower;
200
+		struct {
201
+			__le32 status_error;  /* ext status/error */
202
+			__le16 length;
203
+			__le16 vlan;          /* VLAN tag */
204
+		} upper;
205
+	} wb;  /* writeback */
206
+};
207
+
208
+#define MAX_PS_BUFFERS 4
209
+/* Receive Descriptor - Packet Split */
210
+union e1000_rx_desc_packet_split {
211
+	struct {
212
+		/* one buffer for protocol header(s), three data buffers */
213
+		__le64 buffer_addr[MAX_PS_BUFFERS];
214
+	} read;
215
+	struct {
216
+		struct {
217
+			__le32 mrq;           /* Multiple Rx Queues */
218
+			union {
219
+				__le32 rss;           /* RSS Hash */
220
+				struct {
221
+					__le16 ip_id;    /* IP id */
222
+					__le16 csum;     /* Packet Checksum */
223
+				} csum_ip;
224
+			} hi_dword;
225
+		} lower;
226
+		struct {
227
+			__le32 status_error;  /* ext status/error */
228
+			__le16 length0;       /* length of buffer 0 */
229
+			__le16 vlan;          /* VLAN tag */
230
+		} middle;
231
+		struct {
232
+			__le16 header_status;
233
+			__le16 length[3];     /* length of buffers 1-3 */
234
+		} upper;
235
+		__le64 reserved;
236
+	} wb; /* writeback */
237
+};
238
+
239
+/* Transmit Descriptor */
240
+struct e1000_tx_desc {
241
+	__le64 buffer_addr;   /* Address of the descriptor's data buffer */
242
+	union {
243
+		__le32 data;
244
+		struct {
245
+			__le16 length;    /* Data buffer length */
246
+			u8 cso;           /* Checksum offset */
247
+			u8 cmd;           /* Descriptor control */
248
+		} flags;
249
+	} lower;
250
+	union {
251
+		__le32 data;
252
+		struct {
253
+			u8 status;        /* Descriptor status */
254
+			u8 css;           /* Checksum start */
255
+			__le16 special;
256
+		} fields;
257
+	} upper;
258
+};
259
+
260
+/* Offload Context Descriptor */
261
+struct e1000_context_desc {
262
+	union {
263
+		__le32 ip_config;
264
+		struct {
265
+			u8 ipcss;         /* IP checksum start */
266
+			u8 ipcso;         /* IP checksum offset */
267
+			__le16 ipcse;     /* IP checksum end */
268
+		} ip_fields;
269
+	} lower_setup;
270
+	union {
271
+		__le32 tcp_config;
272
+		struct {
273
+			u8 tucss;         /* TCP checksum start */
274
+			u8 tucso;         /* TCP checksum offset */
275
+			__le16 tucse;     /* TCP checksum end */
276
+		} tcp_fields;
277
+	} upper_setup;
278
+	__le32 cmd_and_length;
279
+	union {
280
+		__le32 data;
281
+		struct {
282
+			u8 status;        /* Descriptor status */
283
+			u8 hdr_len;       /* Header length */
284
+			__le16 mss;       /* Maximum segment size */
285
+		} fields;
286
+	} tcp_seg_setup;
287
+};
288
+
289
+/* Offload data descriptor */
290
+struct e1000_data_desc {
291
+	__le64 buffer_addr;   /* Address of the descriptor's buffer address */
292
+	union {
293
+		__le32 data;
294
+		struct {
295
+			__le16 length;    /* Data buffer length */
296
+			u8 typ_len_ext;
297
+			u8 cmd;
298
+		} flags;
299
+	} lower;
300
+	union {
301
+		__le32 data;
302
+		struct {
303
+			u8 status;        /* Descriptor status */
304
+			u8 popts;         /* Packet Options */
305
+			__le16 special;
306
+		} fields;
307
+	} upper;
308
+};
309
+
310
+/* Statistics counters collected by the MAC */
311
+struct e1000_hw_stats {
312
+	u64 crcerrs;
313
+	u64 algnerrc;
314
+	u64 symerrs;
315
+	u64 rxerrc;
316
+	u64 mpc;
317
+	u64 scc;
318
+	u64 ecol;
319
+	u64 mcc;
320
+	u64 latecol;
321
+	u64 colc;
322
+	u64 dc;
323
+	u64 tncrs;
324
+	u64 sec;
325
+	u64 cexterr;
326
+	u64 rlec;
327
+	u64 xonrxc;
328
+	u64 xontxc;
329
+	u64 xoffrxc;
330
+	u64 xofftxc;
331
+	u64 fcruc;
332
+	u64 prc64;
333
+	u64 prc127;
334
+	u64 prc255;
335
+	u64 prc511;
336
+	u64 prc1023;
337
+	u64 prc1522;
338
+	u64 gprc;
339
+	u64 bprc;
340
+	u64 mprc;
341
+	u64 gptc;
342
+	u64 gorc;
343
+	u64 gotc;
344
+	u64 rnbc;
345
+	u64 ruc;
346
+	u64 rfc;
347
+	u64 roc;
348
+	u64 rjc;
349
+	u64 mgprc;
350
+	u64 mgpdc;
351
+	u64 mgptc;
352
+	u64 tor;
353
+	u64 tot;
354
+	u64 tpr;
355
+	u64 tpt;
356
+	u64 ptc64;
357
+	u64 ptc127;
358
+	u64 ptc255;
359
+	u64 ptc511;
360
+	u64 ptc1023;
361
+	u64 ptc1522;
362
+	u64 mptc;
363
+	u64 bptc;
364
+	u64 tsctc;
365
+	u64 tsctfc;
366
+	u64 iac;
367
+	u64 icrxptc;
368
+	u64 icrxatc;
369
+	u64 ictxptc;
370
+	u64 ictxatc;
371
+	u64 ictxqec;
372
+	u64 ictxqmtc;
373
+	u64 icrxdmtc;
374
+	u64 icrxoc;
375
+	u64 cbtmpc;
376
+	u64 htdpmc;
377
+	u64 cbrdpc;
378
+	u64 cbrmpc;
379
+	u64 rpthc;
380
+	u64 hgptc;
381
+	u64 htcbdpc;
382
+	u64 hgorc;
383
+	u64 hgotc;
384
+	u64 lenerrs;
385
+	u64 scvpc;
386
+	u64 hrmpc;
387
+	u64 doosync;
388
+};
389
+
390
+
391
+struct e1000_phy_stats {
392
+	u32 idle_errors;
393
+	u32 receive_errors;
394
+};
395
+
396
+struct e1000_host_mng_dhcp_cookie {
397
+	u32 signature;
398
+	u8  status;
399
+	u8  reserved0;
400
+	u16 vlan_id;
401
+	u32 reserved1;
402
+	u16 reserved2;
403
+	u8  reserved3;
404
+	u8  checksum;
405
+};
406
+
407
+/* Host Interface "Rev 1" */
408
+struct e1000_host_command_header {
409
+	u8 command_id;
410
+	u8 command_length;
411
+	u8 command_options;
412
+	u8 checksum;
413
+};
414
+
415
+#define E1000_HI_MAX_DATA_LENGTH     252
416
+struct e1000_host_command_info {
417
+	struct e1000_host_command_header command_header;
418
+	u8 command_data[E1000_HI_MAX_DATA_LENGTH];
419
+};
420
+
421
+/* Host Interface "Rev 2" */
422
+struct e1000_host_mng_command_header {
423
+	u8  command_id;
424
+	u8  checksum;
425
+	u16 reserved1;
426
+	u16 reserved2;
427
+	u16 command_length;
428
+};
429
+
430
+#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
431
+struct e1000_host_mng_command_info {
432
+	struct e1000_host_mng_command_header command_header;
433
+	u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
434
+};
435
+
436
+#include "igb_mac.h"
437
+#include "igb_phy.h"
438
+#include "igb_nvm.h"
439
+#include "igb_manage.h"
440
+
441
+struct e1000_mac_operations {
442
+	/* Function pointers for the MAC. */
443
+	s32  (*init_params)(struct e1000_hw *);
444
+	s32  (*id_led_init)(struct e1000_hw *);
445
+	s32  (*blink_led)(struct e1000_hw *);
446
+	s32  (*check_for_link)(struct e1000_hw *);
447
+	bool (*check_mng_mode)(struct e1000_hw *hw);
448
+	s32  (*cleanup_led)(struct e1000_hw *);
449
+	void (*clear_hw_cntrs)(struct e1000_hw *);
450
+	void (*clear_vfta)(struct e1000_hw *);
451
+	s32  (*get_bus_info)(struct e1000_hw *);
452
+	void (*set_lan_id)(struct e1000_hw *);
453
+	s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
454
+	s32  (*led_on)(struct e1000_hw *);
455
+	s32  (*led_off)(struct e1000_hw *);
456
+	void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
457
+	s32  (*reset_hw)(struct e1000_hw *);
458
+	s32  (*init_hw)(struct e1000_hw *);
459
+	void (*shutdown_serdes)(struct e1000_hw *);
460
+	s32  (*setup_link)(struct e1000_hw *);
461
+	s32  (*setup_physical_interface)(struct e1000_hw *);
462
+	s32  (*setup_led)(struct e1000_hw *);
463
+	void (*write_vfta)(struct e1000_hw *, u32, u32);
464
+	void (*mta_set)(struct e1000_hw *, u32);
465
+	void (*config_collision_dist)(struct e1000_hw *);
466
+	void (*rar_set)(struct e1000_hw *, u8*, u32);
467
+	s32  (*read_mac_addr)(struct e1000_hw *);
468
+	s32  (*validate_mdi_setting)(struct e1000_hw *);
469
+	s32  (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
470
+	s32  (*mng_write_cmd_header)(struct e1000_hw *hw,
471
+                      struct e1000_host_mng_command_header*);
472
+	s32  (*mng_enable_host_if)(struct e1000_hw *);
473
+	s32  (*wait_autoneg)(struct e1000_hw *);
474
+};
475
+
476
+struct e1000_phy_operations {
477
+	s32  (*init_params)(struct e1000_hw *);
478
+	s32  (*acquire)(struct e1000_hw *);
479
+	s32  (*check_polarity)(struct e1000_hw *);
480
+	s32  (*check_reset_block)(struct e1000_hw *);
481
+	s32  (*commit)(struct e1000_hw *);
482
+#if 0
483
+	s32  (*force_speed_duplex)(struct e1000_hw *);
484
+#endif
485
+	s32  (*get_cfg_done)(struct e1000_hw *hw);
486
+#if 0
487
+	s32  (*get_cable_length)(struct e1000_hw *);
488
+#endif
489
+	s32  (*get_info)(struct e1000_hw *);
490
+	s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
491
+	s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
492
+	void (*release)(struct e1000_hw *);
493
+	s32  (*reset)(struct e1000_hw *);
494
+	s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
495
+	s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
496
+	s32  (*write_reg)(struct e1000_hw *, u32, u16);
497
+	s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
498
+	void (*power_up)(struct e1000_hw *);
499
+	void (*power_down)(struct e1000_hw *);
500
+};
501
+
502
+struct e1000_nvm_operations {
503
+	s32  (*init_params)(struct e1000_hw *);
504
+	s32  (*acquire)(struct e1000_hw *);
505
+	s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
506
+	void (*release)(struct e1000_hw *);
507
+	void (*reload)(struct e1000_hw *);
508
+	s32  (*update)(struct e1000_hw *);
509
+	s32  (*valid_led_default)(struct e1000_hw *, u16 *);
510
+	s32  (*validate)(struct e1000_hw *);
511
+	s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
512
+};
513
+
514
+struct e1000_mac_info {
515
+	struct e1000_mac_operations ops;
516
+	u8 addr[6];
517
+	u8 perm_addr[6];
518
+
519
+	enum e1000_mac_type type;
520
+
521
+	u32 collision_delta;
522
+	u32 ledctl_default;
523
+	u32 ledctl_mode1;
524
+	u32 ledctl_mode2;
525
+	u32 mc_filter_type;
526
+	u32 tx_packet_delta;
527
+	u32 txcw;
528
+
529
+	u16 current_ifs_val;
530
+	u16 ifs_max_val;
531
+	u16 ifs_min_val;
532
+	u16 ifs_ratio;
533
+	u16 ifs_step_size;
534
+	u16 mta_reg_count;
535
+	u16 uta_reg_count;
536
+
537
+	/* Maximum size of the MTA register table in all supported adapters */
538
+	#define MAX_MTA_REG 128
539
+	u32 mta_shadow[MAX_MTA_REG];
540
+	u16 rar_entry_count;
541
+
542
+	u8  forced_speed_duplex;
543
+
544
+	bool adaptive_ifs;
545
+	bool arc_subsystem_valid;
546
+	bool asf_firmware_present;
547
+	bool autoneg;
548
+	bool autoneg_failed;
549
+	bool get_link_status;
550
+	bool in_ifs_mode;
551
+	enum e1000_serdes_link_state serdes_link_state;
552
+	bool serdes_has_link;
553
+	bool tx_pkt_filtering;
554
+};
555
+
556
+struct e1000_phy_info {
557
+	struct e1000_phy_operations ops;
558
+	enum e1000_phy_type type;
559
+
560
+	enum e1000_1000t_rx_status local_rx;
561
+	enum e1000_1000t_rx_status remote_rx;
562
+	enum e1000_ms_type ms_type;
563
+	enum e1000_ms_type original_ms_type;
564
+	enum e1000_rev_polarity cable_polarity;
565
+	enum e1000_smart_speed smart_speed;
566
+
567
+	u32 addr;
568
+	u32 id;
569
+	u32 reset_delay_us; /* in usec */
570
+	u32 revision;
571
+
572
+	enum e1000_media_type media_type;
573
+
574
+	u16 autoneg_advertised;
575
+	u16 autoneg_mask;
576
+	u16 cable_length;
577
+	u16 max_cable_length;
578
+	u16 min_cable_length;
579
+
580
+	u8 mdix;
581
+
582
+	bool disable_polarity_correction;
583
+	bool is_mdix;
584
+	bool polarity_correction;
585
+	bool reset_disable;
586
+	bool speed_downgraded;
587
+	bool autoneg_wait_to_complete;
588
+};
589
+
590
+struct e1000_nvm_info {
591
+	struct e1000_nvm_operations ops;
592
+	enum e1000_nvm_type type;
593
+	enum e1000_nvm_override override;
594
+
595
+	u32 flash_bank_size;
596
+	u32 flash_base_addr;
597
+
598
+	u16 word_size;
599
+	u16 delay_usec;
600
+	u16 address_bits;
601
+	u16 opcode_bits;
602
+	u16 page_size;
603
+};
604
+
605
+struct e1000_bus_info {
606
+	enum e1000_bus_type type;
607
+	enum e1000_bus_speed speed;
608
+	enum e1000_bus_width width;
609
+
610
+	u16 func;
611
+	u16 pci_cmd_word;
612
+};
613
+
614
+struct e1000_fc_info {
615
+	u32 high_water;          /* Flow control high-water mark */
616
+	u32 low_water;           /* Flow control low-water mark */
617
+	u16 pause_time;          /* Flow control pause timer */
618
+	bool send_xon;           /* Flow control send XON */
619
+	bool strict_ieee;        /* Strict IEEE mode */
620
+	enum e1000_fc_mode current_mode; /* FC mode in effect */
621
+	enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
622
+};
623
+
624
+struct e1000_mbx_operations {
625
+	s32 (*init_params)(struct e1000_hw *hw);
626
+	s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
627
+	s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
628
+	s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
629
+	s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
630
+	s32 (*check_for_msg)(struct e1000_hw *, u16);
631
+	s32 (*check_for_ack)(struct e1000_hw *, u16);
632
+	s32 (*check_for_rst)(struct e1000_hw *, u16);
633
+};
634
+
635
+struct e1000_mbx_stats {
636
+	u32 msgs_tx;
637
+	u32 msgs_rx;
638
+
639
+	u32 acks;
640
+	u32 reqs;
641
+	u32 rsts;
642
+};
643
+
644
+struct e1000_mbx_info {
645
+	struct e1000_mbx_operations ops;
646
+	struct e1000_mbx_stats stats;
647
+	u32 timeout;
648
+	u32 usec_delay;
649
+	u16 size;
650
+};
651
+
652
+struct e1000_dev_spec_82575 {
653
+	bool sgmii_active;
654
+	bool global_device_reset;
655
+};
656
+
657
+struct e1000_dev_spec_vf {
658
+	u32	vf_number;
659
+	u32	v2p_mailbox;
660
+};
661
+
662
+
663
+struct e1000_hw {
664
+	void *back;
665
+
666
+	u8 __iomem *hw_addr;
667
+	u8 __iomem *flash_address;
668
+	unsigned long io_base;
669
+
670
+	struct e1000_mac_info  mac;
671
+	struct e1000_fc_info   fc;
672
+	struct e1000_phy_info  phy;
673
+	struct e1000_nvm_info  nvm;
674
+	struct e1000_bus_info  bus;
675
+	struct e1000_mbx_info mbx;
676
+	struct e1000_host_mng_dhcp_cookie mng_cookie;
677
+
678
+	union {
679
+		struct e1000_dev_spec_82575	_82575;
680
+		struct e1000_dev_spec_vf	vf;
681
+	} dev_spec;
682
+
683
+	u16 device_id;
684
+	u16 subsystem_vendor_id;
685
+	u16 subsystem_device_id;
686
+	u16 vendor_id;
687
+
688
+	u8  revision_id;
689
+};
690
+
691
+#include "igb_82575.h"
692
+
693
+/* These functions must be implemented by drivers */
694
+s32  igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
695
+s32  igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
696
+
697
+#endif /* _IGB_HW_H_ */

+ 1991
- 0
src/drivers/net/igb/igb_mac.c
Файловите разлики са ограничени, защото са твърде много
Целия файл


+ 82
- 0
src/drivers/net/igb/igb_mac.h Целия файл

@@ -0,0 +1,82 @@
1
+/*******************************************************************************
2
+
3
+  Intel(R) Gigabit Ethernet Linux driver
4
+  Copyright(c) 2007-2009 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
+
26
+*******************************************************************************/
27
+
28
+FILE_LICENCE ( GPL2_ONLY );
29
+
30
+#ifndef _IGB_MAC_H_
31
+#define _IGB_MAC_H_
32
+
33
+/*
34
+ * Functions that should not be called directly from drivers but can be used
35
+ * by other files in this 'shared code'
36
+ */
37
+void igb_init_mac_ops_generic(struct e1000_hw *hw);
38
+s32  igb_blink_led_generic(struct e1000_hw *hw);
39
+s32  igb_check_for_copper_link_generic(struct e1000_hw *hw);
40
+s32  igb_check_for_fiber_link_generic(struct e1000_hw *hw);
41
+s32  igb_check_for_serdes_link_generic(struct e1000_hw *hw);
42
+s32  igb_cleanup_led_generic(struct e1000_hw *hw);
43
+s32  igb_config_fc_after_link_up_generic(struct e1000_hw *hw);
44
+s32  igb_disable_pcie_master_generic(struct e1000_hw *hw);
45
+s32  igb_force_mac_fc_generic(struct e1000_hw *hw);
46
+s32  igb_get_auto_rd_done_generic(struct e1000_hw *hw);
47
+s32  igb_get_bus_info_pcie_generic(struct e1000_hw *hw);
48
+void igb_set_lan_id_single_port(struct e1000_hw *hw);
49
+s32  igb_get_hw_semaphore_generic(struct e1000_hw *hw);
50
+s32  igb_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
51
+                                               u16 *duplex);
52
+s32  igb_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
53
+                                                     u16 *speed, u16 *duplex);
54
+s32  igb_id_led_init_generic(struct e1000_hw *hw);
55
+s32  igb_led_on_generic(struct e1000_hw *hw);
56
+s32  igb_led_off_generic(struct e1000_hw *hw);
57
+void igb_update_mc_addr_list_generic(struct e1000_hw *hw,
58
+	                               u8 *mc_addr_list, u32 mc_addr_count);
59
+s32  igb_set_fc_watermarks_generic(struct e1000_hw *hw);
60
+s32  igb_setup_fiber_serdes_link_generic(struct e1000_hw *hw);
61
+s32  igb_setup_led_generic(struct e1000_hw *hw);
62
+s32  igb_setup_link_generic(struct e1000_hw *hw);
63
+s32  igb_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
64
+                                       u32 offset, u8 data);
65
+
66
+u32  igb_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr);
67
+
68
+void igb_clear_hw_cntrs_base_generic(struct e1000_hw *hw);
69
+void igb_clear_vfta_generic(struct e1000_hw *hw);
70
+void igb_config_collision_dist_generic(struct e1000_hw *hw);
71
+void igb_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count);
72
+void igb_mta_set_generic(struct e1000_hw *hw, u32 hash_value);
73
+void igb_pcix_mmrbc_workaround_generic(struct e1000_hw *hw);
74
+void igb_put_hw_semaphore_generic(struct e1000_hw *hw);
75
+void igb_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index);
76
+s32  igb_check_alt_mac_addr_generic(struct e1000_hw *hw);
77
+void igb_reset_adaptive_generic(struct e1000_hw *hw);
78
+void igb_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop);
79
+void igb_update_adaptive_generic(struct e1000_hw *hw);
80
+void igb_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value);
81
+
82
+#endif /* _IGB_MAC_H_ */

+ 1013
- 0
src/drivers/net/igb/igb_main.c
Файловите разлики са ограничени, защото са твърде много
Целия файл


+ 388
- 0
src/drivers/net/igb/igb_manage.c Целия файл

@@ -0,0 +1,388 @@
1
+/*******************************************************************************
2
+
3
+  Intel(R) Gigabit Ethernet Linux driver
4
+  Copyright(c) 2007-2009 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
+
26
+*******************************************************************************/
27
+
28
+FILE_LICENCE ( GPL2_ONLY );
29
+
30
+#include "igb.h"
31
+
32
+#if 0
33
+
34
+static u8 e1000_calculate_checksum(u8 *buffer, u32 length);
35
+
36
+/**
37
+ *  e1000_calculate_checksum - Calculate checksum for buffer
38
+ *  @buffer: pointer to EEPROM
39
+ *  @length: size of EEPROM to calculate a checksum for
40
+ *
41
+ *  Calculates the checksum for some buffer on a specified length.  The
42
+ *  checksum calculated is returned.
43
+ **/
44
+static u8 e1000_calculate_checksum(u8 *buffer, u32 length)
45
+{
46
+	u32 i;
47
+	u8  sum = 0;
48
+
49
+	DEBUGFUNC("igb_calculate_checksum");
50
+
51
+	if (!buffer)
52
+		return 0;
53
+
54
+	for (i = 0; i < length; i++)
55
+		sum += buffer[i];
56
+
57
+	return (u8) (0 - sum);
58
+}
59
+
60
+/**
61
+ *  e1000_mng_enable_host_if_generic - Checks host interface is enabled
62
+ *  @hw: pointer to the HW structure
63
+ *
64
+ *  Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
65
+ *
66
+ *  This function checks whether the HOST IF is enabled for command operation
67
+ *  and also checks whether the previous command is completed.  It busy waits
68
+ *  in case of previous command is not completed.
69
+ **/
70
+s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw)
71
+{
72
+	u32 hicr;
73
+	s32 ret_val = E1000_SUCCESS;
74
+	u8  i;
75
+
76
+	DEBUGFUNC("igb_mng_enable_host_if_generic");
77
+
78
+	/* Check that the host interface is enabled. */
79
+	hicr = E1000_READ_REG(hw, E1000_HICR);
80
+	if ((hicr & E1000_HICR_EN) == 0) {
81
+		DEBUGOUT("E1000_HOST_EN bit disabled.\n");
82
+		ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
83
+		goto out;
84
+	}
85
+	/* check the previous command is completed */
86
+	for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
87
+		hicr = E1000_READ_REG(hw, E1000_HICR);
88
+		if (!(hicr & E1000_HICR_C))
89
+			break;
90
+		msec_delay_irq(1);
91
+	}
92
+
93
+	if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
94
+		DEBUGOUT("Previous command timeout failed .\n");
95
+		ret_val = -E1000_ERR_HOST_INTERFACE_COMMAND;
96
+		goto out;
97
+	}
98
+
99
+out:
100
+	return ret_val;
101
+}
102
+
103
+/**
104
+ *  e1000_check_mng_mode_generic - Generic check management mode
105
+ *  @hw: pointer to the HW structure
106
+ *
107
+ *  Reads the firmware semaphore register and returns true (>0) if
108
+ *  manageability is enabled, else false (0).
109
+ **/
110
+bool e1000_check_mng_mode_generic(struct e1000_hw *hw)
111
+{
112
+	u32 fwsm;
113
+
114
+	DEBUGFUNC("igb_check_mng_mode_generic");
115
+
116
+	fwsm = E1000_READ_REG(hw, E1000_FWSM);
117
+
118
+	return (fwsm & E1000_FWSM_MODE_MASK) ==
119
+	        (E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
120
+}
121
+
122
+/**
123
+ *  e1000_enable_tx_pkt_filtering_generic - Enable packet filtering on TX
124
+ *  @hw: pointer to the HW structure
125
+ *
126
+ *  Enables packet filtering on transmit packets if manageability is enabled
127
+ *  and host interface is enabled.
128
+ **/
129
+bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw)
130
+{
131
+	struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
132
+	u32 *buffer = (u32 *)&hw->mng_cookie;
133
+	u32 offset;
134
+	s32 ret_val, hdr_csum, csum;
135
+	u8 i, len;
136
+	bool tx_filter = true;
137
+
138
+	DEBUGFUNC("igb_enable_tx_pkt_filtering_generic");
139
+
140
+	/* No manageability, no filtering */
141
+	if (!hw->mac.ops.check_mng_mode(hw)) {
142
+		tx_filter = false;
143
+		goto out;
144
+	}
145
+
146
+	/*
147
+	 * If we can't read from the host interface for whatever
148
+	 * reason, disable filtering.
149
+	 */
150
+	ret_val = hw->mac.ops.mng_enable_host_if(hw);
151
+	if (ret_val != E1000_SUCCESS) {
152
+		tx_filter = false;
153
+		goto out;
154
+	}
155
+
156
+	/* Read in the header.  Length and offset are in dwords. */
157
+	len    = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
158
+	offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
159
+	for (i = 0; i < len; i++) {
160
+		*(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw,
161
+		                                           E1000_HOST_IF,
162
+		                                           offset + i);
163
+	}
164
+	hdr_csum = hdr->checksum;
165
+	hdr->checksum = 0;
166
+	csum = e1000_calculate_checksum((u8 *)hdr,
167
+	                                E1000_MNG_DHCP_COOKIE_LENGTH);
168
+	/*
169
+	 * If either the checksums or signature don't match, then
170
+	 * the cookie area isn't considered valid, in which case we
171
+	 * take the safe route of assuming Tx filtering is enabled.
172
+	 */
173
+	if (hdr_csum != csum)
174
+		goto out;
175
+	if (hdr->signature != E1000_IAMT_SIGNATURE)
176
+		goto out;
177
+
178
+	/* Cookie area is valid, make the final check for filtering. */
179
+	if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))
180
+		tx_filter = false;
181
+
182
+out:
183
+	hw->mac.tx_pkt_filtering = tx_filter;
184
+	return tx_filter;
185
+}
186
+
187
+/**
188
+ *  e1000_mng_write_dhcp_info_generic - Writes DHCP info to host interface
189
+ *  @hw: pointer to the HW structure
190
+ *  @buffer: pointer to the host interface
191
+ *  @length: size of the buffer
192
+ *
193
+ *  Writes the DHCP information to the host interface.
194
+ **/
195
+s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, u8 *buffer,
196
+                                      u16 length)
197
+{
198
+	struct e1000_host_mng_command_header hdr;
199
+	s32 ret_val;
200
+	u32 hicr;
201
+
202
+	DEBUGFUNC("igb_mng_write_dhcp_info_generic");
203
+
204
+	hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
205
+	hdr.command_length = length;
206
+	hdr.reserved1 = 0;
207
+	hdr.reserved2 = 0;
208
+	hdr.checksum = 0;
209
+
210
+	/* Enable the host interface */
211
+	ret_val = hw->mac.ops.mng_enable_host_if(hw);
212
+	if (ret_val)
213
+		goto out;
214
+
215
+	/* Populate the host interface with the contents of "buffer". */
216
+	ret_val = hw->mac.ops.mng_host_if_write(hw, buffer, length,
217
+	                                  sizeof(hdr), &(hdr.checksum));
218
+	if (ret_val)
219
+		goto out;
220
+
221
+	/* Write the manageability command header */
222
+	ret_val = hw->mac.ops.mng_write_cmd_header(hw, &hdr);
223
+	if (ret_val)
224
+		goto out;
225
+
226
+	/* Tell the ARC a new command is pending. */
227
+	hicr = E1000_READ_REG(hw, E1000_HICR);
228
+	E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
229
+
230
+out:
231
+	return ret_val;
232
+}
233
+
234
+/**
235
+ *  e1000_mng_write_cmd_header_generic - Writes manageability command header
236
+ *  @hw: pointer to the HW structure
237
+ *  @hdr: pointer to the host interface command header
238
+ *
239
+ *  Writes the command header after does the checksum calculation.
240
+ **/
241
+s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
242
+                                    struct e1000_host_mng_command_header *hdr)
243
+{
244
+	u16 i, length = sizeof(struct e1000_host_mng_command_header);
245
+
246
+	DEBUGFUNC("igb_mng_write_cmd_header_generic");
247
+
248
+	/* Write the whole command header structure with new checksum. */
249
+
250
+	hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
251
+
252
+	length >>= 2;
253
+	/* Write the relevant command block into the ram area. */
254
+	for (i = 0; i < length; i++) {
255
+		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
256
+		                            *((u32 *) hdr + i));
257
+		E1000_WRITE_FLUSH(hw);
258
+	}
259
+
260
+	return E1000_SUCCESS;
261
+}
262
+
263
+/**
264
+ *  e1000_mng_host_if_write_generic - Write to the manageability host interface
265
+ *  @hw: pointer to the HW structure
266
+ *  @buffer: pointer to the host interface buffer
267
+ *  @length: size of the buffer
268
+ *  @offset: location in the buffer to write to
269
+ *  @sum: sum of the data (not checksum)
270
+ *
271
+ *  This function writes the buffer content at the offset given on the host if.
272
+ *  It also does alignment considerations to do the writes in most efficient
273
+ *  way.  Also fills up the sum of the buffer in *buffer parameter.
274
+ **/
275
+s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
276
+                                    u16 length, u16 offset, u8 *sum)
277
+{
278
+	u8 *tmp;
279
+	u8 *bufptr = buffer;
280
+	u32 data = 0;
281
+	s32 ret_val = E1000_SUCCESS;
282
+	u16 remaining, i, j, prev_bytes;
283
+
284
+	DEBUGFUNC("igb_mng_host_if_write_generic");
285
+
286
+	/* sum = only sum of the data and it is not checksum */
287
+
288
+	if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
289
+		ret_val = -E1000_ERR_PARAM;
290
+		goto out;
291
+	}
292
+
293
+	tmp = (u8 *)&data;
294
+	prev_bytes = offset & 0x3;
295
+	offset >>= 2;
296
+
297
+	if (prev_bytes) {
298
+		data = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset);
299
+		for (j = prev_bytes; j < sizeof(u32); j++) {
300
+			*(tmp + j) = *bufptr++;
301
+			*sum += *(tmp + j);
302
+		}
303
+		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset, data);
304
+		length -= j - prev_bytes;
305
+		offset++;
306
+	}
307
+
308
+	remaining = length & 0x3;
309
+	length -= remaining;
310
+
311
+	/* Calculate length in DWORDs */
312
+	length >>= 2;
313
+
314
+	/*
315
+	 * The device driver writes the relevant command block into the
316
+	 * ram area.
317
+	 */
318
+	for (i = 0; i < length; i++) {
319
+		for (j = 0; j < sizeof(u32); j++) {
320
+			*(tmp + j) = *bufptr++;
321
+			*sum += *(tmp + j);
322
+		}
323
+
324
+		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
325
+		                            data);
326
+	}
327
+	if (remaining) {
328
+		for (j = 0; j < sizeof(u32); j++) {
329
+			if (j < remaining)
330
+				*(tmp + j) = *bufptr++;
331
+			else
332
+				*(tmp + j) = 0;
333
+
334
+			*sum += *(tmp + j);
335
+		}
336
+		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i, data);
337
+	}
338
+
339
+out:
340
+	return ret_val;
341
+}
342
+
343
+/**
344
+ *  e1000_enable_mng_pass_thru - Enable processing of ARP's
345
+ *  @hw: pointer to the HW structure
346
+ *
347
+ *  Verifies the hardware needs to allow ARPs to be processed by the host.
348
+ **/
349
+bool e1000_enable_mng_pass_thru(struct e1000_hw *hw)
350
+{
351
+	u32 manc;
352
+	u32 fwsm, factps;
353
+	bool ret_val = false;
354
+
355
+	DEBUGFUNC("igb_enable_mng_pass_thru");
356
+
357
+	if (!hw->mac.asf_firmware_present)
358
+		goto out;
359
+
360
+	manc = E1000_READ_REG(hw, E1000_MANC);
361
+
362
+	if (!(manc & E1000_MANC_RCV_TCO_EN) ||
363
+	    !(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
364
+		goto out;
365
+
366
+	if (hw->mac.arc_subsystem_valid) {
367
+		fwsm = E1000_READ_REG(hw, E1000_FWSM);
368
+		factps = E1000_READ_REG(hw, E1000_FACTPS);
369
+
370
+		if (!(factps & E1000_FACTPS_MNGCG) &&
371
+		    ((fwsm & E1000_FWSM_MODE_MASK) ==
372
+		     (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
373
+			ret_val = true;
374
+			goto out;
375
+		}
376
+	} else {
377
+		if ((manc & E1000_MANC_SMBUS_EN) &&
378
+		    !(manc & E1000_MANC_ASF_EN)) {
379
+			ret_val = true;
380
+			goto out;
381
+		}
382
+	}
383
+
384
+out:
385
+	return ret_val;
386
+}
387
+
388
+#endif

+ 83
- 0
src/drivers/net/igb/igb_manage.h Целия файл

@@ -0,0 +1,83 @@
1
+/*******************************************************************************
2
+
3
+  Intel(R) Gigabit Ethernet Linux driver
4
+  Copyright(c) 2007-2009 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
+
26
+*******************************************************************************/
27
+
28
+FILE_LICENCE ( GPL2_ONLY );
29
+
30
+#ifndef _IGB_MANAGE_H_
31
+#define _IGB_MANAGE_H_
32
+
33
+bool e1000_check_mng_mode_generic(struct e1000_hw *hw);
34
+bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw);
35
+s32  e1000_mng_enable_host_if_generic(struct e1000_hw *hw);
36
+s32  e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
37
+                                     u16 length, u16 offset, u8 *sum);
38
+s32  e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
39
+                                    struct e1000_host_mng_command_header *hdr);
40
+s32  e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw,
41
+                                       u8 *buffer, u16 length);
42
+bool e1000_enable_mng_pass_thru(struct e1000_hw *hw);
43
+
44
+enum e1000_mng_mode {
45
+	e1000_mng_mode_none = 0,
46
+	e1000_mng_mode_asf,
47
+	e1000_mng_mode_pt,
48
+	e1000_mng_mode_ipmi,
49
+	e1000_mng_mode_host_if_only
50
+};
51
+
52
+#define E1000_FACTPS_MNGCG    0x20000000
53
+
54
+#define E1000_FWSM_MODE_MASK  0xE
55
+#define E1000_FWSM_MODE_SHIFT 1
56
+
57
+#define E1000_MNG_IAMT_MODE                  0x3
58
+#define E1000_MNG_DHCP_COOKIE_LENGTH         0x10
59
+#define E1000_MNG_DHCP_COOKIE_OFFSET         0x6F0
60
+#define E1000_MNG_DHCP_COMMAND_TIMEOUT       10
61
+#define E1000_MNG_DHCP_TX_PAYLOAD_CMD        64
62
+#define E1000_MNG_DHCP_COOKIE_STATUS_PARSING 0x1
63
+#define E1000_MNG_DHCP_COOKIE_STATUS_VLAN    0x2
64
+
65
+#define E1000_VFTA_ENTRY_SHIFT               5
66
+#define E1000_VFTA_ENTRY_MASK                0x7F
67
+#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK      0x1F
68
+
69
+#define E1000_HI_MAX_BLOCK_BYTE_LENGTH       1792 /* Num of bytes in range */
70
+#define E1000_HI_MAX_BLOCK_DWORD_LENGTH      448 /* Num of dwords in range */
71
+#define E1000_HI_COMMAND_TIMEOUT             500 /* Process HI command limit */
72
+
73
+#define E1000_HICR_EN              0x01  /* Enable bit - RO */
74
+/* Driver sets this bit when done to put command in RAM */
75
+#define E1000_HICR_C               0x02
76
+#define E1000_HICR_SV              0x04  /* Status Validity */
77
+#define E1000_HICR_FW_RESET_ENABLE 0x40
78
+#define E1000_HICR_FW_RESET        0x80
79
+
80
+/* Intel(R) Active Management Technology signature */
81
+#define E1000_IAMT_SIGNATURE  0x544D4149
82
+
83
+#endif /* _IGB_MANAGE_H_ */

+ 627
- 0
src/drivers/net/igb/igb_nvm.c Целия файл

@@ -0,0 +1,627 @@
1
+/*******************************************************************************
2
+
3
+  Intel(R) Gigabit Ethernet Linux driver
4
+  Copyright(c) 2007-2009 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
+
26
+*******************************************************************************/
27
+
28
+FILE_LICENCE ( GPL2_ONLY );
29
+
30
+#include "igb.h"
31
+
32
+static void igb_stop_nvm(struct e1000_hw *hw);
33
+static void igb_reload_nvm_generic(struct e1000_hw *hw);
34
+
35
+/**
36
+ *  igb_init_nvm_ops_generic - Initialize NVM function pointers
37
+ *  @hw: pointer to the HW structure
38
+ *
39
+ *  Setups up the function pointers to no-op functions
40
+ **/
41
+void igb_init_nvm_ops_generic(struct e1000_hw *hw)
42
+{
43
+	struct e1000_nvm_info *nvm = &hw->nvm;
44
+	DEBUGFUNC("igb_init_nvm_ops_generic");
45
+
46
+	/* Initialize function pointers */
47
+	nvm->ops.reload = igb_reload_nvm_generic;
48
+}
49
+
50
+/**
51
+ *  igb_raise_eec_clk - Raise EEPROM clock
52
+ *  @hw: pointer to the HW structure
53
+ *  @eecd: pointer to the EEPROM
54
+ *
55
+ *  Enable/Raise the EEPROM clock bit.
56
+ **/
57
+static void igb_raise_eec_clk(struct e1000_hw *hw, u32 *eecd)
58
+{
59
+	*eecd = *eecd | E1000_EECD_SK;
60
+	E1000_WRITE_REG(hw, E1000_EECD, *eecd);
61
+	E1000_WRITE_FLUSH(hw);
62
+	usec_delay(hw->nvm.delay_usec);
63
+}
64
+
65
+/**
66
+ *  igb_lower_eec_clk - Lower EEPROM clock
67
+ *  @hw: pointer to the HW structure
68
+ *  @eecd: pointer to the EEPROM
69
+ *
70
+ *  Clear/Lower the EEPROM clock bit.
71
+ **/
72
+static void igb_lower_eec_clk(struct e1000_hw *hw, u32 *eecd)
73
+{
74
+	*eecd = *eecd & ~E1000_EECD_SK;
75
+	E1000_WRITE_REG(hw, E1000_EECD, *eecd);
76
+	E1000_WRITE_FLUSH(hw);
77
+	usec_delay(hw->nvm.delay_usec);
78
+}
79
+
80
+/**
81
+ *  igb_shift_out_eec_bits - Shift data bits our to the EEPROM
82
+ *  @hw: pointer to the HW structure
83
+ *  @data: data to send to the EEPROM
84
+ *  @count: number of bits to shift out
85
+ *
86
+ *  We need to shift 'count' bits out to the EEPROM.  So, the value in the
87
+ *  "data" parameter will be shifted out to the EEPROM one bit at a time.
88
+ *  In order to do this, "data" must be broken down into bits.
89
+ **/
90
+static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count)
91
+{
92
+	struct e1000_nvm_info *nvm = &hw->nvm;
93
+	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
94
+	u32 mask;
95
+
96
+	DEBUGFUNC("igb_shift_out_eec_bits");
97
+
98
+	mask = 0x01 << (count - 1);
99
+	if (nvm->type == e1000_nvm_eeprom_spi)
100
+		eecd |= E1000_EECD_DO;
101
+
102
+	do {
103
+		eecd &= ~E1000_EECD_DI;
104
+
105
+		if (data & mask)
106
+			eecd |= E1000_EECD_DI;
107
+
108
+		E1000_WRITE_REG(hw, E1000_EECD, eecd);
109
+		E1000_WRITE_FLUSH(hw);
110
+
111
+		usec_delay(nvm->delay_usec);
112
+
113
+		igb_raise_eec_clk(hw, &eecd);
114
+		igb_lower_eec_clk(hw, &eecd);
115
+
116
+		mask >>= 1;
117
+	} while (mask);
118
+
119
+	eecd &= ~E1000_EECD_DI;
120
+	E1000_WRITE_REG(hw, E1000_EECD, eecd);
121
+}
122
+
123
+/**
124
+ *  igb_shift_in_eec_bits - Shift data bits in from the EEPROM
125
+ *  @hw: pointer to the HW structure
126
+ *  @count: number of bits to shift in
127
+ *
128
+ *  In order to read a register from the EEPROM, we need to shift 'count' bits
129
+ *  in from the EEPROM.  Bits are "shifted in" by raising the clock input to
130
+ *  the EEPROM (setting the SK bit), and then reading the value of the data out
131
+ *  "DO" bit.  During this "shifting in" process the data in "DI" bit should
132
+ *  always be clear.
133
+ **/
134
+static u16 igb_shift_in_eec_bits(struct e1000_hw *hw, u16 count)
135
+{
136
+	u32 eecd;
137
+	u32 i;
138
+	u16 data;
139
+
140
+	DEBUGFUNC("igb_shift_in_eec_bits");
141
+
142
+	eecd = E1000_READ_REG(hw, E1000_EECD);
143
+
144
+	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
145
+	data = 0;
146
+
147
+	for (i = 0; i < count; i++) {
148
+		data <<= 1;
149
+		igb_raise_eec_clk(hw, &eecd);
150
+
151
+		eecd = E1000_READ_REG(hw, E1000_EECD);
152
+
153
+		eecd &= ~E1000_EECD_DI;
154
+		if (eecd & E1000_EECD_DO)
155
+			data |= 1;
156
+
157
+		igb_lower_eec_clk(hw, &eecd);
158
+	}
159
+
160
+	return data;
161
+}
162
+
163
+/**
164
+ *  igb_poll_eerd_eewr_done - Poll for EEPROM read/write completion
165
+ *  @hw: pointer to the HW structure
166
+ *  @ee_reg: EEPROM flag for polling
167
+ *
168
+ *  Polls the EEPROM status bit for either read or write completion based
169
+ *  upon the value of 'ee_reg'.
170
+ **/
171
+s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg)
172
+{
173
+	u32 attempts = 100000;
174
+	u32 i, reg = 0;
175
+	s32 ret_val = -E1000_ERR_NVM;
176
+
177
+	DEBUGFUNC("igb_poll_eerd_eewr_done");
178
+
179
+	for (i = 0; i < attempts; i++) {
180
+		if (ee_reg == E1000_NVM_POLL_READ)
181
+			reg = E1000_READ_REG(hw, E1000_EERD);
182
+		else
183
+			reg = E1000_READ_REG(hw, E1000_EEWR);
184
+
185
+		if (reg & E1000_NVM_RW_REG_DONE) {
186
+			ret_val = E1000_SUCCESS;
187
+			break;
188
+		}
189
+
190
+		usec_delay(5);
191
+	}
192
+
193
+	return ret_val;
194
+}
195
+
196
+/**
197
+ *  igb_acquire_nvm_generic - Generic request for access to EEPROM
198
+ *  @hw: pointer to the HW structure
199
+ *
200
+ *  Set the EEPROM access request bit and wait for EEPROM access grant bit.
201
+ *  Return successful if access grant bit set, else clear the request for
202
+ *  EEPROM access and return -E1000_ERR_NVM (-1).
203
+ **/
204
+s32 igb_acquire_nvm_generic(struct e1000_hw *hw)
205
+{
206
+	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
207
+	s32 timeout = E1000_NVM_GRANT_ATTEMPTS;
208
+	s32 ret_val = E1000_SUCCESS;
209
+
210
+	DEBUGFUNC("igb_acquire_nvm_generic");
211
+
212
+	E1000_WRITE_REG(hw, E1000_EECD, eecd | E1000_EECD_REQ);
213
+	eecd = E1000_READ_REG(hw, E1000_EECD);
214
+
215
+	while (timeout) {
216
+		if (eecd & E1000_EECD_GNT)
217
+			break;
218
+		usec_delay(5);
219
+		eecd = E1000_READ_REG(hw, E1000_EECD);
220
+		timeout--;
221
+	}
222
+
223
+	if (!timeout) {
224
+		eecd &= ~E1000_EECD_REQ;
225
+		E1000_WRITE_REG(hw, E1000_EECD, eecd);
226
+		DEBUGOUT("Could not acquire NVM grant\n");
227
+		ret_val = -E1000_ERR_NVM;
228
+	}
229
+
230
+	return ret_val;
231
+}
232
+
233
+/**
234
+ *  igb_standby_nvm - Return EEPROM to standby state
235
+ *  @hw: pointer to the HW structure
236
+ *
237
+ *  Return the EEPROM to a standby state.
238
+ **/
239
+static void igb_standby_nvm(struct e1000_hw *hw)
240
+{
241
+	struct e1000_nvm_info *nvm = &hw->nvm;
242
+	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
243
+
244
+	DEBUGFUNC("igb_standby_nvm");
245
+
246
+	if (nvm->type == e1000_nvm_eeprom_spi) {
247
+		/* Toggle CS to flush commands */
248
+		eecd |= E1000_EECD_CS;
249
+		E1000_WRITE_REG(hw, E1000_EECD, eecd);
250
+		E1000_WRITE_FLUSH(hw);
251
+		usec_delay(nvm->delay_usec);
252
+		eecd &= ~E1000_EECD_CS;
253
+		E1000_WRITE_REG(hw, E1000_EECD, eecd);
254
+		E1000_WRITE_FLUSH(hw);
255
+		usec_delay(nvm->delay_usec);
256
+	}
257
+}
258
+
259
+/**
260
+ *  igb_stop_nvm - Terminate EEPROM command
261
+ *  @hw: pointer to the HW structure
262
+ *
263
+ *  Terminates the current command by inverting the EEPROM's chip select pin.
264
+ **/
265
+static void igb_stop_nvm(struct e1000_hw *hw)
266
+{
267
+	u32 eecd;
268
+
269
+	DEBUGFUNC("igb_stop_nvm");
270
+
271
+	eecd = E1000_READ_REG(hw, E1000_EECD);
272
+	if (hw->nvm.type == e1000_nvm_eeprom_spi) {
273
+		/* Pull CS high */
274
+		eecd |= E1000_EECD_CS;
275
+		igb_lower_eec_clk(hw, &eecd);
276
+	}
277
+}
278
+
279
+/**
280
+ *  igb_release_nvm_generic - Release exclusive access to EEPROM
281
+ *  @hw: pointer to the HW structure
282
+ *
283
+ *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
284
+ **/
285
+void igb_release_nvm_generic(struct e1000_hw *hw)
286
+{
287
+	u32 eecd;
288
+
289
+	DEBUGFUNC("igb_release_nvm_generic");
290
+
291
+	igb_stop_nvm(hw);
292
+
293
+	eecd = E1000_READ_REG(hw, E1000_EECD);
294
+	eecd &= ~E1000_EECD_REQ;
295
+	E1000_WRITE_REG(hw, E1000_EECD, eecd);
296
+}
297
+
298
+/**
299
+ *  igb_ready_nvm_eeprom - Prepares EEPROM for read/write
300
+ *  @hw: pointer to the HW structure
301
+ *
302
+ *  Setups the EEPROM for reading and writing.
303
+ **/
304
+static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw)
305
+{
306
+	struct e1000_nvm_info *nvm = &hw->nvm;
307
+	u32 eecd = E1000_READ_REG(hw, E1000_EECD);
308
+	s32 ret_val = E1000_SUCCESS;
309
+	u16 timeout = 0;
310
+	u8 spi_stat_reg;
311
+
312
+	DEBUGFUNC("igb_ready_nvm_eeprom");
313
+
314
+	if (nvm->type == e1000_nvm_eeprom_spi) {
315
+		/* Clear SK and CS */
316
+		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
317
+		E1000_WRITE_REG(hw, E1000_EECD, eecd);
318
+		usec_delay(1);
319
+		timeout = NVM_MAX_RETRY_SPI;
320
+
321
+		/*
322
+		 * Read "Status Register" repeatedly until the LSB is cleared.
323
+		 * The EEPROM will signal that the command has been completed
324
+		 * by clearing bit 0 of the internal status register.  If it's
325
+		 * not cleared within 'timeout', then error out.
326
+		 */
327
+		while (timeout) {
328
+			igb_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI,
329
+			                         hw->nvm.opcode_bits);
330
+			spi_stat_reg = (u8)igb_shift_in_eec_bits(hw, 8);
331
+			if (!(spi_stat_reg & NVM_STATUS_RDY_SPI))
332
+				break;
333
+
334
+			usec_delay(5);
335
+			igb_standby_nvm(hw);
336
+			timeout--;
337
+		}
338
+
339
+		if (!timeout) {
340
+			DEBUGOUT("SPI NVM Status error\n");
341
+			ret_val = -E1000_ERR_NVM;
342
+			goto out;
343
+		}
344
+	}
345
+
346
+out:
347
+	return ret_val;
348
+}
349
+
350
+/**
351
+ *  igb_read_nvm_eerd - Reads EEPROM using EERD register
352
+ *  @hw: pointer to the HW structure
353
+ *  @offset: offset of word in the EEPROM to read
354
+ *  @words: number of words to read
355
+ *  @data: word read from the EEPROM
356
+ *
357
+ *  Reads a 16 bit word from the EEPROM using the EERD register.
358
+ **/
359
+s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
360
+{
361
+	struct e1000_nvm_info *nvm = &hw->nvm;
362
+	u32 i, eerd = 0;
363
+	s32 ret_val = E1000_SUCCESS;
364
+
365
+	DEBUGFUNC("igb_read_nvm_eerd");
366
+
367
+	/*
368
+	 * A check for invalid values:  offset too large, too many words,
369
+	 * too many words for the offset, and not enough words.
370
+	 */
371
+	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
372
+	    (words == 0)) {
373
+		DEBUGOUT("nvm parameter(s) out of bounds\n");
374
+		ret_val = -E1000_ERR_NVM;
375
+		goto out;
376
+	}
377
+
378
+	for (i = 0; i < words; i++) {
379
+		eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) +
380
+		       E1000_NVM_RW_REG_START;
381
+
382
+		E1000_WRITE_REG(hw, E1000_EERD, eerd);
383
+		ret_val = igb_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ);
384
+		if (ret_val)
385
+			break;
386
+
387
+		data[i] = (E1000_READ_REG(hw, E1000_EERD) >>
388
+		           E1000_NVM_RW_REG_DATA);
389
+	}
390
+
391
+out:
392
+	return ret_val;
393
+}
394
+
395
+/**
396
+ *  igb_write_nvm_spi - Write to EEPROM using SPI
397
+ *  @hw: pointer to the HW structure
398
+ *  @offset: offset within the EEPROM to be written to
399
+ *  @words: number of words to write
400
+ *  @data: 16 bit word(s) to be written to the EEPROM
401
+ *
402
+ *  Writes data to EEPROM at offset using SPI interface.
403
+ *
404
+ *  If e1000_update_nvm_checksum is not called after this function , the
405
+ *  EEPROM will most likely contain an invalid checksum.
406
+ **/
407
+s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data)
408
+{
409
+	struct e1000_nvm_info *nvm = &hw->nvm;
410
+	s32 ret_val;
411
+	u16 widx = 0;
412
+
413
+	DEBUGFUNC("igb_write_nvm_spi");
414
+
415
+	/*
416
+	 * A check for invalid values:  offset too large, too many words,
417
+	 * and not enough words.
418
+	 */
419
+	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
420
+	    (words == 0)) {
421
+		DEBUGOUT("nvm parameter(s) out of bounds\n");
422
+		ret_val = -E1000_ERR_NVM;
423
+		goto out;
424
+	}
425
+
426
+	ret_val = nvm->ops.acquire(hw);
427
+	if (ret_val)
428
+		goto out;
429
+
430
+	while (widx < words) {
431
+		u8 write_opcode = NVM_WRITE_OPCODE_SPI;
432
+
433
+		ret_val = igb_ready_nvm_eeprom(hw);
434
+		if (ret_val)
435
+			goto release;
436
+
437
+		igb_standby_nvm(hw);
438
+
439
+		/* Send the WRITE ENABLE command (8 bit opcode) */
440
+		igb_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI,
441
+		                         nvm->opcode_bits);
442
+
443
+		igb_standby_nvm(hw);
444
+
445
+		/*
446
+		 * Some SPI eeproms use the 8th address bit embedded in the
447
+		 * opcode
448
+		 */
449
+		if ((nvm->address_bits == 8) && (offset >= 128))
450
+			write_opcode |= NVM_A8_OPCODE_SPI;
451
+
452
+		/* Send the Write command (8-bit opcode + addr) */
453
+		igb_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);
454
+		igb_shift_out_eec_bits(hw, (u16)((offset + widx) * 2),
455
+		                         nvm->address_bits);
456
+
457
+		/* Loop to allow for up to whole page write of eeprom */
458
+		while (widx < words) {
459
+			u16 word_out = data[widx];
460
+			word_out = (word_out >> 8) | (word_out << 8);
461
+			igb_shift_out_eec_bits(hw, word_out, 16);
462
+			widx++;
463
+
464
+			if ((((offset + widx) * 2) % nvm->page_size) == 0) {
465
+				igb_standby_nvm(hw);
466
+				break;
467
+			}
468
+		}
469
+	}
470
+
471
+	msec_delay(10);
472
+release:
473
+	nvm->ops.release(hw);
474
+
475
+out:
476
+	return ret_val;
477
+}
478
+
479
+/**
480
+ *  igb_read_pba_num_generic - Read device part number
481
+ *  @hw: pointer to the HW structure
482
+ *  @pba_num: pointer to device part number
483
+ *
484
+ *  Reads the product board assembly (PBA) number from the EEPROM and stores
485
+ *  the value in pba_num.
486
+ **/
487
+s32 igb_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num)
488
+{
489
+	s32  ret_val;
490
+	u16 nvm_data;
491
+
492
+	DEBUGFUNC("igb_read_pba_num_generic");
493
+
494
+	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);
495
+	if (ret_val) {
496
+		DEBUGOUT("NVM Read Error\n");
497
+		goto out;
498
+	}
499
+	*pba_num = (u32)(nvm_data << 16);
500
+
501
+	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data);
502
+	if (ret_val) {
503
+		DEBUGOUT("NVM Read Error\n");
504
+		goto out;
505
+	}
506
+	*pba_num |= nvm_data;
507
+
508
+out:
509
+	return ret_val;
510
+}
511
+
512
+/**
513
+ *  igb_read_mac_addr_generic - Read device MAC address
514
+ *  @hw: pointer to the HW structure
515
+ *
516
+ *  Reads the device MAC address from the EEPROM and stores the value.
517
+ *  Since devices with two ports use the same EEPROM, we increment the
518
+ *  last bit in the MAC address for the second port.
519
+ **/
520
+s32 igb_read_mac_addr_generic(struct e1000_hw *hw)
521
+{
522
+	u32 rar_high;
523
+	u32 rar_low;
524
+	u16 i;
525
+
526
+	rar_high = E1000_READ_REG(hw, E1000_RAH(0));
527
+	rar_low = E1000_READ_REG(hw, E1000_RAL(0));
528
+
529
+	for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++)
530
+		hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));
531
+
532
+	for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++)
533
+		hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));
534
+
535
+	for (i = 0; i < ETH_ADDR_LEN; i++)
536
+		hw->mac.addr[i] = hw->mac.perm_addr[i];
537
+
538
+	return E1000_SUCCESS;
539
+}
540
+
541
+/**
542
+ *  igb_validate_nvm_checksum_generic - Validate EEPROM checksum
543
+ *  @hw: pointer to the HW structure
544
+ *
545
+ *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
546
+ *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
547
+ **/
548
+s32 igb_validate_nvm_checksum_generic(struct e1000_hw *hw)
549
+{
550
+	s32 ret_val = E1000_SUCCESS;
551
+	u16 checksum = 0;
552
+	u16 i, nvm_data;
553
+
554
+	DEBUGFUNC("igb_validate_nvm_checksum_generic");
555
+
556
+	for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) {
557
+		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
558
+		if (ret_val) {
559
+			DEBUGOUT("NVM Read Error\n");
560
+			goto out;
561
+		}
562
+		checksum += nvm_data;
563
+	}
564
+
565
+	if (checksum != (u16) NVM_SUM) {
566
+		DEBUGOUT("NVM Checksum Invalid\n");
567
+		ret_val = -E1000_ERR_NVM;
568
+		goto out;
569
+	}
570
+
571
+out:
572
+	return ret_val;
573
+}
574
+
575
+/**
576
+ *  igb_update_nvm_checksum_generic - Update EEPROM checksum
577
+ *  @hw: pointer to the HW structure
578
+ *
579
+ *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
580
+ *  up to the checksum.  Then calculates the EEPROM checksum and writes the
581
+ *  value to the EEPROM.
582
+ **/
583
+s32 igb_update_nvm_checksum_generic(struct e1000_hw *hw)
584
+{
585
+	s32  ret_val;
586
+	u16 checksum = 0;
587
+	u16 i, nvm_data;
588
+
589
+	DEBUGFUNC("igb_update_nvm_checksum");
590
+
591
+	for (i = 0; i < NVM_CHECKSUM_REG; i++) {
592
+		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
593
+		if (ret_val) {
594
+			DEBUGOUT("NVM Read Error while updating checksum.\n");
595
+			goto out;
596
+		}
597
+		checksum += nvm_data;
598
+	}
599
+	checksum = (u16) NVM_SUM - checksum;
600
+	ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);
601
+	if (ret_val) {
602
+		DEBUGOUT("NVM Write Error while updating checksum.\n");
603
+        }
604
+out:
605
+	return ret_val;
606
+}
607
+
608
+/**
609
+ *  igb_reload_nvm_generic - Reloads EEPROM
610
+ *  @hw: pointer to the HW structure
611
+ *
612
+ *  Reloads the EEPROM by setting the "Reinitialize from EEPROM" bit in the
613
+ *  extended control register.
614
+ **/
615
+static void igb_reload_nvm_generic(struct e1000_hw *hw)
616
+{
617
+	u32 ctrl_ext;
618
+
619
+	DEBUGFUNC("igb_reload_nvm_generic");
620
+
621
+	usec_delay(10);
622
+	ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
623
+	ctrl_ext |= E1000_CTRL_EXT_EE_RST;
624
+	E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
625
+	E1000_WRITE_FLUSH(hw);
626
+}
627
+

+ 52
- 0
src/drivers/net/igb/igb_nvm.h Целия файл

@@ -0,0 +1,52 @@
1
+/*******************************************************************************
2
+
3
+  Intel(R) Gigabit Ethernet Linux driver
4
+  Copyright(c) 2007-2009 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
+
26
+*******************************************************************************/
27
+
28
+FILE_LICENCE ( GPL2_ONLY );
29
+
30
+#ifndef _IGB_NVM_H_
31
+#define _IGB_NVM_H_
32
+
33
+void igb_init_nvm_ops_generic(struct e1000_hw *hw);
34
+s32  igb_acquire_nvm_generic(struct e1000_hw *hw);
35
+
36
+s32  igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg);
37
+s32  igb_read_mac_addr_generic(struct e1000_hw *hw);
38
+s32  igb_read_pba_num_generic(struct e1000_hw *hw, u32 *pba_num);
39
+s32  igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words,
40
+                         u16 *data);
41
+s32  igb_valid_led_default_generic(struct e1000_hw *hw, u16 *data);
42
+s32  igb_validate_nvm_checksum_generic(struct e1000_hw *hw);
43
+s32  igb_write_nvm_eewr(struct e1000_hw *hw, u16 offset,
44
+                          u16 words, u16 *data);
45
+s32  igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words,
46
+                         u16 *data);
47
+s32  igb_update_nvm_checksum_generic(struct e1000_hw *hw);
48
+void igb_release_nvm_generic(struct e1000_hw *hw);
49
+
50
+#define E1000_STM_OPCODE  0xDB00
51
+
52
+#endif /* _IGB_NVM_H_ */

+ 129
- 0
src/drivers/net/igb/igb_osdep.h Целия файл

@@ -0,0 +1,129 @@
1
+/*******************************************************************************
2
+
3
+  Intel(R) Gigabit Ethernet Linux driver
4
+  Copyright(c) 2007-2009 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
+
26
+*******************************************************************************/
27
+
28
+FILE_LICENCE ( GPL2_ONLY );
29
+
30
+/* glue for the OS independent part of e1000
31
+ * includes register access macros
32
+ */
33
+
34
+#ifndef _IGB_OSDEP_H_
35
+#define _IGB_OSDEP_H_
36
+
37
+/* Begin OS Dependencies */
38
+
39
+#define u8         unsigned char
40
+#define bool       boolean_t
41
+#define dma_addr_t unsigned long
42
+#define __le16     uint16_t
43
+#define __le32     uint32_t
44
+#define __le64     uint64_t
45
+
46
+#define __iomem
47
+#define __devinit
48
+
49
+#define msleep(x) mdelay(x)
50
+
51
+#define ETH_FCS_LEN 4
52
+
53
+typedef int spinlock_t;
54
+typedef enum {
55
+    false = 0,
56
+    true = 1
57
+} boolean_t;
58
+
59
+#define TRUE  1
60
+#define FALSE 0
61
+
62
+#define usec_delay(x) udelay(x)
63
+#define msec_delay(x) mdelay(x)
64
+#define msec_delay_irq(x) mdelay(x)
65
+
66
+/* End OS Dependencies */
67
+
68
+#define PCI_COMMAND_REGISTER   PCI_COMMAND
69
+#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
70
+#define ETH_ADDR_LEN           ETH_ALEN
71
+
72
+#ifdef __BIG_ENDIAN
73
+#define E1000_BIG_ENDIAN __BIG_ENDIAN
74
+#endif
75
+
76
+
77
+#define DEBUGOUT(S) if (0) { printf(S); }
78
+#define DEBUGOUT1(S, A...) if (0) { printf(S, A); }
79
+
80
+#define DEBUGFUNC(F) DEBUGOUT(F "\n")
81
+#define DEBUGOUT2 DEBUGOUT1
82
+#define DEBUGOUT3 DEBUGOUT2
83
+#define DEBUGOUT7 DEBUGOUT3
84
+
85
+#define E1000_REGISTER(a, reg) (reg)
86
+
87
+#define E1000_WRITE_REG(a, reg, value) do {  \
88
+                writel((value), ((a)->hw_addr + E1000_REGISTER(a, reg))); } while (0)
89
+
90
+#define E1000_READ_REG(a, reg) (readl((a)->hw_addr + E1000_REGISTER(a, reg)))
91
+
92
+#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) do { \
93
+          writel((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 2))); } while (0);
94
+
95
+#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
96
+    readl((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 2)))
97
+
98
+#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
99
+#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
100
+
101
+#define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
102
+    writew((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 1))))
103
+
104
+#define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
105
+    readw((a)->hw_addr + E1000_REGISTER(a, reg) + ((offset) << 1)))
106
+
107
+#define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
108
+    writeb((value), ((a)->hw_addr + E1000_REGISTER(a, reg) + (offset))))
109
+
110
+#define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
111
+    readb((a)->hw_addr + E1000_REGISTER(a, reg) + (offset)))
112
+
113
+#define E1000_WRITE_REG_IO(a, reg, offset) do { \
114
+    outl(reg, ((a)->io_base));                  \
115
+    outl(offset, ((a)->io_base + 4));      } while (0)
116
+
117
+#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS)
118
+
119
+#define E1000_WRITE_FLASH_REG(a, reg, value) ( \
120
+    writel((value), ((a)->flash_address + reg)))
121
+
122
+#define E1000_WRITE_FLASH_REG16(a, reg, value) ( \
123
+    writew((value), ((a)->flash_address + reg)))
124
+
125
+#define E1000_READ_FLASH_REG(a, reg) (readl((a)->flash_address + reg))
126
+
127
+#define E1000_READ_FLASH_REG16(a, reg) (readw((a)->flash_address + reg))
128
+
129
+#endif /* _IGB_OSDEP_H_ */

+ 2470
- 0
src/drivers/net/igb/igb_phy.c
Файловите разлики са ограничени, защото са твърде много
Целия файл


+ 171
- 0
src/drivers/net/igb/igb_phy.h Целия файл

@@ -0,0 +1,171 @@
1
+/*******************************************************************************
2
+
3
+  Intel(R) Gigabit Ethernet Linux driver
4
+  Copyright(c) 2007-2009 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
+
26
+*******************************************************************************/
27
+
28
+FILE_LICENCE ( GPL2_ONLY );
29
+
30
+#ifndef _IGB_PHY_H_
31
+#define _IGB_PHY_H_
32
+
33
+void igb_init_phy_ops_generic(struct e1000_hw *hw);
34
+s32  igb_check_downshift_generic(struct e1000_hw *hw);
35
+s32  igb_check_polarity_m88(struct e1000_hw *hw);
36
+s32  igb_check_polarity_igp(struct e1000_hw *hw);
37
+s32  igb_check_polarity_ife(struct e1000_hw *hw);
38
+s32  igb_check_reset_block_generic(struct e1000_hw *hw);
39
+s32  igb_copper_link_autoneg(struct e1000_hw *hw);
40
+s32  igb_copper_link_setup_igp(struct e1000_hw *hw);
41
+s32  igb_copper_link_setup_m88(struct e1000_hw *hw);
42
+#if 0
43
+s32  igb_phy_force_speed_duplex_igp(struct e1000_hw *hw);
44
+s32  igb_phy_force_speed_duplex_m88(struct e1000_hw *hw);
45
+s32  igb_phy_force_speed_duplex_ife(struct e1000_hw *hw);
46
+#endif
47
+#if 0
48
+s32  igb_get_cable_length_m88(struct e1000_hw *hw);
49
+s32  igb_get_cable_length_igp_2(struct e1000_hw *hw);
50
+#endif
51
+s32  igb_get_cfg_done_generic(struct e1000_hw *hw);
52
+s32  igb_get_phy_id(struct e1000_hw *hw);
53
+s32  igb_get_phy_info_igp(struct e1000_hw *hw);
54
+s32  igb_get_phy_info_m88(struct e1000_hw *hw);
55
+s32  igb_phy_sw_reset_generic(struct e1000_hw *hw);
56
+#if 0
57
+void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
58
+#endif
59
+s32  igb_phy_hw_reset_generic(struct e1000_hw *hw);
60
+s32  igb_phy_reset_dsp_generic(struct e1000_hw *hw);
61
+s32  igb_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);
62
+s32  igb_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);
63
+s32  igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
64
+s32  igb_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);
65
+s32  igb_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
66
+s32  igb_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active);
67
+s32  igb_setup_copper_link_generic(struct e1000_hw *hw);
68
+s32  igb_wait_autoneg_generic(struct e1000_hw *hw);
69
+s32  igb_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);
70
+s32  igb_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data);
71
+s32  igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
72
+s32  igb_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);
73
+s32  igb_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
74
+s32  igb_phy_reset_dsp(struct e1000_hw *hw);
75
+s32  igb_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
76
+                                u32 usec_interval, bool *success);
77
+s32  igb_phy_init_script_igp3(struct e1000_hw *hw);
78
+enum e1000_phy_type igb_get_phy_type_from_id(u32 phy_id);
79
+s32  igb_determine_phy_address(struct e1000_hw *hw);
80
+void igb_power_up_phy_copper(struct e1000_hw *hw);
81
+void igb_power_down_phy_copper(struct e1000_hw *hw);
82
+s32  igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
83
+s32  igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
84
+s32  igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
85
+s32  igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
86
+
87
+#define E1000_MAX_PHY_ADDR                4
88
+
89
+/* IGP01E1000 Specific Registers */
90
+#define IGP01E1000_PHY_PORT_CONFIG        0x10 /* Port Config */
91
+#define IGP01E1000_PHY_PORT_STATUS        0x11 /* Status */
92
+#define IGP01E1000_PHY_PORT_CTRL          0x12 /* Control */
93
+#define IGP01E1000_PHY_LINK_HEALTH        0x13 /* PHY Link Health */
94
+#define IGP01E1000_GMII_FIFO              0x14 /* GMII FIFO */
95
+#define IGP01E1000_PHY_CHANNEL_QUALITY    0x15 /* PHY Channel Quality */
96
+#define IGP02E1000_PHY_POWER_MGMT         0x19 /* Power Management */
97
+#define IGP01E1000_PHY_PAGE_SELECT        0x1F /* Page Select */
98
+#define BM_PHY_PAGE_SELECT                22   /* Page Select for BM */
99
+#define IGP_PAGE_SHIFT                    5
100
+#define PHY_REG_MASK                      0x1F
101
+
102
+#define IGP01E1000_PHY_PCS_INIT_REG       0x00B4
103
+#define IGP01E1000_PHY_POLARITY_MASK      0x0078
104
+
105
+#define IGP01E1000_PSCR_AUTO_MDIX         0x1000
106
+#define IGP01E1000_PSCR_FORCE_MDI_MDIX    0x2000 /* 0=MDI, 1=MDIX */
107
+
108
+#define IGP01E1000_PSCFR_SMART_SPEED      0x0080
109
+
110
+/* Enable flexible speed on link-up */
111
+#define IGP01E1000_GMII_FLEX_SPD          0x0010
112
+#define IGP01E1000_GMII_SPD               0x0020 /* Enable SPD */
113
+
114
+#define IGP02E1000_PM_SPD                 0x0001 /* Smart Power Down */
115
+#define IGP02E1000_PM_D0_LPLU             0x0002 /* For D0a states */
116
+#define IGP02E1000_PM_D3_LPLU             0x0004 /* For all other states */
117
+
118
+#define IGP01E1000_PLHR_SS_DOWNGRADE      0x8000
119
+
120
+#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
121
+#define IGP01E1000_PSSR_MDIX              0x0800
122
+#define IGP01E1000_PSSR_SPEED_MASK        0xC000
123
+#define IGP01E1000_PSSR_SPEED_1000MBPS    0xC000
124
+
125
+#define IGP02E1000_PHY_CHANNEL_NUM        4
126
+#define IGP02E1000_PHY_AGC_A              0x11B1
127
+#define IGP02E1000_PHY_AGC_B              0x12B1
128
+#define IGP02E1000_PHY_AGC_C              0x14B1
129
+#define IGP02E1000_PHY_AGC_D              0x18B1
130
+
131
+#define IGP02E1000_AGC_LENGTH_SHIFT       9   /* Course - 15:13, Fine - 12:9 */
132
+#define IGP02E1000_AGC_LENGTH_MASK        0x7F
133
+#define IGP02E1000_AGC_RANGE              15
134
+
135
+#define IGP03E1000_PHY_MISC_CTRL          0x1B
136
+#define IGP03E1000_PHY_MISC_DUPLEX_MANUAL_SET  0x1000 /* Manually Set Duplex */
137
+
138
+#define E1000_CABLE_LENGTH_UNDEFINED      0xFF
139
+
140
+#define E1000_KMRNCTRLSTA_OFFSET          0x001F0000
141
+#define E1000_KMRNCTRLSTA_OFFSET_SHIFT    16
142
+#define E1000_KMRNCTRLSTA_REN             0x00200000
143
+#define E1000_KMRNCTRLSTA_DIAG_OFFSET     0x3    /* Kumeran Diagnostic */
144
+#define E1000_KMRNCTRLSTA_TIMEOUTS        0x4    /* Kumeran Timeouts */
145
+#define E1000_KMRNCTRLSTA_INBAND_PARAM    0x9    /* Kumeran InBand Parameters */
146
+#define E1000_KMRNCTRLSTA_DIAG_NELPBK     0x1000 /* Nearend Loopback mode */
147
+
148
+#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
149
+#define IFE_PHY_SPECIAL_CONTROL     0x11 /* 100BaseTx PHY Special Control */
150
+#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Control */
151
+#define IFE_PHY_MDIX_CONTROL        0x1C /* MDI/MDI-X Control */
152
+
153
+/* IFE PHY Extended Status Control */
154
+#define IFE_PESC_POLARITY_REVERSED    0x0100
155
+
156
+/* IFE PHY Special Control */
157
+#define IFE_PSC_AUTO_POLARITY_DISABLE      0x0010
158
+#define IFE_PSC_FORCE_POLARITY             0x0020
159
+#define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100
160
+
161
+/* IFE PHY Special Control and LED Control */
162
+#define IFE_PSCL_PROBE_MODE            0x0020
163
+#define IFE_PSCL_PROBE_LEDS_OFF        0x0006 /* Force LEDs 0 and 2 off */
164
+#define IFE_PSCL_PROBE_LEDS_ON         0x0007 /* Force LEDs 0 and 2 on */
165
+
166
+/* IFE PHY MDIX Control */
167
+#define IFE_PMC_MDIX_STATUS      0x0020 /* 1=MDI-X, 0=MDI */
168
+#define IFE_PMC_FORCE_MDIX       0x0040 /* 1=force MDI-X, 0=force MDI */
169
+#define IFE_PMC_AUTO_MDIX        0x0080 /* 1=enable auto MDI/MDI-X, 0=disable */
170
+
171
+#endif /* _IGB_PHY_H_ */

+ 486
- 0
src/drivers/net/igb/igb_regs.h Целия файл

@@ -0,0 +1,486 @@
1
+/*******************************************************************************
2
+
3
+  Intel(R) Gigabit Ethernet Linux driver
4
+  Copyright(c) 2007-2009 Intel Corporation.
5
+
6
+  This program is free software; you can redistribute it and/or modify it
7
+  under the terms and conditions of the GNU General Public License,
8
+  version 2, as published by the Free Software Foundation.
9
+
10
+  This program is distributed in the hope it will be useful, but WITHOUT
11
+  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12
+  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13
+  more details.
14
+
15
+  You should have received a copy of the GNU General Public License along with
16
+  this program; if not, write to the Free Software Foundation, Inc.,
17
+  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
+
19
+  The full GNU General Public License is included in this distribution in
20
+  the file called "COPYING".
21
+
22
+  Contact Information:
23
+  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24
+  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
+
26
+*******************************************************************************/
27
+
28
+FILE_LICENCE ( GPL2_ONLY );
29
+
30
+#ifndef _IGB_REGS_H_
31
+#define _IGB_REGS_H_
32
+
33
+#define E1000_CTRL     0x00000  /* Device Control - RW */
34
+#define E1000_CTRL_DUP 0x00004  /* Device Control Duplicate (Shadow) - RW */
35
+#define E1000_STATUS   0x00008  /* Device Status - RO */
36
+#define E1000_EECD     0x00010  /* EEPROM/Flash Control - RW */
37
+#define E1000_EERD     0x00014  /* EEPROM Read - RW */
38
+#define E1000_CTRL_EXT 0x00018  /* Extended Device Control - RW */
39
+#define E1000_FLA      0x0001C  /* Flash Access - RW */
40
+#define E1000_MDIC     0x00020  /* MDI Control - RW */
41
+#define E1000_SCTL     0x00024  /* SerDes Control - RW */
42
+#define E1000_FCAL     0x00028  /* Flow Control Address Low - RW */
43
+#define E1000_FCAH     0x0002C  /* Flow Control Address High -RW */
44
+#define E1000_FEXT     0x0002C  /* Future Extended - RW */
45
+#define E1000_FEXTNVM  0x00028  /* Future Extended NVM - RW */
46
+#define E1000_FCT      0x00030  /* Flow Control Type - RW */
47
+#define E1000_CONNSW   0x00034  /* Copper/Fiber switch control - RW */
48
+#define E1000_VET      0x00038  /* VLAN Ether Type - RW */
49
+#define E1000_ICR      0x000C0  /* Interrupt Cause Read - R/clr */
50
+#define E1000_ITR      0x000C4  /* Interrupt Throttling Rate - RW */
51
+#define E1000_ICS      0x000C8  /* Interrupt Cause Set - WO */
52
+#define E1000_IMS      0x000D0  /* Interrupt Mask Set - RW */
53
+#define E1000_IMC      0x000D8  /* Interrupt Mask Clear - WO */
54
+#define E1000_IAM      0x000E0  /* Interrupt Acknowledge Auto Mask */
55
+#define E1000_RCTL     0x00100  /* Rx Control - RW */
56
+#define E1000_FCTTV    0x00170  /* Flow Control Transmit Timer Value - RW */
57
+#define E1000_TXCW     0x00178  /* Tx Configuration Word - RW */
58
+#define E1000_RXCW     0x00180  /* Rx Configuration Word - RO */
59
+#define E1000_EICR     0x01580  /* Ext. Interrupt Cause Read - R/clr */
60
+#define E1000_EITR(_n) (0x01680 + (0x4 * (_n)))
61
+#define E1000_EICS     0x01520  /* Ext. Interrupt Cause Set - W0 */
62
+#define E1000_EIMS     0x01524  /* Ext. Interrupt Mask Set/Read - RW */
63
+#define E1000_EIMC     0x01528  /* Ext. Interrupt Mask Clear - WO */
64
+#define E1000_EIAC     0x0152C  /* Ext. Interrupt Auto Clear - RW */
65
+#define E1000_EIAM     0x01530  /* Ext. Interrupt Ack Auto Clear Mask - RW */
66
+#define E1000_GPIE     0x01514  /* General Purpose Interrupt Enable - RW */
67
+#define E1000_IVAR0    0x01700  /* Interrupt Vector Allocation (array) - RW */
68
+#define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
69
+#define E1000_TCTL     0x00400  /* Tx Control - RW */
70
+#define E1000_TCTL_EXT 0x00404  /* Extended Tx Control - RW */
71
+#define E1000_TIPG     0x00410  /* Tx Inter-packet gap -RW */
72
+#define E1000_TBT      0x00448  /* Tx Burst Timer - RW */
73
+#define E1000_AIT      0x00458  /* Adaptive Interframe Spacing Throttle - RW */
74
+#define E1000_LEDCTL   0x00E00  /* LED Control - RW */
75
+#define E1000_EXTCNF_CTRL  0x00F00  /* Extended Configuration Control */
76
+#define E1000_EXTCNF_SIZE  0x00F08  /* Extended Configuration Size */
77
+#define E1000_PHY_CTRL     0x00F10  /* PHY Control Register in CSR */
78
+#define E1000_PBA      0x01000  /* Packet Buffer Allocation - RW */
79
+#define E1000_PBS      0x01008  /* Packet Buffer Size */
80
+#define E1000_EEMNGCTL 0x01010  /* MNG EEprom Control */
81
+#define E1000_EEARBC   0x01024  /* EEPROM Auto Read Bus Control */
82
+#define E1000_FLASHT   0x01028  /* FLASH Timer Register */
83
+#define E1000_EEWR     0x0102C  /* EEPROM Write Register - RW */
84
+#define E1000_FLSWCTL  0x01030  /* FLASH control register */
85
+#define E1000_FLSWDATA 0x01034  /* FLASH data register */
86
+#define E1000_FLSWCNT  0x01038  /* FLASH Access Counter */
87
+#define E1000_FLOP     0x0103C  /* FLASH Opcode Register */
88
+#define E1000_I2CCMD   0x01028  /* SFPI2C Command Register - RW */
89
+#define E1000_I2CPARAMS 0x0102C /* SFPI2C Parameters Register - RW */
90
+#define E1000_WDSTP    0x01040  /* Watchdog Setup - RW */
91
+#define E1000_SWDSTS   0x01044  /* SW Device Status - RW */
92
+#define E1000_FRTIMER  0x01048  /* Free Running Timer - RW */
93
+#define E1000_TCPTIMER 0x0104C  /* TCP Timer - RW */
94
+#define E1000_VPDDIAG  0x01060  /* VPD Diagnostic - RO */
95
+#define E1000_ICR_V2   0x01500  /* Interrupt Cause - new location - RC */
96
+#define E1000_ICS_V2   0x01504  /* Interrupt Cause Set - new location - WO */
97
+#define E1000_IMS_V2   0x01508  /* Interrupt Mask Set/Read - new location - RW */
98
+#define E1000_IMC_V2   0x0150C  /* Interrupt Mask Clear - new location - WO */
99
+#define E1000_IAM_V2   0x01510  /* Interrupt Ack Auto Mask - new location - RW */
100
+#define E1000_ERT      0x02008  /* Early Rx Threshold - RW */
101
+#define E1000_FCRTL    0x02160  /* Flow Control Receive Threshold Low - RW */
102
+#define E1000_FCRTH    0x02168  /* Flow Control Receive Threshold High - RW */
103
+#define E1000_PSRCTL   0x02170  /* Packet Split Receive Control - RW */
104
+#define E1000_RDFPCQ(_n)  (0x02430 + (0x4 * (_n)))
105
+#define E1000_PBRTH    0x02458  /* PB Rx Arbitration Threshold - RW */
106
+#define E1000_FCRTV    0x02460  /* Flow Control Refresh Timer Value - RW */
107
+/* Split and Replication Rx Control - RW */
108
+#define E1000_RDPUMB   0x025CC  /* DMA Rx Descriptor uC Mailbox - RW */
109
+#define E1000_RDPUAD   0x025D0  /* DMA Rx Descriptor uC Addr Command - RW */
110
+#define E1000_RDPUWD   0x025D4  /* DMA Rx Descriptor uC Data Write - RW */
111
+#define E1000_RDPURD   0x025D8  /* DMA Rx Descriptor uC Data Read - RW */
112
+#define E1000_RDPUCTL  0x025DC  /* DMA Rx Descriptor uC Control - RW */
113
+#define E1000_PBDIAG   0x02458  /* Packet Buffer Diagnostic - RW */
114
+#define E1000_RXPBS    0x02404  /* Rx Packet Buffer Size - RW */
115
+#define E1000_RDTR     0x02820  /* Rx Delay Timer - RW */
116
+#define E1000_RADV     0x0282C  /* Rx Interrupt Absolute Delay Timer - RW */
117
+/*
118
+ * Convenience macros
119
+ *
120
+ * Note: "_n" is the queue number of the register to be written to.
121
+ *
122
+ * Example usage:
123
+ * E1000_RDBAL_REG(current_rx_queue)
124
+ */
125
+#define E1000_RDBAL(_n)      ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \
126
+                                         (0x0C000 + ((_n) * 0x40)))
127
+#define E1000_RDBAH(_n)      ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \
128
+                                         (0x0C004 + ((_n) * 0x40)))
129
+#define E1000_RDLEN(_n)      ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \
130
+                                         (0x0C008 + ((_n) * 0x40)))
131
+#define E1000_SRRCTL(_n)     ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \
132
+                                         (0x0C00C + ((_n) * 0x40)))
133
+#define E1000_RDH(_n)        ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \
134
+                                         (0x0C010 + ((_n) * 0x40)))
135
+#define E1000_RXCTL(_n)      ((_n) < 4 ? (0x02814 + ((_n) * 0x100)) : \
136
+                                         (0x0C014 + ((_n) * 0x40)))
137
+#define E1000_DCA_RXCTRL(_n) E1000_RXCTL(_n)
138
+#define E1000_RDT(_n)        ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \
139
+                                         (0x0C018 + ((_n) * 0x40)))
140
+#define E1000_RXDCTL(_n)     ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \
141
+                                         (0x0C028 + ((_n) * 0x40)))
142
+#define E1000_RQDPC(_n)      ((_n) < 4 ? (0x02830 + ((_n) * 0x100)) : \
143
+                                         (0x0C030 + ((_n) * 0x40)))
144
+#define E1000_TDBAL(_n)      ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \
145
+                                         (0x0E000 + ((_n) * 0x40)))
146
+#define E1000_TDBAH(_n)      ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \
147
+                                         (0x0E004 + ((_n) * 0x40)))
148
+#define E1000_TDLEN(_n)      ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \
149
+                                         (0x0E008 + ((_n) * 0x40)))
150
+#define E1000_TDH(_n)        ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \
151
+                                         (0x0E010 + ((_n) * 0x40)))
152
+#define E1000_TXCTL(_n)      ((_n) < 4 ? (0x03814 + ((_n) * 0x100)) : \
153
+                                         (0x0E014 + ((_n) * 0x40)))
154
+#define E1000_DCA_TXCTRL(_n) E1000_TXCTL(_n)
155
+#define E1000_TDT(_n)        ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \
156
+                                         (0x0E018 + ((_n) * 0x40)))
157
+#define E1000_TXDCTL(_n)     ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \
158
+                                         (0x0E028 + ((_n) * 0x40)))
159
+#define E1000_TDWBAL(_n)     ((_n) < 4 ? (0x03838 + ((_n) * 0x100)) : \
160
+                                         (0x0E038 + ((_n) * 0x40)))
161
+#define E1000_TDWBAH(_n)     ((_n) < 4 ? (0x0383C + ((_n) * 0x100)) : \
162
+                                         (0x0E03C + ((_n) * 0x40)))
163
+#define E1000_TARC(_n)                   (0x03840 + ((_n) * 0x100))
164
+#define E1000_RSRPD    0x02C00  /* Rx Small Packet Detect - RW */
165
+#define E1000_RAID     0x02C08  /* Receive Ack Interrupt Delay - RW */
166
+#define E1000_TXDMAC   0x03000  /* Tx DMA Control - RW */
167
+#define E1000_KABGTXD  0x03004  /* AFE Band Gap Transmit Ref Data */
168
+#define E1000_PSRTYPE(_i)       (0x05480 + ((_i) * 4))
169
+#define E1000_RAL(_i)  (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
170
+                                       (0x054E0 + ((_i - 16) * 8)))
171
+#define E1000_RAH(_i)  (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
172
+                                       (0x054E4 + ((_i - 16) * 8)))
173
+#define E1000_IP4AT_REG(_i)     (0x05840 + ((_i) * 8))
174
+#define E1000_IP6AT_REG(_i)     (0x05880 + ((_i) * 4))
175
+#define E1000_WUPM_REG(_i)      (0x05A00 + ((_i) * 4))
176
+#define E1000_FFMT_REG(_i)      (0x09000 + ((_i) * 8))
177
+#define E1000_FFVT_REG(_i)      (0x09800 + ((_i) * 8))
178
+#define E1000_FFLT_REG(_i)      (0x05F00 + ((_i) * 8))
179
+#define E1000_PBSLAC   0x03100  /* Packet Buffer Slave Access Control */
180
+#define E1000_PBSLAD(_n)  (0x03110 + (0x4 * (_n)))  /* Packet Buffer DWORD (_n) */
181
+#define E1000_TXPBS    0x03404  /* Tx Packet Buffer Size - RW */
182
+#define E1000_TDFH     0x03410  /* Tx Data FIFO Head - RW */
183
+#define E1000_TDFT     0x03418  /* Tx Data FIFO Tail - RW */
184
+#define E1000_TDFHS    0x03420  /* Tx Data FIFO Head Saved - RW */
185
+#define E1000_TDFTS    0x03428  /* Tx Data FIFO Tail Saved - RW */
186
+#define E1000_TDFPC    0x03430  /* Tx Data FIFO Packet Count - RW */
187
+#define E1000_TDPUMB   0x0357C  /* DMA Tx Descriptor uC Mail Box - RW */
188
+#define E1000_TDPUAD   0x03580  /* DMA Tx Descriptor uC Addr Command - RW */
189
+#define E1000_TDPUWD   0x03584  /* DMA Tx Descriptor uC Data Write - RW */
190
+#define E1000_TDPURD   0x03588  /* DMA Tx Descriptor uC Data  Read  - RW */
191
+#define E1000_TDPUCTL  0x0358C  /* DMA Tx Descriptor uC Control - RW */
192
+#define E1000_DTXCTL   0x03590  /* DMA Tx Control - RW */
193
+#define E1000_DTXTCPFLGL 0x0359C /* DMA Tx Control flag low - RW */
194
+#define E1000_DTXTCPFLGH 0x035A0 /* DMA Tx Control flag high - RW */
195
+#define E1000_DTXMXSZRQ  0x03540 /* DMA Tx Max Total Allow Size Requests - RW */
196
+#define E1000_TIDV     0x03820  /* Tx Interrupt Delay Value - RW */
197
+#define E1000_TADV     0x0382C  /* Tx Interrupt Absolute Delay Val - RW */
198
+#define E1000_TSPMT    0x03830  /* TCP Segmentation PAD & Min Threshold - RW */
199
+#define E1000_CRCERRS  0x04000  /* CRC Error Count - R/clr */
200
+#define E1000_ALGNERRC 0x04004  /* Alignment Error Count - R/clr */
201
+#define E1000_SYMERRS  0x04008  /* Symbol Error Count - R/clr */
202
+#define E1000_RXERRC   0x0400C  /* Receive Error Count - R/clr */
203
+#define E1000_MPC      0x04010  /* Missed Packet Count - R/clr */
204
+#define E1000_SCC      0x04014  /* Single Collision Count - R/clr */
205
+#define E1000_ECOL     0x04018  /* Excessive Collision Count - R/clr */
206
+#define E1000_MCC      0x0401C  /* Multiple Collision Count - R/clr */
207
+#define E1000_LATECOL  0x04020  /* Late Collision Count - R/clr */
208
+#define E1000_COLC     0x04028  /* Collision Count - R/clr */
209
+#define E1000_DC       0x04030  /* Defer Count - R/clr */
210
+#define E1000_TNCRS    0x04034  /* Tx-No CRS - R/clr */
211
+#define E1000_SEC      0x04038  /* Sequence Error Count - R/clr */
212
+#define E1000_CEXTERR  0x0403C  /* Carrier Extension Error Count - R/clr */
213
+#define E1000_RLEC     0x04040  /* Receive Length Error Count - R/clr */
214
+#define E1000_XONRXC   0x04048  /* XON Rx Count - R/clr */
215
+#define E1000_XONTXC   0x0404C  /* XON Tx Count - R/clr */
216
+#define E1000_XOFFRXC  0x04050  /* XOFF Rx Count - R/clr */
217
+#define E1000_XOFFTXC  0x04054  /* XOFF Tx Count - R/clr */
218
+#define E1000_FCRUC    0x04058  /* Flow Control Rx Unsupported Count- R/clr */
219
+#define E1000_PRC64    0x0405C  /* Packets Rx (64 bytes) - R/clr */
220
+#define E1000_PRC127   0x04060  /* Packets Rx (65-127 bytes) - R/clr */
221
+#define E1000_PRC255   0x04064  /* Packets Rx (128-255 bytes) - R/clr */
222
+#define E1000_PRC511   0x04068  /* Packets Rx (255-511 bytes) - R/clr */
223
+#define E1000_PRC1023  0x0406C  /* Packets Rx (512-1023 bytes) - R/clr */
224
+#define E1000_PRC1522  0x04070  /* Packets Rx (1024-1522 bytes) - R/clr */
225
+#define E1000_GPRC     0x04074  /* Good Packets Rx Count - R/clr */
226
+#define E1000_BPRC     0x04078  /* Broadcast Packets Rx Count - R/clr */
227
+#define E1000_MPRC     0x0407C  /* Multicast Packets Rx Count - R/clr */
228
+#define E1000_GPTC     0x04080  /* Good Packets Tx Count - R/clr */
229
+#define E1000_GORCL    0x04088  /* Good Octets Rx Count Low - R/clr */
230
+#define E1000_GORCH    0x0408C  /* Good Octets Rx Count High - R/clr */
231
+#define E1000_GOTCL    0x04090  /* Good Octets Tx Count Low - R/clr */
232
+#define E1000_GOTCH    0x04094  /* Good Octets Tx Count High - R/clr */
233
+#define E1000_RNBC     0x040A0  /* Rx No Buffers Count - R/clr */
234
+#define E1000_RUC      0x040A4  /* Rx Undersize Count - R/clr */
235
+#define E1000_RFC      0x040A8  /* Rx Fragment Count - R/clr */
236
+#define E1000_ROC      0x040AC  /* Rx Oversize Count - R/clr */
237
+#define E1000_RJC      0x040B0  /* Rx Jabber Count - R/clr */
238
+#define E1000_MGTPRC   0x040B4  /* Management Packets Rx Count - R/clr */
239
+#define E1000_MGTPDC   0x040B8  /* Management Packets Dropped Count - R/clr */
240
+#define E1000_MGTPTC   0x040BC  /* Management Packets Tx Count - R/clr */
241
+#define E1000_TORL     0x040C0  /* Total Octets Rx Low - R/clr */
242
+#define E1000_TORH     0x040C4  /* Total Octets Rx High - R/clr */
243
+#define E1000_TOTL     0x040C8  /* Total Octets Tx Low - R/clr */
244
+#define E1000_TOTH     0x040CC  /* Total Octets Tx High - R/clr */
245
+#define E1000_TPR      0x040D0  /* Total Packets Rx - R/clr */
246
+#define E1000_TPT      0x040D4  /* Total Packets Tx - R/clr */
247
+#define E1000_PTC64    0x040D8  /* Packets Tx (64 bytes) - R/clr */
248
+#define E1000_PTC127   0x040DC  /* Packets Tx (65-127 bytes) - R/clr */
249
+#define E1000_PTC255   0x040E0  /* Packets Tx (128-255 bytes) - R/clr */
250
+#define E1000_PTC511   0x040E4  /* Packets Tx (256-511 bytes) - R/clr */
251
+#define E1000_PTC1023  0x040E8  /* Packets Tx (512-1023 bytes) - R/clr */
252
+#define E1000_PTC1522  0x040EC  /* Packets Tx (1024-1522 Bytes) - R/clr */
253
+#define E1000_MPTC     0x040F0  /* Multicast Packets Tx Count - R/clr */
254
+#define E1000_BPTC     0x040F4  /* Broadcast Packets Tx Count - R/clr */
255
+#define E1000_TSCTC    0x040F8  /* TCP Segmentation Context Tx - R/clr */
256
+#define E1000_TSCTFC   0x040FC  /* TCP Segmentation Context Tx Fail - R/clr */
257
+#define E1000_IAC      0x04100  /* Interrupt Assertion Count */
258
+#define E1000_ICRXPTC  0x04104  /* Interrupt Cause Rx Pkt Timer Expire Count */
259
+#define E1000_ICRXATC  0x04108  /* Interrupt Cause Rx Abs Timer Expire Count */
260
+#define E1000_ICTXPTC  0x0410C  /* Interrupt Cause Tx Pkt Timer Expire Count */
261
+#define E1000_ICTXATC  0x04110  /* Interrupt Cause Tx Abs Timer Expire Count */
262
+#define E1000_ICTXQEC  0x04118  /* Interrupt Cause Tx Queue Empty Count */
263
+#define E1000_ICTXQMTC 0x0411C  /* Interrupt Cause Tx Queue Min Thresh Count */
264
+#define E1000_ICRXDMTC 0x04120  /* Interrupt Cause Rx Desc Min Thresh Count */
265
+#define E1000_ICRXOC   0x04124  /* Interrupt Cause Receiver Overrun Count */
266
+
267
+#define E1000_LSECTXUT        0x04300  /* LinkSec Tx Untagged Packet Count - OutPktsUntagged */
268
+#define E1000_LSECTXPKTE      0x04304  /* LinkSec Encrypted Tx Packets Count - OutPktsEncrypted */
269
+#define E1000_LSECTXPKTP      0x04308  /* LinkSec Protected Tx Packet Count - OutPktsProtected */
270
+#define E1000_LSECTXOCTE      0x0430C  /* LinkSec Encrypted Tx Octets Count - OutOctetsEncrypted */
271
+#define E1000_LSECTXOCTP      0x04310  /* LinkSec Protected Tx Octets Count - OutOctetsProtected */
272
+#define E1000_LSECRXUT        0x04314  /* LinkSec Untagged non-Strict Rx Packet Count - InPktsUntagged/InPktsNoTag */
273
+#define E1000_LSECRXOCTD      0x0431C  /* LinkSec Rx Octets Decrypted Count - InOctetsDecrypted */
274
+#define E1000_LSECRXOCTV      0x04320  /* LinkSec Rx Octets Validated - InOctetsValidated */
275
+#define E1000_LSECRXBAD       0x04324  /* LinkSec Rx Bad Tag - InPktsBadTag */
276
+#define E1000_LSECRXNOSCI     0x04328  /* LinkSec Rx Packet No SCI Count - InPktsNoSci */
277
+#define E1000_LSECRXUNSCI     0x0432C  /* LinkSec Rx Packet Unknown SCI Count - InPktsUnknownSci */
278
+#define E1000_LSECRXUNCH      0x04330  /* LinkSec Rx Unchecked Packets Count - InPktsUnchecked */
279
+#define E1000_LSECRXDELAY     0x04340  /* LinkSec Rx Delayed Packet Count - InPktsDelayed */
280
+#define E1000_LSECRXLATE      0x04350  /* LinkSec Rx Late Packets Count - InPktsLate */
281
+#define E1000_LSECRXOK(_n)    (0x04360 + (0x04 * (_n))) /* LinkSec Rx Packet OK Count - InPktsOk */
282
+#define E1000_LSECRXINV(_n)   (0x04380 + (0x04 * (_n))) /* LinkSec Rx Invalid Count - InPktsInvalid */
283
+#define E1000_LSECRXNV(_n)    (0x043A0 + (0x04 * (_n))) /* LinkSec Rx Not Valid Count - InPktsNotValid */
284
+#define E1000_LSECRXUNSA      0x043C0  /* LinkSec Rx Unused SA Count - InPktsUnusedSa */
285
+#define E1000_LSECRXNUSA      0x043D0  /* LinkSec Rx Not Using SA Count - InPktsNotUsingSa */
286
+#define E1000_LSECTXCAP       0x0B000  /* LinkSec Tx Capabilities Register - RO */
287
+#define E1000_LSECRXCAP       0x0B300  /* LinkSec Rx Capabilities Register - RO */
288
+#define E1000_LSECTXCTRL      0x0B004  /* LinkSec Tx Control - RW */
289
+#define E1000_LSECRXCTRL      0x0B304  /* LinkSec Rx Control - RW */
290
+#define E1000_LSECTXSCL       0x0B008  /* LinkSec Tx SCI Low - RW */
291
+#define E1000_LSECTXSCH       0x0B00C  /* LinkSec Tx SCI High - RW */
292
+#define E1000_LSECTXSA        0x0B010  /* LinkSec Tx SA0 - RW */
293
+#define E1000_LSECTXPN0       0x0B018  /* LinkSec Tx SA PN 0 - RW */
294
+#define E1000_LSECTXPN1       0x0B01C  /* LinkSec Tx SA PN 1 - RW */
295
+#define E1000_LSECRXSCL       0x0B3D0  /* LinkSec Rx SCI Low - RW */
296
+#define E1000_LSECRXSCH       0x0B3E0  /* LinkSec Rx SCI High - RW */
297
+#define E1000_LSECTXKEY0(_n)  (0x0B020 + (0x04 * (_n))) /* LinkSec Tx 128-bit Key 0 - WO */
298
+#define E1000_LSECTXKEY1(_n)  (0x0B030 + (0x04 * (_n))) /* LinkSec Tx 128-bit Key 1 - WO */
299
+#define E1000_LSECRXSA(_n)    (0x0B310 + (0x04 * (_n))) /* LinkSec Rx SAs - RW */
300
+#define E1000_LSECRXPN(_n)    (0x0B330 + (0x04 * (_n))) /* LinkSec Rx SAs - RW */
301
+/*
302
+ * LinkSec Rx Keys  - where _n is the SA no. and _m the 4 dwords of the 128 bit
303
+ * key - RW.
304
+ */
305
+#define E1000_LSECRXKEY(_n, _m) (0x0B350 + (0x10 * (_n)) + (0x04 * (_m)))
306
+
307
+#define E1000_SSVPC             0x041A0  /* Switch Security Violation Packet Count */
308
+#define E1000_IPSCTRL           0xB430   /* IpSec Control Register */
309
+#define E1000_IPSRXCMD          0x0B408  /* IPSec Rx Command Register - RW */
310
+#define E1000_IPSRXIDX          0x0B400  /* IPSec Rx Index - RW */
311
+#define E1000_IPSRXIPADDR(_n)   (0x0B420+ (0x04 * (_n)))  /* IPSec Rx IPv4/v6 Address - RW */
312
+#define E1000_IPSRXKEY(_n)      (0x0B410 + (0x04 * (_n))) /* IPSec Rx 128-bit Key - RW */
313
+#define E1000_IPSRXSALT         0x0B404  /* IPSec Rx Salt - RW */
314
+#define E1000_IPSRXSPI          0x0B40C  /* IPSec Rx SPI - RW */
315
+#define E1000_IPSTXKEY(_n)      (0x0B460 + (0x04 * (_n))) /* IPSec Tx 128-bit Key - RW */
316
+#define E1000_IPSTXSALT         0x0B454  /* IPSec Tx Salt - RW */
317
+#define E1000_IPSTXIDX          0x0B450  /* IPSec Tx SA IDX - RW */
318
+#define E1000_PCS_CFG0    0x04200  /* PCS Configuration 0 - RW */
319
+#define E1000_PCS_LCTL    0x04208  /* PCS Link Control - RW */
320
+#define E1000_PCS_LSTAT   0x0420C  /* PCS Link Status - RO */
321
+#define E1000_CBTMPC      0x0402C  /* Circuit Breaker Tx Packet Count */
322
+#define E1000_HTDPMC      0x0403C  /* Host Transmit Discarded Packets */
323
+#define E1000_CBRDPC      0x04044  /* Circuit Breaker Rx Dropped Count */
324
+#define E1000_CBRMPC      0x040FC  /* Circuit Breaker Rx Packet Count */
325
+#define E1000_RPTHC       0x04104  /* Rx Packets To Host */
326
+#define E1000_HGPTC       0x04118  /* Host Good Packets Tx Count */
327
+#define E1000_HTCBDPC     0x04124  /* Host Tx Circuit Breaker Dropped Count */
328
+#define E1000_HGORCL      0x04128  /* Host Good Octets Received Count Low */
329
+#define E1000_HGORCH      0x0412C  /* Host Good Octets Received Count High */
330
+#define E1000_HGOTCL      0x04130  /* Host Good Octets Transmit Count Low */
331
+#define E1000_HGOTCH      0x04134  /* Host Good Octets Transmit Count High */
332
+#define E1000_LENERRS     0x04138  /* Length Errors Count */
333
+#define E1000_SCVPC       0x04228  /* SerDes/SGMII Code Violation Pkt Count */
334
+#define E1000_HRMPC       0x0A018  /* Header Redirection Missed Packet Count */
335
+#define E1000_PCS_ANADV   0x04218  /* AN advertisement - RW */
336
+#define E1000_PCS_LPAB    0x0421C  /* Link Partner Ability - RW */
337
+#define E1000_PCS_NPTX    0x04220  /* AN Next Page Transmit - RW */
338
+#define E1000_PCS_LPABNP  0x04224  /* Link Partner Ability Next Page - RW */
339
+#define E1000_1GSTAT_RCV  0x04228  /* 1GSTAT Code Violation Packet Count - RW */
340
+#define E1000_RXCSUM   0x05000  /* Rx Checksum Control - RW */
341
+#define E1000_RLPML    0x05004  /* Rx Long Packet Max Length */
342
+#define E1000_RFCTL    0x05008  /* Receive Filter Control*/
343
+#define E1000_MTA      0x05200  /* Multicast Table Array - RW Array */
344
+#define E1000_RA       0x05400  /* Receive Address - RW Array */
345
+#define E1000_RA2      0x054E0  /* 2nd half of receive address array - RW Array */
346
+#define E1000_VFTA     0x05600  /* VLAN Filter Table Array - RW Array */
347
+#define E1000_VT_CTL   0x0581C  /* VMDq Control - RW */
348
+#define E1000_VFQA0    0x0B000  /* VLAN Filter Queue Array 0 - RW Array */
349
+#define E1000_VFQA1    0x0B200  /* VLAN Filter Queue Array 1 - RW Array */
350
+#define E1000_WUC      0x05800  /* Wakeup Control - RW */
351
+#define E1000_WUFC     0x05808  /* Wakeup Filter Control - RW */
352
+#define E1000_WUS      0x05810  /* Wakeup Status - RO */
353
+#define E1000_MANC     0x05820  /* Management Control - RW */
354
+#define E1000_IPAV     0x05838  /* IP Address Valid - RW */
355
+#define E1000_IP4AT    0x05840  /* IPv4 Address Table - RW Array */
356
+#define E1000_IP6AT    0x05880  /* IPv6 Address Table - RW Array */
357
+#define E1000_WUPL     0x05900  /* Wakeup Packet Length - RW */
358
+#define E1000_WUPM     0x05A00  /* Wakeup Packet Memory - RO A */
359
+#define E1000_PBACL    0x05B68  /* MSIx PBA Clear - Read/Write 1's to clear */
360
+#define E1000_FFLT     0x05F00  /* Flexible Filter Length Table - RW Array */
361
+#define E1000_HOST_IF  0x08800  /* Host Interface */
362
+#define E1000_FFMT     0x09000  /* Flexible Filter Mask Table - RW Array */
363
+#define E1000_FFVT     0x09800  /* Flexible Filter Value Table - RW Array */
364
+#define E1000_FHFT(_n)  (0x09000 + (_n * 0x100)) /* Flexible Host Filter Table */
365
+#define E1000_FHFT_EXT(_n) (0x09A00 + (_n * 0x100)) /* Ext Flexible Host Filter Table */
366
+
367
+
368
+#define E1000_KMRNCTRLSTA 0x00034 /* MAC-PHY interface - RW */
369
+#define E1000_MDPHYA      0x0003C /* PHY address - RW */
370
+#define E1000_MANC2H      0x05860 /* Management Control To Host - RW */
371
+#define E1000_SW_FW_SYNC  0x05B5C /* Software-Firmware Synchronization - RW */
372
+#define E1000_CCMCTL      0x05B48 /* CCM Control Register */
373
+#define E1000_GIOCTL      0x05B44 /* GIO Analog Control Register */
374
+#define E1000_SCCTL       0x05B4C /* PCIc PLL Configuration Register */
375
+#define E1000_GCR         0x05B00 /* PCI-Ex Control */
376
+#define E1000_GCR2        0x05B64 /* PCI-Ex Control #2 */
377
+#define E1000_GSCL_1    0x05B10 /* PCI-Ex Statistic Control #1 */
378
+#define E1000_GSCL_2    0x05B14 /* PCI-Ex Statistic Control #2 */
379
+#define E1000_GSCL_3    0x05B18 /* PCI-Ex Statistic Control #3 */
380
+#define E1000_GSCL_4    0x05B1C /* PCI-Ex Statistic Control #4 */
381
+#define E1000_FACTPS    0x05B30 /* Function Active and Power State to MNG */
382
+#define E1000_SWSM      0x05B50 /* SW Semaphore */
383
+#define E1000_FWSM      0x05B54 /* FW Semaphore */
384
+#define E1000_SWSM2     0x05B58 /* Driver-only SW semaphore (not used by BOOT agents) */
385
+#define E1000_DCA_ID    0x05B70 /* DCA Requester ID Information - RO */
386
+#define E1000_DCA_CTRL  0x05B74 /* DCA Control - RW */
387
+#define E1000_FFLT_DBG  0x05F04 /* Debug Register */
388
+#define E1000_HICR      0x08F00 /* Host Interface Control */
389
+
390
+/* RSS registers */
391
+#define E1000_CPUVEC    0x02C10 /* CPU Vector Register - RW */
392
+#define E1000_MRQC      0x05818 /* Multiple Receive Control - RW */
393
+#define E1000_IMIR(_i)      (0x05A80 + ((_i) * 4))  /* Immediate Interrupt */
394
+#define E1000_IMIREXT(_i)   (0x05AA0 + ((_i) * 4))  /* Immediate Interrupt Ext*/
395
+#define E1000_IMIRVP    0x05AC0 /* Immediate Interrupt Rx VLAN Priority - RW */
396
+#define E1000_MSIXBM(_i)    (0x01600 + ((_i) * 4)) /* MSI-X Allocation Register
397
+                                                    * (_i) - RW */
398
+#define E1000_MSIXTADD(_i)  (0x0C000 + ((_i) * 0x10)) /* MSI-X Table entry addr
399
+                                                       * low reg - RW */
400
+#define E1000_MSIXTUADD(_i) (0x0C004 + ((_i) * 0x10)) /* MSI-X Table entry addr
401
+                                                       * upper reg - RW */
402
+#define E1000_MSIXTMSG(_i)  (0x0C008 + ((_i) * 0x10)) /* MSI-X Table entry
403
+                                                       * message reg - RW */
404
+#define E1000_MSIXVCTRL(_i) (0x0C00C + ((_i) * 0x10)) /* MSI-X Table entry
405
+                                                       * vector ctrl reg - RW */
406
+#define E1000_MSIXPBA    0x0E000 /* MSI-X Pending bit array */
407
+#define E1000_RETA(_i)  (0x05C00 + ((_i) * 4)) /* Redirection Table - RW */
408
+#define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* RSS Random Key - RW */
409
+#define E1000_RSSIM     0x05864 /* RSS Interrupt Mask */
410
+#define E1000_RSSIR     0x05868 /* RSS Interrupt Request */
411
+/* VT Registers */
412
+#define E1000_SWPBS     0x03004 /* Switch Packet Buffer Size - RW */
413
+#define E1000_MBVFICR   0x00C80 /* Mailbox VF Cause - RWC */
414
+#define E1000_MBVFIMR   0x00C84 /* Mailbox VF int Mask - RW */
415
+#define E1000_VFLRE     0x00C88 /* VF Register Events - RWC */
416
+#define E1000_VFRE      0x00C8C /* VF Receive Enables */
417
+#define E1000_VFTE      0x00C90 /* VF Transmit Enables */
418
+#define E1000_QDE       0x02408 /* Queue Drop Enable - RW */
419
+#define E1000_DTXSWC    0x03500 /* DMA Tx Switch Control - RW */
420
+#define E1000_RPLOLR    0x05AF0 /* Replication Offload - RW */
421
+#define E1000_UTA       0x0A000 /* Unicast Table Array - RW */
422
+#define E1000_IOVTCL    0x05BBC /* IOV Control Register */
423
+#define E1000_VMRCTL    0X05D80 /* Virtual Mirror Rule Control */
424
+/* These act per VF so an array friendly macro is used */
425
+#define E1000_V2PMAILBOX(_n)   (0x00C40 + (4 * (_n)))
426
+#define E1000_P2VMAILBOX(_n)   (0x00C00 + (4 * (_n)))
427
+#define E1000_VMBMEM(_n)       (0x00800 + (64 * (_n)))
428
+#define E1000_VFVMBMEM(_n)     (0x00800 + (_n))
429
+#define E1000_VMOLR(_n)        (0x05AD0 + (4 * (_n)))
430
+#define E1000_VLVF(_n)         (0x05D00 + (4 * (_n))) /* VLAN Virtual Machine
431
+                                                       * Filter - RW */
432
+/* Time Sync */
433
+#define E1000_TSYNCRXCTL 0x0B620 /* Rx Time Sync Control register - RW */
434
+#define E1000_TSYNCTXCTL 0x0B614 /* Tx Time Sync Control register - RW */
435
+#define E1000_TSYNCRXCFG 0x05F50 /* Time Sync Rx Configuration - RW */
436
+#define E1000_RXSTMPL    0x0B624 /* Rx timestamp Low - RO */
437
+#define E1000_RXSTMPH    0x0B628 /* Rx timestamp High - RO */
438
+#define E1000_RXSATRL    0x0B62C /* Rx timestamp attribute low - RO */
439
+#define E1000_RXSATRH    0x0B630 /* Rx timestamp attribute high - RO */
440
+#define E1000_TXSTMPL    0x0B618 /* Tx timestamp value Low - RO */
441
+#define E1000_TXSTMPH    0x0B61C /* Tx timestamp value High - RO */
442
+#define E1000_SYSTIML    0x0B600 /* System time register Low - RO */
443
+#define E1000_SYSTIMH    0x0B604 /* System time register High - RO */
444
+#define E1000_TIMINCA    0x0B608 /* Increment attributes register - RW */
445
+
446
+/* Filtering Registers */
447
+#define E1000_SAQF(_n)  (0x05980 + (4 * (_n))) /* Source Address Queue Fltr */
448
+#define E1000_DAQF(_n)  (0x059A0 + (4 * (_n))) /* Dest Address Queue Fltr */
449
+#define E1000_SPQF(_n)  (0x059C0 + (4 * (_n))) /* Source Port Queue Fltr */
450
+#define E1000_FTQF(_n)  (0x059E0 + (4 * (_n))) /* 5-tuple Queue Fltr */
451
+#define E1000_TTQF(_n)  (0x059E0 + (4 * (_n))) /* 2-tuple Queue Fltr */
452
+#define E1000_SYNQF(_n) (0x055FC + (4 * (_n))) /* SYN Packet Queue Fltr */
453
+#define E1000_ETQF(_n)  (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */
454
+
455
+#define E1000_RTTDCS            0x3600  /* Reedtown Tx Desc plane control and status */
456
+#define E1000_RTTPCS            0x3474  /* Reedtown Tx Packet Plane control and status */
457
+#define E1000_RTRPCS            0x2474  /* Rx packet plane control and status */
458
+#define E1000_RTRUP2TC          0x05AC4 /* Rx User Priority to Traffic Class */
459
+#define E1000_RTTUP2TC          0x0418  /* Transmit User Priority to Traffic Class */
460
+#define E1000_RTTDTCRC(_n)      (0x3610 + ((_n) * 4)) /* Tx Desc plane TC Rate-scheduler config */
461
+#define E1000_RTTPTCRC(_n)      (0x3480 + ((_n) * 4)) /* Tx Packet plane TC Rate-Scheduler Config */
462
+#define E1000_RTRPTCRC(_n)      (0x2480 + ((_n) * 4)) /* Rx Packet plane TC Rate-Scheduler Config */
463
+#define E1000_RTTDTCRS(_n)      (0x3630 + ((_n) * 4)) /* Tx Desc Plane TC Rate-Scheduler Status */
464
+#define E1000_RTTDTCRM(_n)      (0x3650 + ((_n) * 4)) /* Tx Desc Plane TC Rate-Scheduler MMW */
465
+#define E1000_RTTPTCRS(_n)      (0x34A0 + ((_n) * 4)) /* Tx Packet plane TC Rate-Scheduler Status */
466
+#define E1000_RTTPTCRM(_n)      (0x34C0 + ((_n) * 4)) /* Tx Packet plane TC Rate-scheduler MMW */
467
+#define E1000_RTRPTCRS(_n)      (0x24A0 + ((_n) * 4)) /* Rx Packet plane TC Rate-Scheduler Status */
468
+#define E1000_RTRPTCRM(_n)      (0x24C0 + ((_n) * 4)) /* Rx Packet plane TC Rate-Scheduler MMW */
469
+#define E1000_RTTDVMRM(_n)      (0x3670 + ((_n) * 4)) /* Tx Desc plane VM Rate-Scheduler MMW*/
470
+#define E1000_RTTBCNRM(_n)      (0x3690 + ((_n) * 4)) /* Tx BCN Rate-Scheduler MMW */
471
+#define E1000_RTTDQSEL          0x3604  /* Tx Desc Plane Queue Select */
472
+#define E1000_RTTDVMRC          0x3608  /* Tx Desc Plane VM Rate-Scheduler Config */
473
+#define E1000_RTTDVMRS          0x360C  /* Tx Desc Plane VM Rate-Scheduler Status */
474
+#define E1000_RTTBCNRC          0x36B0  /* Tx BCN Rate-Scheduler Config */
475
+#define E1000_RTTBCNRS          0x36B4  /* Tx BCN Rate-Scheduler Status */
476
+#define E1000_RTTBCNCR          0xB200  /* Tx BCN Control Register */
477
+#define E1000_RTTBCNTG          0x35A4  /* Tx BCN Tagging */
478
+#define E1000_RTTBCNCP          0xB208  /* Tx BCN Congestion point */
479
+#define E1000_RTRBCNCR          0xB20C  /* Rx BCN Control Register */
480
+#define E1000_RTTBCNRD          0x36B8  /* Tx BCN Rate Drift */
481
+#define E1000_PFCTOP            0x1080  /* Priority Flow Control Type and Opcode */
482
+#define E1000_RTTBCNIDX         0xB204  /* Tx BCN Congestion Point */
483
+#define E1000_RTTBCNACH         0x0B214 /* Tx BCN Control High */
484
+#define E1000_RTTBCNACL         0x0B210 /* Tx BCN Control Low */
485
+
486
+#endif /* _IGB_REGS_H_ */

+ 1
- 0
src/include/gpxe/errfile.h Целия файл

@@ -120,6 +120,7 @@ FILE_LICENCE ( GPL2_OR_LATER );
120 120
 #define ERRFILE_vxge_main	     ( ERRFILE_DRIVER | 0x00550000 )
121 121
 #define ERRFILE_vxge_config	     ( ERRFILE_DRIVER | 0x00560000 )
122 122
 #define ERRFILE_vxge_traffic	     ( ERRFILE_DRIVER | 0x00570000 )
123
+#define ERRFILE_igb_main	     ( ERRFILE_DRIVER | 0x00580000 )
123 124
 
124 125
 #define ERRFILE_scsi		     ( ERRFILE_DRIVER | 0x00700000 )
125 126
 #define ERRFILE_arbel		     ( ERRFILE_DRIVER | 0x00710000 )

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