Conjecture: The hardware issues 64-bit DMA writes of status descriptors, which some PCI bridges seem to split into two 32-bit writes in reverse order (i.e. dword 1 first). This means that we sometimes observe a partial status descriptor. Add an explicit check to ensure that the descriptor is complete before processing it. Also ensure that the RDS consumer counter is incremented only when we know that we have actually consumed an RX descriptor.tags/v0.9.4
|
|
||
1445 |
|
1445 |
|
1446 |
|
1446 |
|
1447 |
|
1447 |
|
1448 |
|
|
|
1449 |
|
|
|
1450 |
|
|
|
|
1448 |
|
|
|
1449 |
|
|
|
1450 |
|
|
|
1451 |
|
|
|
1452 |
|
|
|
1453 |
|
|
|
1454 |
|
|
|
1455 |
|
|
|
1456 |
|
|
|
1457 |
|
|
|
1458 |
|
|
|
1459 |
|
|
|
1460 |
|
|
|
1461 |
|
|
1451 |
|
1462 |
|
1452 |
|
1463 |
|
1453 |
|
1464 |
|
|
|
||
1459 |
|
1470 |
|
1460 |
|
1471 |
|
1461 |
|
1472 |
|
1462 |
|
|
|
1463 |
|
|
|
|
1473 |
|
|
|
1474 |
|
|
|
1475 |
|
|
|
1476 |
|
|
|
1477 |
|
|
|
1478 |
|
|
|
1479 |
|
|
|
1480 |
|
|
|
1481 |
|
|
|
1482 |
|
|
|
1483 |
|
|
|
1484 |
|
|
|
1485 |
|
|
|
1486 |
|
|
1464 |
|
1487 |
|
1465 |
|
1488 |
|
1466 |
|
1489 |
|
1467 |
|
1490 |
|
1468 |
|
1491 |
|
1469 |
|
|
|
1470 |
|
1492 |
|
1471 |
|
1493 |
|
1472 |
|
|
|
1473 |
|
|
|
1474 |
|
|
|
1475 |
|
|
|
1476 |
|
|
|
1477 |
|
|
|
1478 |
|
|
|
1479 |
|
|
|
1480 |
|
|
|
1481 |
|
1494 |
|
1482 |
|
1495 |
|
1483 |
|
1496 |
|