[ioapi] Generalise i386 raw I/O API to x86

Signed-off-by: Michael Brown <mcb30@ipxe.org>

src/arch/i386/core/x86_io.c → src/arch/x86/core/x86_io.c

  *
  * This routine uses MMX instructions.
  */
-static uint64_t x86_readq ( volatile uint64_t *io_addr ) {
+static __unused uint64_t i386_readq ( volatile uint64_t *io_addr ) {
 	uint64_t data;
         __asm__ __volatile__ ( "pushl %%edx\n\t"
 			       "pushl %%eax\n\t"
  *
  * This routine uses MMX instructions.
  */
-static void x86_writeq ( uint64_t data, volatile uint64_t *io_addr ) {
+static __unused void i386_writeq ( uint64_t data, volatile uint64_t *io_addr ) {
 	__asm__ __volatile__ ( "pushl %%edx\n\t"
 			       "pushl %%eax\n\t"
 			       "movq (%%esp), %%mm0\n\t"
 PROVIDE_IOAPI_INLINE ( x86, readb );
 PROVIDE_IOAPI_INLINE ( x86, readw );
 PROVIDE_IOAPI_INLINE ( x86, readl );
-PROVIDE_IOAPI ( x86, readq, x86_readq );
 PROVIDE_IOAPI_INLINE ( x86, writeb );
 PROVIDE_IOAPI_INLINE ( x86, writew );
 PROVIDE_IOAPI_INLINE ( x86, writel );
-PROVIDE_IOAPI ( x86, writeq, x86_writeq );
 PROVIDE_IOAPI_INLINE ( x86, inb );
 PROVIDE_IOAPI_INLINE ( x86, inw );
 PROVIDE_IOAPI_INLINE ( x86, inl );
 PROVIDE_IOAPI_INLINE ( x86, outsl );
 PROVIDE_IOAPI_INLINE ( x86, iodelay );
 PROVIDE_IOAPI_INLINE ( x86, mb );
+#ifdef __x86_64__
+PROVIDE_IOAPI_INLINE ( x86, readq );
+PROVIDE_IOAPI_INLINE ( x86, writeq );
+#else
+PROVIDE_IOAPI ( x86, readq, i386_readq );
+PROVIDE_IOAPI ( x86, writeq, i386_writeq );
+#endif

src/arch/i386/include/bits/io.h → src/arch/x86/include/bits/io.h

 
 /** @file
  *
- * i386-specific I/O API implementations
+ * x86-specific I/O API implementations
  *
  */
 

src/arch/i386/include/ipxe/x86_io.h → src/arch/x86/include/ipxe/x86_io.h

  *
  * iPXE I/O API for x86
  *
- * i386 uses direct pointer dereferences for accesses to memory-mapped
+ * x86 uses direct pointer dereferences for accesses to memory-mapped
  * I/O space, and the inX/outX instructions for accesses to
  * port-mapped I/O space.
  *
- * 64-bit atomic accesses (readq() and writeq()) use MMX instructions,
- * and will crash original Pentium and earlier CPUs.  Fortunately, no
- * hardware that requires atomic 64-bit accesses will physically fit
- * into a machine with such an old CPU anyway.
+ * 64-bit atomic accesses (readq() and writeq()) use MMX instructions
+ * under i386, and will crash original Pentium and earlier CPUs.
+ * Fortunately, no hardware that requires atomic 64-bit accesses will
+ * physically fit into a machine with such an old CPU anyway.
  */
 
 FILE_LICENCE ( GPL2_OR_LATER );
 }
 
 /*
- * MMIO reads and writes up to 32 bits
+ * MMIO reads and writes up to native word size
  *
  */
 
 X86_READX ( readb, uint8_t );
 X86_READX ( readw, uint16_t );
 X86_READX ( readl, uint32_t );
+#ifdef __x86_64__
+X86_READX ( readq, uint64_t );
+#endif
 
 #define X86_WRITEX( _api_func, _type )					      \
 static inline __always_inline void					      \
 X86_WRITEX ( writeb, uint8_t );
 X86_WRITEX ( writew, uint16_t );
 X86_WRITEX ( writel, uint32_t );
+#ifdef __x86_64__
+X86_WRITEX ( writeq, uint64_t );
+#endif
 
 /*
  * PIO reads and writes up to 32 bits

src/arch/x86_64/include/bits/io.h

-#ifndef _BITS_IO_H
-#define _BITS_IO_H
-
-/** @file
- *
- * x86_64-specific I/O API implementations
- *
- */
-
-#endif /* _BITS_IO_H */