Selaa lähdekoodia

Merge from Etherboot 5.4

tags/v0.9.3
Michael Brown 18 vuotta sitten
vanhempi
commit
46e7bd5b52
2 muutettua tiedostoa jossa 559 lisäystä ja 64 poistoa
  1. 445
    64
      src/drivers/net/r8169.c
  2. 114
    0
      src/drivers/net/smc9000.h

+ 445
- 64
src/drivers/net/r8169.c Näytä tiedosto

@@ -23,7 +23,9 @@
23 23
 *    Written 2002 ShuChen <shuchen@realtek.com.tw>
24 24
 *	  See Linux Driver for full information
25 25
 *	
26
-*    Linux Driver Version 1.27a, 10.02.2002
26
+*    Linux Driver Versions: 
27
+*	1.27a, 10.02.2002
28
+*	RTL8169_VERSION "2.2"   <2004/08/09>
27 29
 * 
28 30
 *    Thanks to:
29 31
 *    	Jean Chen of RealTek Semiconductor Corp. for
@@ -37,6 +39,7 @@
37 39
 *    v1.0	11-26-2003	timlegge	Initial port of Linux driver
38 40
 *    v1.5	01-17-2004	timlegge	Initial driver output cleanup
39 41
 *    v1.6	03-27-2004	timlegge	Additional Cleanup
42
+*    v1.7	11-22-2005	timlegge	Update to RealTek Driver Version 2.2
40 43
 *    
41 44
 *    Indent Options: indent -kr -i8
42 45
 ***************************************************************************/
@@ -68,6 +71,25 @@ static u32 ioaddr;
68 71
 
69 72
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
70 73
 
74
+#undef RTL8169_DEBUG
75
+#undef RTL8169_JUMBO_FRAME_SUPPORT
76
+#undef RTL8169_HW_FLOW_CONTROL_SUPPORT
77
+
78
+
79
+#undef RTL8169_IOCTL_SUPPORT
80
+#undef RTL8169_DYNAMIC_CONTROL
81
+#define RTL8169_USE_IO
82
+
83
+
84
+#ifdef RTL8169_DEBUG
85
+#define assert(expr) \
86
+               if(!(expr)) { printk( "Assertion failed! %s,%s,%s,line=%d\n", #expr,__FILE__,__FUNCTION__,__LINE__); }
87
+#define DBG_PRINT( fmt, args...)   printk("r8169: " fmt, ## args);
88
+#else
89
+#define assert(expr) do {} while (0)
90
+#define DBG_PRINT( fmt, args...)   ;
91
+#endif				// end of #ifdef RTL8169_DEBUG
92
+
71 93
 /* media options 
72 94
         _10_Half = 0x01,
73 95
         _10_Full = 0x02,
@@ -97,8 +119,10 @@ static int multicast_filter_limit = 32;
97 119
 #define TX_FIFO_THRESH 256	/* In bytes */
98 120
 
99 121
 #define RX_FIFO_THRESH	7	/* 7 means NO threshold, Rx buffer level before first PCI xfer.  */
100
-#define RX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */
101
-#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */
122
+#define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */
123
+#define TX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */
124
+#define ETTh                0x3F	/* 0x3F means NO threshold */
125
+
102 126
 #define EarlyTxThld 	0x3F	/* 0x3F means NO early transmit */
103 127
 #define RxPacketMaxSize	0x0800	/* Maximum size supported is 16K-1 */
104 128
 #define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */
@@ -110,6 +134,28 @@ static int multicast_filter_limit = 32;
110 134
 #define RTL_MIN_IO_SIZE 0x80
111 135
 #define TX_TIMEOUT  (6*HZ)
112 136
 
137
+#define RTL8169_TIMER_EXPIRE_TIME 100	//100
138
+
139
+#define ETH_HDR_LEN         14
140
+#define DEFAULT_MTU         1500
141
+#define DEFAULT_RX_BUF_LEN  1536
142
+
143
+
144
+#ifdef RTL8169_JUMBO_FRAME_SUPPORT
145
+#define MAX_JUMBO_FRAME_MTU    ( 10000 )
146
+#define MAX_RX_SKBDATA_SIZE    ( MAX_JUMBO_FRAME_MTU + ETH_HDR_LEN )
147
+#else
148
+#define MAX_RX_SKBDATA_SIZE 1600
149
+#endif				//end #ifdef RTL8169_JUMBO_FRAME_SUPPORT
150
+
151
+#ifdef RTL8169_USE_IO
152
+#define RTL_W8(reg, val8)   outb ((val8), ioaddr + (reg))
153
+#define RTL_W16(reg, val16) outw ((val16), ioaddr + (reg))
154
+#define RTL_W32(reg, val32) outl ((val32), ioaddr + (reg))
155
+#define RTL_R8(reg)         inb (ioaddr + (reg))
156
+#define RTL_R16(reg)        inw (ioaddr + (reg))
157
+#define RTL_R32(reg)        ((unsigned long) inl (ioaddr + (reg)))
158
+#else
113 159
 /* write/read MMIO register */
114 160
 #define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))
115 161
 #define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))
@@ -117,10 +163,30 @@ static int multicast_filter_limit = 32;
117 163
 #define RTL_R8(reg)		readb (ioaddr + (reg))
118 164
 #define RTL_R16(reg)		readw (ioaddr + (reg))
119 165
 #define RTL_R32(reg)		((unsigned long) readl (ioaddr + (reg)))
166
+#endif
167
+
168
+#define MCFG_METHOD_1		0x01
169
+#define MCFG_METHOD_2		0x02
170
+#define MCFG_METHOD_3		0x03
171
+#define MCFG_METHOD_4		0x04
172
+
173
+#define PCFG_METHOD_1		0x01	//PHY Reg 0x03 bit0-3 == 0x0000
174
+#define PCFG_METHOD_2		0x02	//PHY Reg 0x03 bit0-3 == 0x0001
175
+#define PCFG_METHOD_3		0x03	//PHY Reg 0x03 bit0-3 == 0x0002
176
+
177
+static struct {
178
+	const char *name;
179
+	u8 mcfg;		/* depend on RTL8169 docs */
180
+	u32 RxConfigMask;	/* should clear the bits supported by this chip */
181
+} rtl_chip_info[] = {
182
+	{
183
+	"RTL-8169", MCFG_METHOD_1, 0xff7e1880,}, {
184
+	"RTL8169s/8110s", MCFG_METHOD_2, 0xff7e1880}, {
185
+"RTL8169s/8110s", MCFG_METHOD_3, 0xff7e1880},};
120 186
 
121 187
 enum RTL8169_registers {
122
-	MAC0 = 0,		/* Ethernet hardware address. */
123
-	MAR0 = 8,		/* Multicast filter. */
188
+	MAC0 = 0x0,		/* Ethernet hardware address. */
189
+	MAR0 = 0x8,		/* Multicast filter. */
124 190
 	TxDescStartAddr = 0x20,
125 191
 	TxHDescStartAddr = 0x28,
126 192
 	FLASH = 0x30,
@@ -148,7 +214,7 @@ enum RTL8169_registers {
148 214
 	RxMaxSize = 0xDA,
149 215
 	CPlusCmd = 0xE0,
150 216
 	RxDescStartAddr = 0xE4,
151
-	EarlyTxThres = 0xEC,
217
+	ETThReg = 0xEC,
152 218
 	FuncEvent = 0xF0,
153 219
 	FuncEventMask = 0xF4,
154 220
 	FuncPresetState = 0xF8,
@@ -162,7 +228,7 @@ enum RTL8169_register_content {
162 228
 	SWInt = 0x0100,
163 229
 	TxDescUnavail = 0x80,
164 230
 	RxFIFOOver = 0x40,
165
-	RxUnderrun = 0x20,
231
+	LinkChg = 0x20,
166 232
 	RxOverflow = 0x10,
167 233
 	TxErr = 0x08,
168 234
 	TxOK = 0x04,
@@ -232,6 +298,10 @@ enum RTL8169_register_content {
232 298
 
233 299
 	/* PHY_1000_CTRL_REG = 9; */
234 300
 	PHY_Cap_1000_Full = 0x0200,
301
+	PHY_Cap_1000_Half = 0x0100,
302
+
303
+	PHY_Cap_PAUSE = 0x0400,
304
+	PHY_Cap_ASYM_PAUSE = 0x0800,
235 305
 
236 306
 	PHY_Cap_Null = 0x0,
237 307
 
@@ -246,14 +316,6 @@ enum RTL8169_register_content {
246 316
 	TBILinkOK = 0x02000000,
247 317
 };
248 318
 
249
-static struct {
250
-	const char *name;
251
-	u8 version;		/* depend on RTL8169 docs */
252
-	u32 RxConfigMask;	/* should clear the bits supported by this chip */
253
-} rtl_chip_info[] = {
254
-	{
255
-"RTL-8169", 0x00, 0xff7e1880,},};
256
-
257 319
 enum _DescStatusBit {
258 320
 	OWNbit = 0x80000000,
259 321
 	EORbit = 0x40000000,
@@ -299,6 +361,8 @@ struct {
299 361
 static struct rtl8169_private {
300 362
 	void *mmio_addr;	/* memory map physical address */
301 363
 	int chipset;
364
+	int pcfg;
365
+	int mcfg;
302 366
 	unsigned long cur_rx;	/* Index into the Rx descriptor buffer of next Rx pkt. */
303 367
 	unsigned long cur_tx;	/* Index into the Tx descriptor buffer of next Rx pkt. */
304 368
 	struct TxDesc *TxDescArray;	/* Index of 256-alignment Tx Descriptor buffer */
@@ -310,10 +374,67 @@ static struct rtl8169_private {
310 374
 static struct rtl8169_private *tpc;
311 375
 
312 376
 static const u16 rtl8169_intr_mask =
313
-    SYSErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver | TxErr |
314
-    TxOK | RxErr | RxOK;
377
+    LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
315 378
 static const unsigned int rtl8169_rx_config =
316
-    (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
379
+    (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift) |
380
+    0x0000000E;
381
+
382
+static void rtl8169_hw_PHY_config(struct nic *nic __unused);
383
+//static void rtl8169_hw_PHY_reset(struct net_device *dev);
384
+
385
+#define RTL8169_WRITE_GMII_REG_BIT( ioaddr, reg, bitnum, bitval )\
386
+{ \
387
+       int val; \
388
+       if( bitval == 1 ){ val = ( RTL8169_READ_GMII_REG( ioaddr, reg ) | (bitval<<bitnum) ) & 0xffff ; } \
389
+       else{ val = ( RTL8169_READ_GMII_REG( ioaddr, reg ) & (~(0x0001<<bitnum)) ) & 0xffff ; } \
390
+       RTL8169_WRITE_GMII_REG( ioaddr, reg, val ); \
391
+ }
392
+
393
+//=================================================================
394
+//      PHYAR
395
+//      bit             Symbol
396
+//      31              Flag
397
+//      30-21   reserved
398
+//      20-16   5-bit GMII/MII register address
399
+//      15-0    16-bit GMII/MII register data
400
+//=================================================================
401
+void RTL8169_WRITE_GMII_REG(unsigned long ioaddr, int RegAddr, int value)
402
+{
403
+	int i;
404
+
405
+	RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
406
+	udelay(1000);
407
+
408
+	for (i = 2000; i > 0; i--) {
409
+		// Check if the RTL8169 has completed writing to the specified MII register
410
+		if (!(RTL_R32(PHYAR) & 0x80000000)) {
411
+			break;
412
+		} else {
413
+			udelay(100);
414
+		}		// end of if( ! (RTL_R32(PHYAR)&0x80000000) )
415
+	}			// end of for() loop
416
+}
417
+
418
+//=================================================================
419
+int RTL8169_READ_GMII_REG(unsigned long ioaddr, int RegAddr)
420
+{
421
+	int i, value = -1;
422
+
423
+	RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
424
+	udelay(1000);
425
+
426
+	for (i = 2000; i > 0; i--) {
427
+		// Check if the RTL8169 has completed retrieving data from the specified MII register
428
+		if (RTL_R32(PHYAR) & 0x80000000) {
429
+			value = (int) (RTL_R32(PHYAR) & 0xFFFF);
430
+			break;
431
+		} else {
432
+			udelay(100);
433
+		}		// end of if( RTL_R32(PHYAR) & 0x80000000 )
434
+	}			// end of for() loop
435
+	return value;
436
+}
437
+
317 438
 
318 439
 static void mdio_write(int RegAddr, int value)
319 440
 {
@@ -351,27 +472,41 @@ static int mdio_read(int RegAddr)
351 472
 	return value;
352 473
 }
353 474
 
475
+#define IORESOURCE_MEM 0x00000200
476
+
354 477
 static int rtl8169_init_board(struct pci_device *pdev)
355 478
 {
356 479
 	int i;
357
-	unsigned long rtreg_base, rtreg_len;
358
-	u32 tmp;
480
+	unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
359 481
 
360
-	rtreg_base = pci_bar_start(pdev, PCI_BASE_ADDRESS_1);
361
-	rtreg_len = pci_bar_size(pdev, PCI_BASE_ADDRESS_1);
482
+	adjust_pci_device(pdev);
362 483
 
363
-	/* check for weird/broken PCI region reporting */
364
-	if (rtreg_len < RTL_MIN_IO_SIZE) {
365
-		printf("Invalid PCI region size(s), aborting\n");
366
-	}
484
+	mmio_start = pci_bar_start(pdev, PCI_BASE_ADDRESS_1);
485
+//       mmio_end = pci_resource_end (pdev, 1);
486
+//       mmio_flags = pci_resource_flags (pdev, PCI_BASE_ADDRESS_1);
487
+	mmio_len = pci_bar_size(pdev, PCI_BASE_ADDRESS_1);
367 488
 
368
-	adjust_pci_device(pdev);
369
-/*      pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); */
489
+	// make sure PCI base addr 1 is MMIO
490
+//     if (!(mmio_flags & IORESOURCE_MEM)) {
491
+//             printf ("region #1 not an MMIO resource, aborting\n");
492
+//             return 0;
493
+//     }
370 494
 
371
-	/* ioremap MMIO region */
372
-	ioaddr = (unsigned long) ioremap(rtreg_base, rtreg_len);
373
-	if (ioaddr == 0)
495
+	// check for weird/broken PCI region reporting
496
+	if (mmio_len < RTL_MIN_IO_SIZE) {
497
+		printf("Invalid PCI region size(s), aborting\n");
498
+		return 0;
499
+	}
500
+#ifdef RTL8169_USE_IO
501
+	ioaddr = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
502
+#else
503
+	// ioremap MMIO region
504
+	ioaddr = (unsigned long) ioremap(mmio_start, mmio_len);
505
+	if (ioaddr == 0) {
506
+		printk("cannot remap MMIO, aborting\n");
374 507
 		return 0;
508
+	}
509
+#endif
375 510
 
376 511
 	tpc->mmio_addr = &ioaddr;
377 512
 	/* Soft reset the chip. */
@@ -383,13 +518,40 @@ static int rtl8169_init_board(struct pci_device *pdev)
383 518
 			break;
384 519
 		else
385 520
 			udelay(10);
521
+	// identify config method
522
+	{
523
+		unsigned long val32 = (RTL_R32(TxConfig) & 0x7c800000);
524
+		if (val32 == (0x1 << 28)) {
525
+			tpc->mcfg = MCFG_METHOD_4;
526
+		} else if (val32 == (0x1 << 26)) {
527
+			tpc->mcfg = MCFG_METHOD_3;
528
+		} else if (val32 == (0x1 << 23)) {
529
+			tpc->mcfg = MCFG_METHOD_2;
530
+		} else if (val32 == 0x00000000) {
531
+			tpc->mcfg = MCFG_METHOD_1;
532
+		} else {
533
+			tpc->mcfg = MCFG_METHOD_1;
534
+		}
535
+	}
536
+	{
537
+		unsigned char val8 =
538
+		    (unsigned char) (RTL8169_READ_GMII_REG(ioaddr, 3) &
539
+				     0x000f);
540
+		if (val8 == 0x00) {
541
+			tpc->pcfg = PCFG_METHOD_1;
542
+		} else if (val8 == 0x01) {
543
+			tpc->pcfg = PCFG_METHOD_2;
544
+		} else if (val8 == 0x02) {
545
+			tpc->pcfg = PCFG_METHOD_3;
546
+		} else {
547
+			tpc->pcfg = PCFG_METHOD_3;
548
+		}
549
+	}
386 550
 
387 551
 	/* identify chip attached to board */
388
-	tmp = RTL_R32(TxConfig);
389
-	tmp = ((tmp & 0x7c000000) + ((tmp & 0x00800000) << 2)) >> 24;
390 552
 
391 553
 	for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--)
392
-		if (tmp == rtl_chip_info[i].version) {
554
+		if (tpc->mcfg == rtl_chip_info[i].mcfg) {
393 555
 			tpc->chipset = i;
394 556
 			goto match;
395 557
 		}
@@ -397,8 +559,10 @@ static int rtl8169_init_board(struct pci_device *pdev)
397 559
 	dprintf(("PCI device: unknown chip version, assuming RTL-8169\n"));
398 560
 	dprintf(("PCI device: TxConfig = 0x%hX\n",
399 561
 		 (unsigned long) RTL_R32(TxConfig)));
562
+
400 563
 	tpc->chipset = 0;
401 564
 	return 1;
565
+
402 566
       match:
403 567
 	return 0;
404 568
 
@@ -407,6 +571,31 @@ static int rtl8169_init_board(struct pci_device *pdev)
407 571
 /**************************************************************************
408 572
 IRQ - Wait for a frame
409 573
 ***************************************************************************/
574
+void r8169_irq(struct nic *nic __unused, irq_action_t action)
575
+{
576
+	int intr_status = 0;
577
+	int interested = RxOverflow | RxFIFOOver | RxErr | RxOK;
578
+
579
+	switch (action) {
580
+	case DISABLE:
581
+	case ENABLE:
582
+		intr_status = RTL_R16(IntrStatus);
583
+		/* h/w no longer present (hotplug?) or major error, 
584
+		   bail */
585
+		if (intr_status == 0xFFFF)
586
+			break;
587
+		
588
+		intr_status = intr_status & ~interested;
589
+		if (action == ENABLE)
590
+			intr_status = intr_status | interested;
591
+		RTL_W16(IntrMask, intr_status);
592
+		break;
593
+	case FORCE:
594
+		RTL_W8(TxPoll, (RTL_R8(TxPoll) | 0x01));
595
+		break;
596
+	}
597
+}
598
+
410 599
 static void r8169_irq ( struct nic *nic __unused, irq_action_t action ) {
411 600
 	int intr_status = 0;
412 601
 	int interested = RxUnderrun | RxOverflow | RxFIFOOver | RxErr | RxOK;
@@ -443,15 +632,15 @@ static int r8169_poll(struct nic *nic, int retreive)
443 632
 	unsigned int intr_status = 0;
444 633
 	cur_rx = tpc->cur_rx;
445 634
 	if ((tpc->RxDescArray[cur_rx].status & OWNbit) == 0) {
446
-	         /* There is a packet ready */
447
-  	         if(!retreive)
448
-  	                 return 1;
635
+		/* There is a packet ready */
636
+		if (!retreive)
637
+			return 1;
449 638
 		intr_status = RTL_R16(IntrStatus);
450 639
 		/* h/w no longer present (hotplug?) or major error,
451
-			bail */
640
+		   bail */
452 641
 		if (intr_status == 0xFFFF)
453 642
 			return 0;
454
-		RTL_W16(IntrStatus, intr_status & 
643
+		RTL_W16(IntrStatus, intr_status &
455 644
 			~(RxFIFOOver | RxOverflow | RxOK));
456 645
 
457 646
 		if (!(tpc->RxDescArray[cur_rx].status & RxRES)) {
@@ -472,7 +661,7 @@ static int r8169_poll(struct nic *nic, int retreive)
472 661
 		/* FIXME: shouldn't I reset the status on an error */
473 662
 		cur_rx = (cur_rx + 1) % NUM_RX_DESC;
474 663
 		tpc->cur_rx = cur_rx;
475
-		RTL_W16(IntrStatus, intr_status & 
664
+		RTL_W16(IntrStatus, intr_status &
476 665
 			(RxFIFOOver | RxOverflow | RxOK));
477 666
 
478 667
 		return 1;
@@ -569,7 +758,7 @@ static void rtl8169_hw_start(struct nic *nic)
569 758
 
570 759
 	RTL_W8(Cfg9346, Cfg9346_Unlock);
571 760
 	RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
572
-	RTL_W8(EarlyTxThres, EarlyTxThld);
761
+	RTL_W8(ETThReg, ETTh);
573 762
 
574 763
 	/* For gigabit rtl8169 */
575 764
 	RTL_W16(RxMaxSize, RxPacketMaxSize);
@@ -585,6 +774,27 @@ static void rtl8169_hw_start(struct nic *nic)
585 774
 						TxInterFrameGapShift));
586 775
 
587 776
 
777
+	RTL_W16(CPlusCmd, RTL_R16(CPlusCmd));
778
+
779
+	if (tpc->mcfg == MCFG_METHOD_2 || tpc->mcfg == MCFG_METHOD_3) {
780
+		RTL_W16(CPlusCmd,
781
+			(RTL_R16(CPlusCmd) | (1 << 14) | (1 << 3)));
782
+		DBG_PRINT
783
+		    ("Set MAC Reg C+CR Offset 0xE0: bit-3 and bit-14\n");
784
+	} else {
785
+		RTL_W16(CPlusCmd, (RTL_R16(CPlusCmd) | (1 << 3)));
786
+		DBG_PRINT("Set MAC Reg C+CR Offset 0xE0: bit-3.\n");
787
+	}
788
+
789
+	{
790
+		//RTL_W16(0xE2, 0x1517);
791
+		//RTL_W16(0xE2, 0x152a);
792
+		//RTL_W16(0xE2, 0x282a);
793
+		RTL_W16(0xE2, 0x0000);
794
+	}
795
+
796
+
797
+
588 798
 	tpc->cur_rx = 0;
589 799
 
590 800
 	RTL_W32(TxDescStartAddr, virt_to_le32desc(tpc->TxDescArray));
@@ -598,6 +808,9 @@ static void rtl8169_hw_start(struct nic *nic)
598 808
 
599 809
 	/* no early-rx interrupts */
600 810
 	RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
811
+
812
+	RTL_W16(IntrMask, rtl8169_intr_mask);
813
+
601 814
 }
602 815
 
603 816
 static void rtl8169_init_ring(struct nic *nic __unused)
@@ -616,9 +829,9 @@ static void rtl8169_init_ring(struct nic *nic __unused)
616 829
 	for (i = 0; i < NUM_RX_DESC; i++) {
617 830
 		if (i == (NUM_RX_DESC - 1))
618 831
 			tpc->RxDescArray[i].status =
619
-			    (OWNbit | EORbit) + RX_BUF_SIZE;
832
+			    (OWNbit | EORbit) | RX_BUF_SIZE;
620 833
 		else
621
-			tpc->RxDescArray[i].status = OWNbit + RX_BUF_SIZE;
834
+			tpc->RxDescArray[i].status = OWNbit | RX_BUF_SIZE;
622 835
 
623 836
 		tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
624 837
 		tpc->RxDescArray[i].buf_addr =
@@ -681,6 +894,8 @@ static struct nic_operations r8169_operations = {
681 894
 
682 895
 static struct pci_id r8169_nics[] = {
683 896
 	PCI_ROM(0x10ec, 0x8169, "r8169", "RealTek RTL8169 Gigabit Ethernet"),
897
+        PCI_ROM(0x16ec, 0x0116, "usr-r8169", "US Robotics RTL8169 Gigabit Ethernet"),
898
+        PCI_ROM(0x1186, 0x4300, "dlink-r8169", "D-Link RTL8169 Gigabit Ethernet"),
684 899
 };
685 900
 
686 901
 PCI_DRIVER ( r8169_driver, r8169_nics, PCI_NO_CLASS );
@@ -720,9 +935,31 @@ static int r8169_probe ( struct nic *nic, struct pci_device *pci ) {
720 935
 	printf("%s: %! at ioaddr %hX, ", pci->name, nic->node_addr,
721 936
 	       ioaddr);
722 937
 
938
+	// Config PHY
939
+	rtl8169_hw_PHY_config(nic);
940
+
941
+	DBG_PRINT("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
942
+	RTL_W8(0x82, 0x01);
943
+
944
+	if (tpc->mcfg < MCFG_METHOD_3) {
945
+		DBG_PRINT("Set PCI Latency=0x40\n");
946
+		pci_write_config_byte(pci, PCI_LATENCY_TIMER, 0x40);
947
+	}
948
+
949
+	if (tpc->mcfg == MCFG_METHOD_2) {
950
+		DBG_PRINT("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
951
+		RTL_W8(0x82, 0x01);
952
+		DBG_PRINT("Set PHY Reg 0x0bh = 0x00h\n");
953
+		RTL8169_WRITE_GMII_REG(ioaddr, 0x0b, 0x0000);	//w 0x0b 15 0 0
954
+	}
955
+
723 956
 	/* if TBI is not endbled */
724 957
 	if (!(RTL_R8(PHYstatus) & TBI_Enable)) {
725
-		int val = mdio_read(PHY_AUTO_NEGO_REG);
958
+		int val = RTL8169_READ_GMII_REG(ioaddr, PHY_AUTO_NEGO_REG);
959
+
960
+#ifdef RTL8169_HW_FLOW_CONTROL_SUPPORT
961
+		val |= PHY_Cap_PAUSE | PHY_Cap_ASYM_PAUSE;
962
+#endif				//end #define RTL8169_HW_FLOW_CONTROL_SUPPORT
726 963
 
727 964
 		option = media;
728 965
 		/* Force RTL8169 in 10/100/1000 Full/Half mode. */
@@ -753,34 +990,38 @@ static int r8169_probe ( struct nic *nic, struct pci_device *pci ) {
753 990
 			default:
754 991
 				break;
755 992
 			}
756
-			/* leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
757
-			mdio_write(PHY_AUTO_NEGO_REG,
758
-				   Cap10_100 | (val & 0x1F));
759
-			mdio_write(PHY_1000_CTRL_REG, Cap1000);
993
+			RTL8169_WRITE_GMII_REG(ioaddr, PHY_AUTO_NEGO_REG, Cap10_100 | (val & 0xC1F));	//leave PHY_AUTO_NEGO_REG bit4:0 unchanged
994
+			RTL8169_WRITE_GMII_REG(ioaddr, PHY_1000_CTRL_REG,
995
+					       Cap1000);
760 996
 		} else {
761 997
 			dprintf(("Auto-negotiation Enabled.\n",
762 998
 				 pci->name));
763 999
 
764
-			/* enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged */
765
-			mdio_write(PHY_AUTO_NEGO_REG,
766
-				   PHY_Cap_10_Half | PHY_Cap_10_Full |
767
-				   PHY_Cap_100_Half | PHY_Cap_100_Full |
768
-				   (val & 0x1F));
1000
+			// enable 10/100 Full/Half Mode, leave PHY_AUTO_NEGO_REG bit4:0 unchanged
1001
+			RTL8169_WRITE_GMII_REG(ioaddr, PHY_AUTO_NEGO_REG,
1002
+					       PHY_Cap_10_Half |
1003
+					       PHY_Cap_10_Full |
1004
+					       PHY_Cap_100_Half |
1005
+					       PHY_Cap_100_Full | (val &
1006
+								   0xC1F));
769 1007
 
770
-			/* enable 1000 Full Mode */
771
-			mdio_write(PHY_1000_CTRL_REG, PHY_Cap_1000_Full);
1008
+			// enable 1000 Full Mode
1009
+//                     RTL8169_WRITE_GMII_REG( ioaddr, PHY_1000_CTRL_REG, PHY_Cap_1000_Full );
1010
+			RTL8169_WRITE_GMII_REG(ioaddr, PHY_1000_CTRL_REG, PHY_Cap_1000_Full | PHY_Cap_1000_Half);	//rtl8168
772 1011
 
773
-		}
1012
+		}		// end of if( option > 0 )
774 1013
 
775
-		/* Enable auto-negotiation and restart auto-nigotiation */
776
-		mdio_write(PHY_CTRL_REG,
777
-			   PHY_Enable_Auto_Nego | PHY_Restart_Auto_Nego);
1014
+		// Enable auto-negotiation and restart auto-nigotiation
1015
+		RTL8169_WRITE_GMII_REG(ioaddr, PHY_CTRL_REG,
1016
+				       PHY_Enable_Auto_Nego |
1017
+				       PHY_Restart_Auto_Nego);
778 1018
 		udelay(100);
779 1019
 
780
-		/* wait for auto-negotiation process */
1020
+		// wait for auto-negotiation process
781 1021
 		for (i = 10000; i > 0; i--) {
782
-			/* Check if auto-negotiation complete */
783
-			if (mdio_read(PHY_STAT_REG) & PHY_Auto_Neco_Comp) {
1022
+			//check if auto-negotiation complete
1023
+			if (RTL8169_READ_GMII_REG(ioaddr, PHY_STAT_REG) &
1024
+			    PHY_Auto_Neco_Comp) {
784 1025
 				udelay(100);
785 1026
 				option = RTL_R8(PHYstatus);
786 1027
 				if (option & _1000bpsF) {
@@ -797,8 +1038,9 @@ static int r8169_probe ( struct nic *nic, struct pci_device *pci ) {
797 1038
 				break;
798 1039
 			} else {
799 1040
 				udelay(100);
800
-			}
801
-		}		/* end for-loop to wait for auto-negotiation process */
1041
+			}	// end of if( RTL8169_READ_GMII_REG(ioaddr, 1) & 0x20 )
1042
+		}		// end for-loop to wait for auto-negotiation process
1043
+
802 1044
 
803 1045
 	} else {
804 1046
 		udelay(100);
@@ -819,5 +1061,144 @@ static int r8169_probe ( struct nic *nic, struct pci_device *pci ) {
819 1061
 
820 1062
 }
821 1063
 
1064
+//======================================================================================================
1065
+/*
1066
+static void rtl8169_hw_PHY_reset(struct nic *nic __unused)
1067
+{
1068
+        int val, phy_reset_expiretime = 50;
1069
+        struct rtl8169_private *priv = dev->priv;
1070
+        unsigned long ioaddr = priv->ioaddr;
1071
+
1072
+        DBG_PRINT("%s: Reset RTL8169s PHY\n", dev->name);
1073
+
1074
+        val = ( RTL8169_READ_GMII_REG( ioaddr, 0 ) | 0x8000 ) & 0xffff;
1075
+        RTL8169_WRITE_GMII_REG( ioaddr, 0, val );
1076
+
1077
+        do //waiting for phy reset
1078
+        {
1079
+                if( RTL8169_READ_GMII_REG( ioaddr, 0 ) & 0x8000 ){
1080
+                        phy_reset_expiretime --;
1081
+                        udelay(100);
1082
+                }
1083
+                else{
1084
+                        break;
1085
+                }
1086
+        }while( phy_reset_expiretime >= 0 );
1087
+
1088
+        assert( phy_reset_expiretime > 0 );
1089
+}
1090
+
1091
+*/
1092
+
1093
+//======================================================================================================
1094
+static void rtl8169_hw_PHY_config(struct nic *nic __unused)
1095
+{
1096
+
1097
+	DBG_PRINT("priv->mcfg=%d, priv->pcfg=%d\n", tpc->mcfg, tpc->pcfg);
1098
+
1099
+	if (tpc->mcfg == MCFG_METHOD_4) {
1100
+/*
1101
+                RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x1F, 0x0001 );
1102
+                RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x1b, 0x841e );
1103
+                RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x0e, 0x7bfb );
1104
+                RTL8169_WRITE_GMII_REG( (unsigned long)ioaddr, 0x09, 0x273a );
1105
+*/
1106
+
1107
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1108
+				       0x0002);
1109
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1110
+				       0x90D0);
1111
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1112
+				       0x0000);
1113
+	} else if ((tpc->mcfg == MCFG_METHOD_2)
1114
+		   || (tpc->mcfg == MCFG_METHOD_3)) {
1115
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1116
+				       0x0001);
1117
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x15,
1118
+				       0x1000);
1119
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x18,
1120
+				       0x65C7);
1121
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1122
+				       0x0000);
1123
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1124
+				       0x00A1);
1125
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1126
+				       0x0008);
1127
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1128
+				       0x1020);
1129
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1130
+				       0x1000);
1131
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1132
+				       0x0800);
1133
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1134
+				       0x0000);
1135
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1136
+				       0x7000);
1137
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1138
+				       0xFF41);
1139
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1140
+				       0xDE60);
1141
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1142
+				       0x0140);
1143
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1144
+				       0x0077);
1145
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1146
+				       0x7800);
1147
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1148
+				       0x7000);
1149
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1150
+				       0xA000);
1151
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1152
+				       0xDF01);
1153
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1154
+				       0xDF20);
1155
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1156
+				       0xFF95);
1157
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1158
+				       0xFA00);
1159
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1160
+				       0xA800);
1161
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1162
+				       0xA000);
1163
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1164
+				       0xB000);
1165
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1166
+				       0xFF41);
1167
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1168
+				       0xDE20);
1169
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1170
+				       0x0140);
1171
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1172
+				       0x00BB);
1173
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1174
+				       0xB800);
1175
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1176
+				       0xB000);
1177
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1178
+				       0xF000);
1179
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x03,
1180
+				       0xDF01);
1181
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x02,
1182
+				       0xDF20);
1183
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x01,
1184
+				       0xFF95);
1185
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x00,
1186
+				       0xBF00);
1187
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1188
+				       0xF800);
1189
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1190
+				       0xF000);
1191
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x04,
1192
+				       0x0000);
1193
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x1F,
1194
+				       0x0000);
1195
+		RTL8169_WRITE_GMII_REG((unsigned long) ioaddr, 0x0B,
1196
+				       0x0000);
1197
+	} else {
1198
+		DBG_PRINT("tpc->mcfg=%d. Discard hw PHY config.\n",
1199
+			  tpc->mcfg);
1200
+	}
1201
+}
1202
+
822 1203
 DRIVER ( "r8169/PCI", nic_driver, pci_driver, r8169_driver,
823 1204
 	 r8169_probe, r8169_disable );

+ 114
- 0
src/drivers/net/smc9000.h Näytä tiedosto

@@ -109,6 +109,24 @@ typedef unsigned long int		dword;
109 109
 #define RPC_LED_RX      (0x07)  // LED = RX packet occurred
110 110
 #define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
111 111
 
112
+// Receive/Phy Control Register
113
+/* BANK 0  */
114
+#define RPC_REG         0x000A
115
+#define RPC_SPEED       0x2000  // When 1 PHY is in 100Mbps mode.
116
+#define RPC_DPLX        0x1000  // When 1 PHY is in Full-Duplex Mode
117
+#define RPC_ANEG        0x0800  // When 1 PHY is in Auto-Negotiate Mode
118
+#define RPC_LSXA_SHFT   5       // Bits to shift LS2A,LS1A,LS0A to lsb
119
+#define RPC_LSXB_SHFT   2       // Bits to get LS2B,LS1B,LS0B to lsb
120
+#define RPC_LED_100_10  (0x00)  // LED = 100Mbps OR's with 10Mbps link detect
121
+#define RPC_LED_RES     (0x01)  // LED = Reserved
122
+#define RPC_LED_10      (0x02)  // LED = 10Mbps link detect
123
+#define RPC_LED_FD      (0x03)  // LED = Full Duplex Mode
124
+#define RPC_LED_TX_RX   (0x04)  // LED = TX or RX packet occurred
125
+#define RPC_LED_100     (0x05)  // LED = 100Mbps link dectect
126
+#define RPC_LED_TX      (0x06)  // LED = TX packet occurred
127
+#define RPC_LED_RX      (0x07)  // LED = RX packet occurred
128
+#define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
129
+
112 130
 /* BANK 1 */
113 131
 #define CONFIG			0
114 132
 #define CFG_AUI_SELECT		0x100
@@ -210,6 +228,102 @@ typedef unsigned long int		dword;
210 228
 #define RS_MULTICAST	0x0001
211 229
 #define RS_ERRORS	(RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
212 230
 
231
+// Management Interface Register (MII)
232
+#define MII_REG         0x0008
233
+#define MII_MSK_CRS100  0x4000 // Disables CRS100 detection during tx half dup
234
+#define MII_MDOE        0x0008 // MII Output Enable
235
+#define MII_MCLK        0x0004 // MII Clock, pin MDCLK
236
+#define MII_MDI         0x0002 // MII Input, pin MDI
237
+#define MII_MDO         0x0001 // MII Output, pin MDO
238
+
239
+// PHY Register Addresses (LAN91C111 Internal PHY)
240
+
241
+// PHY Control Register
242
+#define PHY_CNTL_REG            0x00
243
+#define PHY_CNTL_RST            0x8000  // 1=PHY Reset
244
+#define PHY_CNTL_LPBK           0x4000  // 1=PHY Loopback
245
+#define PHY_CNTL_SPEED          0x2000  // 1=100Mbps, 0=10Mpbs
246
+#define PHY_CNTL_ANEG_EN        0x1000 // 1=Enable Auto negotiation
247
+#define PHY_CNTL_PDN            0x0800  // 1=PHY Power Down mode
248
+#define PHY_CNTL_MII_DIS        0x0400  // 1=MII 4 bit interface disabled
249
+#define PHY_CNTL_ANEG_RST       0x0200 // 1=Reset Auto negotiate
250
+#define PHY_CNTL_DPLX           0x0100  // 1=Full Duplex, 0=Half Duplex
251
+#define PHY_CNTL_COLTST         0x0080  // 1= MII Colision Test
252
+
253
+// PHY Status Register
254
+#define PHY_STAT_REG            0x01
255
+#define PHY_STAT_CAP_T4         0x8000  // 1=100Base-T4 capable
256
+#define PHY_STAT_CAP_TXF        0x4000  // 1=100Base-X full duplex capable
257
+#define PHY_STAT_CAP_TXH        0x2000  // 1=100Base-X half duplex capable
258
+#define PHY_STAT_CAP_TF         0x1000  // 1=10Mbps full duplex capable
259
+#define PHY_STAT_CAP_TH         0x0800  // 1=10Mbps half duplex capable
260
+#define PHY_STAT_CAP_SUPR       0x0040  // 1=recv mgmt frames with not preamble
261
+#define PHY_STAT_ANEG_ACK       0x0020  // 1=ANEG has completed
262
+#define PHY_STAT_REM_FLT        0x0010  // 1=Remote Fault detected
263
+#define PHY_STAT_CAP_ANEG       0x0008  // 1=Auto negotiate capable
264
+#define PHY_STAT_LINK           0x0004  // 1=valid link
265
+#define PHY_STAT_JAB            0x0002  // 1=10Mbps jabber condition
266
+#define PHY_STAT_EXREG          0x0001  // 1=extended registers implemented
267
+
268
+// PHY Identifier Registers
269
+#define PHY_ID1_REG             0x02    // PHY Identifier 1
270
+#define PHY_ID2_REG             0x03    // PHY Identifier 2
271
+
272
+// PHY Auto-Negotiation Advertisement Register
273
+#define PHY_AD_REG              0x04
274
+#define PHY_AD_NP               0x8000  // 1=PHY requests exchange of Next Page
275
+#define PHY_AD_ACK              0x4000  // 1=got link code word from remote
276
+#define PHY_AD_RF               0x2000  // 1=advertise remote fault
277
+#define PHY_AD_T4               0x0200  // 1=PHY is capable of 100Base-T4
278
+#define PHY_AD_TX_FDX           0x0100  // 1=PHY is capable of 100Base-TX FDPLX
279
+#define PHY_AD_TX_HDX           0x0080  // 1=PHY is capable of 100Base-TX HDPLX
280
+#define PHY_AD_10_FDX           0x0040  // 1=PHY is capable of 10Base-T FDPLX
281
+#define PHY_AD_10_HDX           0x0020  // 1=PHY is capable of 10Base-T HDPLX
282
+#define PHY_AD_CSMA             0x0001  // 1=PHY is capable of 802.3 CMSA
283
+
284
+// PHY Auto-negotiation Remote End Capability Register
285
+#define PHY_RMT_REG             0x05
286
+// Uses same bit definitions as PHY_AD_REG
287
+
288
+// PHY Configuration Register 1
289
+#define PHY_CFG1_REG            0x10
290
+#define PHY_CFG1_LNKDIS         0x8000  // 1=Rx Link Detect Function disabled
291
+#define PHY_CFG1_XMTDIS         0x4000  // 1=TP Transmitter Disabled
292
+#define PHY_CFG1_XMTPDN         0x2000  // 1=TP Transmitter Powered Down
293
+#define PHY_CFG1_BYPSCR         0x0400  // 1=Bypass scrambler/descrambler
294
+#define PHY_CFG1_UNSCDS         0x0200  // 1=Unscramble Idle Reception Disable
295
+#define PHY_CFG1_EQLZR          0x0100  // 1=Rx Equalizer Disabled
296
+#define PHY_CFG1_CABLE          0x0080  // 1=STP(150ohm), 0=UTP(100ohm)
297
+#define PHY_CFG1_RLVL0          0x0040  // 1=Rx Squelch level reduced by 4.5db
298
+#define PHY_CFG1_TLVL_SHIFT     2       // Transmit Output Level Adjust
299
+#define PHY_CFG1_TLVL_MASK      0x003C
300
+#define PHY_CFG1_TRF_MASK       0x0003  // Transmitter Rise/Fall time
301
+
302
+
303
+// PHY Configuration Register 2
304
+#define PHY_CFG2_REG            0x11
305
+#define PHY_CFG2_APOLDIS        0x0020  // 1=Auto Polarity Correction disabled
306
+#define PHY_CFG2_JABDIS         0x0010  // 1=Jabber disabled
307
+#define PHY_CFG2_MREG           0x0008  // 1=Multiple register access (MII mgt)
308
+#define PHY_CFG2_INTMDIO        0x0004  // 1=Interrupt signaled with MDIO pulseo
309
+
310
+// PHY Status Output (and Interrupt status) Register
311
+#define PHY_INT_REG             0x12    // Status Output (Interrupt Status)
312
+#define PHY_INT_INT             0x8000  // 1=bits have changed since last read
313
+#define PHY_INT_LNKFAIL         0x4000  // 1=Link Not detected
314
+#define PHY_INT_LOSSSYNC        0x2000  // 1=Descrambler has lost sync
315
+#define PHY_INT_CWRD            0x1000  // 1=Invalid 4B5B code detected on rx
316
+#define PHY_INT_SSD             0x0800  // 1=No Start Of Stream detected on rx
317
+#define PHY_INT_ESD             0x0400  // 1=No End Of Stream detected on rx
318
+#define PHY_INT_RPOL            0x0200  // 1=Reverse Polarity detected
319
+#define PHY_INT_JAB             0x0100  // 1=Jabber detected
320
+#define PHY_INT_SPDDET          0x0080  // 1=100Base-TX mode, 0=10Base-T mode
321
+#define PHY_INT_DPLXDET         0x0040  // 1=Device in Full Duplex
322
+
323
+// PHY Interrupt/Status Mask Register
324
+#define PHY_MASK_REG            0x13    // Interrupt Mask
325
+// Uses the same bit definitions as PHY_INT_REG
326
+
213 327
 
214 328
 // PHY Register Addresses (LAN91C111 Internal PHY)
215 329
 

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