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+#ifndef _HERMON_H
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+#define _HERMON_H
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+
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+/** @file
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+ *
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+ * Mellanox Hermon Infiniband HCA driver
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+ *
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+ */
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+
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+#include <stdint.h>
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+#include <gpxe/uaccess.h>
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+#include "mlx_bitops.h"
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+#include "MT25408_PRM.h"
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+
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+/*
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+ * Hardware constants
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+ *
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+ */
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+
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+/* PCI BARs */
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+#define HERMON_PCI_CONFIG_BAR PCI_BASE_ADDRESS_0
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+#define HERMON_PCI_CONFIG_BAR_SIZE 0x100000
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+#define HERMON_PCI_UAR_BAR PCI_BASE_ADDRESS_2
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+
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+/* Work queue entry and completion queue entry opcodes */
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+#define HERMON_OPCODE_SEND 0x0a
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+#define HERMON_OPCODE_RECV_ERROR 0xfe
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+#define HERMON_OPCODE_SEND_ERROR 0xff
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+
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+/* HCA command register opcodes */
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+#define HERMON_HCR_QUERY_DEV_CAP 0x0003
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+#define HERMON_HCR_QUERY_FW 0x0004
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+#define HERMON_HCR_INIT_HCA 0x0007
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+#define HERMON_HCR_CLOSE_HCA 0x0008
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+#define HERMON_HCR_INIT_PORT 0x0009
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+#define HERMON_HCR_CLOSE_PORT 0x000a
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+#define HERMON_HCR_SW2HW_MPT 0x000d
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+#define HERMON_HCR_WRITE_MTT 0x0011
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+#define HERMON_HCR_MAP_EQ 0x0012
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+#define HERMON_HCR_SW2HW_EQ 0x0013
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+#define HERMON_HCR_HW2SW_EQ 0x0014
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+#define HERMON_HCR_SW2HW_CQ 0x0016
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+#define HERMON_HCR_HW2SW_CQ 0x0017
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+#define HERMON_HCR_RST2INIT_QP 0x0019
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+#define HERMON_HCR_INIT2RTR_QP 0x001a
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+#define HERMON_HCR_RTR2RTS_QP 0x001b
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+#define HERMON_HCR_2RST_QP 0x0021
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+#define HERMON_HCR_MAD_IFC 0x0024
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+#define HERMON_HCR_READ_MCG 0x0025
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+#define HERMON_HCR_WRITE_MCG 0x0026
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+#define HERMON_HCR_MGID_HASH 0x0027
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+#define HERMON_HCR_RUN_FW 0x0ff6
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+#define HERMON_HCR_DISABLE_LAM 0x0ff7
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+#define HERMON_HCR_ENABLE_LAM 0x0ff8
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+#define HERMON_HCR_UNMAP_ICM 0x0ff9
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+#define HERMON_HCR_MAP_ICM 0x0ffa
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+#define HERMON_HCR_UNMAP_ICM_AUX 0x0ffb
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+#define HERMON_HCR_MAP_ICM_AUX 0x0ffc
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+#define HERMON_HCR_SET_ICM_SIZE 0x0ffd
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+#define HERMON_HCR_UNMAP_FA 0x0ffe
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+#define HERMON_HCR_MAP_FA 0x0fff
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+
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+/* Service types */
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+#define HERMON_ST_UD 0x03
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+
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+/* MTUs */
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+#define HERMON_MTU_2048 0x04
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+
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+#define HERMON_INVALID_LKEY 0x00000100UL
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+
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+#define HERMON_PAGE_SIZE 4096
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+
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+#define HERMON_DB_POST_SND_OFFSET 0x14
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+
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+/*
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+ * Datatypes that seem to be missing from the autogenerated documentation
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+ *
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+ */
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+struct hermonprm_mgm_hash_st {
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+ pseudo_bit_t reserved0[0x00020];
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+/* -------------- */
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+ pseudo_bit_t hash[0x00010];
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+ pseudo_bit_t reserved1[0x00010];
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+} __attribute__ (( packed ));
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+
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+struct hermonprm_mcg_entry_st {
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+ struct hermonprm_mcg_hdr_st hdr;
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+ struct hermonprm_mcg_qp_dw_st qp[8];
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+} __attribute__ (( packed ));
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+
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+struct hermonprm_cq_db_record_st {
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+ pseudo_bit_t update_ci[0x00018];
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+ pseudo_bit_t reserved0[0x00008];
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+/* -------------- */
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+ pseudo_bit_t arm_ci[0x00018];
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+ pseudo_bit_t cmd[0x00003];
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+ pseudo_bit_t reserved1[0x00001];
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+ pseudo_bit_t cmd_sn[0x00002];
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+ pseudo_bit_t reserved2[0x00002];
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+} __attribute__ (( packed ));
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+
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+struct hermonprm_send_db_register_st {
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+ pseudo_bit_t reserved[0x00008];
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+ pseudo_bit_t qn[0x00018];
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+} __attribute__ (( packed ));
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+
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+struct hermonprm_scalar_parameter_st {
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+ pseudo_bit_t value_hi[0x00020];
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+/* -------------- */
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+ pseudo_bit_t value[0x00020];
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+} __attribute__ (( packed ));
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+
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+/*
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+ * Wrapper structures for hardware datatypes
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+ *
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+ */
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+
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+struct MLX_DECLARE_STRUCT ( hermonprm_completion_queue_context );
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+struct MLX_DECLARE_STRUCT ( hermonprm_completion_queue_entry );
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+struct MLX_DECLARE_STRUCT ( hermonprm_completion_with_error );
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+struct MLX_DECLARE_STRUCT ( hermonprm_cq_db_record );
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+struct MLX_DECLARE_STRUCT ( hermonprm_eqc );
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+struct MLX_DECLARE_STRUCT ( hermonprm_hca_command_register );
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+struct MLX_DECLARE_STRUCT ( hermonprm_init_hca );
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+struct MLX_DECLARE_STRUCT ( hermonprm_init_port );
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+struct MLX_DECLARE_STRUCT ( hermonprm_mad_ifc );
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+struct MLX_DECLARE_STRUCT ( hermonprm_mcg_entry );
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+struct MLX_DECLARE_STRUCT ( hermonprm_mgm_hash );
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+struct MLX_DECLARE_STRUCT ( hermonprm_mpt );
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+struct MLX_DECLARE_STRUCT ( hermonprm_mtt );
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+struct MLX_DECLARE_STRUCT ( hermonprm_qp_db_record );
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+struct MLX_DECLARE_STRUCT ( hermonprm_qp_ee_state_transitions );
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+struct MLX_DECLARE_STRUCT ( hermonprm_query_dev_cap );
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+struct MLX_DECLARE_STRUCT ( hermonprm_query_fw );
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+struct MLX_DECLARE_STRUCT ( hermonprm_queue_pair_ee_context_entry );
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+struct MLX_DECLARE_STRUCT ( hermonprm_scalar_parameter );
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+struct MLX_DECLARE_STRUCT ( hermonprm_send_db_register );
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+struct MLX_DECLARE_STRUCT ( hermonprm_ud_address_vector );
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+struct MLX_DECLARE_STRUCT ( hermonprm_virtual_physical_mapping );
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+struct MLX_DECLARE_STRUCT ( hermonprm_wqe_segment_ctrl_send );
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+struct MLX_DECLARE_STRUCT ( hermonprm_wqe_segment_data_ptr );
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+struct MLX_DECLARE_STRUCT ( hermonprm_wqe_segment_ud );
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+
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+/*
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+ * Composite hardware datatypes
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+ *
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+ */
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+
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+struct hermonprm_write_mtt {
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+ struct hermonprm_scalar_parameter mtt_base_addr;
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+ struct hermonprm_scalar_parameter reserved;
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+ struct hermonprm_mtt mtt;
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+} __attribute__ (( packed ));
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+
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+#define HERMON_MAX_GATHER 1
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+
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+struct hermonprm_ud_send_wqe {
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+ struct hermonprm_wqe_segment_ctrl_send ctrl;
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+ struct hermonprm_wqe_segment_ud ud;
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+ struct hermonprm_wqe_segment_data_ptr data[HERMON_MAX_GATHER];
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+} __attribute__ (( packed ));
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+
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+#define HERMON_MAX_SCATTER 1
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+
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+struct hermonprm_recv_wqe {
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+ struct hermonprm_wqe_segment_data_ptr data[HERMON_MAX_SCATTER];
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+} __attribute__ (( packed ));
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+
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+union hermonprm_completion_entry {
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+ struct hermonprm_completion_queue_entry normal;
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+ struct hermonprm_completion_with_error error;
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+} __attribute__ (( packed ));
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+
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+union hermonprm_doorbell_register {
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+ struct hermonprm_send_db_register send;
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+ uint32_t dword[1];
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+} __attribute__ (( packed ));
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+
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+union hermonprm_mad {
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+ struct hermonprm_mad_ifc ifc;
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+ union ib_mad mad;
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+} __attribute__ (( packed ));
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+
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+/*
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+ * gPXE-specific definitions
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+ *
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+ */
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+
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+/** Hermon device capabilitiess */
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+struct hermon_dev_cap {
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+ /** CMPT entry size */
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+ size_t cmpt_entry_size;
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+ /** Number of reserved QPs */
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+ unsigned int reserved_qps;
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+ /** QP context entry size */
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+ size_t qpc_entry_size;
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+ /** Alternate path context entry size */
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+ size_t altc_entry_size;
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+ /** Auxiliary context entry size */
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+ size_t auxc_entry_size;
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+ /** Number of reserved SRQs */
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+ unsigned int reserved_srqs;
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+ /** SRQ context entry size */
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+ size_t srqc_entry_size;
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+ /** Number of reserved CQs */
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+ unsigned int reserved_cqs;
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+ /** CQ context entry size */
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+ size_t cqc_entry_size;
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+ /** Number of reserved EQs */
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+ unsigned int reserved_eqs;
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+ /** EQ context entry size */
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+ size_t eqc_entry_size;
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+ /** Number of reserved MTTs */
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+ unsigned int reserved_mtts;
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+ /** MTT entry size */
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+ size_t mtt_entry_size;
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+ /** Number of reserved MRWs */
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+ unsigned int reserved_mrws;
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+ /** DMPT entry size */
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+ size_t dmpt_entry_size;
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+ /** Number of reserved UARs */
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+ unsigned int reserved_uars;
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+};
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+
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+/** Number of cMPT entries of each type */
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+#define HERMON_CMPT_MAX_ENTRIES ( 1 << 24 )
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+
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+/** Hermon ICM memory map entry */
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+struct hermon_icm_map {
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+ /** Offset (virtual address within ICM) */
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+ uint64_t offset;
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+ /** Length */
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+ size_t len;
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+};
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+
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+/** Discontiguous regions within Hermon ICM */
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+enum hermon_icm_map_regions {
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+ HERMON_ICM_QP_CMPT = 0,
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+ HERMON_ICM_SRQ_CMPT,
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+ HERMON_ICM_CQ_CMPT,
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+ HERMON_ICM_EQ_CMPT,
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+ HERMON_ICM_OTHER,
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+ HERMON_ICM_NUM_REGIONS
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+};
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+
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+/** UAR page for doorbell accesses
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+ *
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+ * Pages 0-127 are reserved for event queue doorbells only, so we use
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+ * page 128.
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+ */
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+#define HERMON_UAR_PAGE 128
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+
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+/** Maximum number of allocatable MTT entries
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+ *
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+ * This is a policy decision, not a device limit.
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+ */
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+#define HERMON_MAX_MTTS 64
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+
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+/** A Hermon MTT descriptor */
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+struct hermon_mtt {
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+ /** MTT offset */
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+ unsigned int mtt_offset;
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+ /** Number of pages */
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+ unsigned int num_pages;
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+ /** MTT base address */
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+ unsigned int mtt_base_addr;
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+ /** Offset within page */
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+ unsigned int page_offset;
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+};
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+
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+/** Alignment of Hermon send work queue entries */
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+#define HERMON_SEND_WQE_ALIGN 128
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+
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+/** A Hermon send work queue entry */
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+union hermon_send_wqe {
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+ struct hermonprm_ud_send_wqe ud;
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+ uint8_t force_align[HERMON_SEND_WQE_ALIGN];
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+} __attribute__ (( packed ));
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+
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+/** A Hermon send work queue */
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+struct hermon_send_work_queue {
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+ /** Number of work queue entries, including headroom
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+ *
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+ * Hermon requires us to leave unused space within the send
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+ * WQ, so we create a send WQ with more entries than are
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+ * requested in the create_qp() call.
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+ */
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+ unsigned int num_wqes;
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+ /** Work queue entries */
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+ union hermon_send_wqe *wqe;
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+ /** Size of work queue */
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+ size_t wqe_size;
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+};
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+
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+/** Alignment of Hermon receive work queue entries */
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+#define HERMON_RECV_WQE_ALIGN 16
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+
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+/** A Hermon receive work queue entry */
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+union hermon_recv_wqe {
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+ struct hermonprm_recv_wqe recv;
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+ uint8_t force_align[HERMON_RECV_WQE_ALIGN];
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+} __attribute__ (( packed ));
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+
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+/** A Hermon receive work queue */
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+struct hermon_recv_work_queue {
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+ /** Work queue entries */
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+ union hermon_recv_wqe *wqe;
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+ /** Size of work queue */
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+ size_t wqe_size;
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+ /** Doorbell */
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+ struct hermonprm_qp_db_record doorbell __attribute__ (( aligned (4) ));
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+};
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+
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+/** Maximum number of allocatable queue pairs
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+ *
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+ * This is a policy decision, not a device limit.
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+ */
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+#define HERMON_MAX_QPS 8
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+
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+/** Base queue pair number */
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+#define HERMON_QPN_BASE 0x550000
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+
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+/** A Hermon queue pair */
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+struct hermon_queue_pair {
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+ /** Work queue buffer */
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+ void *wqe;
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+ /** Size of work queue buffer */
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+ size_t wqe_size;
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+ /** MTT descriptor */
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+ struct hermon_mtt mtt;
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+ /** Send work queue */
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+ struct hermon_send_work_queue send;
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+ /** Receive work queue */
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+ struct hermon_recv_work_queue recv;
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+};
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+
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+/** Maximum number of allocatable completion queues
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+ *
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+ * This is a policy decision, not a device limit.
|
|
340
|
+ */
|
|
341
|
+#define HERMON_MAX_CQS 8
|
|
342
|
+
|
|
343
|
+/** A Hermon completion queue */
|
|
344
|
+struct hermon_completion_queue {
|
|
345
|
+ /** Completion queue entries */
|
|
346
|
+ union hermonprm_completion_entry *cqe;
|
|
347
|
+ /** Size of completion queue */
|
|
348
|
+ size_t cqe_size;
|
|
349
|
+ /** MTT descriptor */
|
|
350
|
+ struct hermon_mtt mtt;
|
|
351
|
+ /** Doorbell */
|
|
352
|
+ struct hermonprm_cq_db_record doorbell __attribute__ (( aligned (8) ));
|
|
353
|
+};
|
|
354
|
+
|
|
355
|
+/** Maximum number of allocatable event queues
|
|
356
|
+ *
|
|
357
|
+ * This is a policy decision, not a device limit.
|
|
358
|
+ */
|
|
359
|
+#define HERMON_MAX_EQS 4
|
|
360
|
+
|
|
361
|
+/** A Hermon resource bitmask */
|
|
362
|
+typedef uint32_t hermon_bitmask_t;
|
|
363
|
+
|
|
364
|
+/** Size of a hermon resource bitmask */
|
|
365
|
+#define HERMON_BITMASK_SIZE(max_entries) \
|
|
366
|
+ ( ( (max_entries) + ( 8 * sizeof ( hermon_bitmask_t ) ) - 1 ) / \
|
|
367
|
+ ( 8 * sizeof ( hermon_bitmask_t ) ) )
|
|
368
|
+
|
|
369
|
+/** A Hermon device */
|
|
370
|
+struct hermon {
|
|
371
|
+ /** PCI configuration registers */
|
|
372
|
+ void *config;
|
|
373
|
+ /** PCI user Access Region */
|
|
374
|
+ void *uar;
|
|
375
|
+
|
|
376
|
+ /** Command toggle */
|
|
377
|
+ unsigned int toggle;
|
|
378
|
+ /** Command input mailbox */
|
|
379
|
+ void *mailbox_in;
|
|
380
|
+ /** Command output mailbox */
|
|
381
|
+ void *mailbox_out;
|
|
382
|
+
|
|
383
|
+ /** Firmware area in external memory */
|
|
384
|
+ userptr_t firmware_area;
|
|
385
|
+ /** ICM map */
|
|
386
|
+ struct hermon_icm_map icm_map[HERMON_ICM_NUM_REGIONS];
|
|
387
|
+ /** ICM area */
|
|
388
|
+ userptr_t icm;
|
|
389
|
+
|
|
390
|
+ /** Reserved LKey
|
|
391
|
+ *
|
|
392
|
+ * Used to get unrestricted memory access.
|
|
393
|
+ */
|
|
394
|
+ unsigned long reserved_lkey;
|
|
395
|
+
|
|
396
|
+ /** Completion queue in-use bitmask */
|
|
397
|
+ hermon_bitmask_t cq_inuse[ HERMON_BITMASK_SIZE ( HERMON_MAX_CQS ) ];
|
|
398
|
+ /** Queue pair in-use bitmask */
|
|
399
|
+ hermon_bitmask_t qp_inuse[ HERMON_BITMASK_SIZE ( HERMON_MAX_QPS ) ];
|
|
400
|
+ /** MTT entry in-use bitmask */
|
|
401
|
+ hermon_bitmask_t mtt_inuse[ HERMON_BITMASK_SIZE ( HERMON_MAX_MTTS ) ];
|
|
402
|
+
|
|
403
|
+ /** Device capabilities */
|
|
404
|
+ struct hermon_dev_cap cap;
|
|
405
|
+};
|
|
406
|
+
|
|
407
|
+/** Global protection domain */
|
|
408
|
+#define HERMON_GLOBAL_PD 0x123456
|
|
409
|
+
|
|
410
|
+/** Memory key prefix */
|
|
411
|
+#define HERMON_MKEY_PREFIX 0x77000000UL
|
|
412
|
+
|
|
413
|
+/*
|
|
414
|
+ * HCA commands
|
|
415
|
+ *
|
|
416
|
+ */
|
|
417
|
+
|
|
418
|
+#define HERMON_HCR_BASE 0x80680
|
|
419
|
+#define HERMON_HCR_REG(x) ( HERMON_HCR_BASE + 4 * (x) )
|
|
420
|
+#define HERMON_HCR_MAX_WAIT_MS 2000
|
|
421
|
+#define HERMON_MBOX_ALIGN 4096
|
|
422
|
+#define HERMON_MBOX_SIZE 512
|
|
423
|
+
|
|
424
|
+/* HCA command is split into
|
|
425
|
+ *
|
|
426
|
+ * bits 11:0 Opcode
|
|
427
|
+ * bit 12 Input uses mailbox
|
|
428
|
+ * bit 13 Output uses mailbox
|
|
429
|
+ * bits 22:14 Input parameter length (in dwords)
|
|
430
|
+ * bits 31:23 Output parameter length (in dwords)
|
|
431
|
+ *
|
|
432
|
+ * Encoding the information in this way allows us to cut out several
|
|
433
|
+ * parameters to the hermon_command() call.
|
|
434
|
+ */
|
|
435
|
+#define HERMON_HCR_IN_MBOX 0x00001000UL
|
|
436
|
+#define HERMON_HCR_OUT_MBOX 0x00002000UL
|
|
437
|
+#define HERMON_HCR_OPCODE( _command ) ( (_command) & 0xfff )
|
|
438
|
+#define HERMON_HCR_IN_LEN( _command ) ( ( (_command) >> 12 ) & 0x7fc )
|
|
439
|
+#define HERMON_HCR_OUT_LEN( _command ) ( ( (_command) >> 21 ) & 0x7fc )
|
|
440
|
+
|
|
441
|
+/** Build HCR command from component parts */
|
|
442
|
+#define HERMON_HCR_INOUT_CMD( _opcode, _in_mbox, _in_len, \
|
|
443
|
+ _out_mbox, _out_len ) \
|
|
444
|
+ ( (_opcode) | \
|
|
445
|
+ ( (_in_mbox) ? HERMON_HCR_IN_MBOX : 0 ) | \
|
|
446
|
+ ( ( (_in_len) / 4 ) << 14 ) | \
|
|
447
|
+ ( (_out_mbox) ? HERMON_HCR_OUT_MBOX : 0 ) | \
|
|
448
|
+ ( ( (_out_len) / 4 ) << 23 ) )
|
|
449
|
+
|
|
450
|
+#define HERMON_HCR_IN_CMD( _opcode, _in_mbox, _in_len ) \
|
|
451
|
+ HERMON_HCR_INOUT_CMD ( _opcode, _in_mbox, _in_len, 0, 0 )
|
|
452
|
+
|
|
453
|
+#define HERMON_HCR_OUT_CMD( _opcode, _out_mbox, _out_len ) \
|
|
454
|
+ HERMON_HCR_INOUT_CMD ( _opcode, 0, 0, _out_mbox, _out_len )
|
|
455
|
+
|
|
456
|
+#define HERMON_HCR_VOID_CMD( _opcode ) \
|
|
457
|
+ HERMON_HCR_INOUT_CMD ( _opcode, 0, 0, 0, 0 )
|
|
458
|
+
|
|
459
|
+#endif /* _HERMON_H */
|