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[realtek] Replace driver for Realtek Gigabit NICs

Tested-by: Thomas Miletich <thomas.miletich@gmail.com>
Debugged-by: Thomas Miletich <thomas.miletich@gmail.com>
Tested-by: Robin Smidsrød <robin@smidsrod.no>
Signed-off-by: Michael Brown <mcb30@ipxe.org>
tags/v1.20.1
Michael Brown преди 12 години
родител
ревизия
2a0154db5b
променени са 5 файла, в които са добавени 985 реда и са изтрити 2718 реда
  1. 0
    2232
      src/drivers/net/r8169.c
  2. 0
    486
      src/drivers/net/r8169.h
  3. 779
    0
      src/drivers/net/realtek.c
  4. 205
    0
      src/drivers/net/realtek.h
  5. 1
    0
      src/include/ipxe/errfile.h

+ 0
- 2232
src/drivers/net/r8169.c
Файловите разлики са ограничени, защото са твърде много
Целия файл


+ 0
- 486
src/drivers/net/r8169.h Целия файл

@@ -1,486 +0,0 @@
1
-/*
2
- * Copyright (c) 2008 Marty Connor <mdc@etherboot.org>
3
- * Copyright (c) 2008 Entity Cyber, Inc.
4
- *
5
- * This program is free software; you can redistribute it and/or
6
- * modify it under the terms of the GNU General Public License as
7
- * published by the Free Software Foundation; either version 2 of the
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- * License, or any later version.
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- *
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- * This program is distributed in the hope that it will be useful, but
11
- * WITHOUT ANY WARRANTY; without even the implied warranty of
12
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13
- * General Public License for more details.
14
- *
15
- * You should have received a copy of the GNU General Public License
16
- * along with this program; if not, write to the Free Software
17
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18
- *
19
- * This driver is based on rtl8169 data sheets and work by:
20
- *
21
- * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
22
- * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
23
- * Copyright (c) a lot of people too. Please respect their work.
24
- *
25
- */
26
-
27
-FILE_LICENCE ( GPL2_OR_LATER );
28
-
29
-#ifndef _R8169_H_
30
-#define _R8169_H_
31
-
32
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
33
-
34
-/** FIXME: include/linux/pci_regs.h has these PCI regs, maybe
35
-	   we need such a file in iPXE?
36
-**/
37
-#define  PCI_EXP_DEVCTL	        8	/* Device Control */
38
-#define  PCI_EXP_DEVCTL_READRQ	0x7000	/* Max_Read_Request_Size */
39
-#define  PCI_EXP_LNKCTL		16	/* Link Control */
40
-#define  PCI_EXP_LNKCTL_CLKREQ_EN 0x100	/* Enable clkreq */
41
-#define  PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800  /* Enable No Snoop */
42
-
43
-/** FIXME: update mii.h in src/include/mii.h from Linux sources
44
-	   so we don't have to include these definitiions.
45
-**/
46
-/* The forced speed, 10Mb, 100Mb, gigabit, 2.5Gb, 10GbE. */
47
-#define SPEED_10		10
48
-#define SPEED_100		100
49
-#define SPEED_1000		1000
50
-#define SPEED_2500		2500
51
-#define SPEED_10000		10000
52
-
53
-/* Duplex, half or full. */
54
-#define DUPLEX_HALF		0x00
55
-#define DUPLEX_FULL		0x01
56
-
57
-#define AUTONEG_DISABLE		0x00
58
-#define AUTONEG_ENABLE		0x01
59
-
60
-/* MAC address length */
61
-#define MAC_ADDR_LEN	6
62
-
63
-#define MAX_READ_REQUEST_SHIFT	12
64
-#define RX_FIFO_THRESH	7	/* 7 means NO threshold, Rx buffer level before first PCI xfer. */
65
-#define RX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */
66
-#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */
67
-#define EarlyTxThld	0x3F	/* 0x3F means NO early transmit */
68
-#define RxPacketMaxSize	0x3FE8	/* 16K - 1 - ETH_HLEN - VLAN - CRC... */
69
-#define SafeMtu		0x1c20	/* ... actually life sucks beyond ~7k */
70
-#define InterFrameGap	0x03	/* 3 means InterFrameGap = the shortest one */
71
-
72
-#define R8169_REGS_SIZE		256
73
-#define R8169_NAPI_WEIGHT	64
74
-#define NUM_TX_DESC	8	/* Number of Tx descriptor registers */
75
-#define NUM_RX_DESC	8	/* Number of Rx descriptor registers */
76
-#define RX_BUF_SIZE	1536	/* Rx Buffer size */
77
-#define R8169_TX_RING_BYTES	(NUM_TX_DESC * sizeof(struct TxDesc))
78
-#define R8169_RX_RING_BYTES	(NUM_RX_DESC * sizeof(struct RxDesc))
79
-
80
-#define TX_RING_ALIGN		256
81
-#define RX_RING_ALIGN		256
82
-
83
-#define RTL8169_TX_TIMEOUT	(6*HZ)
84
-#define RTL8169_PHY_TIMEOUT	(10*HZ)
85
-
86
-#define RTL_EEPROM_SIG		cpu_to_le32(0x8129)
87
-#define RTL_EEPROM_SIG_MASK	cpu_to_le32(0xffff)
88
-#define RTL_EEPROM_SIG_ADDR	0x0000
89
-
90
-/* write/read MMIO register */
91
-#define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))
92
-#define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))
93
-#define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))
94
-#define RTL_R8(reg)		readb (ioaddr + (reg))
95
-#define RTL_R16(reg)		readw (ioaddr + (reg))
96
-#define RTL_R32(reg)		((unsigned long) readl (ioaddr + (reg)))
97
-
98
-enum mac_version {
99
-	RTL_GIGA_MAC_VER_01 = 0x01, // 8169
100
-	RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
101
-	RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
102
-	RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
103
-	RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
104
-	RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
105
-	RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
106
-	RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
107
-	RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
108
-	RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
109
-	RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
110
-	RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
111
-	RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
112
-	RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
113
-	RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
114
-	RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
115
-	RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
116
-	RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
117
-	RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
118
-	RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
119
-	RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
120
-	RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
121
-	RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
122
-	RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
123
-	RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
124
-};
125
-
126
-#define _R(NAME,MAC,MASK) \
127
-	{ .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
128
-
129
-static const struct {
130
-	const char *name;
131
-	u8 mac_version;
132
-	u32 RxConfigMask;	/* Clears the bits supported by this chip */
133
-} rtl_chip_info[] = {
134
-	_R("RTL8169",		RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
135
-	_R("RTL8169s",		RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
136
-	_R("RTL8110s",		RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
137
-	_R("RTL8169sb/8110sb",	RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
138
-	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
139
-	_R("RTL8169sc/8110sc",	RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
140
-	_R("RTL8102e",		RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
141
-	_R("RTL8102e",		RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
142
-	_R("RTL8102e",		RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
143
-	_R("RTL8101e",		RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
144
-	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
145
-	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
146
-	_R("RTL8101e",		RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
147
-	_R("RTL8100e",		RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
148
-	_R("RTL8100e",		RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
149
-	_R("RTL8168b/8111b",	RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
150
-	_R("RTL8101e",		RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
151
-	_R("RTL8168cp/8111cp",	RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
152
-	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
153
-	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
154
-	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
155
-	_R("RTL8168c/8111c",	RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
156
-	_R("RTL8168cp/8111cp",	RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
157
-	_R("RTL8168cp/8111cp",	RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
158
-	_R("RTL8168d/8111d",	RTL_GIGA_MAC_VER_25, 0xff7e1880)  // PCI-E
159
-};
160
-#undef _R
161
-
162
-enum cfg_version {
163
-	RTL_CFG_0 = 0x00,
164
-	RTL_CFG_1,
165
-	RTL_CFG_2
166
-};
167
-
168
-#if 0
169
-/** Device Table from Linux Driver **/
170
-static struct pci_device_id rtl8169_pci_tbl[] = {
171
-	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8129), 0, 0, RTL_CFG_0 },
172
-	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8136), 0, 0, RTL_CFG_2 },
173
-	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8167), 0, 0, RTL_CFG_0 },
174
-	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8168), 0, 0, RTL_CFG_1 },
175
-	{ PCI_DEVICE(PCI_VENDOR_ID_REALTEK,	0x8169), 0, 0, RTL_CFG_0 },
176
-	{ PCI_DEVICE(PCI_VENDOR_ID_DLINK,	0x4300), 0, 0, RTL_CFG_0 },
177
-	{ PCI_DEVICE(PCI_VENDOR_ID_AT,		0xc107), 0, 0, RTL_CFG_0 },
178
-	{ PCI_DEVICE(0x16ec,			0x0116), 0, 0, RTL_CFG_0 },
179
-	{ PCI_VENDOR_ID_LINKSYS,		0x1032,
180
-		PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
181
-	{ 0x0001,				0x8168,
182
-		PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
183
-	{0,},
184
-};
185
-#endif
186
-
187
-enum rtl_registers {
188
-	MAC0		= 0,	/* Ethernet hardware address. */
189
-	MAC4		= 4,
190
-	MAR0		= 8,	/* Multicast filter. */
191
-	CounterAddrLow		= 0x10,
192
-	CounterAddrHigh		= 0x14,
193
-	TxDescStartAddrLow	= 0x20,
194
-	TxDescStartAddrHigh	= 0x24,
195
-	TxHDescStartAddrLow	= 0x28,
196
-	TxHDescStartAddrHigh	= 0x2c,
197
-	FLASH		= 0x30,
198
-	ERSR		= 0x36,
199
-	ChipCmd		= 0x37,
200
-	TxPoll		= 0x38,
201
-	IntrMask	= 0x3c,
202
-	IntrStatus	= 0x3e,
203
-	TxConfig	= 0x40,
204
-	RxConfig	= 0x44,
205
-	RxMissed	= 0x4c,
206
-	Cfg9346		= 0x50,
207
-	Config0		= 0x51,
208
-	Config1		= 0x52,
209
-	Config2		= 0x53,
210
-	Config3		= 0x54,
211
-	Config4		= 0x55,
212
-	Config5		= 0x56,
213
-	MultiIntr	= 0x5c,
214
-	PHYAR		= 0x60,
215
-	PHYstatus	= 0x6c,
216
-	RxMaxSize	= 0xda,
217
-	CPlusCmd	= 0xe0,
218
-	IntrMitigate	= 0xe2,
219
-	RxDescAddrLow	= 0xe4,
220
-	RxDescAddrHigh	= 0xe8,
221
-	EarlyTxThres	= 0xec,
222
-	FuncEvent	= 0xf0,
223
-	FuncEventMask	= 0xf4,
224
-	FuncPresetState	= 0xf8,
225
-	FuncForceEvent	= 0xfc,
226
-};
227
-
228
-enum rtl8110_registers {
229
-	TBICSR			= 0x64,
230
-	TBI_ANAR		= 0x68,
231
-	TBI_LPAR		= 0x6a,
232
-};
233
-
234
-enum rtl8168_8101_registers {
235
-	CSIDR			= 0x64,
236
-	CSIAR			= 0x68,
237
-#define	CSIAR_FLAG			0x80000000
238
-#define	CSIAR_WRITE_CMD			0x80000000
239
-#define	CSIAR_BYTE_ENABLE		0x0f
240
-#define	CSIAR_BYTE_ENABLE_SHIFT		12
241
-#define	CSIAR_ADDR_MASK			0x0fff
242
-
243
-	EPHYAR			= 0x80,
244
-#define	EPHYAR_FLAG			0x80000000
245
-#define	EPHYAR_WRITE_CMD		0x80000000
246
-#define	EPHYAR_REG_MASK			0x1f
247
-#define	EPHYAR_REG_SHIFT		16
248
-#define	EPHYAR_DATA_MASK		0xffff
249
-	DBG_REG			= 0xd1,
250
-#define	FIX_NAK_1			(1 << 4)
251
-#define	FIX_NAK_2			(1 << 3)
252
-};
253
-
254
-enum rtl_register_content {
255
-	/* InterruptStatusBits */
256
-	SYSErr		= 0x8000,
257
-	PCSTimeout	= 0x4000,
258
-	SWInt		= 0x0100,
259
-	TxDescUnavail	= 0x0080,
260
-	RxFIFOOver	= 0x0040,
261
-	LinkChg		= 0x0020,
262
-	RxOverflow	= 0x0010,
263
-	TxErr		= 0x0008,
264
-	TxOK		= 0x0004,
265
-	RxErr		= 0x0002,
266
-	RxOK		= 0x0001,
267
-
268
-	/* RxStatusDesc */
269
-	RxFOVF	= (1 << 23),
270
-	RxRWT	= (1 << 22),
271
-	RxRES	= (1 << 21),
272
-	RxRUNT	= (1 << 20),
273
-	RxCRC	= (1 << 19),
274
-
275
-	/* ChipCmdBits */
276
-	CmdReset	= 0x10,
277
-	CmdRxEnb	= 0x08,
278
-	CmdTxEnb	= 0x04,
279
-	RxBufEmpty	= 0x01,
280
-
281
-	/* TXPoll register p.5 */
282
-	HPQ		= 0x80,		/* Poll cmd on the high prio queue */
283
-	NPQ		= 0x40,		/* Poll cmd on the low prio queue */
284
-	FSWInt		= 0x01,		/* Forced software interrupt */
285
-
286
-	/* Cfg9346Bits */
287
-	Cfg9346_Lock	= 0x00,
288
-	Cfg9346_Unlock	= 0xc0,
289
-
290
-	/* rx_mode_bits */
291
-	AcceptErr	= 0x20,
292
-	AcceptRunt	= 0x10,
293
-	AcceptBroadcast	= 0x08,
294
-	AcceptMulticast	= 0x04,
295
-	AcceptMyPhys	= 0x02,
296
-	AcceptAllPhys	= 0x01,
297
-
298
-	/* RxConfigBits */
299
-	RxCfgFIFOShift	= 13,
300
-	RxCfgDMAShift	=  8,
301
-
302
-	/* TxConfigBits */
303
-	TxInterFrameGapShift = 24,
304
-	TxDMAShift = 8,	/* DMA burst value (0-7) is shift this many bits */
305
-
306
-	/* Config1 register p.24 */
307
-	LEDS1		= (1 << 7),
308
-	LEDS0		= (1 << 6),
309
-	MSIEnable	= (1 << 5),	/* Enable Message Signaled Interrupt */
310
-	Speed_down	= (1 << 4),
311
-	MEMMAP		= (1 << 3),
312
-	IOMAP		= (1 << 2),
313
-	VPD		= (1 << 1),
314
-	PMEnable	= (1 << 0),	/* Power Management Enable */
315
-
316
-	/* Config2 register p. 25 */
317
-	PCI_Clock_66MHz = 0x01,
318
-	PCI_Clock_33MHz = 0x00,
319
-
320
-	/* Config3 register p.25 */
321
-	MagicPacket	= (1 << 5),	/* Wake up when receives a Magic Packet */
322
-	LinkUp		= (1 << 4),	/* Wake up when the cable connection is re-established */
323
-	Beacon_en	= (1 << 0),	/* 8168 only. Reserved in the 8168b */
324
-
325
-	/* Config5 register p.27 */
326
-	BWF		= (1 << 6),	/* Accept Broadcast wakeup frame */
327
-	MWF		= (1 << 5),	/* Accept Multicast wakeup frame */
328
-	UWF		= (1 << 4),	/* Accept Unicast wakeup frame */
329
-	LanWake		= (1 << 1),	/* LanWake enable/disable */
330
-	PMEStatus	= (1 << 0),	/* PME status can be reset by PCI RST# */
331
-
332
-	/* TBICSR p.28 */
333
-	TBIReset	= 0x80000000,
334
-	TBILoopback	= 0x40000000,
335
-	TBINwEnable	= 0x20000000,
336
-	TBINwRestart	= 0x10000000,
337
-	TBILinkOk	= 0x02000000,
338
-	TBINwComplete	= 0x01000000,
339
-
340
-	/* CPlusCmd p.31 */
341
-	EnableBist	= (1 << 15),	// 8168 8101
342
-	Mac_dbgo_oe	= (1 << 14),	// 8168 8101
343
-	Normal_mode	= (1 << 13),	// unused
344
-	Force_half_dup	= (1 << 12),	// 8168 8101
345
-	Force_rxflow_en	= (1 << 11),	// 8168 8101
346
-	Force_txflow_en	= (1 << 10),	// 8168 8101
347
-	Cxpl_dbg_sel	= (1 << 9),	// 8168 8101
348
-	ASF		= (1 << 8),	// 8168 8101
349
-	PktCntrDisable	= (1 << 7),	// 8168 8101
350
-	Mac_dbgo_sel	= 0x001c,	// 8168
351
-	RxVlan		= (1 << 6),
352
-	RxChkSum	= (1 << 5),
353
-	PCIDAC		= (1 << 4),
354
-	PCIMulRW	= (1 << 3),
355
-	INTT_0		= 0x0000,	// 8168
356
-	INTT_1		= 0x0001,	// 8168
357
-	INTT_2		= 0x0002,	// 8168
358
-	INTT_3		= 0x0003,	// 8168
359
-
360
-	/* rtl8169_PHYstatus */
361
-	TBI_Enable	= 0x80,
362
-	TxFlowCtrl	= 0x40,
363
-	RxFlowCtrl	= 0x20,
364
-	_1000bpsF	= 0x10,
365
-	_100bps		= 0x08,
366
-	_10bps		= 0x04,
367
-	LinkStatus	= 0x02,
368
-	FullDup		= 0x01,
369
-
370
-	/* _TBICSRBit */
371
-	TBILinkOK	= 0x02000000,
372
-
373
-	/* DumpCounterCommand */
374
-	CounterDump	= 0x8,
375
-};
376
-
377
-enum desc_status_bit {
378
-	DescOwn		= (1 << 31), /* Descriptor is owned by NIC */
379
-	RingEnd		= (1 << 30), /* End of descriptor ring */
380
-	FirstFrag	= (1 << 29), /* First segment of a packet */
381
-	LastFrag	= (1 << 28), /* Final segment of a packet */
382
-
383
-	/* Tx private */
384
-	LargeSend	= (1 << 27), /* TCP Large Send Offload (TSO) */
385
-	MSSShift	= 16,        /* MSS value position */
386
-	MSSMask		= 0xfff,     /* MSS value + LargeSend bit: 12 bits */
387
-	IPCS		= (1 << 18), /* Calculate IP checksum */
388
-	UDPCS		= (1 << 17), /* Calculate UDP/IP checksum */
389
-	TCPCS		= (1 << 16), /* Calculate TCP/IP checksum */
390
-	TxVlanTag	= (1 << 17), /* Add VLAN tag */
391
-
392
-	/* Rx private */
393
-	PID1		= (1 << 18), /* Protocol ID bit 1/2 */
394
-	PID0		= (1 << 17), /* Protocol ID bit 2/2 */
395
-
396
-#define RxProtoUDP	(PID1)
397
-#define RxProtoTCP	(PID0)
398
-#define RxProtoIP	(PID1 | PID0)
399
-#define RxProtoMask	RxProtoIP
400
-
401
-	IPFail		= (1 << 16), /* IP checksum failed */
402
-	UDPFail		= (1 << 15), /* UDP/IP checksum failed */
403
-	TCPFail		= (1 << 14), /* TCP/IP checksum failed */
404
-	RxVlanTag	= (1 << 16), /* VLAN tag available */
405
-};
406
-
407
-#define RsvdMask	0x3fffc000
408
-
409
-struct TxDesc {
410
-	volatile uint32_t opts1;
411
-	volatile uint32_t opts2;
412
-	volatile uint32_t addr_lo;
413
-	volatile uint32_t addr_hi;
414
-};
415
-
416
-struct RxDesc {
417
-	volatile uint32_t opts1;
418
-	volatile uint32_t opts2;
419
-	volatile uint32_t addr_lo;
420
-	volatile uint32_t addr_hi;
421
-};
422
-
423
-enum features {
424
-	RTL_FEATURE_WOL		= (1 << 0),
425
-	RTL_FEATURE_MSI		= (1 << 1),
426
-	RTL_FEATURE_GMII	= (1 << 2),
427
-};
428
-
429
-static void rtl_hw_start_8169(struct net_device *);
430
-static void rtl_hw_start_8168(struct net_device *);
431
-static void rtl_hw_start_8101(struct net_device *);
432
-
433
-struct rtl8169_private {
434
-
435
-	struct pci_device *pci_dev;
436
-	struct net_device *netdev;
437
-	uint8_t *hw_addr;
438
-	void *mmio_addr;
439
-	uint32_t irqno;
440
-
441
-	int chipset;
442
-	int mac_version;
443
-	u16 intr_event;
444
-
445
-	struct io_buffer *tx_iobuf[NUM_TX_DESC];
446
-	struct io_buffer *rx_iobuf[NUM_RX_DESC];
447
-
448
-	struct TxDesc *tx_base;
449
-	struct RxDesc *rx_base;
450
-
451
-	uint32_t tx_curr;
452
-	uint32_t rx_curr;
453
-
454
-	uint32_t tx_tail;
455
-
456
-	uint32_t tx_fill_ctr;
457
-
458
-	u16 cp_cmd;
459
-
460
-	int phy_auto_nego_reg;
461
-	int phy_1000_ctrl_reg;
462
-
463
-	int ( *set_speed ) (struct net_device *, u8 autoneg, u16 speed, u8 duplex );
464
-	void ( *phy_reset_enable ) ( void *ioaddr );
465
-	void ( *hw_start ) ( struct net_device * );
466
-	unsigned int ( *phy_reset_pending ) ( void *ioaddr );
467
-	unsigned int ( *link_ok ) ( void *ioaddr );
468
-
469
-	int pcie_cap;
470
-
471
-	unsigned features;
472
-
473
-};
474
-
475
-static const unsigned int rtl8169_rx_config =
476
-	(RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
477
-
478
-#endif /* _R8169_H_ */
479
-
480
-/*
481
- * Local variables:
482
- *  c-basic-offset: 8
483
- *  c-indent-level: 8
484
- *  tab-width: 8
485
- * End:
486
- */

+ 779
- 0
src/drivers/net/realtek.c Целия файл

@@ -0,0 +1,779 @@
1
+/*
2
+ * Copyright (C) 2012 Michael Brown <mbrown@fensystems.co.uk>.
3
+ *
4
+ * (EEPROM code originally implemented for rtl8139.c)
5
+ *
6
+ * This program is free software; you can redistribute it and/or
7
+ * modify it under the terms of the GNU General Public License as
8
+ * published by the Free Software Foundation; either version 2 of the
9
+ * License, or (at your option) any later version.
10
+ *
11
+ * This program is distributed in the hope that it will be useful, but
12
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
13
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
+ * General Public License for more details.
15
+ *
16
+ * You should have received a copy of the GNU General Public License
17
+ * along with this program; if not, write to the Free Software
18
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19
+ * 02110-1301, USA.
20
+ */
21
+
22
+FILE_LICENCE ( GPL2_OR_LATER );
23
+
24
+#include <stdint.h>
25
+#include <string.h>
26
+#include <unistd.h>
27
+#include <errno.h>
28
+#include <byteswap.h>
29
+#include <ipxe/netdevice.h>
30
+#include <ipxe/ethernet.h>
31
+#include <ipxe/if_ether.h>
32
+#include <ipxe/iobuf.h>
33
+#include <ipxe/malloc.h>
34
+#include <ipxe/pci.h>
35
+#include <ipxe/nvs.h>
36
+#include <ipxe/threewire.h>
37
+#include <ipxe/bitbash.h>
38
+#include <ipxe/mii.h>
39
+#include "realtek.h"
40
+
41
+/** @file
42
+ *
43
+ * Realtek 10/100/1000 network card driver
44
+ *
45
+ * Based on the following datasheets:
46
+ *
47
+ *    http://www.datasheetarchive.com/dl/Datasheets-8/DSA-153536.pdf
48
+ *    http://www.datasheetarchive.com/indexdl/Datasheet-028/DSA00494723.pdf
49
+ */
50
+
51
+/******************************************************************************
52
+ *
53
+ * EEPROM interface
54
+ *
55
+ ******************************************************************************
56
+ */
57
+
58
+/** Pin mapping for SPI bit-bashing interface */
59
+static const uint8_t realtek_eeprom_bits[] = {
60
+	[SPI_BIT_SCLK]	= RTL_9346CR_EESK,
61
+	[SPI_BIT_MOSI]	= RTL_9346CR_EEDI,
62
+	[SPI_BIT_MISO]	= RTL_9346CR_EEDO,
63
+	[SPI_BIT_SS(0)]	= ( RTL_9346CR_EECS | RTL_9346CR_EEM1 ),
64
+};
65
+
66
+/**
67
+ * Read input bit
68
+ *
69
+ * @v basher		Bit-bashing interface
70
+ * @v bit_id		Bit number
71
+ * @ret zero		Input is a logic 0
72
+ * @ret non-zero	Input is a logic 1
73
+ */
74
+static int realtek_spi_read_bit ( struct bit_basher *basher,
75
+				  unsigned int bit_id ) {
76
+	struct realtek_nic *rtl = container_of ( basher, struct realtek_nic,
77
+						 spibit.basher );
78
+	uint8_t mask = realtek_eeprom_bits[bit_id];
79
+	uint8_t reg;
80
+
81
+	reg = readb ( rtl->regs + RTL_9346CR );
82
+	return ( reg & mask );
83
+}
84
+
85
+/**
86
+ * Set/clear output bit
87
+ *
88
+ * @v basher		Bit-bashing interface
89
+ * @v bit_id		Bit number
90
+ * @v data		Value to write
91
+ */
92
+static void realtek_spi_write_bit ( struct bit_basher *basher,
93
+				    unsigned int bit_id, unsigned long data ) {
94
+	struct realtek_nic *rtl = container_of ( basher, struct realtek_nic,
95
+						 spibit.basher );
96
+	uint8_t mask = realtek_eeprom_bits[bit_id];
97
+	uint8_t reg;
98
+
99
+	reg = readb ( rtl->regs + RTL_9346CR );
100
+	reg &= ~mask;
101
+	reg |= ( data & mask );
102
+	writeb ( reg, rtl->regs + RTL_9346CR );
103
+}
104
+
105
+/** SPI bit-bashing interface */
106
+static struct bit_basher_operations realtek_basher_ops = {
107
+	.read = realtek_spi_read_bit,
108
+	.write = realtek_spi_write_bit,
109
+};
110
+
111
+/**
112
+ * Initialise EEPROM
113
+ *
114
+ * @v netdev		Network device
115
+ */
116
+static void realtek_init_eeprom ( struct net_device *netdev ) {
117
+	struct realtek_nic *rtl = netdev->priv;
118
+
119
+	/* Initialise SPI bit-bashing interface */
120
+	rtl->spibit.basher.op = &realtek_basher_ops;
121
+	rtl->spibit.bus.mode = SPI_MODE_THREEWIRE;
122
+	init_spi_bit_basher ( &rtl->spibit );
123
+
124
+	/* Detect EEPROM type and initialise three-wire device */
125
+	if ( readl ( rtl->regs + RTL_RCR ) & RTL_RCR_9356SEL ) {
126
+		DBGC ( rtl, "REALTEK %p EEPROM is a 93C56\n", rtl );
127
+		init_at93c56 ( &rtl->eeprom, 16 );
128
+	} else {
129
+		DBGC ( rtl, "REALTEK %p EEPROM is a 93C46\n", rtl );
130
+		init_at93c46 ( &rtl->eeprom, 16 );
131
+	}
132
+	rtl->eeprom.bus = &rtl->spibit.bus;
133
+
134
+	/* Initialise space for non-volatile options, if available
135
+	 *
136
+	 * We use offset 0x40 (i.e. address 0x20), length 0x40.  This
137
+	 * block is marked as VPD in the Realtek datasheets, so we use
138
+	 * it only if we detect that the card is not supporting VPD.
139
+	 */
140
+	if ( readb ( rtl->regs + RTL_CONFIG1 ) & RTL_CONFIG1_VPD ) {
141
+		DBGC ( rtl, "REALTEK %p EEPROM in use for VPD; cannot use "
142
+		       "for options\n", rtl );
143
+	} else {
144
+		nvo_init ( &rtl->nvo, &rtl->eeprom.nvs, RTL_EEPROM_VPD,
145
+			   RTL_EEPROM_VPD_LEN, NULL, &netdev->refcnt );
146
+	}
147
+}
148
+
149
+/******************************************************************************
150
+ *
151
+ * MII interface
152
+ *
153
+ ******************************************************************************
154
+ */
155
+
156
+/**
157
+ * Read from MII register
158
+ *
159
+ * @v mii		MII interface
160
+ * @v reg		Register address
161
+ * @ret value		Data read, or negative error
162
+ */
163
+static int realtek_mii_read ( struct mii_interface *mii, unsigned int reg ) {
164
+	struct realtek_nic *rtl = container_of ( mii, struct realtek_nic, mii );
165
+	unsigned int i;
166
+	uint32_t value;
167
+
168
+	/* Initiate read */
169
+	writel ( RTL_PHYAR_VALUE ( 0, reg, 0 ), rtl->regs + RTL_PHYAR );
170
+
171
+	/* Wait for read to complete */
172
+	for ( i = 0 ; i < RTL_MII_MAX_WAIT_US ; i++ ) {
173
+
174
+		/* If read is not complete, delay 1us and retry */
175
+		value = readl ( rtl->regs + RTL_PHYAR );
176
+		if ( ! ( value & RTL_PHYAR_FLAG ) ) {
177
+			udelay ( 1 );
178
+			continue;
179
+		}
180
+
181
+		/* Return register value */
182
+		return ( RTL_PHYAR_DATA ( value ) );
183
+	}
184
+
185
+	DBGC ( rtl, "REALTEK %p timed out waiting for MII read\n", rtl );
186
+	return -ETIMEDOUT;
187
+}
188
+
189
+/**
190
+ * Write to MII register
191
+ *
192
+ * @v mii		MII interface
193
+ * @v reg		Register address
194
+ * @v data		Data to write
195
+ * @ret rc		Return status code
196
+ */
197
+static int realtek_mii_write ( struct mii_interface *mii, unsigned int reg,
198
+			       unsigned int data) {
199
+	struct realtek_nic *rtl = container_of ( mii, struct realtek_nic, mii );
200
+	unsigned int i;
201
+
202
+	/* Initiate write */
203
+	writel ( RTL_PHYAR_VALUE ( RTL_PHYAR_FLAG, reg, data ),
204
+		 rtl->regs + RTL_PHYAR );
205
+
206
+	/* Wait for write to complete */
207
+	for ( i = 0 ; i < RTL_MII_MAX_WAIT_US ; i++ ) {
208
+
209
+		/* If write is not complete, delay 1us and retry */
210
+		if ( readl ( rtl->regs + RTL_PHYAR ) & RTL_PHYAR_FLAG ) {
211
+			udelay ( 1 );
212
+			continue;
213
+		}
214
+
215
+		return 0;
216
+	}
217
+
218
+	DBGC ( rtl, "REALTEK %p timed out waiting for MII write\n", rtl );
219
+	return -ETIMEDOUT;
220
+}
221
+
222
+/** Realtek MII operations */
223
+static struct mii_operations realtek_mii_operations = {
224
+	.read = realtek_mii_read,
225
+	.write = realtek_mii_write,
226
+};
227
+
228
+/******************************************************************************
229
+ *
230
+ * Device reset
231
+ *
232
+ ******************************************************************************
233
+ */
234
+
235
+/**
236
+ * Reset hardware
237
+ *
238
+ * @v rtl		Realtek device
239
+ * @ret rc		Return status code
240
+ */
241
+static int realtek_reset ( struct realtek_nic *rtl ) {
242
+	unsigned int i;
243
+
244
+	/* Issue reset */
245
+	writeb ( RTL_CR_RST, rtl->regs + RTL_CR );
246
+
247
+	/* Wait for reset to complete */
248
+	for ( i = 0 ; i < RTL_RESET_MAX_WAIT_MS ; i++ ) {
249
+
250
+		/* If reset is not complete, delay 1ms and retry */
251
+		if ( readb ( rtl->regs + RTL_CR ) & RTL_CR_RST ) {
252
+			mdelay ( 1 );
253
+			continue;
254
+		}
255
+
256
+		/* Enable PCI Dual Address Cycle (for 64-bit systems) */
257
+		writew ( ( RTL_CPCR_DAC | RTL_CPCR_MULRW ),
258
+			 rtl->regs + RTL_CPCR );
259
+
260
+		return 0;
261
+	}
262
+
263
+	DBGC ( rtl, "REALTEK %p timed out waiting for reset\n", rtl );
264
+	return -ETIMEDOUT;
265
+}
266
+
267
+/******************************************************************************
268
+ *
269
+ * Link state
270
+ *
271
+ ******************************************************************************
272
+ */
273
+
274
+/**
275
+ * Check link state
276
+ *
277
+ * @v netdev		Network device
278
+ */
279
+static void realtek_check_link ( struct net_device *netdev ) {
280
+	struct realtek_nic *rtl = netdev->priv;
281
+
282
+	if ( readb ( rtl->regs + RTL_PHYSTATUS ) & RTL_PHYSTATUS_LINKSTS ) {
283
+		netdev_link_up ( netdev );
284
+	} else {
285
+		netdev_link_down ( netdev );
286
+	}
287
+}
288
+
289
+/******************************************************************************
290
+ *
291
+ * Network device interface
292
+ *
293
+ ******************************************************************************
294
+ */
295
+
296
+/**
297
+ * Create descriptor ring
298
+ *
299
+ * @v rtl		Realtek device
300
+ * @v ring		Descriptor ring
301
+ * @ret rc		Return status code
302
+ */
303
+static int realtek_create_ring ( struct realtek_nic *rtl,
304
+				 struct realtek_ring *ring ) {
305
+	physaddr_t address;
306
+
307
+	/* Allocate descriptor ring */
308
+	ring->desc = malloc_dma ( ring->len, RTL_RING_ALIGN );
309
+	if ( ! ring->desc )
310
+		return -ENOMEM;
311
+
312
+	/* Initialise descriptor ring */
313
+	memset ( ring->desc, 0, ring->len );
314
+
315
+	/* Program ring address */
316
+	address = virt_to_bus ( ring->desc );
317
+	writel ( ( address & 0xffffffffUL ), rtl->regs + ring->reg );
318
+	if ( sizeof ( physaddr_t ) > sizeof ( uint32_t ) ) {
319
+		writel ( ( ( ( uint64_t ) address ) >> 32 ),
320
+			 rtl->regs + ring->reg + 4 );
321
+	}
322
+	DBGC ( rtl, "REALTEK %p ring %02x is at [%08llx,%08llx)\n",
323
+	       rtl, ring->reg, ( ( unsigned long long ) address ),
324
+	       ( ( unsigned long long ) address + ring->len ) );
325
+
326
+	return 0;
327
+}
328
+
329
+/**
330
+ * Destroy descriptor ring
331
+ *
332
+ * @v rtl		Realtek device
333
+ * @v ring		Descriptor ring
334
+ */
335
+static void realtek_destroy_ring ( struct realtek_nic *rtl,
336
+				   struct realtek_ring *ring ) {
337
+
338
+	/* Clear ring address */
339
+	writel ( 0, rtl->regs + ring->reg );
340
+	writel ( 0, rtl->regs + ring->reg + 4 );
341
+
342
+	/* Free descriptor ring */
343
+	free_dma ( ring->desc, ring->len );
344
+	ring->desc = NULL;
345
+	ring->prod = 0;
346
+	ring->cons = 0;
347
+}
348
+
349
+/**
350
+ * Refill receive descriptor ring
351
+ *
352
+ * @v rtl		Realtek device
353
+ */
354
+static void realtek_refill_rx ( struct realtek_nic *rtl ) {
355
+	struct realtek_descriptor *rx;
356
+	struct io_buffer *iobuf;
357
+	unsigned int rx_idx;
358
+	physaddr_t address;
359
+	int is_last;
360
+
361
+	while ( ( rtl->rx.prod - rtl->rx.cons ) < RTL_NUM_RX_DESC ) {
362
+
363
+		/* Allocate I/O buffer */
364
+		iobuf = alloc_iob ( RTL_RX_MAX_LEN );
365
+		if ( ! iobuf ) {
366
+			/* Wait for next refill */
367
+			return;
368
+		}
369
+
370
+		/* Get next receive descriptor */
371
+		rx_idx = ( rtl->rx.prod++ % RTL_NUM_RX_DESC );
372
+		is_last = ( rx_idx == ( RTL_NUM_RX_DESC - 1 ) );
373
+		rx = &rtl->rx.desc[rx_idx];
374
+
375
+		/* Populate receive descriptor */
376
+		address = virt_to_bus ( iobuf->data );
377
+		rx->address = cpu_to_le64 ( address );
378
+		rx->length = RTL_RX_MAX_LEN;
379
+		wmb();
380
+		rx->flags = ( cpu_to_le16 ( RTL_DESC_OWN ) |
381
+			      ( is_last ? cpu_to_le16 ( RTL_DESC_EOR ) : 0 ) );
382
+		wmb();
383
+
384
+		/* Record I/O buffer */
385
+		assert ( rtl->rx_iobuf[rx_idx] == NULL );
386
+		rtl->rx_iobuf[rx_idx] = iobuf;
387
+
388
+		DBGC2 ( rtl, "REALTEK %p RX %d is [%llx,%llx)\n", rtl, rx_idx,
389
+			( ( unsigned long long ) address ),
390
+			( ( unsigned long long ) address + RTL_RX_MAX_LEN ) );
391
+	}
392
+}
393
+
394
+/**
395
+ * Open network device
396
+ *
397
+ * @v netdev		Network device
398
+ * @ret rc		Return status code
399
+ */
400
+static int realtek_open ( struct net_device *netdev ) {
401
+	struct realtek_nic *rtl = netdev->priv;
402
+	uint32_t rcr;
403
+	int rc;
404
+
405
+	/* Create transmit descriptor ring */
406
+	if ( ( rc = realtek_create_ring ( rtl, &rtl->tx ) ) != 0 )
407
+		goto err_create_tx;
408
+
409
+	/* Create receive descriptor ring */
410
+	if ( ( rc = realtek_create_ring ( rtl, &rtl->rx ) ) != 0 )
411
+		goto err_create_rx;
412
+
413
+	/* Configure MTU */
414
+	writew ( RTL_RX_MAX_LEN, rtl->regs + RTL_RMS );
415
+
416
+	/* Accept all packets */
417
+	writel ( 0xffffffffUL, rtl->regs + RTL_MAR0 );
418
+	writel ( 0xffffffffUL, rtl->regs + RTL_MAR4 );
419
+	rcr = readl ( rtl->regs + RTL_RCR );
420
+	writel ( ( rcr | RTL_RCR_AB | RTL_RCR_AM | RTL_RCR_APM | RTL_RCR_AAP ),
421
+		 rtl->regs + RTL_RCR );
422
+
423
+	/* Fill receive ring */
424
+	realtek_refill_rx ( rtl );
425
+
426
+	/* Enable transmitter and receiver */
427
+	writeb ( ( RTL_CR_TE | RTL_CR_RE ), rtl->regs + RTL_CR );
428
+
429
+	return 0;
430
+
431
+	realtek_destroy_ring ( rtl, &rtl->rx );
432
+ err_create_rx:
433
+	realtek_destroy_ring ( rtl, &rtl->tx );
434
+ err_create_tx:
435
+	return rc;
436
+}
437
+
438
+/**
439
+ * Close network device
440
+ *
441
+ * @v netdev		Network device
442
+ */
443
+static void realtek_close ( struct net_device *netdev ) {
444
+	struct realtek_nic *rtl = netdev->priv;
445
+	unsigned int i;
446
+
447
+	/* Disable receiver and transmitter */
448
+	writeb ( 0, rtl->regs + RTL_CR );
449
+
450
+	/* Destroy receive descriptor ring */
451
+	realtek_destroy_ring ( rtl, &rtl->rx );
452
+
453
+	/* Discard any unused receive buffers */
454
+	for ( i = 0 ; i < RTL_NUM_RX_DESC ; i++ ) {
455
+		if ( rtl->rx_iobuf[i] )
456
+			free_iob ( rtl->rx_iobuf[i] );
457
+		rtl->rx_iobuf[i] = NULL;
458
+	}
459
+
460
+	/* Destroy transmit descriptor ring */
461
+	realtek_destroy_ring ( rtl, &rtl->tx );
462
+}
463
+
464
+/**
465
+ * Transmit packet
466
+ *
467
+ * @v netdev		Network device
468
+ * @v iobuf		I/O buffer
469
+ * @ret rc		Return status code
470
+ */
471
+static int realtek_transmit ( struct net_device *netdev,
472
+			      struct io_buffer *iobuf ) {
473
+	struct realtek_nic *rtl = netdev->priv;
474
+	struct realtek_descriptor *tx;
475
+	unsigned int tx_idx;
476
+	physaddr_t address;
477
+	int is_last;
478
+
479
+	/* Get next transmit descriptor */
480
+	if ( ( rtl->tx.prod - rtl->tx.cons ) >= RTL_NUM_TX_DESC ) {
481
+		DBGC ( rtl, "REALTEK %p out of transmit descriptors\n", rtl );
482
+		return -ENOBUFS;
483
+	}
484
+	tx_idx = ( rtl->tx.prod++ % RTL_NUM_TX_DESC );
485
+	is_last = ( tx_idx == ( RTL_NUM_TX_DESC - 1 ) );
486
+	tx = &rtl->tx.desc[tx_idx];
487
+
488
+	/* Populate transmit descriptor */
489
+	address = virt_to_bus ( iobuf->data );
490
+	tx->address = cpu_to_le64 ( address );
491
+	tx->length = cpu_to_le16 ( iob_len ( iobuf ) );
492
+	wmb();
493
+	tx->flags = ( cpu_to_le16 ( RTL_DESC_OWN | RTL_DESC_FS | RTL_DESC_LS ) |
494
+		      ( is_last ? cpu_to_le16 ( RTL_DESC_EOR ) : 0 ) );
495
+	wmb();
496
+
497
+	/* Notify card that there are packets ready to transmit */
498
+	writeb ( RTL_TPPOLL_NPQ, rtl->regs + RTL_TPPOLL );
499
+
500
+	DBGC2 ( rtl, "REALTEK %p TX %d is [%llx,%llx)\n", rtl, tx_idx,
501
+		( ( unsigned long long ) address ),
502
+		( ( unsigned long long ) address + iob_len ( iobuf ) ) );
503
+
504
+	return 0;
505
+}
506
+
507
+/**
508
+ * Poll for completed packets
509
+ *
510
+ * @v netdev		Network device
511
+ */
512
+static void realtek_poll_tx ( struct net_device *netdev ) {
513
+	struct realtek_nic *rtl = netdev->priv;
514
+	struct realtek_descriptor *tx;
515
+	unsigned int tx_idx;
516
+
517
+	/* Check for completed packets */
518
+	while ( rtl->tx.cons != rtl->tx.prod ) {
519
+
520
+		/* Get next transmit descriptor */
521
+		tx_idx = ( rtl->tx.cons % RTL_NUM_TX_DESC );
522
+		tx = &rtl->tx.desc[tx_idx];
523
+
524
+		/* Stop if descriptor is still in use */
525
+		if ( tx->flags & cpu_to_le16 ( RTL_DESC_OWN ) )
526
+			return;
527
+
528
+		DBGC2 ( rtl, "REALTEK %p TX %d complete\n", rtl, tx_idx );
529
+
530
+		/* Complete TX descriptor */
531
+		netdev_tx_complete_next ( netdev );
532
+		rtl->tx.cons++;
533
+	}
534
+}
535
+
536
+/**
537
+ * Poll for received packets
538
+ *
539
+ * @v netdev		Network device
540
+ */
541
+static void realtek_poll_rx ( struct net_device *netdev ) {
542
+	struct realtek_nic *rtl = netdev->priv;
543
+	struct realtek_descriptor *rx;
544
+	struct io_buffer *iobuf;
545
+	unsigned int rx_idx;
546
+	size_t len;
547
+
548
+	/* Check for received packets */
549
+	while ( rtl->rx.cons != rtl->rx.prod ) {
550
+
551
+		/* Get next receive descriptor */
552
+		rx_idx = ( rtl->rx.cons % RTL_NUM_RX_DESC );
553
+		rx = &rtl->rx.desc[rx_idx];
554
+
555
+		/* Stop if descriptor is still in use */
556
+		if ( rx->flags & cpu_to_le16 ( RTL_DESC_OWN ) )
557
+			return;
558
+
559
+		/* Populate I/O buffer */
560
+		iobuf = rtl->rx_iobuf[rx_idx];
561
+		rtl->rx_iobuf[rx_idx] = NULL;
562
+		len = ( le16_to_cpu ( rx->length ) & RTL_DESC_SIZE_MASK );
563
+		iob_put ( iobuf, ( len - 4 /* strip CRC */ ) );
564
+
565
+		DBGC2 ( rtl, "REALTEK %p RX %d complete (length %zd)\n",
566
+			rtl, rx_idx, len );
567
+
568
+		/* Hand off to network stack */
569
+		if ( rx->flags & cpu_to_le16 ( RTL_DESC_RES ) ) {
570
+			netdev_rx_err ( netdev, iobuf, -EIO );
571
+		} else {
572
+			netdev_rx ( netdev, iobuf );
573
+		}
574
+		rtl->rx.cons++;
575
+	}
576
+}
577
+
578
+/**
579
+ * Poll for completed and received packets
580
+ *
581
+ * @v netdev		Network device
582
+ */
583
+static void realtek_poll ( struct net_device *netdev ) {
584
+	struct realtek_nic *rtl = netdev->priv;
585
+	uint16_t isr;
586
+
587
+	/* Check for and acknowledge interrupts */
588
+	isr = readw ( rtl->regs + RTL_ISR );
589
+	if ( ! isr )
590
+		return;
591
+	writew ( isr, rtl->regs + RTL_ISR );
592
+
593
+	/* Poll for TX completions, if applicable */
594
+	if ( isr & ( RTL_IRQ_TER | RTL_IRQ_TOK ) )
595
+		realtek_poll_tx ( netdev );
596
+
597
+	/* Poll for RX completionsm, if applicable */
598
+	if ( isr & ( RTL_IRQ_RER | RTL_IRQ_ROK ) )
599
+		realtek_poll_rx ( netdev );
600
+
601
+	/* Check link state, if applicable */
602
+	if ( isr & RTL_IRQ_PUN_LINKCHG )
603
+		realtek_check_link ( netdev );
604
+
605
+	/* Refill RX ring */
606
+	realtek_refill_rx ( rtl );
607
+}
608
+
609
+/**
610
+ * Enable or disable interrupts
611
+ *
612
+ * @v netdev		Network device
613
+ * @v enable		Interrupts should be enabled
614
+ */
615
+static void realtek_irq ( struct net_device *netdev, int enable ) {
616
+	struct realtek_nic *rtl = netdev->priv;
617
+	uint16_t imr;
618
+
619
+	/* Set interrupt mask */
620
+	imr = ( enable ? ( RTL_IRQ_PUN_LINKCHG | RTL_IRQ_TER | RTL_IRQ_TOK |
621
+			   RTL_IRQ_RER | RTL_IRQ_ROK ) : 0 );
622
+	writew ( imr, rtl->regs + RTL_IMR );
623
+}
624
+
625
+/** Realtek network device operations */
626
+static struct net_device_operations realtek_operations = {
627
+	.open		= realtek_open,
628
+	.close		= realtek_close,
629
+	.transmit	= realtek_transmit,
630
+	.poll		= realtek_poll,
631
+	.irq		= realtek_irq,
632
+};
633
+
634
+/******************************************************************************
635
+ *
636
+ * PCI interface
637
+ *
638
+ ******************************************************************************
639
+ */
640
+
641
+/**
642
+ * Probe PCI device
643
+ *
644
+ * @v pci		PCI device
645
+ * @ret rc		Return status code
646
+ */
647
+static int realtek_probe ( struct pci_device *pci ) {
648
+	struct net_device *netdev;
649
+	struct realtek_nic *rtl;
650
+	unsigned int i;
651
+	int rc;
652
+
653
+	/* Allocate and initialise net device */
654
+	netdev = alloc_etherdev ( sizeof ( *rtl ) );
655
+	if ( ! netdev ) {
656
+		rc = -ENOMEM;
657
+		goto err_alloc;
658
+	}
659
+	netdev_init ( netdev, &realtek_operations );
660
+	rtl = netdev->priv;
661
+	pci_set_drvdata ( pci, netdev );
662
+	netdev->dev = &pci->dev;
663
+	memset ( rtl, 0, sizeof ( *rtl ) );
664
+	realtek_init_ring ( &rtl->tx, RTL_NUM_TX_DESC, RTL_TNPDS );
665
+	realtek_init_ring ( &rtl->rx, RTL_NUM_RX_DESC, RTL_RDSAR );
666
+
667
+	/* Fix up PCI device */
668
+	adjust_pci_device ( pci );
669
+
670
+	/* Map registers */
671
+	rtl->regs = ioremap ( pci->membase, RTL_BAR_SIZE );
672
+
673
+	/* Reset the NIC */
674
+	if ( ( rc = realtek_reset ( rtl ) ) != 0 )
675
+		goto err_reset;
676
+
677
+	/* Initialise EEPROM */
678
+	realtek_init_eeprom ( netdev );
679
+
680
+	/* Read MAC address from EEPROM */
681
+	if ( ( rc = nvs_read ( &rtl->eeprom.nvs, RTL_EEPROM_MAC,
682
+			       netdev->hw_addr, ETH_ALEN ) ) != 0 ) {
683
+		DBGC ( rtl, "REALTEK %p could not read MAC address: %s\n",
684
+		       rtl, strerror ( rc ) );
685
+		goto err_nvs_read;
686
+	}
687
+
688
+	/* The EEPROM may not be present for onboard NICs.  Fall back
689
+	 * to reading the current ID register value, which will
690
+	 * hopefully have been programmed by the platform firmware.
691
+	 */
692
+	if ( ! is_valid_ether_addr ( netdev->hw_addr ) ) {
693
+		DBGC ( rtl, "REALTEK %p seems to have no EEPROM\n", rtl );
694
+		for ( i = 0 ; i < ETH_ALEN ; i++ )
695
+			netdev->hw_addr[i] = readb ( rtl->regs + RTL_IDR0 + i );
696
+	}
697
+
698
+	/* Initialise and reset MII interface */
699
+	mii_init ( &rtl->mii, &realtek_mii_operations );
700
+	if ( ( rc = mii_reset ( &rtl->mii ) ) != 0 ) {
701
+		DBGC ( rtl, "REALTEK %p could not reset MII: %s\n",
702
+		       rtl, strerror ( rc ) );
703
+		goto err_mii_reset;
704
+	}
705
+
706
+	/* Register network device */
707
+	if ( ( rc = register_netdev ( netdev ) ) != 0 )
708
+		goto err_register_netdev;
709
+
710
+	/* Set initial link state */
711
+	realtek_check_link ( netdev );
712
+
713
+	/* Register non-volatile options, if applicable */
714
+	if ( rtl->nvo.nvs ) {
715
+		if ( ( rc = register_nvo ( &rtl->nvo,
716
+					   netdev_settings ( netdev ) ) ) != 0)
717
+			goto err_register_nvo;
718
+	}
719
+
720
+	return 0;
721
+
722
+ err_register_nvo:
723
+	unregister_netdev ( netdev );
724
+ err_register_netdev:
725
+ err_mii_reset:
726
+ err_nvs_read:
727
+	realtek_reset ( rtl );
728
+ err_reset:
729
+	netdev_nullify ( netdev );
730
+	netdev_put ( netdev );
731
+ err_alloc:
732
+	return rc;
733
+}
734
+
735
+/**
736
+ * Remove PCI device
737
+ *
738
+ * @v pci		PCI device
739
+ */
740
+static void realtek_remove ( struct pci_device *pci ) {
741
+	struct net_device *netdev = pci_get_drvdata ( pci );
742
+	struct realtek_nic *rtl = netdev->priv;
743
+
744
+	/* Unregister non-volatile options, if applicable */
745
+	if ( rtl->nvo.nvs )
746
+		unregister_nvo ( &rtl->nvo );
747
+
748
+	/* Unregister network device */
749
+	unregister_netdev ( netdev );
750
+
751
+	/* Reset card */
752
+	realtek_reset ( rtl );
753
+
754
+	/* Free network device */
755
+	netdev_nullify ( netdev );
756
+	netdev_put ( netdev );
757
+}
758
+
759
+/** Realtek PCI device IDs */
760
+static struct pci_device_id realtek_nics[] = {
761
+	PCI_ROM ( 0x10ec, 0x8129, "r8129",	"RTL-8129", 0 ),
762
+	PCI_ROM ( 0x10ec, 0x8136, "r8136",	"RTL8101E/RTL8102E", 0 ),
763
+	PCI_ROM ( 0x10ec, 0x8167, "r8167",	"RTL-8110SC/8169SC", 0 ),
764
+	PCI_ROM ( 0x10ec, 0x8168, "r8168",	"RTL8111/8168B", 0 ),
765
+	PCI_ROM ( 0x10ec, 0x8169, "r8169",	"RTL-8169", 0 ),
766
+	PCI_ROM ( 0x1186, 0x4300, "dge528t",	"DGE-528T", 0 ),
767
+	PCI_ROM ( 0x1259, 0xc107, "allied8169",	"Allied Telesyn 8169", 0 ),
768
+	PCI_ROM ( 0x16ec, 0x0116, "usr997902",	"USR997902", 0 ),
769
+	PCI_ROM ( 0x1737, 0x1032, "linksys8169","Linksys 8169", 0 ),
770
+	PCI_ROM ( 0x0001, 0x8168, "clone8169",	"Cloned 8169", 0 ),
771
+};
772
+
773
+/** Realtek PCI driver */
774
+struct pci_driver realtek_driver __pci_driver = {
775
+	.ids = realtek_nics,
776
+	.id_count = ( sizeof ( realtek_nics ) / sizeof ( realtek_nics[0] ) ),
777
+	.probe = realtek_probe,
778
+	.remove = realtek_remove,
779
+};

+ 205
- 0
src/drivers/net/realtek.h Целия файл

@@ -0,0 +1,205 @@
1
+#ifndef _REALTEK_H
2
+#define _REALTEK_H
3
+
4
+/** @file
5
+ *
6
+ * Realtek 10/100/1000 network card driver
7
+ *
8
+ */
9
+
10
+FILE_LICENCE ( GPL2_OR_LATER );
11
+
12
+#include <ipxe/spi.h>
13
+#include <ipxe/spi_bit.h>
14
+#include <ipxe/nvo.h>
15
+#include <ipxe/if_ether.h>
16
+
17
+/** PCI memory BAR size */
18
+#define RTL_BAR_SIZE 0x100
19
+
20
+/** A packet descriptor */
21
+struct realtek_descriptor {
22
+	/** Buffer size */
23
+	uint16_t length;
24
+	/** Flags */
25
+	uint16_t flags;
26
+	/** Reserved */
27
+	uint32_t reserved;
28
+	/** Buffer address */
29
+	uint64_t address;
30
+} __attribute__ (( packed ));
31
+
32
+/** Descriptor buffer size mask */
33
+#define RTL_DESC_SIZE_MASK 0x3fff
34
+
35
+/** Packet descriptor flags */
36
+enum realtek_descriptor_flags {
37
+	/** Descriptor is owned by NIC */
38
+	RTL_DESC_OWN = 0x8000,
39
+	/** End of descriptor ring */
40
+	RTL_DESC_EOR = 0x4000,
41
+	/** First segment descriptor */
42
+	RTL_DESC_FS = 0x2000,
43
+	/** Last segment descriptor */
44
+	RTL_DESC_LS = 0x1000,
45
+	/** Receive error summary */
46
+	RTL_DESC_RES = 0x0020,
47
+};
48
+
49
+/** Descriptor ring alignment */
50
+#define RTL_RING_ALIGN 256
51
+
52
+/** ID Register 0 (6 bytes) */
53
+#define RTL_IDR0 0x00
54
+
55
+/** Multicast Register 0 (dword) */
56
+#define RTL_MAR0 0x08
57
+
58
+/** Multicast Register 4 (dword) */
59
+#define RTL_MAR4 0x0c
60
+
61
+/** Transmit Normal Priority Descriptors (qword) */
62
+#define RTL_TNPDS 0x20
63
+
64
+/** Number of transmit descriptors */
65
+#define RTL_NUM_TX_DESC 4
66
+
67
+/** Command Register (byte) */
68
+#define RTL_CR 0x37
69
+#define RTL_CR_RST		0x10	/**< Reset */
70
+#define RTL_CR_RE		0x08	/**< Receiver Enable */
71
+#define RTL_CR_TE		0x04	/**< Transmit Enable */
72
+
73
+/** Maximum time to wait for a reset, in milliseconds */
74
+#define RTL_RESET_MAX_WAIT_MS 100
75
+
76
+/** Transmit Priority Polling Register (byte) */
77
+#define RTL_TPPOLL 0x38
78
+#define RTL_TPPOLL_NPQ		0x40	/**< Normal Priority Queue Polling */
79
+
80
+/** Interrupt Mask Register (word) */
81
+#define RTL_IMR 0x3c
82
+#define RTL_IRQ_PUN_LINKCHG	0x20	/**< Packet underrun / link change */
83
+#define RTL_IRQ_TER		0x08	/**< Transmit error */
84
+#define RTL_IRQ_TOK		0x04	/**< Transmit OK */
85
+#define RTL_IRQ_RER		0x02	/**< Receive error */
86
+#define RTL_IRQ_ROK		0x01	/**< Receive OK */
87
+
88
+/** Interrupt Status Register (word) */
89
+#define RTL_ISR 0x3e
90
+
91
+/** Receive (Rx) Configuration Register (dword) */
92
+#define RTL_RCR 0x44
93
+#define RTL_RCR_9356SEL		0x40	/**< EEPROM is a 93C56 */
94
+#define RTL_RCR_AB		0x08	/**< Accept broadcast packets */
95
+#define RTL_RCR_AM		0x04	/**< Accept multicast packets */
96
+#define RTL_RCR_APM		0x02	/**< Accept physical match packets */
97
+#define RTL_RCR_AAP		0x01	/**< Accept all packets */
98
+
99
+/** 93C46 (93C56) Command Register (byte) */
100
+#define RTL_9346CR 0x50
101
+#define RTL_9346CR_EEM1		0x80	/**< Mode select bit 1 */
102
+#define RTL_9346CR_EEM0		0x40	/**< Mode select bit 0 */
103
+#define RTL_9346CR_EECS		0x08	/**< Chip select */
104
+#define RTL_9346CR_EESK		0x04	/**< Clock */
105
+#define RTL_9346CR_EEDI		0x02	/**< Data in */
106
+#define RTL_9346CR_EEDO		0x01	/**< Data out */
107
+
108
+/** Word offset of MAC address within EEPROM */
109
+#define RTL_EEPROM_MAC ( 0x0e / 2 )
110
+
111
+/** Word offset of VPD / non-volatile options within EEPROM */
112
+#define RTL_EEPROM_VPD ( 0x40 / 2 )
113
+
114
+/** Length of VPD / non-volatile options within EEPROM */
115
+#define RTL_EEPROM_VPD_LEN 0x40
116
+
117
+/** Configuration Register 1 (byte) */
118
+#define RTL_CONFIG1 0x52
119
+#define RTL_CONFIG1_VPD		0x02	/**< Vital Product Data enabled */
120
+
121
+/** PHY Access Register (dword) */
122
+#define RTL_PHYAR 0x60
123
+#define RTL_PHYAR_FLAG		0x80000000UL /**< Read/write flag */
124
+
125
+/** Construct PHY Access Register value */
126
+#define RTL_PHYAR_VALUE( flag, reg, data ) ( (flag) | ( (reg) << 16 ) | (data) )
127
+
128
+/** Extract PHY Access Register data */
129
+#define RTL_PHYAR_DATA( value ) ( (value) & 0xffff )
130
+
131
+/** Maximum time to wait for PHY access, in microseconds */
132
+#define RTL_MII_MAX_WAIT_US 500
133
+
134
+/** PHY (GMII, MII, or TBI) Status Register (byte) */
135
+#define RTL_PHYSTATUS 0x6c
136
+#define RTL_PHYSTATUS_LINKSTS	0x02	/**< Link ok */
137
+
138
+/** RX Packet Maximum Size Register (word) */
139
+#define RTL_RMS 0xda
140
+
141
+/** C+ Command Register (word) */
142
+#define RTL_CPCR 0xe0
143
+#define RTL_CPCR_DAC		0x10	/**< PCI Dual Address Cycle Enable */
144
+#define RTL_CPCR_MULRW		0x08	/**< PCI Multiple Read/Write Enable */
145
+
146
+/** Receive Descriptor Start Address Register (qword) */
147
+#define RTL_RDSAR 0xe4
148
+
149
+/** Number of receive descriptors */
150
+#define RTL_NUM_RX_DESC 4
151
+
152
+/** Receive buffer length */
153
+#define RTL_RX_MAX_LEN ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ )
154
+
155
+/** A Realtek descriptor ring */
156
+struct realtek_ring {
157
+	/** Descriptors */
158
+	struct realtek_descriptor *desc;
159
+	/** Producer index */
160
+	unsigned int prod;
161
+	/** Consumer index */
162
+	unsigned int cons;
163
+
164
+	/** Descriptor start address register */
165
+	unsigned int reg;
166
+	/** Length (in bytes) */
167
+	size_t len;
168
+};
169
+
170
+/**
171
+ * Initialise descriptor ring
172
+ *
173
+ * @v ring		Descriptor ring
174
+ * @v count		Number of descriptors
175
+ * @v reg		Descriptor start address register
176
+ */
177
+static inline __attribute__ (( always_inline)) void
178
+realtek_init_ring ( struct realtek_ring *ring, unsigned int count,
179
+		    unsigned int reg ) {
180
+	ring->len = ( count * sizeof ( ring->desc[0] ) );
181
+	ring->reg = reg;
182
+}
183
+
184
+/** A Realtek network card */
185
+struct realtek_nic {
186
+	/** Registers */
187
+	void *regs;
188
+	/** SPI bit-bashing interface */
189
+	struct spi_bit_basher spibit;
190
+	/** EEPROM */
191
+	struct spi_device eeprom;
192
+	/** Non-volatile options */
193
+	struct nvo_block nvo;
194
+	/** MII interface */
195
+	struct mii_interface mii;
196
+
197
+	/** Transmit descriptor ring */
198
+	struct realtek_ring tx;
199
+	/** Receive descriptor ring */
200
+	struct realtek_ring rx;
201
+	/** Receive I/O buffers */
202
+	struct io_buffer *rx_iobuf[RTL_NUM_RX_DESC];
203
+};
204
+
205
+#endif /* _REALTEK_H */

+ 1
- 0
src/include/ipxe/errfile.h Целия файл

@@ -142,6 +142,7 @@ FILE_LICENCE ( GPL2_OR_LATER );
142 142
 #define ERRFILE_ath		     ( ERRFILE_DRIVER | 0x00600000 )
143 143
 #define ERRFILE_vmxnet3		     ( ERRFILE_DRIVER | 0x00610000 )
144 144
 #define ERRFILE_mii		     ( ERRFILE_DRIVER | 0x00620000 )
145
+#define ERRFILE_realtek		     ( ERRFILE_DRIVER | 0x00630000 )
145 146
 
146 147
 #define ERRFILE_scsi		     ( ERRFILE_DRIVER | 0x00700000 )
147 148
 #define ERRFILE_arbel		     ( ERRFILE_DRIVER | 0x00710000 )

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