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[exanic] Add driver for Exablaze ExaNIC cards

Signed-off-by: Michael Brown <mcb30@ipxe.org>
tags/v1.20.1
Michael Brown 7 vuotta sitten
vanhempi
commit
1e5c5a2163
3 muutettua tiedostoa jossa 1169 lisäystä ja 0 poistoa
  1. 911
    0
      src/drivers/net/exanic.c
  2. 257
    0
      src/drivers/net/exanic.h
  3. 1
    0
      src/include/ipxe/errfile.h

+ 911
- 0
src/drivers/net/exanic.c Näytä tiedosto

@@ -0,0 +1,911 @@
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+/*
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+ * Copyright (C) 2017 Michael Brown <mbrown@fensystems.co.uk>.
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+ *
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+ * This program is free software; you can redistribute it and/or
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+ * modify it under the terms of the GNU General Public License as
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+ * published by the Free Software Foundation; either version 2 of the
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+ * License, or (at your option) any later version.
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+ *
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+ * This program is distributed in the hope that it will be useful, but
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+ * WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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+ * General Public License for more details.
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+ *
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+ * You should have received a copy of the GNU General Public License
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+ * along with this program; if not, write to the Free Software
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+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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+ * 02110-1301, USA.
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+ *
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+ * You can also choose to distribute this program under the terms of
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+ * the Unmodified Binary Distribution Licence (as given in the file
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+ * COPYING.UBDL), provided that you have satisfied its requirements.
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+ */
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+
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+FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
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+
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+#include <stdint.h>
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+#include <string.h>
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+#include <strings.h>
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+#include <unistd.h>
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+#include <errno.h>
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+#include <byteswap.h>
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+#include <ipxe/netdevice.h>
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+#include <ipxe/ethernet.h>
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+#include <ipxe/if_ether.h>
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+#include <ipxe/iobuf.h>
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+#include <ipxe/malloc.h>
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+#include <ipxe/umalloc.h>
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+#include <ipxe/pci.h>
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+#include "exanic.h"
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+
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+/** @file
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+ *
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+ * Exablaze ExaNIC driver
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+ *
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+ */
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+
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+/* Disambiguate the various error causes */
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+#define EIO_ABORTED __einfo_error ( EINFO_EIO_ABORTED )
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+#define EINFO_EIO_ABORTED \
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+	__einfo_uniqify ( EINFO_EIO, 0x01, "Frame aborted" )
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+#define EIO_CORRUPT __einfo_error ( EINFO_EIO_CORRUPT )
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+#define EINFO_EIO_CORRUPT \
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+	__einfo_uniqify ( EINFO_EIO, 0x02, "CRC incorrect" )
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+#define EIO_HWOVFL __einfo_error ( EINFO_EIO_HWOVFL )
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+#define EINFO_EIO_HWOVFL \
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+	__einfo_uniqify ( EINFO_EIO, 0x03, "Hardware overflow" )
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+#define EIO_STATUS( status ) \
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+	EUNIQ ( EINFO_EIO, ( (status) & EXANIC_STATUS_ERROR_MASK ), \
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+		EIO_ABORTED, EIO_CORRUPT, EIO_HWOVFL )
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+
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+/**
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+ * Write DMA base address register
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+ *
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+ * @v addr		DMA base address
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+ * @v reg		Register
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+ */
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+static void exanic_write_base ( physaddr_t addr, void *reg ) {
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+	uint32_t lo;
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+	uint32_t hi;
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+
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+	/* Write high and low registers, setting flags as appropriate */
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+	lo = addr;
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+	if ( sizeof ( physaddr_t ) > sizeof ( uint32_t ) ) {
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+		/* 64-bit build; may be a 32-bit or 64-bit address */
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+		hi = ( ( ( uint64_t ) addr ) >> 32 );
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+		if ( ! hi )
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+			lo |= EXANIC_DMA_32_BIT;
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+	} else {
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+		/* 32-bit build; always a 32-bit address */
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+		hi = 0;
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+		lo |= EXANIC_DMA_32_BIT;
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+	}
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+	writel ( hi, ( reg + 0 ) );
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+	writel ( lo, ( reg + 4 ) );
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+}
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+
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+/**
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+ * Clear DMA base address register
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+ *
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+ * @v reg		Register
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+ */
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+static inline void exanic_clear_base ( void *reg ) {
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+
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+	/* Clear both high and low registers */
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+	writel ( 0, ( reg + 0 ) );
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+	writel ( 0, ( reg + 4 ) );
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+}
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+
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+/******************************************************************************
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+ *
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+ * Device reset
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+ *
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+ ******************************************************************************
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+ */
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+
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+/**
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+ * Reset hardware
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+ *
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+ * @v exanic		ExaNIC device
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+ */
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+static void exanic_reset ( struct exanic *exanic ) {
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+	void *port_regs;
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+	unsigned int i;
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+
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+	/* Disable all possible ports */
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+	for ( i = 0 ; i < EXANIC_MAX_PORTS ; i++ ) {
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+		port_regs = ( exanic->regs + EXANIC_PORT_REGS ( i ) );
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+		writel ( 0, ( port_regs + EXANIC_PORT_ENABLE ) );
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+		writel ( 0, ( port_regs + EXANIC_PORT_IRQ ) );
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+		exanic_clear_base ( port_regs + EXANIC_PORT_RX_BASE );
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+	}
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+
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+	/* Disable transmit feedback */
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+	exanic_clear_base ( exanic->regs + EXANIC_TXF_BASE );
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+}
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+
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+/******************************************************************************
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+ *
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+ * MAC address
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+ *
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+ ******************************************************************************
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+ */
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+
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+/**
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+ * Read I2C line status
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+ *
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+ * @v basher		Bit-bashing interface
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+ * @v bit_id		Bit number
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+ * @ret zero		Input is a logic 0
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+ * @ret non-zero	Input is a logic 1
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+ */
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+static int exanic_i2c_read_bit ( struct bit_basher *basher,
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+				 unsigned int bit_id ) {
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+	struct exanic *exanic =
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+		container_of ( basher, struct exanic, basher.basher );
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+	unsigned int shift;
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+	uint32_t i2c;
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+
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+	/* Identify bit */
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+	assert ( bit_id == I2C_BIT_SDA );
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+	shift = exanic->i2cfg.getsda;
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+
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+	/* Read I2C register */
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+	DBG_DISABLE ( DBGLVL_IO );
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+	i2c = readl ( exanic->regs + EXANIC_I2C );
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+	DBG_ENABLE ( DBGLVL_IO );
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+	return ( ( i2c >> shift ) & 1 );
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+}
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+
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+/**
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+ * Write I2C line status
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+ *
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+ * @v basher		Bit-bashing interface
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+ * @v bit_id		Bit number
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+ * @v data		Value to write
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+ */
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+static void exanic_i2c_write_bit ( struct bit_basher *basher,
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+				   unsigned int bit_id, unsigned long data ) {
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+	struct exanic *exanic =
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+		container_of ( basher, struct exanic, basher.basher );
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+	unsigned int shift;
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+	uint32_t mask;
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+	uint32_t i2c;
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+
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+	/* Identify shift */
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+	assert ( ( bit_id == I2C_BIT_SCL ) || ( bit_id == I2C_BIT_SDA ) );
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+	shift = ( ( bit_id == I2C_BIT_SCL ) ?
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+		  exanic->i2cfg.setscl : exanic->i2cfg.setsda );
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+	mask = ( 1UL << shift );
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+
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+	/* Modify I2C register */
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+	DBG_DISABLE ( DBGLVL_IO );
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+	i2c = readl ( exanic->regs + EXANIC_I2C );
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+	i2c &= ~mask;
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+	if ( ! data )
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+		i2c |= mask;
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+	writel ( i2c, ( exanic->regs + EXANIC_I2C ) );
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+	DBG_ENABLE ( DBGLVL_IO );
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+}
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+
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+/** I2C bit-bashing interface operations */
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+static struct bit_basher_operations exanic_i2c_basher_ops = {
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+	.read = exanic_i2c_read_bit,
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+	.write = exanic_i2c_write_bit,
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+};
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+
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+/** Possible I2C bus configurations */
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+static struct exanic_i2c_config exanic_i2cfgs[] = {
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+	/* X2/X10 */
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+	{ .setscl = 7, .setsda = 4, .getsda = 12 },
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+	/* X4 */
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+	{ .setscl = 7, .setsda = 5, .getsda = 13 },
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+};
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+
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+/**
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+ * Initialise EEPROM
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+ *
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+ * @v exanic		ExaNIC device
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+ * @v i2cfg		I2C bus configuration
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+ * @ret rc		Return status code
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+ */
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+static int exanic_try_init_eeprom ( struct exanic *exanic,
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+				    struct exanic_i2c_config *i2cfg ) {
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+	int rc;
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+
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+	/* Configure I2C bus */
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+	memcpy ( &exanic->i2cfg, i2cfg, sizeof ( exanic->i2cfg ) );
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+
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+	/* Initialise I2C bus */
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+	if ( ( rc = init_i2c_bit_basher ( &exanic->basher,
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+					  &exanic_i2c_basher_ops ) ) != 0 ) {
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+		DBGC2 ( exanic, "EXANIC %p found no I2C bus via %d/%d/%d\n",
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+			exanic, exanic->i2cfg.setscl,
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+			exanic->i2cfg.setsda, exanic->i2cfg.getsda );
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+		return rc;
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+	}
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+
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+	/* Check for EEPROM presence */
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+	init_i2c_eeprom ( &exanic->eeprom, EXANIC_EEPROM_ADDRESS );
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+	if ( ( rc = i2c_check_presence ( &exanic->basher.i2c,
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+					 &exanic->eeprom ) ) != 0 ) {
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+		DBGC2 ( exanic, "EXANIC %p found no EEPROM via %d/%d/%d\n",
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+			exanic, exanic->i2cfg.setscl,
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+			exanic->i2cfg.setsda, exanic->i2cfg.getsda );
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+		return rc;
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+	}
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+
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+	DBGC ( exanic, "EXANIC %p found EEPROM via %d/%d/%d\n",
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+	       exanic, exanic->i2cfg.setscl,
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+	       exanic->i2cfg.setsda, exanic->i2cfg.getsda );
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+	return 0;
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+}
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+
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+/**
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+ * Initialise EEPROM
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+ *
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+ * @v exanic		ExaNIC device
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+ * @ret rc		Return status code
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+ */
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+static int exanic_init_eeprom ( struct exanic *exanic ) {
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+	struct exanic_i2c_config *i2cfg;
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+	unsigned int i;
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+	int rc;
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+
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+	/* Try all possible bus configurations */
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+	for ( i = 0 ; i < ( sizeof ( exanic_i2cfgs ) /
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+			    sizeof ( exanic_i2cfgs[0] ) ) ; i++ ) {
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+		i2cfg = &exanic_i2cfgs[i];
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+		if ( ( rc = exanic_try_init_eeprom ( exanic, i2cfg ) ) == 0 )
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+			return 0;
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+	}
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+
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+	DBGC ( exanic, "EXANIC %p found no EEPROM\n", exanic );
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+	return -ENODEV;
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+}
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+
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+/**
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+ * Fetch base MAC address
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+ *
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+ * @v exanic		ExaNIC device
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+ * @ret rc		Return status code
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+ */
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+static int exanic_fetch_mac ( struct exanic *exanic ) {
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+	struct i2c_interface *i2c = &exanic->basher.i2c;
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+	int rc;
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+
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+	/* Initialise EEPROM */
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+	if ( ( rc = exanic_init_eeprom ( exanic ) ) != 0 )
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+		return rc;
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+
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+	/* Fetch base MAC address */
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+	if ( ( rc = i2c->read ( i2c, &exanic->eeprom, 0, exanic->mac,
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+				sizeof ( exanic->mac ) ) ) != 0 ) {
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+		DBGC ( exanic, "EXANIC %p could not read MAC address: %s\n",
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+		       exanic, strerror ( rc ) );
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+		return rc;
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+	}
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+
289
+	return 0;
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+}
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+
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+/******************************************************************************
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+ *
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+ * Link state
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+ *
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+ ******************************************************************************
297
+ */
298
+
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+/**
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+ * Check link state
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+ *
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+ * @v netdev		Network device
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+ */
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+static void exanic_check_link ( struct net_device *netdev ) {
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+	struct exanic_port *port = netdev->priv;
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+	uint32_t status;
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+	uint32_t speed;
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+
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+	/* Report port status changes */
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+	status = readl ( port->regs + EXANIC_PORT_STATUS );
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+	speed = readl ( port->regs + EXANIC_PORT_SPEED );
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+	if ( status != port->status ) {
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+		DBGC ( port, "EXANIC %s port status %#08x speed %dMbps\n",
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+		       netdev->name, status, speed );
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+		if ( status & EXANIC_PORT_STATUS_LINK ) {
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+			netdev_link_up ( netdev );
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+		} else {
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+			netdev_link_down ( netdev );
319
+		}
320
+		port->status = status;
321
+	}
322
+}
323
+
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+/**
325
+ * Check link state periodically
326
+ *
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+ * @v retry		Link state check timer
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+ * @v over		Failure indicator
329
+ */
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+static void exanic_expired ( struct retry_timer *timer, int over __unused ) {
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+	struct exanic_port *port =
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+		container_of ( timer, struct exanic_port, timer );
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+	struct net_device *netdev = port->netdev;
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+	static const uint32_t speeds[] = {
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+		100, 1000, 10000, 40000, 100000,
336
+	};
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+	unsigned int index;
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+
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+	/* Restart timer */
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+	start_timer_fixed ( timer, EXANIC_LINK_INTERVAL );
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+
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+	/* Check link state */
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+	exanic_check_link ( netdev );
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+
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+	/* Do nothing further if link is already up */
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+	if ( netdev_link_ok ( netdev ) )
347
+		return;
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+
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+	/* Do nothing further unless we have a valid list of supported speeds */
350
+	if ( ! port->speeds )
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+		return;
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+
353
+	/* Autonegotiation is not supported; try manually selecting
354
+	 * the next supported link speed.
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+	 */
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+	do {
357
+		if ( ! port->speed )
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+			port->speed = ( 8 * sizeof ( port->speeds ) );
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+		port->speed--;
360
+	} while ( ! ( ( 1UL << port->speed ) & port->speeds ) );
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+	index = ( port->speed - ( ffs ( EXANIC_CAPS_SPEED_MASK ) - 1 ) );
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+	assert ( index < ( sizeof ( speeds ) / sizeof ( speeds[0] ) ) );
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+
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+	/* Attempt the selected speed */
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+	DBGC ( netdev, "EXANIC %s attempting %dMbps\n",
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+	       netdev->name, speeds[index] );
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+	writel ( speeds[index], ( port->regs + EXANIC_PORT_SPEED ) );
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+}
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+
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+/******************************************************************************
371
+ *
372
+ * Network device interface
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+ *
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+ ******************************************************************************
375
+ */
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+
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+/**
378
+ * Open network device
379
+ *
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+ * @v netdev		Network device
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+ * @ret rc		Return status code
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+ */
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+static int exanic_open ( struct net_device *netdev ) {
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+	struct exanic_port *port = netdev->priv;
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+	struct exanic_tx_chunk *tx;
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+	unsigned int i;
387
+
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+	/* Reset transmit region contents */
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+	for ( i = 0 ; i < port->tx_count ; i++ ) {
390
+		tx = ( port->tx + ( i * sizeof ( *tx ) ) );
391
+		writew ( port->txf_slot, &tx->desc.txf_slot );
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+		writeb ( EXANIC_TYPE_RAW, &tx->desc.type );
393
+		writeb ( 0, &tx->desc.flags );
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+		writew ( 0, &tx->pad );
395
+	}
396
+
397
+	/* Reset receive region contents */
398
+	memset_user ( port->rx, 0, 0xff, EXANIC_RX_LEN );
399
+
400
+	/* Reset transmit feedback region */
401
+	*(port->txf) = 0;
402
+
403
+	/* Reset counters */
404
+	port->tx_prod = 0;
405
+	port->tx_cons = 0;
406
+	port->rx_cons = 0;
407
+
408
+	/* Map receive region */
409
+	exanic_write_base ( phys_to_bus ( user_to_phys ( port->rx, 0 ) ),
410
+			    ( port->regs + EXANIC_PORT_RX_BASE ) );
411
+
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+	/* Enable promiscuous mode */
413
+	writel ( EXANIC_PORT_FLAGS_PROMISC,
414
+		 ( port->regs + EXANIC_PORT_FLAGS ) );
415
+
416
+	/* Reset to default speed and clear cached status */
417
+	writel ( port->default_speed, ( port->regs + EXANIC_PORT_SPEED ) );
418
+	port->speed = 0;
419
+	port->status = 0;
420
+
421
+	/* Enable port */
422
+	wmb();
423
+	writel ( EXANIC_PORT_ENABLE_ENABLED,
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+		 ( port->regs + EXANIC_PORT_ENABLE ) );
425
+
426
+	/* Start link state timer */
427
+	start_timer_fixed ( &port->timer, EXANIC_LINK_INTERVAL );
428
+
429
+	return 0;
430
+}
431
+
432
+/**
433
+ * Close network device
434
+ *
435
+ * @v netdev		Network device
436
+ */
437
+static void exanic_close ( struct net_device *netdev ) {
438
+	struct exanic_port *port = netdev->priv;
439
+
440
+	/* Stop link state timer */
441
+	stop_timer ( &port->timer );
442
+
443
+	/* Disable port */
444
+	writel ( 0, ( port->regs + EXANIC_PORT_ENABLE ) );
445
+	wmb();
446
+
447
+	/* Clear receive region */
448
+	exanic_clear_base ( port->regs + EXANIC_PORT_RX_BASE );
449
+
450
+	/* Discard any in-progress receive */
451
+	if ( port->rx_iobuf ) {
452
+		netdev_rx_err ( netdev, port->rx_iobuf, -ECANCELED );
453
+		port->rx_iobuf = NULL;
454
+	}
455
+}
456
+
457
+/**
458
+ * Transmit packet
459
+ *
460
+ * @v netdev		Network device
461
+ * @v iobuf		I/O buffer
462
+ * @ret rc		Return status code
463
+ */
464
+static int exanic_transmit ( struct net_device *netdev,
465
+			     struct io_buffer *iobuf ) {
466
+	struct exanic_port *port = netdev->priv;
467
+	struct exanic_tx_chunk *tx;
468
+	unsigned int tx_fill;
469
+	unsigned int tx_index;
470
+	size_t offset;
471
+	size_t len;
472
+	uint8_t *src;
473
+	uint8_t *dst;
474
+
475
+	/* Sanity check */
476
+	len = iob_len ( iobuf );
477
+	if ( len > sizeof ( tx->data ) ) {
478
+		DBGC ( port, "EXANIC %s transmit too large\n", netdev->name );
479
+		return -ENOTSUP;
480
+	}
481
+
482
+	/* Get next transmit descriptor */
483
+	tx_fill = ( port->tx_prod - port->tx_cons );
484
+	if ( tx_fill >= port->tx_count ) {
485
+		DBGC ( port, "EXANIC %s out of transmit descriptors\n",
486
+		       netdev->name );
487
+		return -ENOBUFS;
488
+	}
489
+	tx_index = ( port->tx_prod & ( port->tx_count - 1 ) );
490
+	offset = ( tx_index * sizeof ( *tx ) );
491
+	tx = ( port->tx + offset );
492
+	DBGC2 ( port, "EXANIC %s TX %04x at [%05zx,%05zx)\n",
493
+		netdev->name, port->tx_prod, ( port->tx_offset + offset ),
494
+		( port->tx_offset + offset +
495
+		  offsetof ( typeof ( *tx ), data ) + len ) );
496
+	port->tx_prod++;
497
+
498
+	/* Populate transmit descriptor */
499
+	writew ( port->tx_prod, &tx->desc.txf_id );
500
+	writew ( ( sizeof ( tx->pad ) + len ), &tx->desc.len );
501
+
502
+	/* Copy data to transmit region.  There is no DMA on the
503
+	 * transmit data path.
504
+	 */
505
+	src = iobuf->data;
506
+	dst = tx->data;
507
+	while ( len-- )
508
+		writeb ( *(src++), dst++ );
509
+
510
+	/* Send transmit command */
511
+	wmb();
512
+	writel ( ( port->tx_offset + offset ),
513
+		 ( port->regs + EXANIC_PORT_TX_COMMAND ) );
514
+
515
+	return 0;
516
+}
517
+
518
+/**
519
+ * Poll for completed packets
520
+ *
521
+ * @v netdev		Network device
522
+ */
523
+static void exanic_poll_tx ( struct net_device *netdev ) {
524
+	struct exanic_port *port = netdev->priv;
525
+
526
+	/* Report any completed packets */
527
+	while ( port->tx_cons != *(port->txf) ) {
528
+		DBGC2 ( port, "EXANIC %s TX %04x complete\n",
529
+			netdev->name, port->tx_cons );
530
+		netdev_tx_complete_next ( netdev );
531
+		port->tx_cons++;
532
+	}
533
+}
534
+
535
+/**
536
+ * Poll for received packets
537
+ *
538
+ * @v netdev		Network device
539
+ */
540
+static void exanic_poll_rx ( struct net_device *netdev ) {
541
+	struct exanic_port *port = netdev->priv;
542
+	struct exanic_rx_chunk *rx;
543
+	struct exanic_rx_descriptor desc;
544
+	uint8_t current;
545
+	uint8_t previous;
546
+	size_t offset;
547
+	size_t len;
548
+
549
+	for ( ; ; port->rx_cons++ ) {
550
+
551
+		/* Fetch descriptor */
552
+		offset = ( ( port->rx_cons * sizeof ( *rx ) ) % EXANIC_RX_LEN );
553
+		copy_from_user ( &desc, port->rx,
554
+				 ( offset + offsetof ( typeof ( *rx ), desc ) ),
555
+				 sizeof ( desc ) );
556
+
557
+		/* Calculate generation */
558
+		current = ( port->rx_cons / ( EXANIC_RX_LEN / sizeof ( *rx ) ));
559
+		previous = ( current - 1 );
560
+
561
+		/* Do nothing if no chunk is ready */
562
+		if ( desc.generation == previous )
563
+			break;
564
+
565
+		/* Allocate I/O buffer if needed */
566
+		if ( ! port->rx_iobuf ) {
567
+			port->rx_iobuf = alloc_iob ( EXANIC_MAX_RX_LEN );
568
+			if ( ! port->rx_iobuf ) {
569
+				/* Wait for next poll */
570
+				break;
571
+			}
572
+			port->rx_rc = 0;
573
+		}
574
+
575
+		/* Calculate chunk length */
576
+		len = ( desc.len ? desc.len : sizeof ( rx->data ) );
577
+
578
+		/* Append data to I/O buffer */
579
+		if ( len <= iob_tailroom ( port->rx_iobuf ) ) {
580
+			copy_from_user ( iob_put ( port->rx_iobuf, len ),
581
+					 port->rx,
582
+					 ( offset + offsetof ( typeof ( *rx ),
583
+							       data ) ), len );
584
+		} else {
585
+			DBGC ( port, "EXANIC %s RX too large\n",
586
+			       netdev->name );
587
+			port->rx_rc = -ERANGE;
588
+		}
589
+
590
+		/* Check for overrun */
591
+		rmb();
592
+		copy_from_user ( &desc.generation, port->rx,
593
+				 ( offset + offsetof ( typeof ( *rx ),
594
+						       desc.generation ) ),
595
+				 sizeof ( desc.generation ) );
596
+		if ( desc.generation != current ) {
597
+			DBGC ( port, "EXANIC %s RX overrun\n", netdev->name );
598
+			port->rx_rc = -ENOBUFS;
599
+			continue;
600
+		}
601
+
602
+		/* Wait for end of packet */
603
+		if ( ! desc.len )
604
+			continue;
605
+
606
+		/* Check for receive errors */
607
+		if ( desc.status & EXANIC_STATUS_ERROR_MASK ) {
608
+			port->rx_rc = -EIO_STATUS ( desc.status );
609
+			DBGC ( port, "EXANIC %s RX %04x error: %s\n",
610
+			       netdev->name, port->rx_cons,
611
+			       strerror ( port->rx_rc ) );
612
+		} else {
613
+			DBGC2 ( port, "EXANIC %s RX %04x\n",
614
+				netdev->name, port->rx_cons );
615
+		}
616
+
617
+		/* Hand off to network stack */
618
+		if ( port->rx_rc ) {
619
+			netdev_rx_err ( netdev, port->rx_iobuf, port->rx_rc );
620
+		} else {
621
+			iob_unput ( port->rx_iobuf, 4 /* strip CRC */ );
622
+			netdev_rx ( netdev, port->rx_iobuf );
623
+		}
624
+		port->rx_iobuf = NULL;
625
+	}
626
+}
627
+
628
+/**
629
+ * Poll for completed and received packets
630
+ *
631
+ * @v netdev		Network device
632
+ */
633
+static void exanic_poll ( struct net_device *netdev ) {
634
+
635
+	/* Poll for completed packets */
636
+	exanic_poll_tx ( netdev );
637
+
638
+	/* Poll for received packets */
639
+	exanic_poll_rx ( netdev );
640
+}
641
+
642
+/** ExaNIC network device operations */
643
+static struct net_device_operations exanic_operations = {
644
+	.open		= exanic_open,
645
+	.close		= exanic_close,
646
+	.transmit	= exanic_transmit,
647
+	.poll		= exanic_poll,
648
+};
649
+
650
+/******************************************************************************
651
+ *
652
+ * PCI interface
653
+ *
654
+ ******************************************************************************
655
+ */
656
+
657
+/**
658
+ * Probe port
659
+ *
660
+ * @v exanic		ExaNIC device
661
+ * @v dev		Parent device
662
+ * @v index		Port number
663
+ * @ret rc		Return status code
664
+ */
665
+static int exanic_probe_port ( struct exanic *exanic, struct device *dev,
666
+			       unsigned int index ) {
667
+	struct net_device *netdev;
668
+	struct exanic_port *port;
669
+	void *port_regs;
670
+	uint32_t status;
671
+	size_t tx_len;
672
+	int rc;
673
+
674
+	/* Do nothing if port is not physically present */
675
+	port_regs = ( exanic->regs + EXANIC_PORT_REGS ( index ) );
676
+	status = readl ( port_regs + EXANIC_PORT_STATUS );
677
+	tx_len = readl ( port_regs + EXANIC_PORT_TX_LEN );
678
+	if ( ( status & EXANIC_PORT_STATUS_ABSENT ) || ( tx_len == 0 ) ) {
679
+		rc = 0;
680
+		goto absent;
681
+	}
682
+
683
+	/* Allocate network device */
684
+	netdev = alloc_etherdev ( sizeof ( *port ) );
685
+	if ( ! netdev ) {
686
+		rc = -ENOMEM;
687
+		goto err_alloc_netdev;
688
+	}
689
+	netdev_init ( netdev, &exanic_operations );
690
+	netdev->dev = dev;
691
+	port = netdev->priv;
692
+	memset ( port, 0, sizeof ( *port ) );
693
+	exanic->port[index] = port;
694
+	port->netdev = netdev;
695
+	port->regs = port_regs;
696
+	timer_init ( &port->timer, exanic_expired, &netdev->refcnt );
697
+
698
+	/* Identify transmit region */
699
+	port->tx_offset = readl ( port->regs + EXANIC_PORT_TX_OFFSET );
700
+	if ( tx_len > EXANIC_MAX_TX_LEN )
701
+		tx_len = EXANIC_MAX_TX_LEN;
702
+	assert ( ! ( tx_len & ( tx_len - 1 ) ) );
703
+	port->tx = ( exanic->tx + port->tx_offset );
704
+	port->tx_count = ( tx_len / sizeof ( struct exanic_tx_chunk ) );
705
+
706
+	/* Identify transmit feedback region */
707
+	port->txf_slot = EXANIC_TXF_SLOT ( index );
708
+	port->txf = ( exanic->txf +
709
+		      ( port->txf_slot * sizeof ( *(port->txf) ) ) );
710
+
711
+	/* Allocate receive region (via umalloc()) */
712
+	port->rx = umalloc ( EXANIC_RX_LEN );
713
+	if ( ! port->rx ) {
714
+		rc = -ENOMEM;
715
+		goto err_alloc_rx;
716
+	}
717
+
718
+	/* Set MAC address */
719
+	memcpy ( netdev->hw_addr, exanic->mac, ETH_ALEN );
720
+	netdev->hw_addr[ ETH_ALEN - 1 ] += index;
721
+
722
+	/* Record default link speed and supported speeds */
723
+	port->default_speed = readl ( port->regs + EXANIC_PORT_SPEED );
724
+	port->speeds = ( exanic->caps & EXANIC_CAPS_SPEED_MASK );
725
+
726
+	/* Register network device */
727
+	if ( ( rc = register_netdev ( netdev ) ) != 0 )
728
+		goto err_register_netdev;
729
+	DBGC ( port, "EXANIC %s port %d TX [%#05zx,%#05zx) TXF %#02x RX "
730
+	       "[%#lx,%#lx)\n", netdev->name, index, port->tx_offset,
731
+	       ( port->tx_offset + tx_len ), port->txf_slot,
732
+	       user_to_phys ( port->rx, 0 ),
733
+	       user_to_phys ( port->rx, EXANIC_RX_LEN ) );
734
+
735
+	/* Set initial link state */
736
+	exanic_check_link ( netdev );
737
+
738
+	return 0;
739
+
740
+	unregister_netdev ( netdev );
741
+ err_register_netdev:
742
+	ufree ( port->rx );
743
+ err_alloc_rx:
744
+	netdev_nullify ( netdev );
745
+	netdev_put ( netdev );
746
+ err_alloc_netdev:
747
+ absent:
748
+	return rc;
749
+}
750
+
751
+/**
752
+ * Probe port
753
+ *
754
+ * @v exanic		ExaNIC device
755
+ * @v index		Port number
756
+ */
757
+static void exanic_remove_port ( struct exanic *exanic, unsigned int index ) {
758
+	struct exanic_port *port;
759
+
760
+	/* Do nothing if port is not physically present */
761
+	port = exanic->port[index];
762
+	if ( ! port )
763
+		return;
764
+
765
+	/* Unregister network device */
766
+	unregister_netdev ( port->netdev );
767
+
768
+	/* Free receive region */
769
+	ufree ( port->rx );
770
+
771
+	/* Free network device */
772
+	netdev_nullify ( port->netdev );
773
+	netdev_put ( port->netdev );
774
+}
775
+
776
+/**
777
+ * Probe PCI device
778
+ *
779
+ * @v pci		PCI device
780
+ * @ret rc		Return status code
781
+ */
782
+static int exanic_probe ( struct pci_device *pci ) {
783
+	struct exanic *exanic;
784
+	unsigned long regs_bar_start;
785
+	unsigned long tx_bar_start;
786
+	size_t tx_bar_len;
787
+	int i;
788
+	int rc;
789
+
790
+	/* Allocate and initialise structure */
791
+	exanic = zalloc ( sizeof ( *exanic ) );
792
+	if ( ! exanic ) {
793
+		rc = -ENOMEM;
794
+		goto err_alloc;
795
+	}
796
+	pci_set_drvdata ( pci, exanic );
797
+
798
+	/* Fix up PCI device */
799
+	adjust_pci_device ( pci );
800
+
801
+	/* Map registers */
802
+	regs_bar_start = pci_bar_start ( pci, EXANIC_REGS_BAR );
803
+	exanic->regs = ioremap ( regs_bar_start, EXANIC_REGS_LEN );
804
+	if ( ! exanic->regs ) {
805
+		rc = -ENODEV;
806
+		goto err_ioremap_regs;
807
+	}
808
+
809
+	/* Reset device */
810
+	exanic_reset ( exanic );
811
+
812
+	/* Read capabilities */
813
+	exanic->caps = readl ( exanic->regs + EXANIC_CAPS );
814
+
815
+	/* Fetch base MAC address */
816
+	if ( ( rc = exanic_fetch_mac ( exanic ) ) != 0 )
817
+		goto err_fetch_mac;
818
+	DBGC ( exanic, "EXANIC %p capabilities %#08x base MAC %s\n",
819
+	       exanic, exanic->caps, eth_ntoa ( exanic->mac ) );
820
+
821
+	/* Map transmit region */
822
+	tx_bar_start = pci_bar_start ( pci, EXANIC_TX_BAR );
823
+	tx_bar_len = pci_bar_size ( pci, EXANIC_TX_BAR );
824
+	exanic->tx = ioremap ( tx_bar_start, tx_bar_len );
825
+	if ( ! exanic->tx ) {
826
+		rc = -ENODEV;
827
+		goto err_ioremap_tx;
828
+	}
829
+
830
+	/* Allocate transmit feedback region (shared between all ports) */
831
+	exanic->txf = malloc_dma ( EXANIC_TXF_LEN, EXANIC_ALIGN );
832
+	if ( ! exanic->txf ) {
833
+		rc = -ENOMEM;
834
+		goto err_alloc_txf;
835
+	}
836
+	memset ( exanic->txf, 0, EXANIC_TXF_LEN );
837
+	exanic_write_base ( virt_to_bus ( exanic->txf ),
838
+			    ( exanic->regs + EXANIC_TXF_BASE ) );
839
+
840
+	/* Allocate and initialise per-port network devices */
841
+	for ( i = 0 ; i < EXANIC_MAX_PORTS ; i++ ) {
842
+		if ( ( rc = exanic_probe_port ( exanic, &pci->dev, i ) ) != 0 )
843
+			goto err_probe_port;
844
+	}
845
+
846
+	return 0;
847
+
848
+	i = EXANIC_MAX_PORTS;
849
+ err_probe_port:
850
+	for ( i-- ; i >= 0 ; i-- )
851
+		exanic_remove_port ( exanic, i );
852
+	exanic_reset ( exanic );
853
+	free_dma ( exanic->txf, EXANIC_TXF_LEN );
854
+ err_alloc_txf:
855
+	iounmap ( exanic->tx );
856
+ err_ioremap_tx:
857
+	iounmap ( exanic->regs );
858
+ err_fetch_mac:
859
+ err_ioremap_regs:
860
+	free ( exanic );
861
+ err_alloc:
862
+	return rc;
863
+}
864
+
865
+/**
866
+ * Remove PCI device
867
+ *
868
+ * @v pci		PCI device
869
+ */
870
+static void exanic_remove ( struct pci_device *pci ) {
871
+	struct exanic *exanic = pci_get_drvdata ( pci );
872
+	unsigned int i;
873
+
874
+	/* Remove all ports */
875
+	for ( i = 0 ; i < EXANIC_MAX_PORTS ; i++ )
876
+		exanic_remove_port ( exanic, i );
877
+
878
+	/* Reset device */
879
+	exanic_reset ( exanic );
880
+
881
+	/* Free transmit feedback region */
882
+	free_dma ( exanic->txf, EXANIC_TXF_LEN );
883
+
884
+	/* Unmap transmit region */
885
+	iounmap ( exanic->tx );
886
+
887
+	/* Unmap registers */
888
+	iounmap ( exanic->regs );
889
+
890
+	/* Free device */
891
+	free ( exanic );
892
+}
893
+
894
+/** ExaNIC PCI device IDs */
895
+static struct pci_device_id exanic_ids[] = {
896
+	PCI_ROM ( 0x10ee, 0x2b00, "exanic-old", "ExaNIC (old)", 0 ),
897
+	PCI_ROM ( 0x1ce4, 0x0001, "exanic-x4", "ExaNIC X4", 0 ),
898
+	PCI_ROM ( 0x1ce4, 0x0002, "exanic-x2", "ExaNIC X2", 0 ),
899
+	PCI_ROM ( 0x1ce4, 0x0003, "exanic-x10", "ExaNIC X10", 0 ),
900
+	PCI_ROM ( 0x1ce4, 0x0004, "exanic-x10gm", "ExaNIC X10 GM", 0 ),
901
+	PCI_ROM ( 0x1ce4, 0x0005, "exanic-x40", "ExaNIC X40", 0 ),
902
+	PCI_ROM ( 0x1ce4, 0x0006, "exanic-x10hpt", "ExaNIC X10 HPT", 0 ),
903
+};
904
+
905
+/** ExaNIC PCI driver */
906
+struct pci_driver exanic_driver __pci_driver = {
907
+	.ids = exanic_ids,
908
+	.id_count = ( sizeof ( exanic_ids ) / sizeof ( exanic_ids[0] ) ),
909
+	.probe = exanic_probe,
910
+	.remove = exanic_remove,
911
+};

+ 257
- 0
src/drivers/net/exanic.h Näytä tiedosto

@@ -0,0 +1,257 @@
1
+#ifndef _EXANIC_H
2
+#define _EXANIC_H
3
+
4
+/** @file
5
+ *
6
+ * Exablaze ExaNIC driver
7
+ *
8
+ */
9
+
10
+FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
11
+
12
+#include <stdint.h>
13
+#include <ipxe/pci.h>
14
+#include <ipxe/ethernet.h>
15
+#include <ipxe/uaccess.h>
16
+#include <ipxe/retry.h>
17
+#include <ipxe/i2c.h>
18
+#include <ipxe/bitbash.h>
19
+
20
+/** Maximum number of ports */
21
+#define EXANIC_MAX_PORTS 8
22
+
23
+/** Register BAR */
24
+#define EXANIC_REGS_BAR PCI_BASE_ADDRESS_0
25
+
26
+/** Transmit region BAR */
27
+#define EXANIC_TX_BAR PCI_BASE_ADDRESS_2
28
+
29
+/** Alignment for DMA regions */
30
+#define EXANIC_ALIGN 0x1000
31
+
32
+/** Flag for 32-bit DMA addresses */
33
+#define EXANIC_DMA_32_BIT 0x00000001UL
34
+
35
+/** Register set length */
36
+#define EXANIC_REGS_LEN 0x2000
37
+
38
+/** Transmit feedback region length */
39
+#define EXANIC_TXF_LEN 0x1000
40
+
41
+/** Transmit feedback slot
42
+ *
43
+ * This is a policy decision.
44
+ */
45
+#define EXANIC_TXF_SLOT( index ) ( 0x40 * (index) )
46
+
47
+/** Receive region length */
48
+#define EXANIC_RX_LEN 0x200000
49
+
50
+/** Transmit feedback base address register */
51
+#define EXANIC_TXF_BASE 0x0014
52
+
53
+/** Capabilities register */
54
+#define EXANIC_CAPS 0x0038
55
+#define EXANIC_CAPS_100M 0x01000000UL		/**< 100Mbps supported */
56
+#define EXANIC_CAPS_1G 0x02000000UL		/**< 1Gbps supported */
57
+#define EXANIC_CAPS_10G 0x04000000UL		/**< 10Gbps supported */
58
+#define EXANIC_CAPS_40G 0x08000000UL		/**< 40Gbps supported */
59
+#define EXANIC_CAPS_100G 0x10000000UL		/**< 100Gbps supported */
60
+#define EXANIC_CAPS_SPEED_MASK 0x1f000000UL	/**< Supported speeds mask */
61
+
62
+/** I2C GPIO register */
63
+#define EXANIC_I2C 0x012c
64
+
65
+/** Port register offset */
66
+#define EXANIC_PORT_REGS( index ) ( 0x0200 + ( 0x40 * (index) ) )
67
+
68
+/** Port enable register */
69
+#define EXANIC_PORT_ENABLE 0x0000
70
+#define EXANIC_PORT_ENABLE_ENABLED 0x00000001UL	/**< Port is enabled */
71
+
72
+/** Port speed register */
73
+#define EXANIC_PORT_SPEED 0x0004
74
+
75
+/** Port status register */
76
+#define EXANIC_PORT_STATUS 0x0008
77
+#define EXANIC_PORT_STATUS_LINK 0x00000008UL	/**< Link is up */
78
+#define EXANIC_PORT_STATUS_ABSENT 0x80000000UL	/**< Port is not present */
79
+
80
+/** Port MAC address (second half) register */
81
+#define EXANIC_PORT_MAC 0x000c
82
+
83
+/** Port flags register */
84
+#define EXANIC_PORT_FLAGS 0x0010
85
+#define EXANIC_PORT_FLAGS_PROMISC 0x00000001UL	/**< Promiscuous mode */
86
+
87
+/** Port receive chunk base address register */
88
+#define EXANIC_PORT_RX_BASE 0x0014
89
+
90
+/** Port transmit command register */
91
+#define EXANIC_PORT_TX_COMMAND 0x0020
92
+
93
+/** Port transmit region offset register */
94
+#define EXANIC_PORT_TX_OFFSET 0x0024
95
+
96
+/** Port transmit region length register */
97
+#define EXANIC_PORT_TX_LEN 0x0028
98
+
99
+/** Port MAC address (first half) register */
100
+#define EXANIC_PORT_OUI 0x0030
101
+
102
+/** Port interrupt configuration register */
103
+#define EXANIC_PORT_IRQ 0x0034
104
+
105
+/** An ExaNIC transmit chunk descriptor */
106
+struct exanic_tx_descriptor {
107
+	/** Feedback ID */
108
+	uint16_t txf_id;
109
+	/** Feedback slot */
110
+	uint16_t txf_slot;
111
+	/** Payload length (including padding */
112
+	uint16_t len;
113
+	/** Payload type */
114
+	uint8_t type;
115
+	/** Flags */
116
+	uint8_t flags;
117
+} __attribute__ (( packed ));
118
+
119
+/** An ExaNIC transmit chunk */
120
+struct exanic_tx_chunk {
121
+	/** Descriptor */
122
+	struct exanic_tx_descriptor desc;
123
+	/** Padding */
124
+	uint8_t pad[2];
125
+	/** Payload data */
126
+	uint8_t data[2038];
127
+} __attribute__ (( packed ));
128
+
129
+/** Raw Ethernet frame type */
130
+#define EXANIC_TYPE_RAW 0x01
131
+
132
+/** An ExaNIC receive chunk descriptor */
133
+struct exanic_rx_descriptor {
134
+	/** Timestamp */
135
+	uint32_t timestamp;
136
+	/** Status (valid only on final chunk) */
137
+	uint8_t status;
138
+	/** Length (zero except on the final chunk) */
139
+	uint8_t len;
140
+	/** Filter number */
141
+	uint8_t filter;
142
+	/** Generation */
143
+	uint8_t generation;
144
+} __attribute__ (( packed ));
145
+
146
+/** An ExaNIC receive chunk */
147
+struct exanic_rx_chunk {
148
+	/** Payload data */
149
+	uint8_t data[120];
150
+	/** Descriptor */
151
+	struct exanic_rx_descriptor desc;
152
+} __attribute__ (( packed ));
153
+
154
+/** Receive status error mask */
155
+#define EXANIC_STATUS_ERROR_MASK 0x0f
156
+
157
+/** An ExaNIC I2C bus configuration */
158
+struct exanic_i2c_config {
159
+	/** GPIO bit for pulling SCL low */
160
+	uint8_t setscl;
161
+	/** GPIO bit for pulling SDA low */
162
+	uint8_t setsda;
163
+	/** GPIO bit for reading SDA */
164
+	uint8_t getsda;
165
+};
166
+
167
+/** EEPROM address */
168
+#define EXANIC_EEPROM_ADDRESS 0x50
169
+
170
+/** An ExaNIC port */
171
+struct exanic_port {
172
+	/** Network device */
173
+	struct net_device *netdev;
174
+	/** Port registers */
175
+	void *regs;
176
+
177
+	/** Transmit region offset */
178
+	size_t tx_offset;
179
+	/** Transmit region */
180
+	void *tx;
181
+	/** Number of transmit descriptors */
182
+	uint16_t tx_count;
183
+	/** Transmit producer counter */
184
+	uint16_t tx_prod;
185
+	/** Transmit consumer counter */
186
+	uint16_t tx_cons;
187
+	/** Transmit feedback slot */
188
+	uint16_t txf_slot;
189
+	/** Transmit feedback region */
190
+	uint16_t *txf;
191
+
192
+	/** Receive region */
193
+	userptr_t rx;
194
+	/** Receive consumer counter */
195
+	unsigned int rx_cons;
196
+	/** Receive I/O buffer (if any) */
197
+	struct io_buffer *rx_iobuf;
198
+	/** Receive status */
199
+	int rx_rc;
200
+
201
+	/** Port status */
202
+	uint32_t status;
203
+	/** Default link speed (as raw register value) */
204
+	uint32_t default_speed;
205
+	/** Speed capability bitmask */
206
+	uint32_t speeds;
207
+	/** Current attempted link speed (as a capability bit index) */
208
+	unsigned int speed;
209
+	/** Port status check timer */
210
+	struct retry_timer timer;
211
+};
212
+
213
+/** An ExaNIC */
214
+struct exanic {
215
+	/** Registers */
216
+	void *regs;
217
+	/** Transmit region */
218
+	void *tx;
219
+	/** Transmit feedback region */
220
+	void *txf;
221
+
222
+	/** I2C bus configuration */
223
+	struct exanic_i2c_config i2cfg;
224
+	/** I2C bit-bashing interface */
225
+	struct i2c_bit_basher basher;
226
+	/** I2C serial EEPROM */
227
+	struct i2c_device eeprom;
228
+
229
+	/** Capabilities */
230
+	uint32_t caps;
231
+	/** Base MAC address */
232
+	uint8_t mac[ETH_ALEN];
233
+
234
+	/** Ports */
235
+	struct exanic_port *port[EXANIC_MAX_PORTS];
236
+};
237
+
238
+/** Maximum used length of transmit region
239
+ *
240
+ * This is a policy decision to avoid overflowing the 16-bit transmit
241
+ * producer and consumer counters.
242
+ */
243
+#define EXANIC_MAX_TX_LEN ( 256 * sizeof ( struct exanic_tx_chunk ) )
244
+
245
+/** Maximum length of received packet
246
+ *
247
+ * This is a policy decision.
248
+ */
249
+#define EXANIC_MAX_RX_LEN ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ )
250
+
251
+/** Interval between link state checks
252
+ *
253
+ * This is a policy decision.
254
+ */
255
+#define EXANIC_LINK_INTERVAL ( 1 * TICKS_PER_SEC )
256
+
257
+#endif /* _EXANIC_H */

+ 1
- 0
src/include/ipxe/errfile.h Näytä tiedosto

@@ -199,6 +199,7 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
199 199
 #define ERRFILE_af_packet	     ( ERRFILE_DRIVER | 0x00c30000 )
200 200
 #define ERRFILE_sfc_hunt	     ( ERRFILE_DRIVER | 0x00c40000 )
201 201
 #define ERRFILE_efx_hunt	     ( ERRFILE_DRIVER | 0x00c50000 )
202
+#define ERRFILE_exanic		     ( ERRFILE_DRIVER | 0x00c60000 )
202 203
 
203 204
 #define ERRFILE_aoe			( ERRFILE_NET | 0x00000000 )
204 205
 #define ERRFILE_arp			( ERRFILE_NET | 0x00010000 )

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