Browse Source

[e1000e] Basic 82579 support

Add support for 82579-based chips such as those found on Sandy Bridge
motherboards.  Based on d3738bb820 in
Linux.

Signed-off-by: Daniel Hokka Zakrisson <daniel@hozac.com>
Signed-off-by: Michael Brown <mcb30@ipxe.org>
tags/v1.20.1
Daniel Hokka Zakrisson 12 years ago
parent
commit
0e4a5ca4c7

+ 2
- 0
src/drivers/net/e1000e/e1000e.h View File

@@ -143,6 +143,7 @@ enum e1000_boards {
143 143
 	board_ich9lan,
144 144
 	board_ich10lan,
145 145
 	board_pchlan,
146
+	board_pch2lan,
146 147
 	board_82583,
147 148
 };
148 149
 
@@ -300,6 +301,7 @@ extern void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw,
300 301
 extern void e1000e_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw);
301 302
 extern void e1000e_gig_downshift_workaround_ich8lan(struct e1000_hw *hw);
302 303
 extern void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw);
304
+extern s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable);
303 305
 
304 306
 extern s32 e1000e_check_for_copper_link(struct e1000_hw *hw);
305 307
 extern s32 e1000e_check_for_fiber_link(struct e1000_hw *hw);

+ 2
- 0
src/drivers/net/e1000e/e1000e_defines.h View File

@@ -675,6 +675,7 @@ FILE_LICENCE ( GPL2_OR_LATER );
675 675
 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE       0x00000001
676 676
 #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE       0x00000008
677 677
 #define E1000_EXTCNF_CTRL_SWFLAG                 0x00000020
678
+#define E1000_EXTCNF_CTRL_GATE_PHY_CFG           0x00000080
678 679
 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK   0x00FF0000
679 680
 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT          16
680 681
 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK   0x0FFF0000
@@ -1261,6 +1262,7 @@ FILE_LICENCE ( GPL2_OR_LATER );
1261 1262
 #define BME1000_E_PHY_ID_R2  0x01410CB1
1262 1263
 #define I82577_E_PHY_ID 0x01540050
1263 1264
 #define I82578_E_PHY_ID 0x004DD040
1265
+#define I82579_E_PHY_ID      0x01540090
1264 1266
 #define M88_VENDOR           0x0141
1265 1267
 
1266 1268
 /* M88E1000 Specific Registers */

+ 4
- 0
src/drivers/net/e1000e/e1000e_hw.h View File

@@ -85,6 +85,8 @@ struct e1000_hw;
85 85
 #define E1000_DEV_ID_PCH_M_HV_LC              0x10EB
86 86
 #define E1000_DEV_ID_PCH_D_HV_DM              0x10EF
87 87
 #define E1000_DEV_ID_PCH_D_HV_DC              0x10F0
88
+#define E1000_DEV_ID_PCH2_LV_LM               0x1502
89
+#define E1000_DEV_ID_PCH2_LV_V                0x1503
88 90
 #define E1000_REVISION_0 0
89 91
 #define E1000_REVISION_1 1
90 92
 #define E1000_REVISION_2 2
@@ -109,6 +111,7 @@ enum e1000_mac_type {
109 111
 	e1000_ich9lan,
110 112
 	e1000_ich10lan,
111 113
 	e1000_pchlan,
114
+	e1000_pch2lan,
112 115
 	e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
113 116
 };
114 117
 
@@ -146,6 +149,7 @@ enum e1000_phy_type {
146 149
 	e1000_phy_bm,
147 150
 	e1000_phy_82578,
148 151
 	e1000_phy_82577,
152
+	e1000_phy_82579,
149 153
 };
150 154
 
151 155
 enum e1000_bus_type {

+ 36
- 15
src/drivers/net/e1000e/e1000e_ich8lan.c View File

@@ -206,7 +206,7 @@ static s32 e1000e_init_phy_params_pchlan(struct e1000_hw *hw)
206 206
 	e1000e_get_phy_id(hw);
207 207
 	phy->type = e1000e_get_phy_type_from_id(phy->id);
208 208
 
209
-	if (phy->type == e1000_phy_82577) {
209
+	if (phy->type == e1000_phy_82577 || phy->type == e1000_phy_82579) {
210 210
 		phy->ops.check_polarity = e1000e_check_polarity_82577;
211 211
 #if 0
212 212
 		phy->ops.force_speed_duplex =
@@ -449,6 +449,7 @@ static s32 e1000e_init_mac_params_ich8lan(struct e1000_hw *hw)
449 449
 		mac->ops.led_off = e1000e_led_off_ich8lan;
450 450
 		break;
451 451
 	case e1000_pchlan:
452
+	case e1000_pch2lan:
452 453
 		/* ID LED init */
453 454
 		mac->ops.id_led_init = e1000e_id_led_init_pchlan;
454 455
 		/* setup LED */
@@ -467,6 +468,14 @@ static s32 e1000e_init_mac_params_ich8lan(struct e1000_hw *hw)
467 468
 	if (mac->type == e1000_ich8lan)
468 469
 		e1000e_set_kmrn_lock_loss_workaround_ich8lan(hw, true);
469 470
 
471
+	/* Disable PHY configuration by hardware, config by software */
472
+	if (mac->type == e1000_pch2lan) {
473
+		u32 extcnf_ctrl = er32(EXTCNF_CTRL);
474
+
475
+		extcnf_ctrl |= E1000_EXTCNF_CTRL_GATE_PHY_CFG;
476
+		ew32(EXTCNF_CTRL, extcnf_ctrl);
477
+	}
478
+
470 479
 
471 480
 	return E1000_SUCCESS;
472 481
 }
@@ -577,6 +586,7 @@ void e1000e_init_function_pointers_ich8lan(struct e1000_hw *hw)
577 586
 		hw->phy.ops.init_params = e1000e_init_phy_params_ich8lan;
578 587
 		break;
579 588
 	case e1000_pchlan:
589
+	case e1000_pch2lan:
580 590
 		hw->phy.ops.init_params = e1000e_init_phy_params_pchlan;
581 591
 		break;
582 592
 	default:
@@ -765,7 +775,8 @@ static s32 e1000e_sw_lcd_config_ich8lan(struct e1000_hw *hw)
765 775
 		/* Check if SW needs to configure the PHY */
766 776
 		if ((hw->device_id == E1000_DEV_ID_ICH8_IGP_M_AMT) ||
767 777
 		    (hw->device_id == E1000_DEV_ID_ICH8_IGP_M) ||
768
-		    (hw->mac.type == e1000_pchlan))
778
+		    (hw->mac.type == e1000_pchlan) ||
779
+		    (hw->mac.type == e1000_pch2lan))
769 780
 			sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG_ICH8M;
770 781
 		else
771 782
 			sw_cfg_mask = E1000_FEXTNVM_SW_CONFIG;
@@ -777,13 +788,15 @@ static s32 e1000e_sw_lcd_config_ich8lan(struct e1000_hw *hw)
777 788
 		/* Wait for basic configuration completes before proceeding */
778 789
 		e1000e_lan_init_done_ich8lan(hw);
779 790
 
780
-		/*
781
-		 * Make sure HW does not configure LCD from PHY
782
-		 * extended configuration before SW configuration
783
-		 */
784
-		data = er32(EXTCNF_CTRL);
785
-		if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
786
-			goto out;
791
+		if (hw->mac.type != e1000_pch2lan) {
792
+			/*
793
+			 * Make sure HW does not configure LCD from PHY
794
+			 * extended configuration before SW configuration
795
+			 */
796
+			data = er32(EXTCNF_CTRL);
797
+			if (data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE)
798
+				goto out;
799
+		}
787 800
 
788 801
 		cnf_size = er32(EXTCNF_SIZE);
789 802
 		cnf_size &= E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK;
@@ -795,7 +808,8 @@ static s32 e1000e_sw_lcd_config_ich8lan(struct e1000_hw *hw)
795 808
 		cnf_base_addr >>= E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT;
796 809
 
797 810
 		if (!(data & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE) &&
798
-		    (hw->mac.type == e1000_pchlan)) {
811
+		    (hw->mac.type == e1000_pchlan ||
812
+		     hw->mac.type == e1000_pch2lan)) {
799 813
 			/*
800 814
 			 * HW configures the SMBus address and LEDs when the
801 815
 			 * OEM and LCD Write Enable bits are set in the NVM.
@@ -1006,16 +1020,18 @@ s32 e1000e_oem_bits_config_ich8lan(struct e1000_hw *hw, bool d0_state)
1006 1020
 	u32 mac_reg;
1007 1021
 	u16 oem_reg;
1008 1022
 
1009
-	if (hw->mac.type != e1000_pchlan)
1023
+	if (hw->mac.type != e1000_pchlan && hw->mac.type != e1000_pch2lan)
1010 1024
 		return ret_val;
1011 1025
 
1012 1026
 	ret_val = hw->phy.ops.acquire(hw);
1013 1027
 	if (ret_val)
1014 1028
 		return ret_val;
1015 1029
 
1016
-	mac_reg = er32(EXTCNF_CTRL);
1017
-	if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1018
-		goto out;
1030
+	if (hw->mac.type != e1000_pch2lan) {
1031
+		mac_reg = er32(EXTCNF_CTRL);
1032
+		if (mac_reg & E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE)
1033
+			goto out;
1034
+	}
1019 1035
 
1020 1036
 	mac_reg = er32(FEXTNVM);
1021 1037
 	if (!(mac_reg & E1000_FEXTNVM_SW_CONFIG_ICH8M))
@@ -2573,7 +2589,7 @@ static s32 e1000e_reset_hw_ich8lan(struct e1000_hw *hw)
2573 2589
 		}
2574 2590
 	}
2575 2591
 	/* Dummy read to clear the phy wakeup bit after lcd reset */
2576
-	if (hw->mac.type == e1000_pchlan)
2592
+	if (hw->mac.type == e1000_pchlan || hw->mac.type == e1000_pch2lan)
2577 2593
 		e1e_rphy(hw, BM_WUC, &reg);
2578 2594
 
2579 2595
 	ret_val = e1000e_sw_lcd_config_ich8lan(hw);
@@ -2791,6 +2807,7 @@ static s32 e1000e_setup_link_ich8lan(struct e1000_hw *hw)
2791 2807
 
2792 2808
 	ew32(FCTTV, hw->fc.pause_time);
2793 2809
 	if ((hw->phy.type == e1000_phy_82578) ||
2810
+	    (hw->phy.type == e1000_phy_82579) ||
2794 2811
 	    (hw->phy.type == e1000_phy_82577)) {
2795 2812
 		ret_val = e1e_wphy(hw,
2796 2813
 		                             PHY_REG(BM_PORT_CTRL_PAGE, 27),
@@ -2859,6 +2876,7 @@ static s32 e1000e_setup_copper_link_ich8lan(struct e1000_hw *hw)
2859 2876
 			goto out;
2860 2877
 		break;
2861 2878
 	case e1000_phy_82577:
2879
+	case e1000_phy_82579:
2862 2880
 		ret_val = e1000e_copper_link_setup_82577(hw);
2863 2881
 		if (ret_val)
2864 2882
 			goto out;
@@ -3388,6 +3406,7 @@ static void e1000e_clear_hw_cntrs_ich8lan(struct e1000_hw *hw __unused)
3388 3406
 
3389 3407
 	/* Clear PHY statistics registers */
3390 3408
 	if ((hw->phy.type == e1000_phy_82578) ||
3409
+	    (hw->phy.type == e1000_phy_82579) ||
3391 3410
 	    (hw->phy.type == e1000_phy_82577)) {
3392 3411
 		e1e_rphy(hw, HV_SCC_UPPER, &phy_data);
3393 3412
 		e1e_rphy(hw, HV_SCC_LOWER, &phy_data);
@@ -3434,6 +3453,8 @@ static struct pci_device_id e1000e_ich8lan_nics[] = {
3434 3453
      PCI_ROM(0x8086, 0x10EB, "E1000_DEV_ID_PCH_M_HV_LC", "E1000_DEV_ID_PCH_M_HV_LC", board_pchlan),
3435 3454
      PCI_ROM(0x8086, 0x10EF, "E1000_DEV_ID_PCH_D_HV_DM", "E1000_DEV_ID_PCH_D_HV_DM", board_pchlan),
3436 3455
      PCI_ROM(0x8086, 0x10F0, "E1000_DEV_ID_PCH_D_HV_DC", "E1000_DEV_ID_PCH_D_HV_DC", board_pchlan),
3456
+     PCI_ROM(0x8086, 0x1502, "E1000_DEV_ID_PCH2_LV_LM", "E1000_DEV_ID_PCH2_LV_LM", board_pch2lan),
3457
+     PCI_ROM(0x8086, 0x1503, "E1000_DEV_ID_PCH2_LV_V", "E1000_DEV_ID_PCH2_LV_V", board_pch2lan),
3437 3458
 };
3438 3459
 
3439 3460
 struct pci_driver e1000e_ich8lan_driver __pci_driver = {

+ 3
- 0
src/drivers/net/e1000e/e1000e_ich8lan.h View File

@@ -146,6 +146,9 @@ FILE_LICENCE ( GPL2_OR_LATER );
146 146
 #define HV_SMB_ADDR_PEC_EN     0x0200
147 147
 #define HV_SMB_ADDR_VALID      0x0080
148 148
 
149
+/* PHY Power Management Control */
150
+#define HV_PM_CTRL             PHY_REG(770, 17)
151
+
149 152
 /* Strapping Option Register - RO */
150 153
 #define E1000_STRAP                     0x0000C
151 154
 #define E1000_STRAP_SMBUS_ADDRESS_MASK  0x00FE0000

+ 17
- 0
src/drivers/net/e1000e/e1000e_main.c View File

@@ -279,6 +279,22 @@ static struct e1000_info e1000_pch_info = {
279 279
 	.get_variants		= e1000e_get_variants_ich8lan,
280 280
 };
281 281
 
282
+static struct e1000_info e1000_pch2_info = {
283
+	.mac			= e1000_pch2lan,
284
+	.flags			= FLAG_IS_ICH
285
+				  | FLAG_HAS_WOL
286
+				  | FLAG_RX_CSUM_ENABLED
287
+				  | FLAG_HAS_CTRLEXT_ON_LOAD
288
+				  | FLAG_HAS_AMT
289
+				  | FLAG_HAS_FLASH
290
+				  | FLAG_HAS_JUMBO_FRAMES
291
+				  | FLAG_APME_IN_WUC,
292
+	.pba			= 26,
293
+	.max_hw_frame_size	= DEFAULT_JUMBO,
294
+	.init_ops		= e1000e_init_function_pointers_ich8lan,
295
+	.get_variants		= e1000e_get_variants_ich8lan,
296
+};
297
+
282 298
 static const struct e1000_info *e1000_info_tbl[] = {
283 299
 	[board_82571]		= &e1000_82571_info,
284 300
 	[board_82572]		= &e1000_82572_info,
@@ -290,6 +306,7 @@ static const struct e1000_info *e1000_info_tbl[] = {
290 306
 	[board_ich9lan]		= &e1000_ich9_info,
291 307
 	[board_ich10lan]	= &e1000_ich10_info,
292 308
 	[board_pchlan]		= &e1000_pch_info,
309
+	[board_pch2lan]		= &e1000_pch2_info,
293 310
 };
294 311
 
295 312
 /* Low-level support routines */

+ 3
- 0
src/drivers/net/e1000e/e1000e_phy.c View File

@@ -2332,6 +2332,9 @@ enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
2332 2332
 	case I82577_E_PHY_ID:
2333 2333
 		phy_type = e1000_phy_82577;
2334 2334
 		break;
2335
+	case I82579_E_PHY_ID:
2336
+		phy_type = e1000_phy_82579;
2337
+		break;
2335 2338
 	default:
2336 2339
 		phy_type = e1000_phy_unknown;
2337 2340
 		break;

Loading…
Cancel
Save