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[golan] Add Connect-IB, ConnectX-4 and ConnectX-4 Lx (Infiniband) support

Signed-off-by: Wissam Shoukair <wissams@mellanox.com>
Signed-off-by: Michael Brown <mcb30@ipxe.org>
tags/v1.20.1
Wissam Shoukair 8 år sedan
förälder
incheckning
0a20373a2f
57 ändrade filer med 13097 tillägg och 0 borttagningar
  1. 8
    0
      src/Makefile
  2. 1168
    0
      src/drivers/infiniband/CIB_PRM.h
  3. 1479
    0
      src/drivers/infiniband/flexboot_nodnic.c
  4. 163
    0
      src/drivers/infiniband/flexboot_nodnic.h
  5. 2663
    0
      src/drivers/infiniband/golan.c
  6. 319
    0
      src/drivers/infiniband/golan.h
  7. 43
    0
      src/drivers/infiniband/mlx_nodnic/include/mlx_cmd.h
  8. 80
    0
      src/drivers/infiniband/mlx_nodnic/include/mlx_device.h
  9. 201
    0
      src/drivers/infiniband/mlx_nodnic/include/mlx_nodnic_data_structures.h
  10. 229
    0
      src/drivers/infiniband/mlx_nodnic/include/mlx_port.h
  11. 77
    0
      src/drivers/infiniband/mlx_nodnic/src/mlx_cmd.c
  12. 339
    0
      src/drivers/infiniband/mlx_nodnic/src/mlx_device.c
  13. 1038
    0
      src/drivers/infiniband/mlx_nodnic/src/mlx_port.c
  14. 113
    0
      src/drivers/infiniband/mlx_utils/include/private/mlx_memory_priv.h
  15. 72
    0
      src/drivers/infiniband/mlx_utils/include/private/mlx_pci_priv.h
  16. 68
    0
      src/drivers/infiniband/mlx_utils/include/private/mlx_utils_priv.h
  17. 47
    0
      src/drivers/infiniband/mlx_utils/include/public/mlx_bail.h
  18. 63
    0
      src/drivers/infiniband/mlx_utils/include/public/mlx_icmd.h
  19. 46
    0
      src/drivers/infiniband/mlx_utils/include/public/mlx_logging.h
  20. 115
    0
      src/drivers/infiniband/mlx_utils/include/public/mlx_memory.h
  21. 78
    0
      src/drivers/infiniband/mlx_utils/include/public/mlx_pci.h
  22. 81
    0
      src/drivers/infiniband/mlx_utils/include/public/mlx_pci_gw.h
  23. 27
    0
      src/drivers/infiniband/mlx_utils/include/public/mlx_types.h
  24. 106
    0
      src/drivers/infiniband/mlx_utils/include/public/mlx_utils.h
  25. 54
    0
      src/drivers/infiniband/mlx_utils/mlx_lib/mlx_blink_leds/mlx_blink_leds.c
  26. 46
    0
      src/drivers/infiniband/mlx_utils/mlx_lib/mlx_blink_leds/mlx_blink_leds.h
  27. 180
    0
      src/drivers/infiniband/mlx_utils/mlx_lib/mlx_link_speed/mlx_link_speed.c
  28. 145
    0
      src/drivers/infiniband/mlx_utils/mlx_lib/mlx_link_speed/mlx_link_speed.h
  29. 60
    0
      src/drivers/infiniband/mlx_utils/mlx_lib/mlx_mtu/mlx_mtu.c
  30. 52
    0
      src/drivers/infiniband/mlx_utils/mlx_lib/mlx_mtu/mlx_mtu.h
  31. 295
    0
      src/drivers/infiniband/mlx_utils/mlx_lib/mlx_nvconfig/mlx_nvconfig.c
  32. 140
    0
      src/drivers/infiniband/mlx_utils/mlx_lib/mlx_nvconfig/mlx_nvconfig.h
  33. 482
    0
      src/drivers/infiniband/mlx_utils/mlx_lib/mlx_nvconfig/mlx_nvconfig_defaults.c
  34. 94
    0
      src/drivers/infiniband/mlx_utils/mlx_lib/mlx_nvconfig/mlx_nvconfig_defaults.h
  35. 259
    0
      src/drivers/infiniband/mlx_utils/mlx_lib/mlx_nvconfig/mlx_nvconfig_prm.h
  36. 145
    0
      src/drivers/infiniband/mlx_utils/mlx_lib/mlx_ocbb/mlx_ocbb.c
  37. 73
    0
      src/drivers/infiniband/mlx_utils/mlx_lib/mlx_ocbb/mlx_ocbb.h
  38. 90
    0
      src/drivers/infiniband/mlx_utils/mlx_lib/mlx_reg_access/mlx_reg_access.c
  39. 82
    0
      src/drivers/infiniband/mlx_utils/mlx_lib/mlx_reg_access/mlx_reg_access.h
  40. 74
    0
      src/drivers/infiniband/mlx_utils/mlx_lib/mlx_vmac/mlx_vmac.c
  41. 60
    0
      src/drivers/infiniband/mlx_utils/mlx_lib/mlx_vmac/mlx_vmac.h
  42. 84
    0
      src/drivers/infiniband/mlx_utils/mlx_lib/mlx_wol_rol/mlx_wol_rol.c
  43. 61
    0
      src/drivers/infiniband/mlx_utils/mlx_lib/mlx_wol_rol/mlx_wol_rol.h
  44. 9
    0
      src/drivers/infiniband/mlx_utils/src/private/uefi/mlx_logging_impl.c
  45. 371
    0
      src/drivers/infiniband/mlx_utils/src/public/mlx_icmd.c
  46. 238
    0
      src/drivers/infiniband/mlx_utils/src/public/mlx_memory.c
  47. 117
    0
      src/drivers/infiniband/mlx_utils/src/public/mlx_pci.c
  48. 392
    0
      src/drivers/infiniband/mlx_utils/src/public/mlx_pci_gw.c
  49. 121
    0
      src/drivers/infiniband/mlx_utils/src/public/mlx_utils.c
  50. 61
    0
      src/drivers/infiniband/mlx_utils_flexboot/include/mlx_logging_priv.h
  51. 60
    0
      src/drivers/infiniband/mlx_utils_flexboot/include/mlx_types_priv.h
  52. 172
    0
      src/drivers/infiniband/mlx_utils_flexboot/src/mlx_memory_priv.c
  53. 182
    0
      src/drivers/infiniband/mlx_utils_flexboot/src/mlx_pci_priv.c
  54. 83
    0
      src/drivers/infiniband/mlx_utils_flexboot/src/mlx_utils_priv.c
  55. 47
    0
      src/drivers/infiniband/nodnic_prm.h
  56. 143
    0
      src/drivers/infiniband/nodnic_shomron_prm.h
  57. 2
    0
      src/include/ipxe/errfile.h

+ 8
- 0
src/Makefile Visa fil

@@ -84,6 +84,14 @@ SRCDIRS		+= drivers/block
84 84
 SRCDIRS		+= drivers/nvs
85 85
 SRCDIRS		+= drivers/bitbash
86 86
 SRCDIRS		+= drivers/infiniband
87
+SRCDIRS		+= drivers/infiniband/mlx_utils_flexboot/src
88
+SRCDIRS		+= drivers/infiniband/mlx_utils/src/public
89
+SRCDIRS		+= drivers/infiniband/mlx_utils/mlx_lib/mlx_reg_access
90
+SRCDIRS		+= drivers/infiniband/mlx_utils/mlx_lib/mlx_nvconfig
91
+SRCDIRS		+= drivers/infiniband/mlx_utils/mlx_lib/mlx_vmac
92
+SRCDIRS		+= drivers/infiniband/mlx_utils/mlx_lib/mlx_blink_leds
93
+SRCDIRS		+= drivers/infiniband/mlx_utils/mlx_lib/mlx_link_speed
94
+SRCDIRS		+= drivers/infiniband/mlx_nodnic/src
87 95
 SRCDIRS		+= drivers/usb
88 96
 SRCDIRS		+= interface/pxe interface/efi interface/smbios
89 97
 SRCDIRS		+= interface/bofm

+ 1168
- 0
src/drivers/infiniband/CIB_PRM.h
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+ 1479
- 0
src/drivers/infiniband/flexboot_nodnic.c
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+ 163
- 0
src/drivers/infiniband/flexboot_nodnic.h Visa fil

@@ -0,0 +1,163 @@
1
+#ifndef SRC_DRIVERS_INFINIBAND_FLEXBOOT_NODNIC_FLEXBOOT_NODNIC_H_
2
+#define SRC_DRIVERS_INFINIBAND_FLEXBOOT_NODNIC_FLEXBOOT_NODNIC_H_
3
+
4
+/*
5
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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+ * 02110-1301, USA.
21
+ */
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+
25
+#include "mlx_nodnic/include/mlx_nodnic_data_structures.h"
26
+#include "nodnic_prm.h"
27
+#include <ipxe/io.h>
28
+#include <ipxe/infiniband.h>
29
+#include <ipxe/netdevice.h>
30
+
31
+/*
32
+ * If defined, use interrupts in NODNIC driver
33
+ */
34
+#define NODNIC_IRQ_ENABLED
35
+
36
+#define FLEXBOOT_NODNIC_MAX_PORTS		2
37
+#define FLEXBOOT_NODNIC_PORT_BASE		1
38
+
39
+#define FLEXBOOT_NODNIC_OPCODE_SEND		0xa
40
+
41
+/* Port protocol */
42
+enum flexboot_nodnic_protocol {
43
+	FLEXBOOT_NODNIC_PROT_IB_IPV6 = 0,
44
+	FLEXBOOT_NODNIC_PROT_ETH,
45
+	FLEXBOOT_NODNIC_PROT_IB_IPV4,
46
+	FLEXBOOT_NODNIC_PROT_FCOE
47
+};
48
+
49
+/** A flexboot nodnic port */
50
+struct flexboot_nodnic_port {
51
+	/** Infiniband device */
52
+	struct ib_device *ibdev;
53
+	/** Network device */
54
+	struct net_device *netdev;
55
+	/** nodic port */
56
+	nodnic_port_priv port_priv;
57
+	/** Port type */
58
+	struct flexboot_nodnic_port_type *type;
59
+	/** Ethernet completion queue */
60
+	struct ib_completion_queue *eth_cq;
61
+	/** Ethernet queue pair */
62
+	struct ib_queue_pair *eth_qp;
63
+};
64
+
65
+
66
+/** A flexboot nodnic queue pair */
67
+struct flexboot_nodnic_queue_pair {
68
+	nodnic_qp *nodnic_queue_pair;
69
+};
70
+
71
+/** A flexboot nodnic cq */
72
+struct flexboot_nodnic_completion_queue {
73
+	nodnic_cq *nodnic_completion_queue;
74
+};
75
+
76
+/** A flexboot_nodnic device */
77
+struct flexboot_nodnic {
78
+	/** PCI device */
79
+	struct pci_device *pci;
80
+	/** nic specific data*/
81
+	struct flexboot_nodnic_callbacks *callbacks;
82
+	/**nodnic device*/
83
+	nodnic_device_priv device_priv;
84
+	/**flexboot_nodnic ports*/
85
+	struct flexboot_nodnic_port port[FLEXBOOT_NODNIC_MAX_PORTS];
86
+	/** Device open request counter */
87
+	unsigned int open_count;
88
+	/** Port masking  */
89
+	u16 port_mask;
90
+	/** device private data */
91
+	void *priv_data;
92
+};
93
+
94
+/** A flexboot_nodnic port type */
95
+struct flexboot_nodnic_port_type {
96
+	/** Register port
97
+	 *
98
+	 * @v flexboot_nodnic		flexboot_nodnic device
99
+	 * @v port		flexboot_nodnic port
100
+	 * @ret mlx_status		Return status code
101
+	 */
102
+	mlx_status ( * register_dev ) (
103
+			struct flexboot_nodnic *flexboot_nodnic,
104
+			struct flexboot_nodnic_port *port
105
+			);
106
+	/** Port state changed
107
+	 *
108
+	 * @v flexboot_nodnic		flexboot_nodnic device
109
+	 * @v port		flexboot_nodnic port
110
+	 * @v link_up		Link is up
111
+	 */
112
+	void ( * state_change ) (
113
+			struct flexboot_nodnic *flexboot_nodnic,
114
+				  struct flexboot_nodnic_port *port,
115
+				  int link_up
116
+				  );
117
+	/** Unregister port
118
+	 *
119
+	 * @v flexboot_nodnic		flexboot_nodnic device
120
+	 * @v port		flexboot_nodnic port
121
+	 */
122
+	void ( * unregister_dev ) (
123
+			struct flexboot_nodnic *flexboot_nodnic,
124
+			struct flexboot_nodnic_port *port
125
+			);
126
+};
127
+
128
+struct cqe_data{
129
+	mlx_boolean owner;
130
+	mlx_uint32 qpn;
131
+	mlx_uint32 is_send;
132
+	mlx_uint32 is_error;
133
+	mlx_uint32 syndrome;
134
+	mlx_uint32 vendor_err_syndrome;
135
+	mlx_uint32 wqe_counter;
136
+	mlx_uint32 byte_cnt;
137
+};
138
+
139
+struct flexboot_nodnic_callbacks {
140
+	mlx_status ( * fill_completion ) ( void *cqe, struct cqe_data *cqe_data );
141
+	mlx_status ( * cqe_set_owner ) ( void *cq, unsigned int num_cqes );
142
+	mlx_size ( * get_cqe_size ) ();
143
+	mlx_status ( * fill_send_wqe[5] ) (
144
+				struct ib_device *ibdev,
145
+				struct ib_queue_pair *qp,
146
+				struct ib_address_vector *av,
147
+				struct io_buffer *iobuf,
148
+				struct nodnic_send_wqbb *wqbb,
149
+				unsigned long wqe_idx
150
+				);
151
+	void ( * irq ) ( struct net_device *netdev, int enable );
152
+};
153
+
154
+int flexboot_nodnic_probe ( struct pci_device *pci,
155
+		struct flexboot_nodnic_callbacks *callbacks,
156
+		void *drv_priv );
157
+void flexboot_nodnic_remove ( struct pci_device *pci );
158
+void flexboot_nodnic_eth_irq ( struct net_device *netdev, int enable );
159
+int flexboot_nodnic_is_supported ( struct pci_device *pci );
160
+void flexboot_nodnic_copy_mac ( uint8_t mac_addr[], uint32_t low_byte,
161
+		uint16_t high_byte );
162
+
163
+#endif /* SRC_DRIVERS_INFINIBAND_FLEXBOOT_NODNIC_FLEXBOOT_NODNIC_H_ */

+ 2663
- 0
src/drivers/infiniband/golan.c
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+ 319
- 0
src/drivers/infiniband/golan.h Visa fil

@@ -0,0 +1,319 @@
1
+#ifndef _GOLAN_H_
2
+#define _GOLAN_H_
3
+
4
+/*
5
+ * Copyright (C) 2013-2015 Mellanox Technologies Ltd.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20
+ * 02110-1301, USA.
21
+ */
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+
25
+#include <byteswap.h>
26
+#include <errno.h>
27
+#include <stdio.h>
28
+#include <unistd.h>
29
+#include <ipxe/io.h>
30
+#include <ipxe/pci.h>
31
+#include <ipxe/pcibackup.h>
32
+#include "CIB_PRM.h"
33
+
34
+#define GOLAN_PCI_CONFIG_BAR_SIZE	0x100000//HERMON_PCI_CONFIG_BAR_SIZE //TODO: What is the BAR size?
35
+
36
+#define GOLAN_PAS_SIZE	sizeof(uint64_t)
37
+
38
+#define GOLAN_INVALID_LKEY 0x00000100UL
39
+
40
+#define GOLAN_MAX_PORTS	2
41
+#define GOLAN_PORT_BASE 1
42
+
43
+#define MELLANOX_VID	0x15b3
44
+#define GOLAN_HCA_BAR	PCI_BASE_ADDRESS_0	//BAR 0
45
+
46
+#define GOLAN_HCR_MAX_WAIT_MS	10000
47
+
48
+#define min(a,b) ((a)<(b)?(a):(b))
49
+
50
+#define GOLAN_PAGE_SHIFT	12
51
+#define	GOLAN_PAGE_SIZE		(1 << GOLAN_PAGE_SHIFT)
52
+#define GOLAN_PAGE_MASK		(GOLAN_PAGE_SIZE - 1)
53
+
54
+#define MAX_MBOX	( GOLAN_PAGE_SIZE / MAILBOX_STRIDE )
55
+#define DEF_CMD_IDX	1
56
+#define MEM_CMD_IDX	0
57
+#define NO_MBOX		0xffff
58
+#define MEM_MBOX	MEM_CMD_IDX
59
+#define GEN_MBOX	DEF_CMD_IDX
60
+
61
+#define CMD_IF_REV	4
62
+
63
+#define MAX_PASE_MBOX	((GOLAN_CMD_PAS_CNT) - 2)
64
+
65
+#define CMD_STATUS( golan , idx )		((struct golan_outbox_hdr *)(get_cmd( (golan) , (idx) )->out))->status
66
+#define CMD_SYND( golan , idx )		((struct golan_outbox_hdr *)(get_cmd( (golan) , (idx) )->out))->syndrome
67
+#define QRY_PAGES_OUT( golan, idx )		((struct golan_query_pages_outbox *)(get_cmd( (golan) , (idx) )->out))
68
+
69
+#define VIRT_2_BE64_BUS( addr )		cpu_to_be64(((unsigned long long )virt_to_bus(addr)))
70
+#define BE64_BUS_2_VIRT( addr )		bus_to_virt(be64_to_cpu(addr))
71
+#define USR_2_BE64_BUS( addr )		cpu_to_be64(((unsigned long long )user_to_phys(addr, 0)))
72
+#define BE64_BUS_2_USR( addr )		be64_to_cpu(phys_to_user(addr))
73
+
74
+#define GET_INBOX(golan, idx)		(&(((struct mbox *)(golan->mboxes.inbox))[idx]))
75
+#define GET_OUTBOX(golan, idx)		(&(((struct mbox *)(golan->mboxes.outbox))[idx]))
76
+
77
+#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
78
+
79
+/* Fw status fields */
80
+typedef enum {
81
+	NO_ERRORS          = 0x0,
82
+	SIGNATURE_ERROR    = 0x1,
83
+	TOKEN_ERROR        = 0x2,
84
+	BAD_BLOCK_NUMBER   = 0x3,
85
+	BAD_OUTPUT_POINTER = 0x4,   // pointer not align to mailbox size
86
+	BAD_INPUT_POINTER  = 0x5,   // pointer not align to mailbox size
87
+	INTERNAL_ERROR     = 0x6,
88
+	INPUT_LEN_ERROR    = 0x7,   // input  length less than 0x8.
89
+	OUTPUT_LEN_ERROR   = 0x8,   // output length less than 0x8.
90
+	RESERVE_NOT_ZERO   = 0x9,
91
+	BAD_CMD_TYPE       = 0x10,
92
+} return_hdr_t;
93
+
94
+struct golan_cmdq_md {
95
+	void	*addr;
96
+	u16	log_stride;
97
+	u16	size;
98
+};
99
+
100
+struct golan_uar {
101
+    uint32_t    	index;
102
+    void        	*virt;
103
+    unsigned long	phys;
104
+};
105
+
106
+/* Queue Pair */
107
+#define GOLAN_SEND_WQE_BB_SIZE			64
108
+#define GOLAN_SEND_UD_WQE_SIZE			sizeof(struct golan_send_wqe_ud)
109
+#define GOLAN_RECV_WQE_SIZE				sizeof(struct golan_recv_wqe_ud)
110
+#define GOLAN_WQEBBS_PER_SEND_UD_WQE	DIV_ROUND_UP(GOLAN_SEND_UD_WQE_SIZE, GOLAN_SEND_WQE_BB_SIZE)
111
+#define GOLAN_SEND_OPCODE			0x0a
112
+#define GOLAN_WQE_CTRL_WQE_IDX_BIT	8
113
+
114
+enum golan_ib_qp_state {
115
+	GOLAN_IB_QPS_RESET,
116
+	GOLAN_IB_QPS_INIT,
117
+	GOLAN_IB_QPS_RTR,
118
+	GOLAN_IB_QPS_RTS,
119
+	GOLAN_IB_QPS_SQD,
120
+	GOLAN_IB_QPS_SQE,
121
+	GOLAN_IB_QPS_ERR
122
+};
123
+
124
+struct golan_send_wqe_ud {
125
+	struct golan_wqe_ctrl_seg ctrl;
126
+	struct golan_av datagram;
127
+	struct golan_wqe_data_seg data;
128
+};
129
+
130
+union golan_send_wqe {
131
+	struct golan_send_wqe_ud ud;
132
+	uint8_t pad[GOLAN_WQEBBS_PER_SEND_UD_WQE * GOLAN_SEND_WQE_BB_SIZE];
133
+};
134
+
135
+struct golan_recv_wqe_ud {
136
+	struct golan_wqe_data_seg data[2];
137
+};
138
+
139
+struct golan_recv_wq {
140
+	struct golan_recv_wqe_ud *wqes;
141
+	/* WQ size in bytes */
142
+	int	size;
143
+	/* In SQ, it will be increased in wqe_size (number of WQEBBs per WQE) */
144
+	u16 next_idx;
145
+	/** GRH buffers (if applicable) */
146
+	struct ib_global_route_header *grh;
147
+	/** Size of GRH buffers */
148
+	size_t grh_size;
149
+};
150
+
151
+struct golan_send_wq {
152
+	union golan_send_wqe *wqes;
153
+	/* WQ size in bytes */
154
+	int size;
155
+	/* In SQ, it will be increased in wqe_size (number of WQEBBs per WQE) */
156
+	u16 next_idx;
157
+};
158
+
159
+struct golan_queue_pair {
160
+	void *wqes;
161
+	int size;
162
+	struct golan_recv_wq rq;
163
+	struct golan_send_wq sq;
164
+	struct golan_qp_db *doorbell_record;
165
+	u32 doorbell_qpn;
166
+	enum golan_ib_qp_state state;
167
+};
168
+
169
+/* Completion Queue */
170
+#define GOLAN_CQE_OPCODE_NOT_VALID	0x0f
171
+#define GOLAN_CQE_OPCODE_BIT		4
172
+#define GOLAN_CQ_DB_RECORD_SIZE		sizeof(uint64_t)
173
+#define GOLAN_CQE_OWNER_MASK		1
174
+
175
+#define MANAGE_PAGES_PSA_OFFSET		0
176
+#define PXE_CMDIF_REF			5
177
+
178
+enum {
179
+	GOLAN_CQE_SW_OWNERSHIP = 0x0,
180
+	GOLAN_CQE_HW_OWNERSHIP = 0x1
181
+};
182
+
183
+enum {
184
+	GOLAN_CQE_SIZE_64	= 0,
185
+	GOLAN_CQE_SIZE_128	= 1
186
+};
187
+
188
+struct golan_completion_queue {
189
+	struct golan_cqe64	*cqes;
190
+	int					size;
191
+	__be64		*doorbell_record;
192
+};
193
+
194
+
195
+/* Event Queue */
196
+#define GOLAN_EQE_SIZE				sizeof(struct golan_eqe)
197
+#define GOLAN_NUM_EQES 				8
198
+#define GOLAN_EQ_DOORBELL_OFFSET		0x40
199
+
200
+#define GOLAN_EQ_MAP_ALL_EVENTS					\
201
+	((1 << GOLAN_EVENT_TYPE_PATH_MIG         	)|	\
202
+	(1 << GOLAN_EVENT_TYPE_COMM_EST          	)|	\
203
+	(1 << GOLAN_EVENT_TYPE_SQ_DRAINED        	)|	\
204
+	(1 << GOLAN_EVENT_TYPE_SRQ_LAST_WQE		)|	\
205
+	(1 << GOLAN_EVENT_TYPE_SRQ_RQ_LIMIT      	)|	\
206
+	(1 << GOLAN_EVENT_TYPE_CQ_ERROR          	)|	\
207
+	(1 << GOLAN_EVENT_TYPE_WQ_CATAS_ERROR    	)|	\
208
+	(1 << GOLAN_EVENT_TYPE_PATH_MIG_FAILED   	)|	\
209
+	(1 << GOLAN_EVENT_TYPE_WQ_INVAL_REQ_ERROR	)|	\
210
+	(1 << GOLAN_EVENT_TYPE_WQ_ACCESS_ERROR	 	)|	\
211
+	(1 << GOLAN_EVENT_TYPE_SRQ_CATAS_ERROR   	)|	\
212
+	(1 << GOLAN_EVENT_TYPE_INTERNAL_ERROR  	 	)|	\
213
+	(1 << GOLAN_EVENT_TYPE_PORT_CHANGE   	  	)|	\
214
+	(1 << GOLAN_EVENT_TYPE_GPIO_EVENT         	)|	\
215
+	(1 << GOLAN_EVENT_TYPE_CLIENT_RE_REGISTER 	)|	\
216
+	(1 << GOLAN_EVENT_TYPE_REMOTE_CONFIG     	)|	\
217
+	(1 << GOLAN_EVENT_TYPE_DB_BF_CONGESTION   	)|	\
218
+	(1 << GOLAN_EVENT_TYPE_STALL_EVENT        	)|	\
219
+	(1 << GOLAN_EVENT_TYPE_PACKET_DROPPED     	)|	\
220
+	(1 << GOLAN_EVENT_TYPE_CMD             	  	)|	\
221
+	(1 << GOLAN_EVENT_TYPE_PAGE_REQUEST       	))
222
+
223
+enum golan_event {
224
+	GOLAN_EVENT_TYPE_COMP			= 0x0,
225
+
226
+	GOLAN_EVENT_TYPE_PATH_MIG		= 0x01,
227
+	GOLAN_EVENT_TYPE_COMM_EST		= 0x02,
228
+	GOLAN_EVENT_TYPE_SQ_DRAINED		= 0x03,
229
+	GOLAN_EVENT_TYPE_SRQ_LAST_WQE		= 0x13,
230
+	GOLAN_EVENT_TYPE_SRQ_RQ_LIMIT		= 0x14,
231
+
232
+	GOLAN_EVENT_TYPE_CQ_ERROR		= 0x04,
233
+	GOLAN_EVENT_TYPE_WQ_CATAS_ERROR		= 0x05,
234
+	GOLAN_EVENT_TYPE_PATH_MIG_FAILED	= 0x07,
235
+	GOLAN_EVENT_TYPE_WQ_INVAL_REQ_ERROR	= 0x10,
236
+	GOLAN_EVENT_TYPE_WQ_ACCESS_ERROR	= 0x11,
237
+	GOLAN_EVENT_TYPE_SRQ_CATAS_ERROR	= 0x12,
238
+
239
+	GOLAN_EVENT_TYPE_INTERNAL_ERROR		= 0x08,
240
+	GOLAN_EVENT_TYPE_PORT_CHANGE		= 0x09,
241
+	GOLAN_EVENT_TYPE_GPIO_EVENT		= 0x15,
242
+//	GOLAN_EVENT_TYPE_CLIENT_RE_REGISTER	= 0x16,
243
+	GOLAN_EVENT_TYPE_REMOTE_CONFIG		= 0x19,
244
+
245
+	GOLAN_EVENT_TYPE_DB_BF_CONGESTION	= 0x1a,
246
+	GOLAN_EVENT_TYPE_STALL_EVENT		= 0x1b,
247
+
248
+	GOLAN_EVENT_TYPE_PACKET_DROPPED		= 0x1f,
249
+
250
+	GOLAN_EVENT_TYPE_CMD			= 0x0a,
251
+	GOLAN_EVENT_TYPE_PAGE_REQUEST		= 0x0b,
252
+	GOLAN_EVENT_TYPE_PAGE_FAULT		= 0x0C,
253
+};
254
+
255
+enum golan_port_sub_event {
256
+    GOLAN_PORT_CHANGE_SUBTYPE_DOWN		= 1,
257
+    GOLAN_PORT_CHANGE_SUBTYPE_ACTIVE		= 4,
258
+    GOLAN_PORT_CHANGE_SUBTYPE_INITIALIZED	= 5,
259
+    GOLAN_PORT_CHANGE_SUBTYPE_LID		= 6,
260
+    GOLAN_PORT_CHANGE_SUBTYPE_PKEY		= 7,
261
+    GOLAN_PORT_CHANGE_SUBTYPE_GUID		= 8,
262
+    GOLAN_PORT_CHANGE_SUBTYPE_CLIENT_REREG	= 9
263
+};
264
+
265
+
266
+enum {
267
+	GOLAN_EQE_SW_OWNERSHIP = 0x0,
268
+	GOLAN_EQE_HW_OWNERSHIP = 0x1
269
+};
270
+
271
+enum {
272
+	GOLAN_EQ_UNARMED	= 0,
273
+	GOLAN_EQ_ARMED		= 1,
274
+};
275
+
276
+struct golan_event_queue {
277
+	uint8_t			eqn;
278
+	uint64_t		mask;
279
+	struct golan_eqe	*eqes;
280
+	int			size;
281
+	__be32			*doorbell;
282
+	uint32_t		cons_index;
283
+};
284
+
285
+struct golan_port {
286
+	/** Infiniband device */
287
+	struct ib_device	*ibdev;
288
+	/** Network device */
289
+	struct net_device	*netdev;
290
+	/** VEP number */
291
+	u8 vep_number;
292
+};
293
+
294
+struct golan_mboxes {
295
+	void 	*inbox;
296
+	void	*outbox;
297
+};
298
+
299
+#define GOLAN_OPEN	0x1
300
+
301
+struct golan {
302
+	struct pci_device		*pci;
303
+	struct golan_hca_init_seg	*iseg;
304
+	struct golan_cmdq_md		cmd;
305
+	struct golan_hca_cap		caps; /* stored as big indian*/
306
+	struct golan_mboxes		mboxes;
307
+	struct list_head		pages;
308
+	uint32_t			cmd_bm;
309
+	uint32_t			total_dma_pages;
310
+	struct golan_uar		uar;
311
+	struct golan_event_queue 	eq;
312
+	uint32_t			pdn;
313
+	u32				mkey;
314
+	u32				flags;
315
+
316
+	struct golan_port		ports[GOLAN_MAX_PORTS];
317
+};
318
+
319
+#endif /* _GOLAN_H_*/

+ 43
- 0
src/drivers/infiniband/mlx_nodnic/include/mlx_cmd.h Visa fil

@@ -0,0 +1,43 @@
1
+#ifndef NODNIC_CMD_H_
2
+#define NODNIC_CMD_H_
3
+
4
+/*
5
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20
+ * 02110-1301, USA.
21
+ */
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+
25
+#include "mlx_nodnic_data_structures.h"
26
+#include "../../mlx_utils/include/public/mlx_utils.h"
27
+#include "../../mlx_utils/include/public/mlx_pci_gw.h"
28
+
29
+mlx_status
30
+nodnic_cmd_read(
31
+				IN nodnic_device_priv *device_priv,
32
+				IN mlx_uint32 address,
33
+				OUT mlx_pci_gw_buffer *buffer
34
+				);
35
+
36
+mlx_status
37
+nodnic_cmd_write(
38
+				IN nodnic_device_priv *device_priv,
39
+				IN mlx_uint32 address,
40
+				IN mlx_pci_gw_buffer buffer
41
+				);
42
+
43
+#endif /* STUB_NODNIC_CMD_H_ */

+ 80
- 0
src/drivers/infiniband/mlx_nodnic/include/mlx_device.h Visa fil

@@ -0,0 +1,80 @@
1
+#ifndef NODNIC_DEVICE_H_
2
+#define NODNIC_DEVICE_H_
3
+
4
+/*
5
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20
+ * 02110-1301, USA.
21
+ */
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+
25
+#include "mlx_nodnic_data_structures.h"
26
+
27
+#define NODIC_SUPPORTED_REVISION 1
28
+//Initialization segment
29
+#define NODNIC_CMDQ_PHY_ADDR_HIGH_OFFSET 0x10
30
+#define NODNIC_CMDQ_PHY_ADDR_LOW_OFFSET 0x14
31
+#define NODNIC_NIC_INTERFACE_OFFSET 0x14
32
+#define NODNIC_INITIALIZING_OFFSET 0x1fc
33
+#define NODNIC_NIC_INTERFACE_SUPPORTED_OFFSET 0x1fc
34
+#define NODNIC_LOCATION_OFFSET 0x240
35
+
36
+#define NODNIC_CMDQ_PHY_ADDR_LOW_MASK 0xFFFFE000
37
+#define NODNIC_NIC_INTERFACE_SUPPORTED_MASK 0x4000000
38
+
39
+#define NODNIC_NIC_INTERFACE_BIT 9
40
+#define NODNIC_DISABLE_INTERFACE_BIT 8
41
+#define NODNIC_NIC_INTERFACE_SUPPORTED_BIT 26
42
+#define NODNIC_INITIALIZING_BIT 31
43
+
44
+#define NODNIC_NIC_DISABLE_INT_OFFSET	0x100c
45
+
46
+//nodnic segment
47
+#define NODNIC_REVISION_OFFSET 0x0
48
+#define NODNIC_HARDWARE_FORMAT_OFFSET 0x0
49
+
50
+
51
+
52
+mlx_status
53
+nodnic_device_init(
54
+				IN nodnic_device_priv *device_priv
55
+				);
56
+
57
+mlx_status
58
+nodnic_device_teardown(
59
+				IN nodnic_device_priv *device_priv
60
+				);
61
+
62
+
63
+mlx_status
64
+nodnic_device_get_cap(
65
+				IN nodnic_device_priv *device_priv
66
+				);
67
+
68
+mlx_status
69
+nodnic_device_clear_int (
70
+				IN nodnic_device_priv *device_priv
71
+				);
72
+
73
+mlx_status
74
+nodnic_device_get_fw_version(
75
+				IN nodnic_device_priv *device_priv,
76
+				OUT mlx_uint16		*fw_ver_minor,
77
+				OUT mlx_uint16  	*fw_ver_sub_minor,
78
+				OUT mlx_uint16  	*fw_ver_major
79
+				);
80
+#endif /* STUB_NODNIC_DEVICE_H_ */

+ 201
- 0
src/drivers/infiniband/mlx_nodnic/include/mlx_nodnic_data_structures.h Visa fil

@@ -0,0 +1,201 @@
1
+#ifndef NODNIC_NODNICDATASTRUCTURES_H_
2
+#define NODNIC_NODNICDATASTRUCTURES_H_
3
+
4
+/*
5
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20
+ * 02110-1301, USA.
21
+ */
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+
25
+#include "../../mlx_utils/include/public/mlx_utils.h"
26
+
27
+/* todo: fix coding convention */
28
+#define NODNIC_MEMORY_ALIGN		0x1000
29
+
30
+#define NODNIC_MAX_MAC_FILTERS 5
31
+#define NODNIC_MAX_MGID_FILTERS 4
32
+
33
+typedef struct _nodnic_device_priv 				nodnic_device_priv;
34
+typedef struct _nodnic_port_priv 				nodnic_port_priv;
35
+typedef struct _nodnic_device_capabilites 		nodnic_device_capabilites;
36
+typedef struct _nodnic_qp 						nodnic_qp;
37
+typedef struct _nodnic_cq 						nodnic_cq;
38
+typedef struct _nodnic_eq						nodnic_eq;
39
+
40
+/* NODNIC Port states
41
+ * Bit 0 - port open/close
42
+ * Bit 1 - port is [not] in disabling DMA
43
+ * 0 - closed and not disabling DMA
44
+ * 1 - opened and not disabling DMA
45
+ * 3 - opened and disabling DMA
46
+ */
47
+#define NODNIC_PORT_OPENED			0b00000001
48
+#define NODNIC_PORT_DISABLING_DMA	0b00000010
49
+
50
+typedef enum {
51
+	ConnectX3 = 0,
52
+	Connectx4
53
+}nodnic_hardware_format;
54
+
55
+
56
+typedef enum {
57
+	NODNIC_QPT_SMI,
58
+	NODNIC_QPT_GSI,
59
+	NODNIC_QPT_UD,
60
+	NODNIC_QPT_RC,
61
+	NODNIC_QPT_ETH,
62
+}nodnic_queue_pair_type;
63
+typedef enum {
64
+	NODNIC_PORT_TYPE_IB = 0,
65
+	NODNIC_PORT_TYPE_ETH,
66
+	NODNIC_PORT_TYPE_UNKNOWN,
67
+}nodnic_port_type;
68
+
69
+
70
+#define RECV_WQE_SIZE 16
71
+#define NODNIC_WQBB_SIZE 64
72
+/** A nodnic send wqbb */
73
+struct nodnic_send_wqbb {
74
+	mlx_uint8 force_align[NODNIC_WQBB_SIZE];
75
+};
76
+struct nodnic_ring {
77
+	mlx_uint32 offset;
78
+	/** Work queue entries */
79
+	/* TODO: add to memory entity */
80
+	mlx_physical_address wqe_physical;
81
+	mlx_void *map;
82
+	/** Size of work queue */
83
+	mlx_size wq_size;
84
+	/** Next work queue entry index
85
+	 *
86
+	 * This is the index of the next entry to be filled (i.e. the
87
+	 * first empty entry).  This value is not bounded by num_wqes;
88
+	 * users must logical-AND with (num_wqes-1) to generate an
89
+	 * array index.
90
+	 */
91
+	mlx_uint32 num_wqes;
92
+	mlx_uint32 qpn;
93
+	mlx_uint32 next_idx;
94
+	mlx_uint32	ring_pi;
95
+};
96
+
97
+struct nodnic_send_ring{
98
+	struct nodnic_ring nodnic_ring;
99
+	struct nodnic_send_wqbb *wqe_virt;
100
+};
101
+
102
+
103
+struct nodnic_recv_ring{
104
+	struct nodnic_ring nodnic_ring;
105
+	void *wqe_virt;
106
+};
107
+struct _nodnic_qp{
108
+	nodnic_queue_pair_type	type;
109
+	struct nodnic_send_ring		send;
110
+	struct nodnic_recv_ring		receive;
111
+};
112
+
113
+struct _nodnic_cq{
114
+	/** cq entries */
115
+	mlx_void *cq_virt;
116
+	mlx_physical_address cq_physical;
117
+	mlx_void *map;
118
+	/** cq */
119
+	mlx_size cq_size;
120
+};
121
+
122
+struct _nodnic_eq{
123
+	mlx_void *eq_virt;
124
+	mlx_physical_address eq_physical;
125
+	mlx_void *map;
126
+	mlx_size eq_size;
127
+};
128
+struct _nodnic_device_capabilites{
129
+	mlx_boolean					support_mac_filters;
130
+	mlx_boolean					support_promisc_filter;
131
+	mlx_boolean					support_promisc_multicast_filter;
132
+	mlx_uint8					log_working_buffer_size;
133
+	mlx_uint8					log_pkey_table_size;
134
+	mlx_boolean					num_ports; // 0 - single port, 1 - dual port
135
+	mlx_uint8					log_max_ring_size;
136
+#ifdef DEVICE_CX3
137
+	mlx_uint8					crspace_doorbells;
138
+#endif
139
+};
140
+
141
+#ifdef DEVICE_CX3
142
+/* This is the structure of the data in the scratchpad
143
+ * Read/Write data from/to its field using PCI accesses only */
144
+typedef struct _nodnic_port_data_flow_gw nodnic_port_data_flow_gw;
145
+struct _nodnic_port_data_flow_gw {
146
+	mlx_uint32	send_doorbell;
147
+	mlx_uint32	recv_doorbell;
148
+	mlx_uint32	reserved2[2];
149
+	mlx_uint32	armcq_cq_ci_dword;
150
+	mlx_uint32	dma_en;
151
+} __attribute__ ((packed));
152
+#endif
153
+
154
+struct _nodnic_device_priv{
155
+	mlx_boolean					is_initiailzied;
156
+	mlx_utils					*utils;
157
+
158
+	//nodnic structure offset in init segment
159
+	mlx_uint32					device_offset;
160
+
161
+	nodnic_device_capabilites	device_cap;
162
+
163
+	mlx_uint8					nodnic_revision;
164
+	nodnic_hardware_format		hardware_format;
165
+	mlx_uint32					pd;
166
+	mlx_uint32					lkey;
167
+	mlx_uint64					device_guid;
168
+	nodnic_port_priv			*ports;
169
+#ifdef DEVICE_CX3
170
+	mlx_void					*crspace_clear_int;
171
+#endif
172
+};
173
+
174
+struct _nodnic_port_priv{
175
+	nodnic_device_priv		*device;
176
+	mlx_uint32				port_offset;
177
+	mlx_uint8				port_state;
178
+	mlx_boolean				network_state;
179
+	mlx_boolean				dma_state;
180
+	nodnic_port_type		port_type;
181
+	mlx_uint8				port_num;
182
+	nodnic_eq				eq;
183
+	mlx_mac_address			mac_filters[5];
184
+	mlx_status (*send_doorbell)(
185
+			IN nodnic_port_priv		*port_priv,
186
+			IN struct nodnic_ring	*ring,
187
+			IN mlx_uint16 index);
188
+	mlx_status (*recv_doorbell)(
189
+			IN nodnic_port_priv		*port_priv,
190
+			IN struct nodnic_ring	*ring,
191
+			IN mlx_uint16 index);
192
+	mlx_status (*set_dma)(
193
+			IN nodnic_port_priv		*port_priv,
194
+			IN mlx_boolean			value);
195
+#ifdef DEVICE_CX3
196
+	nodnic_port_data_flow_gw *data_flow_gw;
197
+#endif
198
+};
199
+
200
+
201
+#endif /* STUB_NODNIC_NODNICDATASTRUCTURES_H_ */

+ 229
- 0
src/drivers/infiniband/mlx_nodnic/include/mlx_port.h Visa fil

@@ -0,0 +1,229 @@
1
+#ifndef NODNIC_PORT_H_
2
+#define NODNIC_PORT_H_
3
+
4
+/*
5
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20
+ * 02110-1301, USA.
21
+ */
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+
25
+#include "mlx_nodnic_data_structures.h"
26
+
27
+#define NODNIC_PORT_MAC_FILTERS_OFFSET 0x10
28
+
29
+typedef enum {
30
+	nodnic_port_option_link_type = 0,
31
+	nodnic_port_option_mac_low,
32
+	nodnic_port_option_mac_high,
33
+	nodnic_port_option_log_cq_size,
34
+	nodnic_port_option_reset_needed,
35
+	nodnic_port_option_mac_filters_en,
36
+	nodnic_port_option_port_state,
37
+	nodnic_port_option_network_en,
38
+	nodnic_port_option_dma_en,
39
+	nodnic_port_option_eq_addr_low,
40
+	nodnic_port_option_eq_addr_high,
41
+	nodnic_port_option_cq_addr_low,
42
+	nodnic_port_option_cq_addr_high,
43
+	nodnic_port_option_port_management_change_event,
44
+	nodnic_port_option_port_promisc_en,
45
+	nodnic_port_option_arm_cq,
46
+	nodnic_port_option_port_promisc_multicast_en,
47
+#ifdef DEVICE_CX3
48
+	nodnic_port_option_crspace_en,
49
+#endif
50
+}nodnic_port_option;
51
+
52
+struct nodnic_port_data_entry{
53
+	nodnic_port_option	option;
54
+	mlx_uint32			offset;
55
+	mlx_uint8			align;
56
+	mlx_uint32			mask;
57
+};
58
+
59
+struct nodnic_qp_data_entry{
60
+	nodnic_queue_pair_type	type;
61
+	mlx_uint32			send_offset;
62
+	mlx_uint32			recv_offset;
63
+};
64
+
65
+
66
+typedef enum {
67
+	nodnic_port_state_down = 0,
68
+	nodnic_port_state_initialize,
69
+	nodnic_port_state_armed,
70
+	nodnic_port_state_active,
71
+}nodnic_port_state;
72
+
73
+mlx_status
74
+nodnic_port_get_state(
75
+					IN  nodnic_port_priv	*port_priv,
76
+					OUT nodnic_port_state			*state
77
+					);
78
+
79
+mlx_status
80
+nodnic_port_get_type(
81
+					IN  nodnic_port_priv	*port_priv,
82
+					OUT nodnic_port_type	*type
83
+					);
84
+
85
+mlx_status
86
+nodnic_port_query(
87
+					IN  nodnic_port_priv	*port_priv,
88
+					IN  nodnic_port_option		option,
89
+					OUT	mlx_uint32				*out
90
+					);
91
+
92
+mlx_status
93
+nodnic_port_set(
94
+					IN  nodnic_port_priv	*port_priv,
95
+					IN  nodnic_port_option		option,
96
+					IN	mlx_uint32				in
97
+					);
98
+
99
+mlx_status
100
+nodnic_port_create_cq(
101
+					IN nodnic_port_priv	*port_priv,
102
+					IN mlx_size	cq_size,
103
+					OUT nodnic_cq	**cq
104
+					);
105
+
106
+mlx_status
107
+nodnic_port_destroy_cq(
108
+					IN nodnic_port_priv	*port_priv,
109
+					IN nodnic_cq	*cq
110
+					);
111
+
112
+mlx_status
113
+nodnic_port_create_qp(
114
+					IN nodnic_port_priv	*port_priv,
115
+					IN nodnic_queue_pair_type	type,
116
+					IN mlx_size	send_wq_size,
117
+					IN mlx_uint32 send_wqe_num,
118
+					IN mlx_size	receive_wq_size,
119
+					IN mlx_uint32 recv_wqe_num,
120
+					OUT nodnic_qp	**qp
121
+					);
122
+
123
+mlx_status
124
+nodnic_port_destroy_qp(
125
+					IN nodnic_port_priv	*port_priv,
126
+					IN nodnic_queue_pair_type	type,
127
+					IN nodnic_qp	*qp
128
+					);
129
+mlx_status
130
+nodnic_port_get_qpn(
131
+			IN nodnic_port_priv	*port_priv,
132
+			IN struct nodnic_ring *ring,
133
+			OUT mlx_uint32 *qpn
134
+			);
135
+mlx_status
136
+nodnic_port_update_ring_doorbell(
137
+					IN nodnic_port_priv	*port_priv,
138
+					IN struct nodnic_ring *ring,
139
+					IN mlx_uint16 index
140
+					);
141
+mlx_status
142
+nodnic_port_get_cq_size(
143
+		IN nodnic_port_priv	*port_priv,
144
+		OUT mlx_uint64 *cq_size
145
+		);
146
+
147
+mlx_status
148
+nodnic_port_allocate_eq(
149
+					IN  nodnic_port_priv	*port_priv,
150
+					IN  mlx_uint8			log_eq_size
151
+					);
152
+mlx_status
153
+nodnic_port_free_eq(
154
+					IN  nodnic_port_priv	*port_priv
155
+					);
156
+
157
+mlx_status
158
+nodnic_port_add_mac_filter(
159
+					IN  nodnic_port_priv	*port_priv,
160
+					IN  mlx_mac_address 	mac
161
+					);
162
+
163
+mlx_status
164
+nodnic_port_remove_mac_filter(
165
+					IN  nodnic_port_priv	*port_priv,
166
+					IN  mlx_mac_address 	mac
167
+					);
168
+mlx_status
169
+nodnic_port_add_mgid_filter(
170
+					IN  nodnic_port_priv	*port_priv,
171
+					IN  mlx_mac_address 	mac
172
+					);
173
+
174
+mlx_status
175
+nodnic_port_remove_mgid_filter(
176
+					IN  nodnic_port_priv	*port_priv,
177
+					IN  mlx_mac_address 	mac
178
+					);
179
+mlx_status
180
+nodnic_port_thin_init(
181
+		IN nodnic_device_priv	*device_priv,
182
+		IN nodnic_port_priv		*port_priv,
183
+		IN mlx_uint8			port_index
184
+		);
185
+
186
+mlx_status
187
+nodnic_port_set_promisc(
188
+		IN nodnic_port_priv		*port_priv,
189
+		IN mlx_boolean			value
190
+		);
191
+
192
+mlx_status
193
+nodnic_port_set_promisc_multicast(
194
+		IN nodnic_port_priv		*port_priv,
195
+		IN mlx_boolean			value
196
+		);
197
+
198
+mlx_status
199
+nodnic_port_init(
200
+		IN nodnic_port_priv		*port_priv
201
+		);
202
+
203
+mlx_status
204
+nodnic_port_close(
205
+		IN nodnic_port_priv		*port_priv
206
+		);
207
+
208
+mlx_status
209
+nodnic_port_enable_dma(
210
+		IN nodnic_port_priv		*port_priv
211
+		);
212
+
213
+mlx_status
214
+nodnic_port_disable_dma(
215
+		IN nodnic_port_priv		*port_priv
216
+		);
217
+
218
+mlx_status
219
+nodnic_port_read_reset_needed(
220
+						IN nodnic_port_priv		*port_priv,
221
+						OUT mlx_boolean			*reset_needed
222
+						);
223
+
224
+mlx_status
225
+nodnic_port_read_port_management_change_event(
226
+						IN nodnic_port_priv		*port_priv,
227
+						OUT mlx_boolean			*change_event
228
+						);
229
+#endif /* STUB_NODNIC_PORT_H_ */

+ 77
- 0
src/drivers/infiniband/mlx_nodnic/src/mlx_cmd.c Visa fil

@@ -0,0 +1,77 @@
1
+/*
2
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
3
+ *
4
+ * This program is free software; you can redistribute it and/or
5
+ * modify it under the terms of the GNU General Public License as
6
+ * published by the Free Software Foundation; either version 2 of the
7
+ * License, or any later version.
8
+ *
9
+ * This program is distributed in the hope that it will be useful, but
10
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
11
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
12
+ * General Public License for more details.
13
+ *
14
+ * You should have received a copy of the GNU General Public License
15
+ * along with this program; if not, write to the Free Software
16
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17
+ * 02110-1301, USA.
18
+ */
19
+
20
+FILE_LICENCE ( GPL2_OR_LATER );
21
+
22
+#include "../include/mlx_cmd.h"
23
+#include "../../mlx_utils/include/public/mlx_pci_gw.h"
24
+#include "../../mlx_utils/include/public/mlx_bail.h"
25
+#include "../../mlx_utils/include/public/mlx_pci.h"
26
+#include "../../mlx_utils/include/public/mlx_logging.h"
27
+
28
+mlx_status
29
+nodnic_cmd_read(
30
+				IN nodnic_device_priv *device_priv,
31
+				IN mlx_uint32 address,
32
+				OUT mlx_pci_gw_buffer *buffer
33
+				)
34
+{
35
+	mlx_status 		status = MLX_SUCCESS;
36
+	mlx_utils 		*utils = NULL;
37
+
38
+	if ( device_priv == NULL || buffer == NULL ) {
39
+		status = MLX_INVALID_PARAMETER;
40
+		goto bad_param;
41
+	}
42
+
43
+	utils = device_priv->utils;
44
+
45
+	status = mlx_pci_gw_read(utils, PCI_GW_SPACE_NODNIC, address, buffer);
46
+	MLX_CHECK_STATUS(device_priv, status, read_error,"mlx_pci_gw_read failed");
47
+
48
+read_error:
49
+bad_param:
50
+	return status;
51
+}
52
+
53
+mlx_status
54
+nodnic_cmd_write(
55
+				IN nodnic_device_priv *device_priv,
56
+				IN mlx_uint32 address,
57
+				IN mlx_pci_gw_buffer buffer
58
+				)
59
+{
60
+	mlx_status 		status = MLX_SUCCESS;
61
+	mlx_utils 		*utils = NULL;
62
+
63
+
64
+	if ( device_priv == NULL ) {
65
+		status = MLX_INVALID_PARAMETER;
66
+		goto bad_param;
67
+	}
68
+
69
+	utils = device_priv->utils;
70
+
71
+
72
+	status = mlx_pci_gw_write(utils, PCI_GW_SPACE_NODNIC, address, buffer);
73
+	MLX_CHECK_STATUS(device_priv, status, write_error,"mlx_pci_gw_write failed");
74
+write_error:
75
+bad_param:
76
+	return status;
77
+}

+ 339
- 0
src/drivers/infiniband/mlx_nodnic/src/mlx_device.c Visa fil

@@ -0,0 +1,339 @@
1
+/*
2
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
3
+ *
4
+ * This program is free software; you can redistribute it and/or
5
+ * modify it under the terms of the GNU General Public License as
6
+ * published by the Free Software Foundation; either version 2 of the
7
+ * License, or any later version.
8
+ *
9
+ * This program is distributed in the hope that it will be useful, but
10
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
11
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
12
+ * General Public License for more details.
13
+ *
14
+ * You should have received a copy of the GNU General Public License
15
+ * along with this program; if not, write to the Free Software
16
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17
+ * 02110-1301, USA.
18
+ */
19
+
20
+FILE_LICENCE ( GPL2_OR_LATER );
21
+
22
+#include "../include/mlx_device.h"
23
+#include "../include/mlx_cmd.h"
24
+#include "../../mlx_utils/include/public/mlx_bail.h"
25
+#include "../../mlx_utils/include/public/mlx_pci.h"
26
+#include "../../mlx_utils/include/public/mlx_memory.h"
27
+#include "../../mlx_utils/include/public/mlx_logging.h"
28
+
29
+#define CHECK_BIT(field, offset)	(((field) & ((mlx_uint32)1 << (offset))) != 0)
30
+
31
+static
32
+mlx_status
33
+check_nodnic_interface_supported(
34
+							IN nodnic_device_priv* device_priv,
35
+							OUT mlx_boolean *out
36
+							)
37
+{
38
+	mlx_status status = MLX_SUCCESS;
39
+	mlx_uint32	output = 0;
40
+	status = nodnic_cmd_read(device_priv, NODNIC_NIC_INTERFACE_SUPPORTED_OFFSET,
41
+			&output);
42
+	MLX_FATAL_CHECK_STATUS(status, read_error, "failed to read nic_interface_supported");
43
+	*out = CHECK_BIT(output, NODNIC_NIC_INTERFACE_SUPPORTED_BIT);
44
+read_error:
45
+	return status;
46
+}
47
+
48
+static
49
+mlx_status
50
+wait_for_device_initialization(
51
+							IN nodnic_device_priv* device_priv
52
+							)
53
+{
54
+	mlx_status status = MLX_SUCCESS;
55
+	mlx_uint8 try = 0;
56
+	mlx_uint32			buffer = 0;
57
+
58
+#define CHECK_DEVICE_INIT_TRIES 10
59
+	for( ; try < CHECK_DEVICE_INIT_TRIES ; try++){
60
+		status = nodnic_cmd_read(device_priv, NODNIC_INITIALIZING_OFFSET, &buffer);
61
+		MLX_CHECK_STATUS(device_priv, status, read_error, "failed to read initializing");
62
+		if( !CHECK_BIT(buffer, NODNIC_INITIALIZING_BIT)){
63
+			goto init_done;
64
+		}
65
+		mlx_utils_delay_in_ms(100);
66
+	}
67
+	status = MLX_FAILED;
68
+read_error:
69
+init_done:
70
+	return status;
71
+}
72
+
73
+static
74
+mlx_status
75
+disable_nodnic_inteface(
76
+						IN nodnic_device_priv *device_priv
77
+						)
78
+{
79
+	mlx_status 			status = MLX_SUCCESS;
80
+	mlx_uint32			buffer = 0;
81
+
82
+	buffer = (1 << NODNIC_DISABLE_INTERFACE_BIT);
83
+	status = nodnic_cmd_write(device_priv, NODNIC_CMDQ_PHY_ADDR_LOW_OFFSET, buffer);
84
+	MLX_FATAL_CHECK_STATUS(status, write_err, "failed to write cmdq_phy_addr + nic_interface");
85
+
86
+	status = wait_for_device_initialization(device_priv);
87
+	MLX_FATAL_CHECK_STATUS(status, init_err, "failed to initialize device");
88
+init_err:
89
+write_err:
90
+	return status;
91
+}
92
+static
93
+mlx_status
94
+nodnic_device_start_nodnic(
95
+				IN nodnic_device_priv *device_priv
96
+				)
97
+{
98
+	mlx_status 			status = MLX_SUCCESS;
99
+	mlx_uint32			buffer = 0;
100
+	mlx_boolean			nodnic_supported = 0;
101
+
102
+	status = wait_for_device_initialization(device_priv);
103
+	MLX_FATAL_CHECK_STATUS(status, wait_for_fw_err, "failed to initialize device");
104
+
105
+	status = check_nodnic_interface_supported(device_priv, &nodnic_supported);
106
+	MLX_FATAL_CHECK_STATUS(status, read_err,"failed to check nic_interface_supported");
107
+
108
+	if(	nodnic_supported == 0 ){
109
+		status = MLX_UNSUPPORTED;
110
+		goto nodnic_unsupported;
111
+	}
112
+	buffer =  (1 << NODNIC_NIC_INTERFACE_BIT);
113
+	status = nodnic_cmd_write(device_priv, NODNIC_NIC_INTERFACE_OFFSET, buffer);
114
+	MLX_FATAL_CHECK_STATUS(status, write_err, "failed to write cmdq_phy_addr + nic_interface");
115
+
116
+	status = wait_for_device_initialization(device_priv);
117
+	MLX_FATAL_CHECK_STATUS(status, init_err, "failed to initialize device");
118
+init_err:
119
+read_err:
120
+write_err:
121
+nodnic_unsupported:
122
+wait_for_fw_err:
123
+	return status;
124
+}
125
+
126
+static
127
+mlx_status
128
+nodnic_device_get_nodnic_data(
129
+				IN nodnic_device_priv *device_priv
130
+				)
131
+{
132
+	mlx_status 			status = MLX_SUCCESS;
133
+	mlx_uint32			buffer = 0;
134
+
135
+	status = nodnic_cmd_read(device_priv, NODNIC_LOCATION_OFFSET, &device_priv->device_offset);
136
+	MLX_FATAL_CHECK_STATUS(status, nodnic_offset_read_err, "failed to read nodnic offset");
137
+
138
+	status = nodnic_cmd_read(device_priv,
139
+			device_priv->device_offset + NODNIC_REVISION_OFFSET, &buffer);
140
+	MLX_FATAL_CHECK_STATUS(status, nodnic_revision_read_err, "failed to read nodnic revision");
141
+
142
+	device_priv->nodnic_revision = (buffer >> 24) & 0xFF;
143
+	if( device_priv->nodnic_revision != NODIC_SUPPORTED_REVISION ){
144
+		MLX_DEBUG_ERROR(device_priv, "nodnic revision not supported\n");
145
+		status = MLX_UNSUPPORTED;
146
+		goto unsupported_revision;
147
+	}
148
+
149
+	status = nodnic_cmd_read(device_priv,
150
+			device_priv->device_offset + NODNIC_HARDWARE_FORMAT_OFFSET, &buffer);
151
+	MLX_FATAL_CHECK_STATUS(status, nodnic_hardware_format_read_err, "failed to read nodnic revision");
152
+	device_priv->hardware_format = (buffer >> 16) & 0xFF;
153
+
154
+	return status;
155
+
156
+unsupported_revision:
157
+nodnic_hardware_format_read_err:
158
+nodnic_offset_read_err:
159
+nodnic_revision_read_err:
160
+	disable_nodnic_inteface(device_priv);
161
+	return status;
162
+}
163
+
164
+mlx_status
165
+nodnic_device_clear_int (
166
+				IN nodnic_device_priv *device_priv
167
+				)
168
+{
169
+	mlx_status 			status = MLX_SUCCESS;
170
+	mlx_uint32			disable = 1;
171
+#ifndef DEVICE_CX3
172
+	status = nodnic_cmd_write(device_priv, NODNIC_NIC_DISABLE_INT_OFFSET, disable);
173
+	MLX_CHECK_STATUS(device_priv, status, clear_int_done, "failed writing to disable_bit");
174
+#else
175
+	mlx_utils *utils = device_priv->utils;
176
+	mlx_uint64 clear_int = (mlx_uint64)(device_priv->crspace_clear_int);
177
+	mlx_uint32 swapped = 0;
178
+
179
+	if (device_priv->device_cap.crspace_doorbells == 0) {
180
+		status = nodnic_cmd_write(device_priv, NODNIC_NIC_DISABLE_INT_OFFSET, disable);
181
+		MLX_CHECK_STATUS(device_priv, status, clear_int_done, "failed writing to disable_bit");
182
+	} else {
183
+		/* Write the new index and update FW that new data was submitted */
184
+		disable = 0x80000000;
185
+		mlx_memory_cpu_to_be32(utils, disable, &swapped);
186
+		mlx_pci_mem_write (utils, MlxPciWidthUint32, 0, clear_int, 1, &swapped);
187
+		mlx_pci_mem_read (utils, MlxPciWidthUint32, 0, clear_int, 1, &swapped);
188
+	}
189
+#endif
190
+clear_int_done:
191
+	return status;
192
+}
193
+
194
+mlx_status
195
+nodnic_device_init(
196
+				IN nodnic_device_priv *device_priv
197
+				)
198
+{
199
+	mlx_status 			status = MLX_SUCCESS;
200
+
201
+	if( device_priv == NULL ){
202
+		status = MLX_INVALID_PARAMETER;
203
+		goto parm_err;
204
+	}
205
+	status = nodnic_device_start_nodnic(device_priv);
206
+	MLX_FATAL_CHECK_STATUS(status, start_nodnic_err, "nodnic_device_start_nodnic failed");
207
+
208
+	status = nodnic_device_get_nodnic_data(device_priv);
209
+	MLX_FATAL_CHECK_STATUS(status, data_err, "nodnic_device_get_nodnic_data failed");
210
+	return status;
211
+data_err:
212
+start_nodnic_err:
213
+parm_err:
214
+	return status;
215
+}
216
+
217
+mlx_status
218
+nodnic_device_teardown(
219
+				IN nodnic_device_priv *device_priv
220
+				)
221
+{
222
+	mlx_status 			status = MLX_SUCCESS;
223
+	status = disable_nodnic_inteface(device_priv);
224
+	MLX_FATAL_CHECK_STATUS(status, disable_failed, "failed to disable nodnic interface");
225
+disable_failed:
226
+	return status;
227
+}
228
+
229
+mlx_status
230
+nodnic_device_get_cap(
231
+				IN nodnic_device_priv *device_priv
232
+				)
233
+{
234
+	mlx_status 					status = MLX_SUCCESS;
235
+	nodnic_device_capabilites 	*device_cap = NULL;
236
+	mlx_uint32					buffer = 0;
237
+	mlx_uint64					guid_l = 0;
238
+	mlx_uint64					guid_h = 0;
239
+	if( device_priv == NULL ){
240
+		status = MLX_INVALID_PARAMETER;
241
+		goto parm_err;
242
+	}
243
+
244
+	device_cap = &device_priv->device_cap;
245
+
246
+	//get device capabilities
247
+	status = nodnic_cmd_read(device_priv, device_priv->device_offset + 0x0, &buffer);
248
+	MLX_FATAL_CHECK_STATUS(status, read_err, "failed to read nodnic first dword");
249
+
250
+#define NODNIC_DEVICE_SUPPORT_MAC_FILTERS_OFFSET 15
251
+#define NODNIC_DEVICE_SUPPORT_PROMISC_FILTER_OFFSET 14
252
+#define NODNIC_DEVICE_SUPPORT_PROMISC_MULT_FILTER_OFFSET 13
253
+#define NODNIC_DEVICE_LOG_WORKING_BUFFER_SIZE_OFFSET 8
254
+#define NODNIC_DEVICE_LOG_WORKING_BUFFER_SIZE_MASK 0x7
255
+#define NODNIC_DEVICE_LOG_PKEY_TABLE_SIZE_OFFSET 4
256
+#define NODNIC_DEVICE_LOG_PKEY_TABLE_SIZE_MASK 0xF
257
+#define NODNIC_DEVICE_NUM_PORTS_OFFSET 0
258
+	device_cap->support_mac_filters = CHECK_BIT(buffer, NODNIC_DEVICE_SUPPORT_MAC_FILTERS_OFFSET);
259
+
260
+	device_cap->support_promisc_filter = CHECK_BIT(buffer, NODNIC_DEVICE_SUPPORT_PROMISC_FILTER_OFFSET);
261
+
262
+	device_cap->support_promisc_multicast_filter = CHECK_BIT(buffer, NODNIC_DEVICE_SUPPORT_PROMISC_MULT_FILTER_OFFSET);
263
+
264
+	device_cap->log_working_buffer_size =
265
+			(buffer >> NODNIC_DEVICE_LOG_WORKING_BUFFER_SIZE_OFFSET) & NODNIC_DEVICE_LOG_WORKING_BUFFER_SIZE_MASK;
266
+
267
+	device_cap->log_pkey_table_size =
268
+			(buffer >> NODNIC_DEVICE_LOG_PKEY_TABLE_SIZE_OFFSET) & NODNIC_DEVICE_LOG_PKEY_TABLE_SIZE_MASK;
269
+
270
+	device_cap->num_ports = CHECK_BIT(buffer, NODNIC_DEVICE_NUM_PORTS_OFFSET) + 1;
271
+
272
+#ifdef DEVICE_CX3
273
+#define NODNIC_DEVICE_CRSPACE_DB_OFFSET 12
274
+	device_cap->crspace_doorbells = CHECK_BIT(buffer, NODNIC_DEVICE_CRSPACE_DB_OFFSET);
275
+#endif
276
+
277
+	status = nodnic_cmd_read(device_priv, device_priv->device_offset + 0x4, &buffer);
278
+	MLX_FATAL_CHECK_STATUS(status, read_err, "failed to read nodnic second dword");
279
+
280
+#define NODNIC_DEVICE_LOG_MAX_RING_SIZE_OFFSET 24
281
+#define NODNIC_DEVICE_LOG_MAX_RING_SIZE_MASK 0x3F
282
+#define NODNIC_DEVICE_PD_MASK 0xFFFFFF
283
+	device_cap->log_max_ring_size =
284
+			(buffer >> NODNIC_DEVICE_LOG_MAX_RING_SIZE_OFFSET) & NODNIC_DEVICE_LOG_MAX_RING_SIZE_MASK;
285
+
286
+	//get device magic numbers
287
+	device_priv->pd = buffer & NODNIC_DEVICE_PD_MASK;
288
+
289
+	status = nodnic_cmd_read(device_priv, device_priv->device_offset + 0x8, &buffer);
290
+	MLX_FATAL_CHECK_STATUS(status, read_err, "failed to read nodnic third dword");
291
+	device_priv->lkey = buffer;
292
+
293
+#ifdef DEVICE_CX3
294
+	if ( device_cap->crspace_doorbells ) {
295
+		status = nodnic_cmd_read(device_priv, device_priv->device_offset + 0x18, &buffer);
296
+		MLX_FATAL_CHECK_STATUS(status, read_err, "failed to read nodnic_crspace_clear_int address");
297
+		device_priv->crspace_clear_int = device_priv->utils->config + buffer;
298
+	}
299
+#endif
300
+
301
+	status = nodnic_cmd_read(device_priv, device_priv->device_offset + 0x10, (mlx_uint32*)&guid_h);
302
+	MLX_FATAL_CHECK_STATUS(status, read_err, "failed to read nodnic guid_h");
303
+	status = nodnic_cmd_read(device_priv, device_priv->device_offset + 0x14, (mlx_uint32*)&guid_l);
304
+	MLX_FATAL_CHECK_STATUS(status, read_err, "failed to read nodnic guid_l");
305
+	device_priv->device_guid = guid_l | (guid_h << 32);
306
+read_err:
307
+parm_err:
308
+	return status;
309
+}
310
+
311
+mlx_status
312
+nodnic_device_get_fw_version(
313
+				IN nodnic_device_priv *device_priv,
314
+				OUT mlx_uint16		*fw_ver_minor,
315
+				OUT mlx_uint16  	*fw_ver_sub_minor,
316
+				OUT mlx_uint16  	*fw_ver_major
317
+				){
318
+	mlx_status 		status = MLX_SUCCESS;
319
+	mlx_uint32		buffer = 0;
320
+
321
+	if( device_priv == NULL ){
322
+		status = MLX_INVALID_PARAMETER;
323
+		goto parm_err;
324
+	}
325
+
326
+	status = nodnic_cmd_read(device_priv, 0x0, &buffer);
327
+	MLX_CHECK_STATUS(device_priv, status, read_err, "failed to read fw revision major and minor");
328
+
329
+	*fw_ver_minor = (mlx_uint16)(buffer >> 16);
330
+	*fw_ver_major = (mlx_uint16)buffer;
331
+
332
+	status = nodnic_cmd_read(device_priv, 0x4, &buffer);
333
+	MLX_CHECK_STATUS(device_priv, status, read_err, "failed to read fw revision sub minor");
334
+
335
+	*fw_ver_sub_minor = (mlx_uint16)buffer;
336
+read_err:
337
+parm_err:
338
+	return status;
339
+}

+ 1038
- 0
src/drivers/infiniband/mlx_nodnic/src/mlx_port.c
Filskillnaden har hållits tillbaka eftersom den är för stor
Visa fil


+ 113
- 0
src/drivers/infiniband/mlx_utils/include/private/mlx_memory_priv.h Visa fil

@@ -0,0 +1,113 @@
1
+#ifndef MLXUTILS_INCLUDE_PRIVATE_MEMORYPRIV_H_
2
+#define MLXUTILS_INCLUDE_PRIVATE_MEMORYPRIV_H_
3
+
4
+/*
5
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20
+ * 02110-1301, USA.
21
+ */
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+
25
+#include "../../../mlx_utils/include/public/mlx_utils.h"
26
+
27
+mlx_status
28
+mlx_memory_alloc_priv(
29
+				IN mlx_utils *utils,
30
+				IN mlx_size size,
31
+				OUT mlx_void **ptr
32
+				);
33
+
34
+mlx_status
35
+mlx_memory_zalloc_priv(
36
+				IN mlx_utils *utils,
37
+				IN mlx_size size,
38
+				OUT mlx_void **ptr
39
+				);
40
+
41
+mlx_status
42
+mlx_memory_free_priv(
43
+				IN mlx_utils *utils,
44
+				IN mlx_void *ptr
45
+				);
46
+mlx_status
47
+mlx_memory_alloc_dma_priv(
48
+					IN mlx_utils *utils,
49
+					IN mlx_size size ,
50
+					IN mlx_size align,
51
+					OUT mlx_void **ptr
52
+					);
53
+
54
+mlx_status
55
+mlx_memory_free_dma_priv(
56
+					IN mlx_utils *utils,
57
+					IN mlx_size size ,
58
+					IN mlx_void *ptr
59
+					);
60
+mlx_status
61
+mlx_memory_map_dma_priv(
62
+					IN mlx_utils *utils,
63
+					IN mlx_void *addr ,
64
+					IN mlx_size number_of_bytes,
65
+					OUT mlx_physical_address *phys_addr,
66
+					OUT mlx_void **mapping
67
+					);
68
+
69
+mlx_status
70
+mlx_memory_ummap_dma_priv(
71
+					IN mlx_utils *utils,
72
+					IN mlx_void *mapping
73
+					);
74
+
75
+mlx_status
76
+mlx_memory_cmp_priv(
77
+					IN mlx_utils *utils,
78
+					IN mlx_void *first_block,
79
+					IN mlx_void *second_block,
80
+					IN mlx_size size,
81
+					OUT mlx_uint32 *out
82
+					);
83
+
84
+mlx_status
85
+mlx_memory_set_priv(
86
+					IN mlx_utils *utils,
87
+					IN mlx_void *block,
88
+					IN mlx_int32 value,
89
+					IN mlx_size size
90
+					);
91
+
92
+mlx_status
93
+mlx_memory_cpy_priv(
94
+					IN mlx_utils *utils,
95
+					OUT mlx_void *destination_buffer,
96
+					IN mlx_void *source_buffer,
97
+					IN mlx_size length
98
+					);
99
+
100
+mlx_status
101
+mlx_memory_cpu_to_be32_priv(
102
+			IN mlx_utils *utils,
103
+			IN mlx_uint32 source,
104
+			IN mlx_uint32 *destination
105
+			);
106
+
107
+mlx_status
108
+mlx_memory_be32_to_cpu_priv(
109
+			IN mlx_utils *utils,
110
+			IN mlx_uint32 source,
111
+			IN mlx_uint32 *destination
112
+			);
113
+#endif /* STUB_MLXUTILS_INCLUDE_PRIVATE_MEMORYPRIV_H_ */

+ 72
- 0
src/drivers/infiniband/mlx_utils/include/private/mlx_pci_priv.h Visa fil

@@ -0,0 +1,72 @@
1
+#ifndef STUB_MLXUTILS_INCLUDE_PRIVATE_PCIPRIV_H_
2
+#define STUB_MLXUTILS_INCLUDE_PRIVATE_PCIPRIV_H_
3
+
4
+/*
5
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20
+ * 02110-1301, USA.
21
+ */
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+
25
+#include "../../include/public/mlx_pci.h"
26
+#include "../../include/public/mlx_utils.h"
27
+
28
+mlx_status
29
+mlx_pci_init_priv(
30
+			IN mlx_utils *utils
31
+			);
32
+
33
+mlx_status
34
+mlx_pci_read_priv(
35
+			IN mlx_utils *utils,
36
+			IN mlx_pci_width width,
37
+			IN mlx_uint32 offset,
38
+			IN mlx_uintn count,
39
+			OUT mlx_void *buffer
40
+			);
41
+
42
+mlx_status
43
+mlx_pci_write_priv(
44
+			IN mlx_utils *utils,
45
+			IN mlx_pci_width width,
46
+			IN mlx_uint32 offset,
47
+			IN mlx_uintn count,
48
+			IN mlx_void *buffer
49
+			);
50
+
51
+mlx_status
52
+mlx_pci_mem_read_priv(
53
+				IN mlx_utils *utils,
54
+				IN mlx_pci_width width,
55
+				IN mlx_uint8 bar_index,
56
+				IN mlx_uint64 offset,
57
+				IN mlx_uintn count,
58
+				OUT mlx_void *buffer
59
+				);
60
+
61
+mlx_status
62
+mlx_pci_mem_write_priv(
63
+				IN mlx_utils *utils,
64
+				IN mlx_pci_width width,
65
+				IN mlx_uint8 bar_index,
66
+				IN mlx_uint64 offset,
67
+				IN mlx_uintn count,
68
+				IN mlx_void *buffer
69
+				);
70
+
71
+
72
+#endif /* STUB_MLXUTILS_INCLUDE_PRIVATE_PCIPRIV_H_ */

+ 68
- 0
src/drivers/infiniband/mlx_utils/include/private/mlx_utils_priv.h Visa fil

@@ -0,0 +1,68 @@
1
+#ifndef SRC_DRIVERS_INFINIBAND_MLX_UTILS_INCLUDE_PRIVATE_MLX_UTILS_PRIV_H_
2
+#define SRC_DRIVERS_INFINIBAND_MLX_UTILS_INCLUDE_PRIVATE_MLX_UTILS_PRIV_H_
3
+
4
+/*
5
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20
+ * 02110-1301, USA.
21
+ */
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+
25
+#include "../../include/public/mlx_utils.h"
26
+
27
+mlx_status
28
+mlx_utils_delay_in_ms_priv(
29
+			IN mlx_uint32 msecs
30
+		);
31
+
32
+mlx_status
33
+mlx_utils_delay_in_us_priv(
34
+			IN mlx_uint32 usecs
35
+		);
36
+
37
+mlx_status
38
+mlx_utils_ilog2_priv(
39
+			IN mlx_uint32 i,
40
+			OUT mlx_uint32 *log
41
+		);
42
+
43
+mlx_status
44
+mlx_utils_init_lock_priv(
45
+			OUT void **lock
46
+		);
47
+
48
+mlx_status
49
+mlx_utils_free_lock_priv(
50
+			IN void *lock
51
+		);
52
+
53
+mlx_status
54
+mlx_utils_acquire_lock_priv (
55
+			IN void *lock
56
+		);
57
+
58
+mlx_status
59
+mlx_utils_release_lock_priv (
60
+			IN void *lock
61
+		);
62
+
63
+mlx_status
64
+mlx_utils_rand_priv (
65
+		IN mlx_utils *utils,
66
+		OUT mlx_uint32 *rand_num
67
+		);
68
+#endif /* SRC_DRIVERS_INFINIBAND_MLX_UTILS_INCLUDE_PRIVATE_MLX_UTILS_PRIV_H_ */

+ 47
- 0
src/drivers/infiniband/mlx_utils/include/public/mlx_bail.h Visa fil

@@ -0,0 +1,47 @@
1
+#ifndef INCLUDE_PUBLIC_MLXBAIL_H_
2
+#define INCLUDE_PUBLIC_MLXBAIL_H_
3
+
4
+/*
5
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20
+ * 02110-1301, USA.
21
+ */
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+
25
+#include "mlx_types.h"
26
+
27
+#define MLX_BAIL_ERROR(id, status,message) MLX_CHECK_STATUS(id, status, bail, message)
28
+
29
+#define MLX_FATAL_CHECK_STATUS(status, label, message)						\
30
+        do {																	\
31
+            if (status != MLX_SUCCESS) {										\
32
+                MLX_DEBUG_FATAL_ERROR(message " (Status = %d)\n", status);	\
33
+                goto label;														\
34
+            }																	\
35
+        } while (0)
36
+
37
+#define MLX_CHECK_STATUS(id, status, label, message)					\
38
+        do {															\
39
+            if (status != MLX_SUCCESS) {								\
40
+                MLX_DEBUG_ERROR(id, message " (Status = %d)\n", status);\
41
+                goto label;												\
42
+            }															\
43
+        } while (0)
44
+
45
+
46
+
47
+#endif /* INCLUDE_PUBLIC_MLXBAIL_H_ */

+ 63
- 0
src/drivers/infiniband/mlx_utils/include/public/mlx_icmd.h Visa fil

@@ -0,0 +1,63 @@
1
+#ifndef MLXUTILS_INCLUDE_PUBLIC_MLX_ICMD_H_
2
+#define MLXUTILS_INCLUDE_PUBLIC_MLX_ICMD_H_
3
+/*
4
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
5
+ *
6
+ * This program is free software; you can redistribute it and/or
7
+ * modify it under the terms of the GNU General Public License as
8
+ * published by the Free Software Foundation; either version 2 of the
9
+ * License, or any later version.
10
+ *
11
+ * This program is distributed in the hope that it will be useful, but
12
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
13
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
+ * General Public License for more details.
15
+ *
16
+ * You should have received a copy of the GNU General Public License
17
+ * along with this program; if not, write to the Free Software
18
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19
+ * 02110-1301, USA.
20
+ */
21
+
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+
25
+#include "mlx_utils.h"
26
+
27
+#define MLX_ICMD_MB_ADDR 0x100000
28
+#define MLX_ICMD_MB_SIZE_ADDR 0x1000
29
+#define MLX_ICMD_CTRL_ADDR 0x0
30
+
31
+#define MLX_ICMD_SEMAPHORE_ADDR 0x0
32
+
33
+#define MLX_ICMD_SEMAPHORE_ID 1234
34
+
35
+enum {
36
+	FLASH_REG_ACCESS	= 0x9001,
37
+	GET_FW_INFO			= 0x8007,
38
+	QUERY_VIRTUAL_MAC	= 0x9003,
39
+	SET_VIRTUAL_MAC		= 0x9004,
40
+	QUERY_WOL_ROL		= 0x9005,
41
+	SET_WOL_ROL			= 0x9006,
42
+	OCBB_INIT			= 0x9007,
43
+	OCBB_QUERY_HEADER_STATUS	= 0x9008,
44
+	OCBB_QUERY_ETOC_STATUS	= 0x9009,
45
+	OCBB_QUERY_SET_EVENT	= 0x900A,
46
+	OCSD_INIT			= 0xf004,
47
+};
48
+
49
+struct mlx_icmd_ocsd {
50
+	mlx_uint32 reserved;
51
+	mlx_uint64 address;
52
+};
53
+
54
+mlx_status
55
+mlx_icmd_send_command(
56
+				IN mlx_utils *utils,
57
+				IN  mlx_uint16 opcode,
58
+				IN OUT mlx_void* data,
59
+				IN mlx_uint32 write_data_size,
60
+				IN mlx_uint32 read_data_size
61
+				);
62
+
63
+#endif /* MLXUTILS_INCLUDE_PUBLIC_MLX_ICMD_H_ */

+ 46
- 0
src/drivers/infiniband/mlx_utils/include/public/mlx_logging.h Visa fil

@@ -0,0 +1,46 @@
1
+#ifndef PUBLIC_INCLUDE_MLX_LOGGER_H_
2
+#define PUBLIC_INCLUDE_MLX_LOGGER_H_
3
+
4
+/*
5
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20
+ * 02110-1301, USA.
21
+ */
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+
25
+#include "../../../mlx_utils_flexboot/include/mlx_logging_priv.h"
26
+
27
+#define MLX_DEBUG_FATAL_ERROR(...)	MLX_DEBUG_FATAL_ERROR_PRIVATE(__VA_ARGS__)
28
+#define MLX_DEBUG_ERROR(...)		MLX_DEBUG_ERROR_PRIVATE(__VA_ARGS__)
29
+#define MLX_DEBUG_WARN(...)			MLX_DEBUG_WARN_PRIVATE(__VA_ARGS__)
30
+#define MLX_DEBUG_INFO1(...)		MLX_DEBUG_INFO1_PRIVATE(__VA_ARGS__)
31
+#define MLX_DEBUG_INFO2(...)		MLX_DEBUG_INFO2_PRIVATE(__VA_ARGS__)
32
+#define MLX_DBG_ERROR(...)			MLX_DBG_ERROR_PRIVATE(__VA_ARGS__)
33
+#define MLX_DBG_WARN(...)			MLX_DBG_WARN_PRIVATE(__VA_ARGS__)
34
+#define MLX_DBG_INFO1(...)			MLX_DBG_INFO1_PRIVATE(__VA_ARGS__)
35
+#define MLX_DBG_INFO2(...)			MLX_DBG_INFO2_PRIVATE(__VA_ARGS__)
36
+
37
+#define MLX_TRACE_1_START()				MLX_DBG_INFO1_PRIVATE("Start\n")
38
+#define MLX_TRACE_1_END()				MLX_DBG_INFO1_PRIVATE("End\n")
39
+#define MLX_TRACE_1_END_STATUS(status)	MLX_DBG_INFO1_PRIVATE("End (%s=%d)\n", #status,status)
40
+#define MLX_TRACE_2_START()				MLX_DBG_INFO2_PRIVATE("Start\n")
41
+#define MLX_TRACE_2_END()				MLX_DBG_INFO2_PRIVATE("End\n")
42
+#define MLX_TRACE_2_END_STATUS(status)	MLX_DBG_INFO2_PRIVATE("End (%s=%d)\n", #status,status)
43
+
44
+
45
+
46
+#endif /* PUBLIC_INCLUDE_MLX_LOGGER_H_ */

+ 115
- 0
src/drivers/infiniband/mlx_utils/include/public/mlx_memory.h Visa fil

@@ -0,0 +1,115 @@
1
+#ifndef MLXUTILS_INCLUDE_PUBLIC_MEMORY_H_
2
+#define MLXUTILS_INCLUDE_PUBLIC_MEMORY_H_
3
+
4
+/*
5
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20
+ * 02110-1301, USA.
21
+ */
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+
25
+#include "mlx_utils.h"
26
+
27
+
28
+mlx_status
29
+mlx_memory_alloc(
30
+				IN mlx_utils *utils,
31
+				IN mlx_size size,
32
+				OUT mlx_void **ptr
33
+				);
34
+
35
+mlx_status
36
+mlx_memory_zalloc(
37
+				IN mlx_utils *utils,
38
+				IN mlx_size size,
39
+				OUT mlx_void **ptr
40
+				);
41
+
42
+mlx_status
43
+mlx_memory_free(
44
+				IN mlx_utils *utils,
45
+				IN mlx_void **ptr
46
+				);
47
+mlx_status
48
+mlx_memory_alloc_dma(
49
+					IN mlx_utils *utils,
50
+					IN mlx_size size ,
51
+					IN mlx_size align,
52
+					OUT mlx_void **ptr
53
+					);
54
+
55
+mlx_status
56
+mlx_memory_free_dma(
57
+					IN mlx_utils *utils,
58
+					IN mlx_size size ,
59
+					IN mlx_void **ptr
60
+					);
61
+mlx_status
62
+mlx_memory_map_dma(
63
+					IN mlx_utils *utils,
64
+					IN mlx_void *Addr ,
65
+					IN mlx_size NumberOfBytes,
66
+					OUT mlx_physical_address *PhysAddr,
67
+					OUT mlx_void **Mapping
68
+					);
69
+
70
+mlx_status
71
+mlx_memory_ummap_dma(
72
+					IN mlx_utils *utils,
73
+					IN mlx_void *Mapping
74
+					);
75
+
76
+mlx_status
77
+mlx_memory_cmp(
78
+					IN mlx_utils *utils,
79
+					IN mlx_void *first_block,
80
+					IN mlx_void *second_block,
81
+					IN mlx_size size,
82
+					OUT mlx_uint32 *out
83
+					);
84
+
85
+mlx_status
86
+mlx_memory_set(
87
+					IN mlx_utils *utils,
88
+					IN mlx_void *block,
89
+					IN mlx_int32 value,
90
+					IN mlx_size size
91
+					);
92
+
93
+mlx_status
94
+mlx_memory_cpy(
95
+					IN mlx_utils *utils,
96
+					OUT mlx_void *destination_buffer,
97
+					IN mlx_void *source_buffer,
98
+					IN mlx_size length
99
+					);
100
+
101
+mlx_status
102
+mlx_memory_cpu_to_be32(
103
+			IN mlx_utils *utils,
104
+			IN mlx_uint32 source,
105
+			IN mlx_uint32 *destination
106
+			);
107
+
108
+mlx_status
109
+mlx_memory_be32_to_cpu(
110
+			IN mlx_utils *utils,
111
+			IN mlx_uint32 source,
112
+			IN mlx_uint32 *destination
113
+			);
114
+
115
+#endif /* STUB_MLXUTILS_INCLUDE_PUBLIC_MEMORY_H_ */

+ 78
- 0
src/drivers/infiniband/mlx_utils/include/public/mlx_pci.h Visa fil

@@ -0,0 +1,78 @@
1
+#ifndef STUB_MLXUTILS_INCLUDE_PUBLIC_PCI_H_
2
+#define STUB_MLXUTILS_INCLUDE_PUBLIC_PCI_H_
3
+
4
+/*
5
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20
+ * 02110-1301, USA.
21
+ */
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+
25
+#include "mlx_utils.h"
26
+
27
+typedef enum {
28
+			  MlxPciWidthUint8      = 0,
29
+			  MlxPciWidthUint16,
30
+			  MlxPciWidthUint32,
31
+			  MlxPciWidthUint64,
32
+} mlx_pci_width;
33
+
34
+mlx_status
35
+mlx_pci_init(
36
+			IN mlx_utils *utils
37
+			);
38
+
39
+mlx_status
40
+mlx_pci_read(
41
+			IN mlx_utils *utils,
42
+			IN mlx_pci_width width,
43
+			IN mlx_uint32 offset,
44
+			IN mlx_uintn count,
45
+			OUT mlx_void *buffer
46
+			);
47
+
48
+mlx_status
49
+mlx_pci_write(
50
+			IN mlx_utils *utils,
51
+			IN mlx_pci_width width,
52
+			IN mlx_uint32 offset,
53
+			IN mlx_uintn count,
54
+			IN mlx_void *buffer
55
+			);
56
+
57
+mlx_status
58
+mlx_pci_mem_read(
59
+				IN mlx_utils *utils,
60
+				IN mlx_pci_width width,
61
+				IN mlx_uint8 bar_index,
62
+				IN mlx_uint64 offset,
63
+				IN mlx_uintn count,
64
+				OUT mlx_void *buffer
65
+				);
66
+
67
+mlx_status
68
+mlx_pci_mem_write(
69
+				IN mlx_utils *utils,
70
+				IN mlx_pci_width width,
71
+				IN mlx_uint8 bar_index,
72
+				IN mlx_uint64 offset,
73
+				IN mlx_uintn count,
74
+				IN mlx_void *buffer
75
+				);
76
+
77
+
78
+#endif /* STUB_MLXUTILS_INCLUDE_PUBLIC_PCI_H_ */

+ 81
- 0
src/drivers/infiniband/mlx_utils/include/public/mlx_pci_gw.h Visa fil

@@ -0,0 +1,81 @@
1
+#ifndef INCLUDE_PUBLIC_MLX_PCI_GW_H_
2
+#define INCLUDE_PUBLIC_MLX_PCI_GW_H_
3
+
4
+/*
5
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20
+ * 02110-1301, USA.
21
+ */
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+
25
+#include "mlx_utils.h"
26
+
27
+#define PCI_GW_FIRST_CAPABILITY_POINTER_OFFSET 0x34
28
+
29
+#define PCI_GW_CAPABILITY_ID 0x9
30
+
31
+#define PCI_GW_CAPABILITY_ID_OFFSET 0x0
32
+#define PCI_GW_CAPABILITY_NEXT_POINTER_OFFSET 0x1
33
+#define PCI_GW_CAPABILITY_SPACE_OFFSET 0x4
34
+#define PCI_GW_CAPABILITY_STATUS_OFFSET 0x7
35
+#define PCI_GW_CAPABILITY_COUNTER_OFFSET 0x8
36
+#define PCI_GW_CAPABILITY_SEMAPHORE_OFFSET 0xC
37
+#define PCI_GW_CAPABILITY_ADDRESS_OFFSET 0x10
38
+#define PCI_GW_CAPABILITY_FLAG_OFFSET 0x10
39
+#define PCI_GW_CAPABILITY_DATA_OFFSET 0x14
40
+
41
+#define PCI_GW_SEMPHORE_TRIES 3000000
42
+#define PCI_GW_GET_OWNERSHIP_TRIES 5000
43
+#define PCI_GW_READ_FLAG_TRIES 3000000
44
+
45
+#define PCI_GW_WRITE_FLAG 0x80000000
46
+
47
+#define PCI_GW_SPACE_NODNIC 0x4
48
+#define PCI_GW_SPACE_ALL_ICMD 0x3
49
+#define PCI_GW_SPACE_SEMAPHORE 0xa
50
+#define PCI_GW_SPACE_CR0 0x2
51
+
52
+typedef mlx_uint32	mlx_pci_gw_buffer;
53
+
54
+
55
+mlx_status
56
+mlx_pci_gw_init(
57
+				IN mlx_utils *utils
58
+				);
59
+mlx_status
60
+mlx_pci_gw_teardown(
61
+				IN mlx_utils *utils
62
+				);
63
+mlx_status
64
+mlx_pci_gw_read(
65
+				IN mlx_utils *utils,
66
+				IN mlx_pci_gw_space space,
67
+				IN mlx_uint32 address,
68
+				OUT mlx_pci_gw_buffer *buffer
69
+				);
70
+
71
+mlx_status
72
+mlx_pci_gw_write(
73
+				IN mlx_utils *utils,
74
+				IN mlx_pci_gw_space space,
75
+				IN mlx_uint32 address,
76
+				IN mlx_pci_gw_buffer buffer
77
+				);
78
+
79
+
80
+
81
+#endif /* INCLUDE_PUBLIC_MLX_PCI_GW_H_ */

+ 27
- 0
src/drivers/infiniband/mlx_utils/include/public/mlx_types.h Visa fil

@@ -0,0 +1,27 @@
1
+#ifndef INCLUDE_PUBLIC_MLXTYPES_H_
2
+#define INCLUDE_PUBLIC_MLXTYPES_H_
3
+
4
+/*
5
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20
+ * 02110-1301, USA.
21
+ */
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+
25
+#include "../../../mlx_utils_flexboot/include/mlx_types_priv.h"
26
+
27
+#endif /* INCLUDE_PUBLIC_MLXBAIL_H_ */

+ 106
- 0
src/drivers/infiniband/mlx_utils/include/public/mlx_utils.h Visa fil

@@ -0,0 +1,106 @@
1
+#ifndef MLXUTILS_INCLUDE_PUBLIC_MLXUTILS_H_
2
+#define MLXUTILS_INCLUDE_PUBLIC_MLXUTILS_H_
3
+
4
+/*
5
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20
+ * 02110-1301, USA.
21
+ */
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+
25
+#include "mlx_logging.h"
26
+#include "mlx_types.h"
27
+
28
+#define IN
29
+#define OUT
30
+
31
+typedef mlx_uint16	mlx_pci_gw_space;
32
+
33
+typedef struct{
34
+	mlx_uint32	pci_cmd_offset;
35
+	mlx_pci_gw_space space;
36
+} __attribute__ (( packed )) mlx_pci_gw;
37
+
38
+typedef struct {
39
+	mlx_boolean icmd_opened;
40
+	mlx_boolean took_semaphore;
41
+	mlx_uint32 max_cmd_size;
42
+} __attribute__ (( packed )) mlx_icmd ;
43
+
44
+typedef  struct{
45
+	mlx_pci *pci;
46
+	mlx_pci_gw pci_gw;
47
+	mlx_icmd icmd;
48
+	void *lock;
49
+#ifdef DEVICE_CX3
50
+	/* ACCESS to BAR0 */
51
+	void *config;
52
+#endif
53
+} __attribute__ (( packed )) mlx_utils;
54
+
55
+mlx_status
56
+mlx_utils_init(
57
+				IN mlx_utils *utils,
58
+				IN mlx_pci *pci
59
+				);
60
+
61
+mlx_status
62
+mlx_utils_teardown(
63
+				IN mlx_utils *utils
64
+				);
65
+mlx_status
66
+mlx_utils_delay_in_ms(
67
+			IN mlx_uint32 msecs
68
+		);
69
+
70
+mlx_status
71
+mlx_utils_delay_in_us(
72
+			IN mlx_uint32 usecs
73
+		);
74
+
75
+mlx_status
76
+mlx_utils_ilog2(
77
+			IN mlx_uint32 i,
78
+			OUT mlx_uint32 *log
79
+		);
80
+
81
+mlx_status
82
+mlx_utils_init_lock(
83
+			IN OUT mlx_utils *utils
84
+		);
85
+
86
+mlx_status
87
+mlx_utils_free_lock(
88
+			IN OUT mlx_utils *utils
89
+		);
90
+
91
+mlx_status
92
+mlx_utils_acquire_lock (
93
+			IN OUT mlx_utils *utils
94
+		);
95
+
96
+mlx_status
97
+mlx_utils_release_lock (
98
+		IN OUT mlx_utils *utils
99
+		);
100
+
101
+mlx_status
102
+mlx_utils_rand (
103
+		IN mlx_utils *utils,
104
+		OUT mlx_uint32 *rand_num
105
+		);
106
+#endif /* STUB_MLXUTILS_INCLUDE_PUBLIC_MLXUTILS_H_ */

+ 54
- 0
src/drivers/infiniband/mlx_utils/mlx_lib/mlx_blink_leds/mlx_blink_leds.c Visa fil

@@ -0,0 +1,54 @@
1
+/*
2
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
3
+ *
4
+ * This program is free software; you can redistribute it and/or
5
+ * modify it under the terms of the GNU General Public License as
6
+ * published by the Free Software Foundation; either version 2 of the
7
+ * License, or any later version.
8
+ *
9
+ * This program is distributed in the hope that it will be useful, but
10
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
11
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
12
+ * General Public License for more details.
13
+ *
14
+ * You should have received a copy of the GNU General Public License
15
+ * along with this program; if not, write to the Free Software
16
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17
+ * 02110-1301, USA.
18
+ */
19
+
20
+FILE_LICENCE ( GPL2_OR_LATER );
21
+
22
+#include "../../mlx_lib/mlx_blink_leds/mlx_blink_leds.h"
23
+#include "../../include/public/mlx_memory.h"
24
+#include "../../include/public/mlx_bail.h"
25
+
26
+mlx_status
27
+mlx_blink_leds(
28
+		IN mlx_utils *utils,
29
+		IN mlx_uint16 secs
30
+		)
31
+{
32
+	mlx_status status = MLX_SUCCESS;
33
+	struct mlx_led_control led_control;
34
+	mlx_uint32 reg_status;
35
+
36
+	if (utils == NULL ) {
37
+		status = MLX_INVALID_PARAMETER;
38
+		goto bad_param;
39
+	}
40
+	mlx_memory_set(utils, &led_control, 0, sizeof(led_control));
41
+	led_control.beacon_duration = secs;
42
+	status = mlx_reg_access(utils, REG_ID_MLCR, REG_ACCESS_WRITE, &led_control, sizeof(led_control),
43
+			&reg_status);
44
+	MLX_CHECK_STATUS(utils, status, reg_err, "mlx_reg_access failed ");
45
+	if (reg_status != 0) {
46
+		MLX_DEBUG_ERROR(utils,"mlx_reg_access failed with status = %d\n", reg_status);
47
+		status = MLX_FAILED;
48
+		goto reg_err;
49
+	}
50
+reg_err:
51
+bad_param:
52
+	return status;
53
+}
54
+

+ 46
- 0
src/drivers/infiniband/mlx_utils/mlx_lib/mlx_blink_leds/mlx_blink_leds.h Visa fil

@@ -0,0 +1,46 @@
1
+#ifndef MLX_BLINK_LEDS_H_
2
+#define MLX_BLINK_LEDS_H_
3
+
4
+/*
5
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20
+ * 02110-1301, USA.
21
+ */
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+
25
+#include "../../mlx_lib/mlx_reg_access/mlx_reg_access.h"
26
+#include "../../include/public/mlx_utils.h"
27
+
28
+struct mlx_led_control {
29
+	mlx_uint32 reserved1	:16;
30
+	mlx_uint32 port	:8;
31
+	mlx_uint32 bla	:8;
32
+/* -------------- */
33
+	mlx_uint32 beacon_duration	:16;
34
+	mlx_uint32 reserved2	:16;
35
+/* -------------- */
36
+	mlx_uint32 beacon_remain	:16;
37
+	mlx_uint32 reserved3	:16;
38
+};
39
+
40
+mlx_status
41
+mlx_blink_leds(
42
+		IN mlx_utils *utils,
43
+		IN mlx_uint16 secs
44
+		);
45
+
46
+#endif /* MLX_NVCONFIG_H_ */

+ 180
- 0
src/drivers/infiniband/mlx_utils/mlx_lib/mlx_link_speed/mlx_link_speed.c Visa fil

@@ -0,0 +1,180 @@
1
+/*
2
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
3
+ *
4
+ * This program is free software; you can redistribute it and/or
5
+ * modify it under the terms of the GNU General Public License as
6
+ * published by the Free Software Foundation; either version 2 of the
7
+ * License, or any later version.
8
+ *
9
+ * This program is distributed in the hope that it will be useful, but
10
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
11
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
12
+ * General Public License for more details.
13
+ *
14
+ * You should have received a copy of the GNU General Public License
15
+ * along with this program; if not, write to the Free Software
16
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17
+ * 02110-1301, USA.
18
+ */
19
+
20
+FILE_LICENCE ( GPL2_OR_LATER );
21
+
22
+#include "../../mlx_lib/mlx_link_speed/mlx_link_speed.h"
23
+#include "../../include/public/mlx_memory.h"
24
+#include "../../include/public/mlx_bail.h"
25
+
26
+mlx_status
27
+mlx_set_link_speed(
28
+		IN mlx_utils *utils,
29
+		IN mlx_uint8 port_num,
30
+		IN LINK_SPEED_TYPE type,
31
+		IN LINK_SPEED speed
32
+		)
33
+{
34
+	mlx_status status = MLX_SUCCESS;
35
+	struct mlx_link_speed link_speed;
36
+	mlx_uint32 reg_status;
37
+
38
+	if (utils == NULL) {
39
+		status = MLX_INVALID_PARAMETER;
40
+		goto bad_param;
41
+	}
42
+
43
+	mlx_memory_set(utils, &link_speed, 0, sizeof(link_speed));
44
+
45
+	link_speed.loacl_port = port_num;
46
+	link_speed.proto_mask = 1 << type;
47
+
48
+	status = mlx_reg_access(utils, REG_ID_PTYS, REG_ACCESS_READ, &link_speed,
49
+			sizeof(link_speed), &reg_status);
50
+
51
+	MLX_CHECK_STATUS(utils, status, reg_err, "mlx_reg_access failed ");
52
+	if (reg_status != 0) {
53
+		MLX_DEBUG_ERROR(utils,"mlx_reg_access failed with status = %d\n", reg_status);
54
+		status = MLX_FAILED;
55
+		goto reg_err;
56
+	}
57
+	switch (speed) {
58
+	case LINK_SPEED_1GB:
59
+		link_speed.eth_proto_admin = link_speed.eth_proto_capability & LINK_SPEED_1GB_MASK;
60
+		break;
61
+	case LINK_SPEED_10GB:
62
+		link_speed.eth_proto_admin = link_speed.eth_proto_capability & LINK_SPEED_10GB_MASK;
63
+		break;
64
+	case LINK_SPEED_40GB:
65
+		link_speed.eth_proto_admin = link_speed.eth_proto_capability & LINK_SPEED_40GB_MASK;
66
+		break;
67
+	case LINK_SPEED_100GB:
68
+		link_speed.eth_proto_admin = link_speed.eth_proto_capability & LINK_SPEED_100GB_MASK;
69
+		break;
70
+	case LINK_SPEED_SDR:
71
+		link_speed.ib_proto_admin = link_speed.ib_proto_capability & LINK_SPEED_SDR_MASK;
72
+		break;
73
+	case LINK_SPEED_DEFAULT:
74
+		if (type == LINK_SPEED_ETH) {
75
+			link_speed.eth_proto_admin = link_speed.eth_proto_capability;
76
+		} else {
77
+			link_speed.ib_proto_admin = link_speed.ib_proto_capability;
78
+		}
79
+		break;
80
+	}
81
+	status = mlx_reg_access(utils, REG_ID_PTYS, REG_ACCESS_WRITE, &link_speed,
82
+				sizeof(link_speed), &reg_status);
83
+	MLX_CHECK_STATUS(utils, status, reg_err, "mlx_reg_access failed ");
84
+	if (reg_status != 0) {
85
+		MLX_DEBUG_ERROR(utils,"mlx_reg_access failed with status = %d\n", reg_status);
86
+		status = MLX_FAILED;
87
+		goto reg_err;
88
+	}
89
+reg_err:
90
+bad_param:
91
+	return status;
92
+}
93
+
94
+mlx_status
95
+mlx_get_max_speed(
96
+		IN mlx_utils *utils,
97
+		IN mlx_uint8 port_num,
98
+		IN LINK_SPEED_TYPE type,
99
+		OUT mlx_uint64 *speed
100
+		)
101
+{
102
+	mlx_status status = MLX_SUCCESS;
103
+	struct mlx_link_speed link_speed;
104
+	mlx_uint32 reg_status;
105
+	mlx_uint64 speed_giga = 0;
106
+	mlx_uint8  lanes_number = 1;
107
+
108
+	*speed = 0;
109
+	if (utils == NULL) {
110
+		status = MLX_INVALID_PARAMETER;
111
+		goto bad_param;
112
+	}
113
+
114
+	mlx_memory_set(utils, &link_speed, 0, sizeof(link_speed));
115
+
116
+	link_speed.loacl_port = port_num;
117
+	link_speed.proto_mask = 1 << type;
118
+
119
+	status = mlx_reg_access(utils, REG_ID_PTYS, REG_ACCESS_READ, &link_speed,
120
+			sizeof(link_speed), &reg_status);
121
+	MLX_CHECK_STATUS(utils, status, reg_err, "mlx_reg_access failed ");
122
+	if (reg_status != 0) {
123
+		MLX_DEBUG_ERROR(utils,"mlx_reg_access failed with status = %d\n", reg_status);
124
+		status = MLX_FAILED;
125
+		goto reg_err;
126
+	}
127
+
128
+	if ( type == LINK_SPEED_ETH ) {
129
+		if ( link_speed.eth_proto_capability & LINK_SPEED_100GB_MASK ) {
130
+			speed_giga = 100;
131
+		} else if ( link_speed.eth_proto_capability & LINK_SPEED_56GB_MASK ) {
132
+			speed_giga = 56;
133
+		} else if ( link_speed.eth_proto_capability & LINK_SPEED_50GB_MASK ) {
134
+			speed_giga = 50;
135
+		} else if ( link_speed.eth_proto_capability & LINK_SPEED_40GB_MASK ) {
136
+			speed_giga = 40;
137
+		} else if (link_speed.eth_proto_capability & LINK_SPEED_25GB_MASK) {
138
+			speed_giga = 25;
139
+		} else if ( link_speed.eth_proto_capability & LINK_SPEED_20GB_MASK ) {
140
+			speed_giga = 20;
141
+		} else if ( link_speed.eth_proto_capability & LINK_SPEED_10GB_MASK) {
142
+			speed_giga = 10;
143
+		} else if ( link_speed.eth_proto_capability & LINK_SPEED_1GB_MASK ) {
144
+			speed_giga = 1;
145
+		}
146
+	} else {
147
+		if ( link_speed.ib_proto_capability & LINK_SPEED_EDR_MASK ) {
148
+			speed_giga = 25;
149
+		} else if ( link_speed.ib_proto_capability & LINK_SPEED_EDR20_MASK ) {
150
+			speed_giga = 20;
151
+		} else if ( link_speed.ib_proto_capability & LINK_SPEED_FDR_MASK ) {
152
+			speed_giga = 14;
153
+		} else if ( link_speed.ib_proto_capability & LINK_SPEED_QDR_MASK ) {
154
+			speed_giga = 10;
155
+		} else if ( link_speed.ib_proto_capability & LINK_SPEED_DDR_MASK ) {
156
+			speed_giga = 5;
157
+		} else if ( link_speed.ib_proto_capability & LINK_SPEED_SDR_MASK ) {
158
+			speed_giga = 2.5;
159
+		}
160
+		if ( link_speed.ib_link_width_capability & LINK_SPEED_WITDH_12_MASK ) {
161
+			lanes_number = 12;
162
+		} else if ( link_speed.ib_link_width_capability & LINK_SPEED_WITDH_8_MASK ) {
163
+			lanes_number = 8;
164
+		} else if (link_speed.ib_link_width_capability & LINK_SPEED_WITDH_4_MASK ) {
165
+			lanes_number = 4;
166
+		} else if (link_speed.ib_link_width_capability & LINK_SPEED_WITDH_2_MASK ) {
167
+			lanes_number = 2;
168
+		} else if (link_speed.ib_link_width_capability & LINK_SPEED_WITDH_1_MASK ) {
169
+			lanes_number = 1;
170
+		}
171
+		speed_giga = speed_giga * lanes_number;
172
+	}
173
+	// Return data in bits
174
+	*speed = speed_giga * GIGA_TO_BIT;
175
+reg_err:
176
+bad_param:
177
+	return status;
178
+}
179
+
180
+

+ 145
- 0
src/drivers/infiniband/mlx_utils/mlx_lib/mlx_link_speed/mlx_link_speed.h Visa fil

@@ -0,0 +1,145 @@
1
+#ifndef MLX_LINK_SPEED_H_
2
+#define MLX_LINK_SPEED_H_
3
+
4
+/*
5
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20
+ * 02110-1301, USA.
21
+ */
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+
25
+#include "../../mlx_lib/mlx_reg_access/mlx_reg_access.h"
26
+#include "../../include/public/mlx_utils.h"
27
+
28
+#define LINK_SPEED_100GB_MASK        (ETH_SPEED_ENABLE_MASK_100GBASECR4 | ETH_SPEED_ENABLE_MASK_100GBASESR4 | ETH_SPEED_ENABLE_MASK_100GBASEKR4 | ETH_SPEED_ENABLE_MASK_100GBASELR4)
29
+#define LINK_SPEED_56GB_MASK         (ETH_SPEED_ENABLE_MASK_56GBASER4)
30
+#define LINK_SPEED_50GB_MASK         (ETH_SPEED_ENABLE_MASK_50GBASECR2 | ETH_SPEED_ENABLE_MASK_50GBASEKR2)
31
+#define LINK_SPEED_40GB_MASK         (ETH_SPEED_ENABLE_MASK_40GBASECR4 | ETH_SPEED_ENABLE_MASK_40GBASEKR4 | ETH_SPEED_ENABLE_MASK_40GBASESR4 | ETH_SPEED_ENABLE_MASK_40GBASELR4)
32
+#define LINK_SPEED_25GB_MASK         (ETH_SPEED_ENABLE_MASK_25GBASECR | ETH_SPEED_ENABLE_MASK_25GBASEKR | ETH_SPEED_ENABLE_MASK_25GBASESR)
33
+#define LINK_SPEED_20GB_MASK         (ETH_SPEED_ENABLE_MASK_20GBASER2)
34
+#define LINK_SPEED_10GB_MASK         (ETH_SPEED_ENABLE_MASK_10GBASECR | ETH_SPEED_ENABLE_MASK_10GBASESR | ETH_SPEED_ENABLE_MASK_10GBASELR | ETH_SPEED_ENABLE_MASK_10GBASEKR)
35
+#define LINK_SPEED_1GB_MASK          (ETH_SPEED_ENABLE_MASK_1000BASECX | ETH_SPEED_ENABLE_MASK_1000BASEKX | ETH_SPEED_ENABLE_MASK_100BaseTX | ETH_SPEED_ENABLE_MASK_1000BASET)
36
+
37
+#define LINK_SPEED_SDR_MASK 0x1
38
+#define LINK_SPEED_DDR_MASK 0x2
39
+#define LINK_SPEED_QDR_MASK 0xC
40
+#define LINK_SPEED_FDR_MASK 0x10
41
+#define LINK_SPEED_EDR20_MASK 0x200
42
+#define LINK_SPEED_EDR_MASK 0x20
43
+
44
+#define LINK_SPEED_WITDH_1_MASK 0x1
45
+#define LINK_SPEED_WITDH_2_MASK 0x2
46
+#define LINK_SPEED_WITDH_4_MASK 0x4
47
+#define LINK_SPEED_WITDH_8_MASK 0x8
48
+#define LINK_SPEED_WITDH_12_MASK 0x10
49
+
50
+#define GIGA_TO_BIT 0x40000000
51
+
52
+enum {
53
+    ETH_SPEED_ENABLE_MASK_1000BASECX  = 0x0001,
54
+    ETH_SPEED_ENABLE_MASK_1000BASEKX  = 0x0002,
55
+    ETH_SPEED_ENABLE_MASK_10GBASECX4  = 0x0004,
56
+    ETH_SPEED_ENABLE_MASK_10GBASEKX4  = 0x0008,
57
+    ETH_SPEED_ENABLE_MASK_10GBASEKR   = 0x0010,
58
+    ETH_SPEED_ENABLE_MASK_20GBASER2   = 0x0020,
59
+    ETH_SPEED_ENABLE_MASK_40GBASECR4  = 0x0040,
60
+    ETH_SPEED_ENABLE_MASK_40GBASEKR4  = 0x0080,
61
+    ETH_SPEED_ENABLE_MASK_56GBASER4   = 0x0100,
62
+    ETH_SPEED_ENABLE_MASK_10GBASECR   = 0x1000,
63
+    ETH_SPEED_ENABLE_MASK_10GBASESR   = 0x2000,
64
+    ETH_SPEED_ENABLE_MASK_10GBASELR   = 0x4000,
65
+    ETH_SPEED_ENABLE_MASK_40GBASESR4  = 0x8000,
66
+    ETH_SPEED_ENABLE_MASK_40GBASELR4  = 0x10000,
67
+    ETH_SPEED_ENABLE_MASK_50GBASEKR4  = 0x80000,
68
+    ETH_SPEED_ENABLE_MASK_100GBASECR4 = 0x100000,
69
+    ETH_SPEED_ENABLE_MASK_100GBASESR4 = 0x200000,
70
+    ETH_SPEED_ENABLE_MASK_100GBASEKR4 = 0x400000,
71
+    ETH_SPEED_ENABLE_MASK_100GBASELR4 = 0x800000,
72
+    ETH_SPEED_ENABLE_MASK_100BaseTX   = 0x1000000,
73
+    ETH_SPEED_ENABLE_MASK_1000BASET   = 0x2000000,
74
+    ETH_SPEED_ENABLE_MASK_10GBASET    = 0x4000000,
75
+    ETH_SPEED_ENABLE_MASK_25GBASECR   = 0x8000000,
76
+    ETH_SPEED_ENABLE_MASK_25GBASEKR   = 0x10000000,
77
+    ETH_SPEED_ENABLE_MASK_25GBASESR   = 0x20000000,
78
+    ETH_SPEED_ENABLE_MASK_50GBASECR2  = 0x40000000,
79
+    ETH_SPEED_ENABLE_MASK_50GBASEKR2  = 0x80000000,
80
+    ETH_SPEED_ENABLE_MASK_BAD         = 0xffff,
81
+};
82
+
83
+
84
+typedef enum {
85
+	LINK_SPEED_IB = 0,
86
+	LINK_SPEED_FC,
87
+	LINK_SPEED_ETH,
88
+} LINK_SPEED_TYPE;
89
+
90
+typedef enum {
91
+	LINK_SPEED_1GB = 0,
92
+	LINK_SPEED_10GB,
93
+	LINK_SPEED_40GB,
94
+	LINK_SPEED_100GB,
95
+	LINK_SPEED_SDR,
96
+	LINK_SPEED_DEFAULT,
97
+} LINK_SPEED;
98
+
99
+struct mlx_link_speed {
100
+	mlx_uint32 proto_mask	:3;
101
+	mlx_uint32 reserved1	:13;
102
+	mlx_uint32 loacl_port	:8;
103
+	mlx_uint32 reserved2	:8;
104
+	/* -------------- */
105
+	mlx_uint32 reserved3	:32;
106
+	/* -------------- */
107
+	mlx_uint32 reserved4	:32;
108
+	/* -------------- */
109
+	mlx_uint32 eth_proto_capability	:32;
110
+	/* -------------- */
111
+	mlx_uint32 ib_proto_capability	:16;
112
+	mlx_uint32 ib_link_width_capability	:16;
113
+	/* -------------- */
114
+	mlx_uint32 reserved5	:32;
115
+	/* -------------- */
116
+	mlx_uint32 eth_proto_admin	:32;
117
+	/* -------------- */
118
+	mlx_uint32 ib_proto_admin	:16;
119
+	mlx_uint32 ib_link_width_admin	:16;
120
+	/* -------------- */
121
+	mlx_uint32 reserved6	:32;
122
+	/* -------------- */
123
+	mlx_uint32 eth_proto_oper	:32;
124
+	/* -------------- */
125
+	mlx_uint32 ib_proto_oper	:16;
126
+	mlx_uint32 ib_link_width_oper	:16;
127
+};
128
+
129
+mlx_status
130
+mlx_set_link_speed(
131
+		IN mlx_utils *utils,
132
+		IN mlx_uint8 port_num,
133
+		IN LINK_SPEED_TYPE type,
134
+		IN LINK_SPEED speed
135
+		);
136
+
137
+mlx_status
138
+mlx_get_max_speed(
139
+		IN mlx_utils *utils,
140
+		IN mlx_uint8 port_num,
141
+		IN LINK_SPEED_TYPE type,
142
+		OUT mlx_uint64 *speed
143
+		);
144
+
145
+#endif /* MLX_LINK_SPEED_H_ */

+ 60
- 0
src/drivers/infiniband/mlx_utils/mlx_lib/mlx_mtu/mlx_mtu.c Visa fil

@@ -0,0 +1,60 @@
1
+/*
2
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
3
+ *
4
+ * This program is free software; you can redistribute it and/or
5
+ * modify it under the terms of the GNU General Public License as
6
+ * published by the Free Software Foundation; either version 2 of the
7
+ * License, or any later version.
8
+ *
9
+ * This program is distributed in the hope that it will be useful, but
10
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
11
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
12
+ * General Public License for more details.
13
+ *
14
+ * You should have received a copy of the GNU General Public License
15
+ * along with this program; if not, write to the Free Software
16
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17
+ * 02110-1301, USA.
18
+ */
19
+
20
+FILE_LICENCE ( GPL2_OR_LATER );
21
+
22
+#include "mlx_mtu.h"
23
+#include "mlx_memory.h"
24
+#include "mlx_bail.h"
25
+
26
+mlx_status
27
+mlx_get_max_mtu(
28
+		IN mlx_utils 	*utils,
29
+		IN mlx_uint8 	port_num,
30
+		OUT mlx_uint32 	*max_mtu
31
+		)
32
+{
33
+	mlx_status status = MLX_SUCCESS;
34
+	struct mlx_mtu mtu;
35
+	mlx_uint32 reg_status;
36
+	*max_mtu = 0;
37
+
38
+	if (utils == NULL) {
39
+		status = MLX_INVALID_PARAMETER;
40
+		goto bad_param;
41
+	}
42
+
43
+	mlx_memory_set(utils, &mtu, 0, sizeof(mtu));
44
+
45
+	mtu.local_port = port_num;
46
+
47
+	status = mlx_reg_access(utils, REG_ID_PMTU, REG_ACCESS_READ, &mtu,
48
+			sizeof(mtu), &reg_status);
49
+	MLX_CHECK_STATUS(utils, status, reg_err, "mlx_reg_access failed ");
50
+	if (reg_status != 0) {
51
+		MLX_DEBUG_ERROR(utils,"mlx_reg_access failed with status = %d\n", reg_status);
52
+		status = MLX_FAILED;
53
+		goto reg_err;
54
+	}
55
+	// Return data in bits
56
+	*max_mtu = mtu.max_mtu * BYTE_TO_BIT;
57
+reg_err:
58
+bad_param:
59
+	return status;
60
+}

+ 52
- 0
src/drivers/infiniband/mlx_utils/mlx_lib/mlx_mtu/mlx_mtu.h Visa fil

@@ -0,0 +1,52 @@
1
+#ifndef MLX_MTU_H_
2
+#define MLX_MTU_H_
3
+
4
+/*
5
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20
+ * 02110-1301, USA.
21
+ */
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+
25
+#include "mlx_reg_access.h"
26
+#include "mlx_utils.h"
27
+
28
+#define BYTE_TO_BIT	0x8
29
+
30
+struct mlx_mtu {
31
+	mlx_uint32 reserved1	:16;
32
+	mlx_uint32 local_port	:8;
33
+	mlx_uint32 reserved2	:8;
34
+	/* -------------- */
35
+	mlx_uint32 reserved3	:16;
36
+	mlx_uint32 max_mtu		:16;
37
+	/* -------------- */
38
+	mlx_uint32 reserved4	:16;
39
+	mlx_uint32 admin_mtu	:16;
40
+	/* -------------- */
41
+	mlx_uint32 reserved5	:16;
42
+	mlx_uint32 oper_mtu		:16;
43
+};
44
+
45
+mlx_status
46
+mlx_get_max_mtu(
47
+		IN mlx_utils 	*utils,
48
+		IN mlx_uint8 	port_num,
49
+		OUT mlx_uint32 	*max_mtu
50
+		);
51
+
52
+#endif /* MLX_MTU_H_ */

+ 295
- 0
src/drivers/infiniband/mlx_utils/mlx_lib/mlx_nvconfig/mlx_nvconfig.c Visa fil

@@ -0,0 +1,295 @@
1
+/*
2
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
3
+ *
4
+ * This program is free software; you can redistribute it and/or
5
+ * modify it under the terms of the GNU General Public License as
6
+ * published by the Free Software Foundation; either version 2 of the
7
+ * License, or any later version.
8
+ *
9
+ * This program is distributed in the hope that it will be useful, but
10
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
11
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
12
+ * General Public License for more details.
13
+ *
14
+ * You should have received a copy of the GNU General Public License
15
+ * along with this program; if not, write to the Free Software
16
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17
+ * 02110-1301, USA.
18
+ */
19
+
20
+FILE_LICENCE ( GPL2_OR_LATER );
21
+
22
+#include "../../mlx_lib/mlx_nvconfig/mlx_nvconfig.h"
23
+#include "../../include/public/mlx_memory.h"
24
+#include "../../include/public/mlx_bail.h"
25
+
26
+#define TlvMappingEntry( _tlv_type, _real_tlv_type, _class_code, _fw_reset_needed) { \
27
+  .tlv_type = _tlv_type,                     \
28
+  .real_tlv_type = _real_tlv_type,                   \
29
+  .class_code = _class_code,                  \
30
+  .fw_reset_needed = _fw_reset_needed,        \
31
+  }
32
+
33
+struct nvconfig_tlv_mapping nvconfig_tlv_mapping[] = {
34
+		TlvMappingEntry(0x10, 0x10, NVRAM_TLV_CLASS_HOST, TRUE),
35
+		TlvMappingEntry(0x12, 0x12, NVRAM_TLV_CLASS_PHYSICAL_PORT, TRUE),
36
+		TlvMappingEntry(0x80, 0x80, NVRAM_TLV_CLASS_GLOBAL, TRUE),
37
+		TlvMappingEntry(0x81, 0x81, NVRAM_TLV_CLASS_GLOBAL, TRUE),
38
+		TlvMappingEntry(0x100, 0x100, NVRAM_TLV_CLASS_GLOBAL, TRUE),
39
+		TlvMappingEntry(0x2001, 0x195, NVRAM_TLV_CLASS_HOST, FALSE),
40
+		TlvMappingEntry(0x2010, 0x210, NVRAM_TLV_CLASS_HOST, FALSE),
41
+		TlvMappingEntry(0x2011, 0x211, NVRAM_TLV_CLASS_GLOBAL, FALSE),
42
+		TlvMappingEntry(0x2020, 0x2020, NVRAM_TLV_CLASS_PHYSICAL_PORT, FALSE),
43
+		TlvMappingEntry(0x2021, 0x221, NVRAM_TLV_CLASS_HOST, FALSE),
44
+		TlvMappingEntry(0x2023, 0x223, NVRAM_TLV_CLASS_HOST, FALSE),
45
+		TlvMappingEntry(0x2100, 0x230, NVRAM_TLV_CLASS_HOST, FALSE),
46
+		TlvMappingEntry(0x2101, 0x231, NVRAM_TLV_CLASS_HOST, FALSE),
47
+		TlvMappingEntry(0x2102, 0x232, NVRAM_TLV_CLASS_HOST, FALSE),
48
+		TlvMappingEntry(0x2103, 0x233, NVRAM_TLV_CLASS_HOST, FALSE),
49
+		TlvMappingEntry(0x2104, 0x234, NVRAM_TLV_CLASS_HOST, FALSE),
50
+		TlvMappingEntry(0x2105, 0x235, NVRAM_TLV_CLASS_HOST, FALSE),
51
+		TlvMappingEntry(0x2106, 0x236, NVRAM_TLV_CLASS_HOST, FALSE),
52
+		TlvMappingEntry(0x2107, 0x237, NVRAM_TLV_CLASS_HOST, FALSE),
53
+		TlvMappingEntry(0x2108, 0x238, NVRAM_TLV_CLASS_HOST, FALSE),
54
+		TlvMappingEntry(0x2109, 0x239, NVRAM_TLV_CLASS_HOST, FALSE),
55
+		TlvMappingEntry(0x210A, 0x23A, NVRAM_TLV_CLASS_HOST, FALSE),
56
+		TlvMappingEntry(0x2200, 0x240, NVRAM_TLV_CLASS_HOST, FALSE),
57
+		TlvMappingEntry(0x2201, 0x241, NVRAM_TLV_CLASS_HOST, FALSE),
58
+		TlvMappingEntry(0x2202, 0x242, NVRAM_TLV_CLASS_HOST, FALSE),
59
+		TlvMappingEntry(0x2203, 0x243, NVRAM_TLV_CLASS_HOST, FALSE),
60
+		TlvMappingEntry(0x2204, 0x244, NVRAM_TLV_CLASS_HOST, FALSE),
61
+		TlvMappingEntry(0x2205, 0x245, NVRAM_TLV_CLASS_HOST, FALSE),
62
+		TlvMappingEntry(0x2207, 0x247, NVRAM_TLV_CLASS_HOST, FALSE),
63
+		TlvMappingEntry(0, 0, 0, 0),
64
+};
65
+
66
+static
67
+mlx_status
68
+nvconfig_set_fw_reset_level(
69
+		IN mlx_utils *utils,
70
+		IN	mlx_uint16	tlv_type
71
+		)
72
+{
73
+#define WARM_REBOOT_RESET ((mlx_uint64)0x1 << 38)
74
+	mlx_status status = MLX_SUCCESS;
75
+	mlx_uint32 reg_status;
76
+	mlx_uint64 mfrl = WARM_REBOOT_RESET ;
77
+	mlx_uint8 index = 0;
78
+	mlx_boolean reset_needed = FALSE;
79
+
80
+	for (index = 0 ; nvconfig_tlv_mapping[index].tlv_type != 0 ; index++) {
81
+		if (nvconfig_tlv_mapping[index].tlv_type == tlv_type) {
82
+			reset_needed = nvconfig_tlv_mapping[index].fw_reset_needed;
83
+		}
84
+	}
85
+
86
+	if (reset_needed == FALSE) {
87
+		goto no_fw_reset_needed;
88
+	}
89
+	status = mlx_reg_access(utils, REG_ID_MFRL, REG_ACCESS_WRITE, &mfrl, sizeof(mfrl),
90
+				&reg_status);
91
+	MLX_CHECK_STATUS(utils, status, reg_err, "mlx_reg_access failed ");
92
+
93
+	if (reg_status != 0) {
94
+		MLX_DEBUG_ERROR(utils,"nvconfig_set_fw_reset_level failed with status = %d\n", reg_status);
95
+		status = MLX_FAILED;
96
+		goto reg_err;
97
+	}
98
+reg_err:
99
+no_fw_reset_needed:
100
+	return status;
101
+}
102
+
103
+
104
+static
105
+mlx_status
106
+nvconfig_get_tlv_type_and_class(
107
+		IN	mlx_uint16	tlv_type,
108
+		OUT mlx_uint16	*real_tlv_type,
109
+		OUT NVRAM_CLASS_CODE *class_code
110
+		)
111
+{
112
+	mlx_uint8 index = 0;
113
+	for ( ; nvconfig_tlv_mapping[index].tlv_type != 0 ; index ++) {
114
+		if ( nvconfig_tlv_mapping[index].tlv_type == tlv_type) {
115
+			*real_tlv_type = nvconfig_tlv_mapping[index].real_tlv_type;
116
+			*class_code = nvconfig_tlv_mapping[index].class_code;
117
+			return MLX_SUCCESS;
118
+		}
119
+	}
120
+	return MLX_NOT_FOUND;
121
+}
122
+static
123
+void
124
+nvconfig_fill_tlv_type(
125
+		IN mlx_uint8 port,
126
+		IN NVRAM_CLASS_CODE class_code,
127
+		IN mlx_uint16 tlv_type,
128
+		OUT union nvconfig_tlv_type *nvconfig_tlv_type
129
+		)
130
+{
131
+	switch (class_code) {
132
+	case NVRAM_TLV_CLASS_GLOBAL:
133
+		nvconfig_tlv_type->global.param_class = NVRAM_TLV_CLASS_GLOBAL;
134
+		nvconfig_tlv_type->global.param_idx = tlv_type;
135
+		break;
136
+	case NVRAM_TLV_CLASS_HOST:
137
+		nvconfig_tlv_type->per_host.param_class = NVRAM_TLV_CLASS_HOST;
138
+		nvconfig_tlv_type->per_host.param_idx = tlv_type;
139
+		break;
140
+	case NVRAM_TLV_CLASS_PHYSICAL_PORT:
141
+		nvconfig_tlv_type->per_port.param_class = NVRAM_TLV_CLASS_PHYSICAL_PORT;
142
+		nvconfig_tlv_type->per_port.param_idx = tlv_type;
143
+		nvconfig_tlv_type->per_port.port = port;
144
+		break;
145
+	}
146
+}
147
+mlx_status
148
+nvconfig_query_capability(
149
+		IN mlx_utils *utils,
150
+		IN mlx_uint8 port,
151
+		IN mlx_uint16 tlv_type,
152
+		OUT mlx_boolean *read_supported,
153
+		OUT mlx_boolean *write_supported
154
+		)
155
+{
156
+	mlx_status status = MLX_SUCCESS;
157
+	struct nvconfig_nvqc nvqc;
158
+	mlx_uint32 reg_status;
159
+	NVRAM_CLASS_CODE class_code;
160
+	mlx_uint16 real_tlv_type;
161
+
162
+	if (utils == NULL || read_supported == NULL || write_supported == NULL) {
163
+		status = MLX_INVALID_PARAMETER;
164
+		goto bad_param;
165
+	}
166
+
167
+	status = nvconfig_get_tlv_type_and_class(tlv_type, &real_tlv_type, &class_code);
168
+	MLX_CHECK_STATUS(utils, status, tlv_not_supported, "tlv not supported");
169
+
170
+	mlx_memory_set(utils, &nvqc, 0, sizeof(nvqc));
171
+	nvconfig_fill_tlv_type(port, class_code, real_tlv_type, &nvqc.tlv_type);
172
+
173
+	status = mlx_reg_access(utils, REG_ID_NVQC, REG_ACCESS_READ, &nvqc, sizeof(nvqc),
174
+			&reg_status);
175
+	MLX_CHECK_STATUS(utils, status, reg_err, "mlx_reg_access failed ");
176
+	if (reg_status != 0) {
177
+		MLX_DEBUG_ERROR(utils,"mlx_reg_access failed with status = %d\n", reg_status);
178
+		status = MLX_FAILED;
179
+		goto reg_err;
180
+	}
181
+	*read_supported = nvqc.support_rd;
182
+	*write_supported = nvqc.support_wr;
183
+reg_err:
184
+tlv_not_supported:
185
+bad_param:
186
+	return status;
187
+}
188
+
189
+mlx_status
190
+nvconfig_nvdata_invalidate(
191
+		IN mlx_utils *utils,
192
+		IN mlx_uint8 port,
193
+		IN mlx_uint16 tlv_type
194
+		)
195
+{
196
+	mlx_status status = MLX_SUCCESS;
197
+	struct nvconfig_header nv_header;
198
+	mlx_uint32 reg_status;
199
+	NVRAM_CLASS_CODE class_code;
200
+	mlx_uint16 real_tlv_type;
201
+
202
+	if (utils == NULL) {
203
+		status = MLX_INVALID_PARAMETER;
204
+		goto bad_param;
205
+	}
206
+
207
+	status = nvconfig_get_tlv_type_and_class(tlv_type, &real_tlv_type, &class_code);
208
+	MLX_CHECK_STATUS(utils, status, tlv_not_supported, "tlv not supported");
209
+
210
+	mlx_memory_set(utils, &nv_header, 0, sizeof(nv_header));
211
+	nvconfig_fill_tlv_type(port, class_code, real_tlv_type, &nv_header.tlv_type);
212
+
213
+	status = mlx_reg_access(utils, REG_ID_NVDI, REG_ACCESS_WRITE, &nv_header, sizeof(nv_header),
214
+			&reg_status);
215
+	MLX_CHECK_STATUS(utils, status, reg_err, "mlx_reg_access failed ");
216
+	if (reg_status != 0) {
217
+		MLX_DEBUG_ERROR(utils,"mlx_reg_access failed with status = %d\n", reg_status);
218
+		status = MLX_FAILED;
219
+		goto reg_err;
220
+	}
221
+reg_err:
222
+tlv_not_supported:
223
+bad_param:
224
+	return status;
225
+}
226
+
227
+mlx_status
228
+nvconfig_nvdata_access(
229
+		IN mlx_utils *utils,
230
+		IN mlx_uint8 port,
231
+		IN mlx_uint16 tlv_type,
232
+		IN REG_ACCESS_OPT opt,
233
+		IN mlx_size data_size,
234
+		IN NV_DEFAULT_OPT def_en,
235
+		IN OUT mlx_uint8 *version,
236
+		IN OUT mlx_void *data
237
+		)
238
+{
239
+	mlx_status status = MLX_SUCCESS;
240
+	struct nvconfig_nvda nvda;
241
+	mlx_uint32 reg_status;
242
+	mlx_uint32 real_size_to_read;
243
+	mlx_uint32 index;
244
+	NVRAM_CLASS_CODE class_code;
245
+	mlx_uint16 real_tlv_type;
246
+	mlx_size data_size_align_to_dword;
247
+
248
+	if (utils == NULL || data == NULL || data_size > NVCONFIG_MAX_TLV_SIZE) {
249
+		status = MLX_INVALID_PARAMETER;
250
+		goto bad_param;
251
+	}
252
+
253
+	status = nvconfig_get_tlv_type_and_class(tlv_type, &real_tlv_type, &class_code);
254
+	MLX_CHECK_STATUS(utils, status, tlv_not_supported, "tlv not supported");
255
+
256
+	data_size_align_to_dword = ((data_size + 3) / sizeof(mlx_uint32)) * sizeof(mlx_uint32);
257
+	mlx_memory_set(utils, &nvda, 0, sizeof(nvda));
258
+	nvda.nv_header.length = data_size_align_to_dword;
259
+	nvda.nv_header.rd_en = 0;
260
+	nvda.nv_header.def_en = def_en;
261
+	nvda.nv_header.over_en = 1;
262
+	nvda.nv_header.version = *version;
263
+
264
+	nvconfig_fill_tlv_type(port, class_code, real_tlv_type, &nvda.nv_header.tlv_type);
265
+
266
+	mlx_memory_cpy(utils, nvda.data, data, data_size);
267
+	for (index = 0 ; index * 4 < NVCONFIG_MAX_TLV_SIZE ; index++) {
268
+		mlx_memory_be32_to_cpu(utils,(((mlx_uint32 *)nvda.data)[index]), ((mlx_uint32 *)nvda.data) + index);
269
+	}
270
+	status = mlx_reg_access(utils, REG_ID_NVDA, opt, &nvda,
271
+			data_size_align_to_dword + sizeof(nvda.nv_header), &reg_status);
272
+	MLX_CHECK_STATUS(utils, status, reg_err, "mlx_reg_access failed ");
273
+	if (reg_status != 0) {
274
+		MLX_DEBUG_ERROR(utils,"mlx_reg_access failed with status = %d\n", reg_status);
275
+		status = MLX_FAILED;
276
+		goto reg_err;
277
+	}
278
+	for (index = 0 ; index * 4 < NVCONFIG_MAX_TLV_SIZE ; index++) {
279
+		mlx_memory_cpu_to_be32(utils,(((mlx_uint32 *)nvda.data)[index]), ((mlx_uint32 *)nvda.data) + index);
280
+	}
281
+	if (opt == REG_ACCESS_READ) {
282
+		real_size_to_read = (nvda.nv_header.length > data_size) ? data_size :
283
+				nvda.nv_header.length;
284
+		mlx_memory_cpy(utils, data, nvda.data, real_size_to_read);
285
+		*version = nvda.nv_header.version;
286
+	} else {
287
+		nvconfig_set_fw_reset_level(utils, tlv_type);
288
+	}
289
+reg_err:
290
+tlv_not_supported:
291
+bad_param:
292
+	return status;
293
+}
294
+
295
+

+ 140
- 0
src/drivers/infiniband/mlx_utils/mlx_lib/mlx_nvconfig/mlx_nvconfig.h Visa fil

@@ -0,0 +1,140 @@
1
+#ifndef MLX_NVCONFIG_H_
2
+#define MLX_NVCONFIG_H_
3
+
4
+/*
5
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20
+ * 02110-1301, USA.
21
+ */
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+
25
+#include "../mlx_reg_access/mlx_reg_access.h"
26
+#include "../../include/public/mlx_utils.h"
27
+
28
+typedef enum {
29
+	NVRAM_TLV_CLASS_GLOBAL = 0,
30
+	NVRAM_TLV_CLASS_PHYSICAL_PORT = 1,
31
+	NVRAM_TLV_CLASS_HOST = 3,
32
+} NVRAM_CLASS_CODE;
33
+
34
+struct nvconfig_tlv_type_per_port {
35
+	 mlx_uint32 param_idx	:16;
36
+	 mlx_uint32 port		:8;
37
+	 mlx_uint32 param_class	:8;
38
+};
39
+
40
+struct nvconfig_tlv_type_per_host {
41
+	mlx_uint32 param_idx	:10;
42
+	mlx_uint32 function		:8;
43
+	mlx_uint32 host			:6;
44
+	mlx_uint32 param_class	:8;
45
+};
46
+
47
+struct nvconfig_tlv_type_global {
48
+	mlx_uint32 param_idx	:24;
49
+	mlx_uint32 param_class	:8;
50
+};
51
+
52
+struct nvconfig_tlv_mapping{
53
+	mlx_uint16	tlv_type;
54
+	mlx_uint16	real_tlv_type;
55
+	NVRAM_CLASS_CODE class_code;
56
+	mlx_boolean fw_reset_needed;
57
+};
58
+
59
+union nvconfig_tlv_type {
60
+	struct nvconfig_tlv_type_per_port per_port;
61
+	struct nvconfig_tlv_type_per_host per_host;
62
+	struct nvconfig_tlv_type_global global;
63
+};
64
+
65
+
66
+struct nvconfig_nvqc {
67
+	union nvconfig_tlv_type tlv_type;
68
+/* -------------- */
69
+	 mlx_uint32 support_rd	:1; /*the configuration item is supported and can be read */
70
+	 mlx_uint32 support_wr	:1; /*the configuration item is supported and can be updated */
71
+	 mlx_uint32 reserved1	:2;
72
+	 mlx_uint32 version		:4; /*The maximum version of the configuration item currently supported by the firmware. */
73
+	 mlx_uint32 reserved2	:24;
74
+};
75
+
76
+
77
+struct nvconfig_header {
78
+	 mlx_uint32 length		:9; /*Size of configuration item data in bytes between 0..256 */
79
+	 mlx_uint32 reserved0	:3;
80
+	 mlx_uint32 version		:4; /* Configuration item version */
81
+	 mlx_uint32 reserved1	:7;
82
+
83
+	 mlx_uint32 def_en		:1; /*Choose whether to access the default value or the user-defined value.
84
+									0x0 Read or write the user-defined value.
85
+									0x1 Read the default value (only valid for reads).*/
86
+
87
+	 mlx_uint32 rd_en		:1; /*enables reading the TLV by lower priorities
88
+									0 - TLV can be read by the subsequent lifecycle priorities.
89
+									1 - TLV cannot be read by the subsequent lifecycle priorities. */
90
+	 mlx_uint32 over_en		:1; /*enables overwriting the TLV by lower priorities
91
+									0 - Can only be overwritten by the current lifecycle priority
92
+									1 - Allowed to be overwritten by subsequent lifecycle priorities */
93
+	 mlx_uint32 header_type	:2;
94
+	 mlx_uint32 priority		:2;
95
+	 mlx_uint32 valid	:2;
96
+/* -------------- */
97
+	 union nvconfig_tlv_type tlv_type;;
98
+/* -------------- */
99
+	mlx_uint32 crc			:16;
100
+	mlx_uint32 reserved		:16;
101
+};
102
+
103
+#define NVCONFIG_MAX_TLV_SIZE 256
104
+
105
+struct nvconfig_nvda {
106
+	struct nvconfig_header nv_header;
107
+	mlx_uint8 data[NVCONFIG_MAX_TLV_SIZE];
108
+};
109
+
110
+
111
+mlx_status
112
+nvconfig_query_capability(
113
+		IN mlx_utils *utils,
114
+		IN mlx_uint8 port,
115
+		IN mlx_uint16 tlv_type,
116
+		OUT mlx_boolean *read_supported,
117
+		OUT mlx_boolean *write_supported
118
+		);
119
+
120
+
121
+mlx_status
122
+nvconfig_nvdata_invalidate(
123
+		IN mlx_utils *utils,
124
+		IN mlx_uint8 port,
125
+		IN mlx_uint16 tlv_type
126
+		);
127
+
128
+mlx_status
129
+nvconfig_nvdata_access(
130
+		IN mlx_utils *utils,
131
+		IN mlx_uint8 port,
132
+		IN mlx_uint16 tlv_type,
133
+		IN REG_ACCESS_OPT opt,
134
+		IN mlx_size data_size,
135
+		IN NV_DEFAULT_OPT def_en,
136
+		IN OUT mlx_uint8 *version,
137
+		IN OUT mlx_void *data
138
+		);
139
+
140
+#endif /* MLX_NVCONFIG_H_ */

+ 482
- 0
src/drivers/infiniband/mlx_utils/mlx_lib/mlx_nvconfig/mlx_nvconfig_defaults.c Visa fil

@@ -0,0 +1,482 @@
1
+/*
2
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
3
+ *
4
+ * This program is free software; you can redistribute it and/or
5
+ * modify it under the terms of the GNU General Public License as
6
+ * published by the Free Software Foundation; either version 2 of the
7
+ * License, or any later version.
8
+ *
9
+ * This program is distributed in the hope that it will be useful, but
10
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
11
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
12
+ * General Public License for more details.
13
+ *
14
+ * You should have received a copy of the GNU General Public License
15
+ * along with this program; if not, write to the Free Software
16
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17
+ * 02110-1301, USA.
18
+ */
19
+
20
+FILE_LICENCE( GPL2_OR_LATER);
21
+
22
+#include "../../mlx_lib/mlx_nvconfig/mlx_nvconfig.h"
23
+#include "../../include/public/mlx_memory.h"
24
+#include "../../include/public/mlx_bail.h"
25
+#include "../../mlx_lib/mlx_nvconfig/mlx_nvconfig_defaults.h"
26
+
27
+struct tlv_default {
28
+	mlx_uint16 tlv_type;
29
+	mlx_size data_size;
30
+	mlx_status (*set_defaults)( IN void *data, IN int status,
31
+			OUT void *def_struct);
32
+};
33
+
34
+#define TlvDefaultEntry( _tlv_type, _data_size, _set_defaults) { \
35
+  .tlv_type = _tlv_type,                     \
36
+  .data_size = sizeof ( _data_size ),                   \
37
+  .set_defaults = _set_defaults,                  \
38
+  }
39
+
40
+static
41
+mlx_status
42
+nvconfig_get_boot_default_conf(
43
+		IN void *data,
44
+		IN int status,
45
+		OUT void *def_struct
46
+		)
47
+{
48
+	union mlx_nvconfig_nic_boot_conf *nic_boot_conf =
49
+			(union mlx_nvconfig_nic_boot_conf *) data;
50
+	struct mlx_nvconfig_port_conf_defaults *port_conf_def =
51
+			(struct mlx_nvconfig_port_conf_defaults *) def_struct;
52
+
53
+	/* boot_option_rom_en is deprecated - enabled always */
54
+	port_conf_def->boot_option_rom_en = DEFAULT_OPTION_ROM_EN;
55
+
56
+	MLX_CHECK_STATUS(NULL, status, nvdata_access_err,
57
+			"TLV not found. Using hard-coded defaults ");
58
+	port_conf_def->boot_vlan = nic_boot_conf->vlan_id;
59
+	port_conf_def->boot_protocol = nic_boot_conf->legacy_boot_prot;
60
+	port_conf_def->boot_retry_count = nic_boot_conf->boot_retry_count;
61
+	port_conf_def->boot_vlan_en = nic_boot_conf->en_vlan;
62
+
63
+	return MLX_SUCCESS;
64
+
65
+nvdata_access_err:
66
+	port_conf_def->boot_vlan = DEFAULT_BOOT_VLAN;
67
+	port_conf_def->boot_protocol = DEFAULT_BOOT_PROTOCOL;
68
+
69
+	return status;
70
+}
71
+
72
+static
73
+mlx_status
74
+nvconfig_get_boot_ext_default_conf(
75
+		IN void *data,
76
+		IN int status,
77
+		OUT void *def_struct
78
+		)
79
+{
80
+	union mlx_nvconfig_nic_boot_ext_conf *nic_boot_ext_conf =
81
+			(union mlx_nvconfig_nic_boot_ext_conf *) data;
82
+	struct mlx_nvconfig_port_conf_defaults *port_conf_def =
83
+			(struct mlx_nvconfig_port_conf_defaults *) def_struct;
84
+
85
+	MLX_CHECK_STATUS(NULL, status, nvdata_access_err,
86
+			"TLV not found. Using hard-coded defaults ");
87
+	port_conf_def->linkup_timeout = nic_boot_ext_conf->linkup_timeout;
88
+	port_conf_def->ip_ver = nic_boot_ext_conf->ip_ver;
89
+
90
+	return MLX_SUCCESS;
91
+
92
+nvdata_access_err:
93
+	port_conf_def->linkup_timeout = DEFAULT_BOOT_LINK_UP_TO;
94
+	port_conf_def->ip_ver = DEFAULT_BOOT_IP_VER;
95
+
96
+	return status;
97
+}
98
+
99
+static
100
+mlx_status
101
+nvconfig_get_iscsi_init_dhcp_default_conf(
102
+		IN void *data,
103
+		IN int status,
104
+		OUT void *def_struct
105
+		)
106
+{
107
+	union mlx_nvconfig_iscsi_init_dhcp_conf *iscsi_init_dhcp_conf =
108
+			(union mlx_nvconfig_iscsi_init_dhcp_conf *) data;
109
+	struct mlx_nvconfig_port_conf_defaults *port_conf_def =
110
+			(struct mlx_nvconfig_port_conf_defaults *) def_struct;
111
+
112
+	MLX_CHECK_STATUS(NULL, status, nvdata_access_err,
113
+			"TLV not found. Using hard-coded defaults ");
114
+	port_conf_def->iscsi_dhcp_params_en = iscsi_init_dhcp_conf->dhcp_iscsi_en;
115
+	port_conf_def->iscsi_ipv4_dhcp_en = iscsi_init_dhcp_conf->ipv4_dhcp_en;
116
+
117
+	return MLX_SUCCESS;
118
+
119
+nvdata_access_err:
120
+	port_conf_def->iscsi_dhcp_params_en = DEFAULT_ISCSI_DHCP_PARAM_EN;
121
+	port_conf_def->iscsi_ipv4_dhcp_en = DEFAULT_ISCSI_IPV4_DHCP_EN;
122
+
123
+	return status;
124
+}
125
+
126
+static
127
+mlx_status
128
+nvconfig_get_ib_boot_default_conf(
129
+		IN void *data,
130
+		IN int status,
131
+		OUT void *def_struct
132
+		)
133
+{
134
+	union mlx_nvconfig_nic_ib_boot_conf *ib_boot_conf =
135
+			(union mlx_nvconfig_nic_ib_boot_conf *) data;
136
+	struct mlx_nvconfig_port_conf_defaults *port_conf_def =
137
+			(struct mlx_nvconfig_port_conf_defaults *) def_struct;
138
+
139
+	MLX_CHECK_STATUS(NULL, status, nvdata_access_err,
140
+			"nvconfig_nvdata_default_access failed ");
141
+	port_conf_def->boot_pkey = ib_boot_conf->boot_pkey;
142
+
143
+nvdata_access_err:
144
+	return status;
145
+}
146
+
147
+static
148
+mlx_status
149
+nvconfig_get_wol_default_conf(
150
+		IN void *data,
151
+		IN int status,
152
+		OUT void *def_struct
153
+		)
154
+{
155
+	union mlx_nvconfig_wol_conf *wol_conf = (union mlx_nvconfig_wol_conf *) data;
156
+	struct mlx_nvconfig_port_conf_defaults *port_conf_def =
157
+			(struct mlx_nvconfig_port_conf_defaults *) def_struct;
158
+
159
+	MLX_CHECK_STATUS(NULL, status, nvdata_access_err,
160
+			"nvconfig_nvdata_default_access failed ");
161
+	port_conf_def->en_wol_magic = wol_conf->en_wol_magic;
162
+
163
+nvdata_access_err:
164
+	return status;
165
+}
166
+
167
+static
168
+mlx_status
169
+nvconfig_get_iscsi_gen_default_conf(
170
+		IN void *data,
171
+		IN int status,
172
+		OUT void *def_struct)
173
+{
174
+	union mlx_nvconfig_iscsi_general *iscsi_gen =
175
+			(union mlx_nvconfig_iscsi_general *) data;
176
+	struct mlx_nvconfig_port_conf_defaults *port_conf_def =
177
+			(struct mlx_nvconfig_port_conf_defaults *) def_struct;
178
+
179
+	MLX_CHECK_STATUS(NULL, status, nvdata_access_err,
180
+			"nvconfig_nvdata_default_access failed ");
181
+	port_conf_def->iscsi_boot_to_target = iscsi_gen->boot_to_target;
182
+	port_conf_def->iscsi_vlan_en = iscsi_gen->vlan_en;
183
+	port_conf_def->iscsi_tcp_timestamps_en = iscsi_gen->tcp_timestamps_en;
184
+	port_conf_def->iscsi_chap_mutual_auth_en = iscsi_gen->chap_mutual_auth_en;
185
+	port_conf_def->iscsi_chap_auth_en = iscsi_gen->chap_auth_en;
186
+	port_conf_def->iscsi_lun_busy_retry_count = iscsi_gen->lun_busy_retry_count;
187
+	port_conf_def->iscsi_link_up_delay_time = iscsi_gen->link_up_delay_time;
188
+
189
+nvdata_access_err:
190
+	return status;
191
+}
192
+
193
+static
194
+mlx_status
195
+nvconfig_get_ib_dhcp_default_conf(
196
+		IN void *data,
197
+		IN int status,
198
+		OUT void *def_struct
199
+		)
200
+{
201
+	union mlx_nvconfig_ib_dhcp_conf *ib_dhcp =
202
+			(union mlx_nvconfig_ib_dhcp_conf *) data;
203
+	struct mlx_nvconfig_port_conf_defaults *port_conf_def =
204
+			(struct mlx_nvconfig_port_conf_defaults *) def_struct;
205
+
206
+	MLX_CHECK_STATUS(NULL, status, nvdata_access_err,
207
+			"nvconfig_nvdata_default_access failed ");
208
+	port_conf_def->client_identifier = ib_dhcp->client_identifier;
209
+	port_conf_def->mac_admin_bit = ib_dhcp->mac_admin_bit;
210
+
211
+nvdata_access_err:
212
+	return status;
213
+}
214
+
215
+static
216
+mlx_status
217
+nvconfig_get_ocsd_ocbb_default_conf( IN void *data,
218
+		IN int status, OUT void *def_struct) {
219
+	union mlx_nvconfig_ocsd_ocbb_conf *ocsd_ocbb =
220
+			(union mlx_nvconfig_ocsd_ocbb_conf *) data;
221
+	struct mlx_nvconfig_conf_defaults *conf_def =
222
+			(struct mlx_nvconfig_conf_defaults *) def_struct;
223
+
224
+	MLX_CHECK_STATUS(NULL, status, nvdata_access_err,
225
+			"TLV not found. Using hard-coded defaults ");
226
+	conf_def->ocsd_ocbb_en = ocsd_ocbb->ocsd_ocbb_en;
227
+
228
+	return MLX_SUCCESS;
229
+
230
+nvdata_access_err:
231
+	conf_def->ocsd_ocbb_en = DEFAULT_OCSD_OCBB_EN;
232
+
233
+	return status;
234
+}
235
+
236
+static
237
+mlx_status
238
+nvconfig_get_vpi_link_default_conf(
239
+		IN void *data,
240
+		IN int status,
241
+		OUT void *def_struct
242
+		)
243
+{
244
+	union mlx_nvconfig_vpi_link_conf *vpi_link =
245
+			(union mlx_nvconfig_vpi_link_conf *) data;
246
+	struct mlx_nvconfig_port_conf_defaults *port_conf_def =
247
+			(struct mlx_nvconfig_port_conf_defaults *) def_struct;
248
+
249
+	MLX_CHECK_STATUS(NULL, status, nvdata_access_err,
250
+			"nvconfig_nvdata_default_access failed ");
251
+	port_conf_def->network_link_type = vpi_link->network_link_type;
252
+	port_conf_def->default_link_type = vpi_link->default_link_type;
253
+
254
+nvdata_access_err:
255
+	return status;
256
+}
257
+
258
+static
259
+mlx_status
260
+nvconfig_get_rom_banner_to_default_conf(
261
+		IN void *data,
262
+		IN int status,
263
+		OUT void *def_struct
264
+		)
265
+{
266
+	union mlx_nvconfig_rom_banner_timeout_conf *rom_banner_timeout_conf =
267
+			(union mlx_nvconfig_rom_banner_timeout_conf *) data;
268
+	struct mlx_nvconfig_conf_defaults *conf_def =
269
+			(struct mlx_nvconfig_conf_defaults *) def_struct;
270
+
271
+	MLX_CHECK_STATUS(NULL, status, nvdata_access_err,
272
+			"TLV not found. Using hard-coded defaults ");
273
+	conf_def->flexboot_menu_to = rom_banner_timeout_conf->rom_banner_to;
274
+
275
+	return MLX_SUCCESS;
276
+
277
+nvdata_access_err:
278
+	conf_def->flexboot_menu_to = DEFAULT_FLEXBOOT_MENU_TO;
279
+
280
+	return status;
281
+}
282
+
283
+static
284
+mlx_status
285
+nvconfig_get_nv_virt_caps_default_conf(
286
+		IN void *data,
287
+		IN int status,
288
+		OUT void *def_struct
289
+		)
290
+{
291
+	union mlx_nvconfig_virt_caps *nv_virt_caps =
292
+			(union mlx_nvconfig_virt_caps *) data;
293
+	struct mlx_nvconfig_conf_defaults *conf_def =
294
+			(struct mlx_nvconfig_conf_defaults *) def_struct;
295
+
296
+	MLX_CHECK_STATUS(NULL, status, nvdata_access_err,
297
+			"TLV not found. Using hard-coded defaults ");
298
+	conf_def->max_vfs = nv_virt_caps->max_vfs_per_pf;
299
+
300
+	return MLX_SUCCESS;
301
+
302
+nvdata_access_err:
303
+	conf_def->max_vfs = DEFAULT_MAX_VFS;
304
+
305
+	return status;
306
+}
307
+
308
+static
309
+mlx_status
310
+nvconfig_get_nv_virt_default_conf(
311
+		IN void *data,
312
+		IN int status,
313
+		OUT void *def_struct
314
+		)
315
+{
316
+	union mlx_nvconfig_virt_conf *nv_virt_conf =
317
+			(union mlx_nvconfig_virt_conf *) data;
318
+	struct mlx_nvconfig_conf_defaults *conf_def =
319
+			(struct mlx_nvconfig_conf_defaults *) def_struct;
320
+
321
+	MLX_CHECK_STATUS(NULL, status, nvdata_access_err,
322
+			"nvconfig_nvdata_default_access failed ");
323
+	conf_def->total_vfs = nv_virt_conf->num_of_vfs;
324
+	conf_def->sriov_en = nv_virt_conf->virt_mode;
325
+
326
+nvdata_access_err:
327
+	return status;
328
+}
329
+
330
+static struct tlv_default tlv_port_defaults[] = {
331
+	TlvDefaultEntry(BOOT_SETTINGS_TYPE, union mlx_nvconfig_nic_boot_conf, &nvconfig_get_boot_default_conf),
332
+	TlvDefaultEntry(BOOT_SETTINGS_EXT_TYPE, union mlx_nvconfig_nic_boot_ext_conf, &nvconfig_get_boot_ext_default_conf),
333
+	TlvDefaultEntry(ISCSI_INITIATOR_DHCP_CONF_TYPE, union mlx_nvconfig_iscsi_init_dhcp_conf, &nvconfig_get_iscsi_init_dhcp_default_conf),
334
+	TlvDefaultEntry(IB_BOOT_SETTING_TYPE, union mlx_nvconfig_nic_ib_boot_conf, &nvconfig_get_ib_boot_default_conf),
335
+	TlvDefaultEntry(WAKE_ON_LAN_TYPE, union mlx_nvconfig_wol_conf, &nvconfig_get_wol_default_conf),
336
+	TlvDefaultEntry(ISCSI_GENERAL_SETTINGS_TYPE, union mlx_nvconfig_iscsi_general, &nvconfig_get_iscsi_gen_default_conf),
337
+	TlvDefaultEntry(IB_DHCP_SETTINGS_TYPE, union mlx_nvconfig_ib_dhcp_conf, &nvconfig_get_ib_dhcp_default_conf),
338
+	TlvDefaultEntry(VPI_LINK_TYPE, union mlx_nvconfig_vpi_link_conf, &nvconfig_get_vpi_link_default_conf),
339
+};
340
+
341
+static struct tlv_default tlv_general_defaults[] = {
342
+	TlvDefaultEntry(BANNER_TO_TYPE, union mlx_nvconfig_rom_banner_timeout_conf, &nvconfig_get_rom_banner_to_default_conf),
343
+	TlvDefaultEntry(GLOPAL_PCI_CAPS_TYPE, union mlx_nvconfig_virt_caps, &nvconfig_get_nv_virt_caps_default_conf),
344
+	TlvDefaultEntry(GLOPAL_PCI_SETTINGS_TYPE, union mlx_nvconfig_virt_conf, &nvconfig_get_nv_virt_default_conf),
345
+	TlvDefaultEntry(OCSD_OCBB_TYPE, union mlx_nvconfig_ocsd_ocbb_conf, &nvconfig_get_ocsd_ocbb_default_conf),
346
+};
347
+
348
+static
349
+mlx_status
350
+nvconfig_nvdata_default_access(
351
+		IN mlx_utils *utils,
352
+		IN mlx_uint8 port,
353
+		IN mlx_uint16 tlv_type,
354
+		IN mlx_size data_size,
355
+		OUT mlx_void *data
356
+		)
357
+{
358
+	mlx_status status = MLX_SUCCESS;
359
+	mlx_uint32 index;
360
+	mlx_uint8 version = 0;
361
+
362
+	status = nvconfig_nvdata_access(utils, port, tlv_type, REG_ACCESS_READ,
363
+			data_size, TLV_ACCESS_DEFAULT_EN, &version, data);
364
+	MLX_CHECK_STATUS(NULL, status, nvdata_access_err,
365
+				"nvconfig_nvdata_access failed ");
366
+	for (index = 0; index * 4 < data_size; index++) {
367
+		mlx_memory_be32_to_cpu(utils, (((mlx_uint32 *) data)[index]),
368
+				((mlx_uint32 *) data) + index);
369
+	}
370
+
371
+nvdata_access_err:
372
+	return status;
373
+}
374
+
375
+static
376
+mlx_status
377
+nvconfig_nvdata_read_default_value(
378
+		IN mlx_utils *utils,
379
+		IN mlx_uint8 modifier,
380
+		IN struct tlv_default *def,
381
+		OUT void *def_struct
382
+		)
383
+{
384
+	mlx_status status = MLX_SUCCESS;
385
+	void *data = NULL;
386
+
387
+	status = mlx_memory_zalloc(utils, def->data_size,&data);
388
+	MLX_CHECK_STATUS(utils, status, memory_err,
389
+				"mlx_memory_zalloc failed ");
390
+	status = nvconfig_nvdata_default_access(utils, modifier, def->tlv_type,
391
+			def->data_size, data);
392
+	def->set_defaults(data, status, def_struct);
393
+	mlx_memory_free(utils, &data);
394
+
395
+memory_err:
396
+	return status;
397
+}
398
+
399
+static
400
+void
401
+nvconfig_nvdata_read_default_values(
402
+		IN mlx_utils *utils,
403
+		IN mlx_uint8 modifier,
404
+		IN struct tlv_default defaults_table[],
405
+		IN mlx_uint8 defaults_table_size,
406
+		OUT void *def_strct
407
+		)
408
+{
409
+	struct tlv_default *defs;
410
+	unsigned int i;
411
+
412
+	for (i = 0; i < defaults_table_size; i++) {
413
+		defs = &defaults_table[i];
414
+		nvconfig_nvdata_read_default_value(utils, modifier, defs, def_strct);
415
+	}
416
+}
417
+
418
+mlx_status
419
+nvconfig_read_port_default_values(
420
+		IN mlx_utils *utils,
421
+		IN mlx_uint8 port,
422
+		OUT struct mlx_nvconfig_port_conf_defaults *port_conf_def
423
+		)
424
+{
425
+	mlx_status status = MLX_SUCCESS;
426
+
427
+	if (utils == NULL || port_conf_def == NULL) {
428
+		status = MLX_INVALID_PARAMETER;
429
+		MLX_DEBUG_ERROR(utils,"bad params.");
430
+		goto bad_param;
431
+	}
432
+	mlx_memory_set(utils, port_conf_def, 0, sizeof(*port_conf_def));
433
+	nvconfig_nvdata_read_default_values(utils, port, tlv_port_defaults,
434
+				(sizeof(tlv_port_defaults)/sizeof(tlv_port_defaults[0])),
435
+				port_conf_def);
436
+
437
+bad_param:
438
+	return status;
439
+}
440
+
441
+mlx_status
442
+nvconfig_read_general_default_values(
443
+		IN mlx_utils *utils,
444
+		OUT struct mlx_nvconfig_conf_defaults *conf_def
445
+		)
446
+{
447
+	mlx_status status = MLX_SUCCESS;
448
+
449
+	if (utils == NULL || conf_def == NULL) {
450
+		status = MLX_INVALID_PARAMETER;
451
+		MLX_DEBUG_ERROR(utils,"bad params.");
452
+		goto bad_param;
453
+	}
454
+	mlx_memory_set(utils, conf_def, 0, sizeof(*conf_def));
455
+	nvconfig_nvdata_read_default_values(utils, 0, tlv_general_defaults,
456
+			(sizeof(tlv_general_defaults)/sizeof(tlv_general_defaults[0])),
457
+			conf_def);
458
+
459
+bad_param:
460
+	return status;
461
+}
462
+
463
+mlx_status
464
+nvconfig_read_rom_ini_values(
465
+		IN mlx_utils *utils,
466
+		OUT struct mlx_nvcofnig_romini *rom_ini
467
+		)
468
+{
469
+	mlx_status status = MLX_SUCCESS;
470
+
471
+	if (utils == NULL || rom_ini == NULL) {
472
+		status = MLX_INVALID_PARAMETER;
473
+		MLX_DEBUG_ERROR(utils,"bad params.");
474
+		goto bad_param;
475
+	}
476
+	mlx_memory_set(utils, rom_ini, 0, sizeof(*rom_ini));
477
+
478
+	status = nvconfig_nvdata_default_access(utils, 0, GLOBAL_ROM_INI_TYPE,
479
+			sizeof(*rom_ini), rom_ini);
480
+bad_param:
481
+	return status;
482
+}

+ 94
- 0
src/drivers/infiniband/mlx_utils/mlx_lib/mlx_nvconfig/mlx_nvconfig_defaults.h Visa fil

@@ -0,0 +1,94 @@
1
+#ifndef MLX_NVCONFIG_DEFAULTS_H_
2
+#define MLX_NVCONFIG_DEFAULTS_H_
3
+
4
+/*
5
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20
+ * 02110-1301, USA.
21
+ */
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+#include "mlx_nvconfig_prm.h"
25
+/*
26
+ * Default values
27
+ */
28
+#define DEFAULT_FLEXBOOT_MENU_TO 4
29
+#define DEFAULT_MAX_VFS 8
30
+#define DEFAULT_BOOT_PROTOCOL 1
31
+#define DEFAULT_OPTION_ROM_EN 1
32
+#define DEFAULT_BOOT_VLAN 1
33
+#define DEFAULT_ISCSI_DHCP_PARAM_EN 1
34
+#define DEFAULT_ISCSI_IPV4_DHCP_EN 1
35
+#define DEFAULT_OCSD_OCBB_EN 1
36
+#define DEFAULT_BOOT_IP_VER 0
37
+#define DEFAULT_BOOT_LINK_UP_TO 0
38
+
39
+struct mlx_nvconfig_port_conf_defaults {
40
+	mlx_uint8 pptx;
41
+	mlx_uint8 pprx;
42
+	mlx_boolean boot_option_rom_en;
43
+	mlx_boolean boot_vlan_en;
44
+	mlx_uint8 boot_retry_count;
45
+	mlx_uint8 boot_protocol;
46
+	mlx_uint8 boot_vlan;
47
+	mlx_uint8 boot_pkey;
48
+	mlx_boolean en_wol_magic;
49
+	mlx_uint8 network_link_type;
50
+	mlx_uint8 iscsi_boot_to_target;
51
+	mlx_boolean iscsi_vlan_en;
52
+	mlx_boolean iscsi_tcp_timestamps_en;
53
+	mlx_boolean iscsi_chap_mutual_auth_en;
54
+	mlx_boolean iscsi_chap_auth_en;
55
+	mlx_boolean iscsi_dhcp_params_en;
56
+	mlx_boolean iscsi_ipv4_dhcp_en;
57
+	mlx_uint8 iscsi_lun_busy_retry_count;
58
+	mlx_uint8 iscsi_link_up_delay_time;
59
+	mlx_uint8 client_identifier;
60
+	mlx_uint8 mac_admin_bit;
61
+	mlx_uint8 default_link_type;
62
+	mlx_uint8 linkup_timeout;
63
+	mlx_uint8 ip_ver;
64
+};
65
+
66
+struct mlx_nvconfig_conf_defaults  {
67
+	mlx_uint8 max_vfs;
68
+	mlx_uint8 total_vfs;
69
+	mlx_uint8 sriov_en;
70
+	mlx_uint8 maximum_uar_bar_size;
71
+	mlx_uint8 uar_bar_size;
72
+	mlx_uint8 flexboot_menu_to;
73
+	mlx_boolean ocsd_ocbb_en;
74
+};
75
+
76
+mlx_status
77
+nvconfig_read_port_default_values(
78
+		IN mlx_utils *utils,
79
+		IN mlx_uint8 port,
80
+		OUT struct mlx_nvconfig_port_conf_defaults *port_conf_def
81
+		);
82
+
83
+mlx_status
84
+nvconfig_read_general_default_values(
85
+		IN mlx_utils *utils,
86
+		OUT struct mlx_nvconfig_conf_defaults *conf_def
87
+		);
88
+
89
+mlx_status
90
+nvconfig_read_rom_ini_values(
91
+		IN mlx_utils *utils,
92
+		OUT struct mlx_nvcofnig_romini *rom_ini
93
+		);
94
+#endif /* MLX_NVCONFIG_DEFAULTS_H_ */

+ 259
- 0
src/drivers/infiniband/mlx_utils/mlx_lib/mlx_nvconfig/mlx_nvconfig_prm.h Visa fil

@@ -0,0 +1,259 @@
1
+#ifndef MLX_NVCONFIG_PRM_H_
2
+#define MLX_NVCONFIG_PRM_H_
3
+
4
+/*
5
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20
+ * 02110-1301, USA.
21
+ */
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+
25
+#include "../../include/public/mlx_types.h"
26
+
27
+enum {
28
+	WAKE_ON_LAN_TYPE				= 0x10,
29
+	VIRTUALIZATION_TYPE				= 0x11,
30
+	VPI_LINK_TYPE					= 0x12,
31
+	BOOT_SETTINGS_EXT_TYPE			= 0x2001,
32
+	BANNER_TO_TYPE 					= 0x2010,
33
+	OCSD_OCBB_TYPE 					= 0x2011,
34
+	FLOW_CONTROL_TYPE				= 0x2020,
35
+	BOOT_SETTINGS_TYPE				= 0x2021,
36
+	ISCSI_GENERAL_SETTINGS_TYPE		= 0x2100,
37
+	IB_BOOT_SETTING_TYPE			= 0x2022,
38
+	IB_DHCP_SETTINGS_TYPE			= 0x2023,
39
+	GLOPAL_PCI_SETTINGS_TYPE		= 0x80,
40
+	GLOPAL_PCI_CAPS_TYPE			= 0x81,
41
+	GLOBAL_ROM_INI_TYPE				= 0x100,
42
+
43
+	// Types for iSCSI strings
44
+	DHCP_VEND_ID					= 0x2101,
45
+	ISCSI_INITIATOR_IPV4_ADDR		= 0x2102,
46
+	ISCSI_INITIATOR_SUBNET			= 0x2103,
47
+	ISCSI_INITIATOR_IPV4_GATEWAY	= 0x2104,
48
+	ISCSI_INITIATOR_IPV4_PRIM_DNS	= 0x2105,
49
+	ISCSI_INITIATOR_IPV4_SECDNS		= 0x2106,
50
+	ISCSI_INITIATOR_NAME			= 0x2107,
51
+	ISCSI_INITIATOR_CHAP_ID			= 0x2108,
52
+	ISCSI_INITIATOR_CHAP_PWD		= 0x2109,
53
+	ISCSI_INITIATOR_DHCP_CONF_TYPE	= 0x210a,
54
+
55
+	CONNECT_FIRST_TGT				= 0x2200,
56
+	FIRST_TGT_IP_ADDRESS			= 0x2201,
57
+	FIRST_TGT_TCP_PORT				= 0x2202,
58
+	FIRST_TGT_BOOT_LUN				= 0x2203,
59
+	FIRST_TGT_ISCSI_NAME			= 0x2204,
60
+	FIRST_TGT_CHAP_ID				= 0x2205,
61
+	FIRST_TGT_CHAP_PWD				= 0x2207,
62
+};
63
+
64
+union mlx_nvconfig_nic_boot_conf {
65
+	struct {
66
+		mlx_uint32	vlan_id				: 12;
67
+		mlx_uint32	link_speed			: 4;
68
+		mlx_uint32	legacy_boot_prot	: 8;
69
+		mlx_uint32	boot_retry_count	: 3;
70
+		mlx_uint32	boot_strap_type		: 3;
71
+		mlx_uint32	en_vlan				: 1;
72
+		mlx_uint32	en_option_rom		: 1;
73
+	};
74
+	mlx_uint32 dword;
75
+};
76
+
77
+union mlx_nvconfig_nic_boot_ext_conf {
78
+	struct {
79
+		mlx_uint32	linkup_timeout	: 8;
80
+		mlx_uint32	ip_ver			: 2;
81
+		mlx_uint32	reserved0		: 22;
82
+	};
83
+	mlx_uint32 dword;
84
+};
85
+
86
+union mlx_nvconfig_rom_banner_timeout_conf {
87
+	struct {
88
+		mlx_uint32	rom_banner_to	: 4;
89
+		mlx_uint32	reserved		: 28;
90
+	};
91
+	mlx_uint32 dword;
92
+};
93
+
94
+union mlx_nvconfig_virt_conf {
95
+	struct {
96
+		mlx_uint32 reserved0				:24;
97
+		mlx_uint32 pf_bar_size_valid		:1;
98
+		mlx_uint32 vf_bar_size_valid		:1;
99
+		mlx_uint32 num_pf_msix_valid		:1;
100
+		mlx_uint32 num_vf_msix_valid		:1;
101
+		mlx_uint32 num_pfs_valid			:1;
102
+		mlx_uint32 fpp_valid				:1;
103
+		mlx_uint32 full_vf_qos_valid		:1;
104
+		mlx_uint32 sriov_valid			:1;
105
+		/*-------------------*/
106
+		mlx_uint32 num_of_vfs				:16;
107
+		mlx_uint32 num_of_pfs				:4;
108
+		mlx_uint32 reserved1				:9;
109
+		mlx_uint32 fpp_en					:1;
110
+		mlx_uint32 full_vf_qos			:1;
111
+		mlx_uint32 virt_mode				:1; //sriov_en
112
+		/*-------------------*/
113
+		mlx_uint32 log_pf_uar_bar_size	:6;
114
+		mlx_uint32 log_vf_uar_bar_size	:6;
115
+		mlx_uint32 num_pf_msix			:10;
116
+		mlx_uint32 num_vf_msix			:10;
117
+	};
118
+	mlx_uint32 dword[3];
119
+};
120
+
121
+union mlx_nvconfig_virt_caps {
122
+	struct {
123
+		mlx_uint32 reserved0				:24;
124
+		mlx_uint32 max_vfs_per_pf_valid	:1;
125
+		mlx_uint32 max_total_msix_valid	:1;
126
+		mlx_uint32 max_total_bar_valid	:1;
127
+		mlx_uint32 num_pfs_supported		:1;
128
+		mlx_uint32 num_vf_msix_supported	:1;
129
+		mlx_uint32 num_pf_msix_supported	:1;
130
+		mlx_uint32 vf_bar_size_supported	:1;
131
+		mlx_uint32 pf_bar_size_supported	:1;
132
+		/*-------------------*/
133
+		mlx_uint32 max_vfs_per_pf			:16;
134
+		mlx_uint32 max_num_pfs			:4;
135
+		mlx_uint32 reserved1				:9;
136
+		mlx_uint32 fpp_support			:1;
137
+		mlx_uint32 vf_qos_control_support	:1;
138
+		mlx_uint32 sriov_support			:1;
139
+		/*-------------------*/
140
+		mlx_uint32 max_log_pf_uar_bar_size	:6;
141
+		mlx_uint32 max_log_vf_uar_bar_size	:6;
142
+		mlx_uint32 max_num_pf_msix			:10;
143
+		mlx_uint32 max_num_vf_msix			:10;
144
+		/*-------------------*/
145
+		mlx_uint32 max_total_msix;
146
+		/*-------------------*/
147
+		mlx_uint32 max_total_bar;
148
+	};
149
+	mlx_uint32 dword[5];
150
+};
151
+
152
+union mlx_nvconfig_iscsi_init_dhcp_conf {
153
+	struct {
154
+		mlx_uint32 reserved0		:30;
155
+		mlx_uint32 dhcp_iscsi_en	:1;
156
+		mlx_uint32 ipv4_dhcp_en	:1;
157
+
158
+	};
159
+	mlx_uint32 dword;
160
+};
161
+
162
+union mlx_nvconfig_nic_ib_boot_conf {
163
+	struct {
164
+		mlx_uint32	boot_pkey			: 16;
165
+		mlx_uint32	reserved0			: 16;
166
+	};
167
+	mlx_uint32 dword;
168
+};
169
+
170
+union mlx_nvconfig_wol_conf {
171
+	struct {
172
+		mlx_uint32	reserved0		:9;
173
+		mlx_uint32	en_wol_passwd	:1;
174
+		mlx_uint32	en_wol_magic	:1;
175
+		mlx_uint32	reserved1		:21;
176
+		mlx_uint32	reserved2		:32;
177
+	};
178
+	mlx_uint32 dword[2];
179
+};
180
+
181
+union mlx_nvconfig_iscsi_general {
182
+	struct {
183
+		mlx_uint32	reserved0			:22;
184
+		mlx_uint32	boot_to_target		:2;
185
+		mlx_uint32	reserved1			:2;
186
+		mlx_uint32	vlan_en				:1;
187
+		mlx_uint32	tcp_timestamps_en	:1;
188
+		mlx_uint32	chap_mutual_auth_en	:1;
189
+		mlx_uint32	chap_auth_en		:1;
190
+		mlx_uint32	reserved2			:2;
191
+		/*-------------------*/
192
+		mlx_uint32	vlan				:12;
193
+		mlx_uint32	reserved3			:20;
194
+		/*-------------------*/
195
+		mlx_uint32	lun_busy_retry_count:8;
196
+		mlx_uint32	link_up_delay_time	:8;
197
+		mlx_uint32	reserved4			:16;
198
+	};
199
+	mlx_uint32 dword[3];
200
+};
201
+
202
+union mlx_nvconfig_ib_dhcp_conf {
203
+	struct {
204
+		mlx_uint32 reserved			:24;
205
+		mlx_uint32 client_identifier	:4;
206
+		mlx_uint32 mac_admin_bit		:4;
207
+	};
208
+	mlx_uint32 dword;
209
+};
210
+
211
+union mlx_nvconfig_ocsd_ocbb_conf {
212
+	struct {
213
+		mlx_uint32	reserved		:31;
214
+		mlx_uint32	ocsd_ocbb_en	:1;
215
+	};
216
+	mlx_uint32 dword;
217
+};
218
+
219
+union mlx_nvconfig_vpi_link_conf {
220
+	struct {
221
+		mlx_uint32	network_link_type	:2;
222
+		mlx_uint32	default_link_type	:2;
223
+		mlx_uint32	reserved		:28;
224
+	};
225
+	mlx_uint32 dword;
226
+};
227
+
228
+struct  mlx_nvcofnig_romini {
229
+	mlx_uint32 reserved0    :1;
230
+	mlx_uint32 shared_memory_en     :1;
231
+	mlx_uint32 hii_vpi_en   :1;
232
+	mlx_uint32 tech_enum    :1;
233
+	mlx_uint32 reserved1    :4;
234
+	mlx_uint32 static_component_name_string :1;
235
+	mlx_uint32 hii_iscsi_configuration      :1;
236
+	mlx_uint32 hii_ibm_aim  :1;
237
+	mlx_uint32 hii_platform_setup   :1;
238
+	mlx_uint32 hii_bdf_decimal      :1;
239
+	mlx_uint32 hii_read_only        :1;
240
+	mlx_uint32 reserved2    :10;
241
+	mlx_uint32 mac_enum             :1;
242
+	mlx_uint32 port_enum    :1;
243
+	mlx_uint32 flash_en             :1;
244
+	mlx_uint32 fmp_en               :1;
245
+	mlx_uint32 bofm_en              :1;
246
+	mlx_uint32 platform_to_driver_en                :1;
247
+	mlx_uint32 hii_en               :1;
248
+	mlx_uint32 undi_en              :1;
249
+	/* -------------- */
250
+	mlx_uint64 dhcp_user_class;
251
+	/* -------------- */
252
+	mlx_uint32 reserved3    :22;
253
+	mlx_uint32 uri_boot_retry_delay :4;
254
+	mlx_uint32 uri_boot_retry       :4;
255
+	mlx_uint32 option_rom_debug     :1;
256
+	mlx_uint32 promiscuous_vlan     :1;
257
+};
258
+
259
+#endif /* MLX_NVCONFIG_PRM_H_ */

+ 145
- 0
src/drivers/infiniband/mlx_utils/mlx_lib/mlx_ocbb/mlx_ocbb.c Visa fil

@@ -0,0 +1,145 @@
1
+/*
2
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
3
+ *
4
+ * This program is free software; you can redistribute it and/or
5
+ * modify it under the terms of the GNU General Public License as
6
+ * published by the Free Software Foundation; either version 2 of the
7
+ * License, or any later version.
8
+ *
9
+ * This program is distributed in the hope that it will be useful, but
10
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
11
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
12
+ * General Public License for more details.
13
+ *
14
+ * You should have received a copy of the GNU General Public License
15
+ * along with this program; if not, write to the Free Software
16
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17
+ * 02110-1301, USA.
18
+ */
19
+
20
+FILE_LICENCE ( GPL2_OR_LATER );
21
+
22
+#include "mlx_ocbb.h"
23
+#include "mlx_icmd.h"
24
+#include "mlx_bail.h"
25
+
26
+mlx_status
27
+mlx_ocbb_init (
28
+	IN mlx_utils *utils,
29
+	IN mlx_uint64 address
30
+	)
31
+{
32
+	mlx_status status = MLX_SUCCESS;
33
+	struct mlx_ocbb_init ocbb_init;
34
+	ocbb_init.address_hi = (mlx_uint32)(address >> 32);
35
+	ocbb_init.address_lo = (mlx_uint32)address;
36
+
37
+	if (utils == NULL) {
38
+		status = MLX_INVALID_PARAMETER;
39
+		goto bad_param;
40
+	}
41
+
42
+	status = mlx_icmd_send_command(
43
+			utils,
44
+			OCBB_INIT,
45
+			&ocbb_init,
46
+			sizeof(ocbb_init),
47
+			0
48
+			);
49
+	MLX_CHECK_STATUS(utils, status, icmd_err, "mlx_icmd_send_command failed");
50
+icmd_err:
51
+bad_param:
52
+	return status;
53
+}
54
+
55
+mlx_status
56
+mlx_ocbb_query_header_status (
57
+	IN mlx_utils *utils,
58
+	OUT mlx_uint8 *ocbb_status
59
+	)
60
+{
61
+	mlx_status status = MLX_SUCCESS;
62
+	struct mlx_ocbb_query_status ocbb_query_status;
63
+
64
+	if (utils == NULL) {
65
+		status = MLX_INVALID_PARAMETER;
66
+		goto bad_param;
67
+	}
68
+
69
+	status = mlx_icmd_send_command(
70
+			utils,
71
+			OCBB_QUERY_HEADER_STATUS,
72
+			&ocbb_query_status,
73
+			0,
74
+			sizeof(ocbb_query_status)
75
+			);
76
+	MLX_CHECK_STATUS(utils, status, icmd_err, "mlx_icmd_send_command failed");
77
+	*ocbb_status = ocbb_query_status.status;
78
+icmd_err:
79
+bad_param:
80
+	return status;
81
+}
82
+
83
+mlx_status
84
+mlx_ocbb_query_etoc_status (
85
+	IN mlx_utils *utils,
86
+	OUT mlx_uint8 *ocbb_status
87
+	)
88
+{
89
+	mlx_status status = MLX_SUCCESS;
90
+	struct mlx_ocbb_query_status ocbb_query_status;
91
+
92
+	if (utils == NULL) {
93
+		status = MLX_INVALID_PARAMETER;
94
+		goto bad_param;
95
+	}
96
+
97
+	status = mlx_icmd_send_command(
98
+			utils,
99
+			OCBB_QUERY_ETOC_STATUS,
100
+			&ocbb_query_status,
101
+			0,
102
+			sizeof(ocbb_query_status)
103
+			);
104
+	MLX_CHECK_STATUS(utils, status, icmd_err, "mlx_icmd_send_command failed");
105
+	*ocbb_status = ocbb_query_status.status;
106
+icmd_err:
107
+bad_param:
108
+	return status;
109
+}
110
+
111
+mlx_status
112
+mlx_ocbb_set_event (
113
+	IN mlx_utils *utils,
114
+	IN mlx_uint64			event_data,
115
+	IN mlx_uint8			event_number,
116
+	IN mlx_uint8			event_length,
117
+	IN mlx_uint8			data_length,
118
+	IN mlx_uint8			data_start_offset
119
+	)
120
+{
121
+	mlx_status status = MLX_SUCCESS;
122
+	struct mlx_ocbb_set_event ocbb_event;
123
+
124
+	if (utils == NULL) {
125
+		status = MLX_INVALID_PARAMETER;
126
+		goto bad_param;
127
+	}
128
+
129
+	ocbb_event.data_length = data_length;
130
+	ocbb_event.data_start_offset = data_start_offset;
131
+	ocbb_event.event_number = event_number;
132
+	ocbb_event.event_data = event_data;
133
+	ocbb_event.event_length = event_length;
134
+	status = mlx_icmd_send_command(
135
+			utils,
136
+			OCBB_QUERY_SET_EVENT,
137
+			&ocbb_event,
138
+			sizeof(ocbb_event),
139
+			0
140
+			);
141
+	MLX_CHECK_STATUS(utils, status, icmd_err, "mlx_icmd_send_command failed");
142
+icmd_err:
143
+bad_param:
144
+	return status;
145
+}

+ 73
- 0
src/drivers/infiniband/mlx_utils/mlx_lib/mlx_ocbb/mlx_ocbb.h Visa fil

@@ -0,0 +1,73 @@
1
+#ifndef MLX_OCBB_H_
2
+#define MLX_OCBB_H_
3
+
4
+/*
5
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20
+ * 02110-1301, USA.
21
+ */
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+
25
+#include "mlx_utils.h"
26
+
27
+#define MLX_OCBB_EVENT_DATA_SIZE 2
28
+struct mlx_ocbb_init {
29
+	mlx_uint32 address_hi;
30
+	mlx_uint32 address_lo;
31
+};
32
+
33
+struct mlx_ocbb_query_status {
34
+	mlx_uint32 reserved	:24;
35
+	mlx_uint32 status	:8;
36
+};
37
+
38
+struct mlx_ocbb_set_event {
39
+	mlx_uint64 event_data;
40
+	mlx_uint32 event_number	:8;
41
+	mlx_uint32 event_length	:8;
42
+	mlx_uint32 data_length	:8;
43
+	mlx_uint32 data_start_offset	:8;
44
+};
45
+
46
+mlx_status
47
+mlx_ocbb_init (
48
+	IN mlx_utils *utils,
49
+	IN mlx_uint64 address
50
+	);
51
+
52
+mlx_status
53
+mlx_ocbb_query_header_status (
54
+	IN mlx_utils *utils,
55
+	OUT mlx_uint8 *ocbb_status
56
+	);
57
+
58
+mlx_status
59
+mlx_ocbb_query_etoc_status (
60
+	IN mlx_utils *utils,
61
+	OUT mlx_uint8 *ocbb_status
62
+	);
63
+
64
+mlx_status
65
+mlx_ocbb_set_event (
66
+	IN mlx_utils *utils,
67
+	IN mlx_uint64			EventData,
68
+	IN mlx_uint8			EventNumber,
69
+	IN mlx_uint8			EventLength,
70
+	IN mlx_uint8			DataLength,
71
+	IN mlx_uint8			DataStartOffset
72
+	);
73
+#endif /* MLX_OCBB_H_ */

+ 90
- 0
src/drivers/infiniband/mlx_utils/mlx_lib/mlx_reg_access/mlx_reg_access.c Visa fil

@@ -0,0 +1,90 @@
1
+/*
2
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
3
+ *
4
+ * This program is free software; you can redistribute it and/or
5
+ * modify it under the terms of the GNU General Public License as
6
+ * published by the Free Software Foundation; either version 2 of the
7
+ * License, or any later version.
8
+ *
9
+ * This program is distributed in the hope that it will be useful, but
10
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
11
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
12
+ * General Public License for more details.
13
+ *
14
+ * You should have received a copy of the GNU General Public License
15
+ * along with this program; if not, write to the Free Software
16
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17
+ * 02110-1301, USA.
18
+ */
19
+
20
+FILE_LICENCE ( GPL2_OR_LATER );
21
+
22
+#include "../../mlx_lib/mlx_reg_access/mlx_reg_access.h"
23
+#include "../../include/public/mlx_icmd.h"
24
+#include "../../include/public/mlx_bail.h"
25
+#include "../../include/public/mlx_memory.h"
26
+
27
+static
28
+mlx_status
29
+init_operation_tlv(
30
+		IN struct mail_box_tlv *mail_box_tlv,
31
+		IN mlx_uint16  reg_id,
32
+		IN REG_ACCESS_OPT reg_opt
33
+		)
34
+{
35
+#define TLV_OPERATION 1
36
+	mail_box_tlv->operation_tlv.Type			= TLV_OPERATION;
37
+#define MAD_CLASS_REG_ACCESS 1
38
+	mail_box_tlv->operation_tlv.cls			= MAD_CLASS_REG_ACCESS;
39
+#define TLV_OPERATION_SIZE 4
40
+	mail_box_tlv->operation_tlv.len			= TLV_OPERATION_SIZE;
41
+	mail_box_tlv->operation_tlv.method			= reg_opt;
42
+	mail_box_tlv->operation_tlv.register_id	= reg_id;
43
+	return MLX_SUCCESS;
44
+}
45
+
46
+mlx_status
47
+mlx_reg_access(
48
+		IN mlx_utils *utils,
49
+		IN mlx_uint16  reg_id,
50
+		IN REG_ACCESS_OPT reg_opt,
51
+		IN OUT mlx_void	*reg_data,
52
+        IN mlx_size reg_size,
53
+        OUT mlx_uint32 *reg_status
54
+		)
55
+{
56
+	mlx_status status = MLX_SUCCESS;
57
+	struct mail_box_tlv mail_box_tlv;
58
+
59
+	if (utils == NULL || reg_data == NULL || reg_status == NULL
60
+			|| reg_size > REG_ACCESS_MAX_REG_SIZE) {
61
+		status = MLX_INVALID_PARAMETER;
62
+		goto bad_param;
63
+	}
64
+
65
+	mlx_memory_set(utils, &mail_box_tlv, 0, sizeof(mail_box_tlv));
66
+
67
+	init_operation_tlv(&mail_box_tlv, reg_id, reg_opt);
68
+
69
+#define REG_ACCESS_TLV_REG 3
70
+#define REG_TLV_HEADER_LEN 4
71
+#define OP_TLV_SIZE 16
72
+	mail_box_tlv.reg_tlv.Type = REG_ACCESS_TLV_REG;
73
+	mail_box_tlv.reg_tlv.len  = ((reg_size + REG_TLV_HEADER_LEN + 3) >> 2); // length is in dwords round up
74
+	mlx_memory_cpy(utils, &mail_box_tlv.reg_tlv.data, reg_data, reg_size);
75
+
76
+	reg_size += OP_TLV_SIZE + REG_TLV_HEADER_LEN;
77
+
78
+	status = mlx_icmd_send_command(utils, FLASH_REG_ACCESS, &mail_box_tlv, reg_size, reg_size);
79
+	MLX_CHECK_STATUS(utils, status, icmd_err, "failed to send icmd");
80
+
81
+	mlx_memory_cpy(utils, reg_data, &mail_box_tlv.reg_tlv.data,
82
+			reg_size - (OP_TLV_SIZE + REG_TLV_HEADER_LEN));
83
+
84
+	*reg_status = mail_box_tlv.operation_tlv.status;
85
+icmd_err:
86
+bad_param:
87
+	return status;
88
+}
89
+
90
+

+ 82
- 0
src/drivers/infiniband/mlx_utils/mlx_lib/mlx_reg_access/mlx_reg_access.h Visa fil

@@ -0,0 +1,82 @@
1
+/*
2
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
3
+ *
4
+ * This program is free software; you can redistribute it and/or
5
+ * modify it under the terms of the GNU General Public License as
6
+ * published by the Free Software Foundation; either version 2 of the
7
+ * License, or any later version.
8
+ *
9
+ * This program is distributed in the hope that it will be useful, but
10
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
11
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
12
+ * General Public License for more details.
13
+ *
14
+ * You should have received a copy of the GNU General Public License
15
+ * along with this program; if not, write to the Free Software
16
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17
+ * 02110-1301, USA.
18
+ */
19
+
20
+FILE_LICENCE ( GPL2_OR_LATER );
21
+
22
+#ifndef MLX_REG_ACCESS_H_
23
+#define MLX_REG_ACCESS_H_
24
+
25
+#include "../../include/public/mlx_icmd.h"
26
+
27
+#define REG_ACCESS_MAX_REG_SIZE 236
28
+
29
+typedef enum {
30
+  REG_ACCESS_READ = 1,
31
+  REG_ACCESS_WRITE = 2,
32
+} REG_ACCESS_OPT;
33
+
34
+typedef enum {
35
+  TLV_ACCESS_DEFAULT_DIS = 0,
36
+  TLV_ACCESS_DEFAULT_EN = 1,
37
+} NV_DEFAULT_OPT;
38
+
39
+#define REG_ID_NVDA  0x9024
40
+#define REG_ID_NVDI  0x9025
41
+#define REG_ID_NVIA 0x9029
42
+#define REG_ID_MLCR  0x902b
43
+#define REG_ID_NVQC  0x9030
44
+#define REG_ID_MFRL 0x9028
45
+#define REG_ID_PTYS 0x5004
46
+#define REG_ID_PMTU 0x5003
47
+
48
+struct operation_tlv {
49
+    mlx_uint32	reserved0	:8;    /* bit_offset:0 */    /* element_size: 8 */
50
+    mlx_uint32	status		:7;    /* bit_offset:8 */    /* element_size: 7 */
51
+    mlx_uint32	dr			:1;    /* bit_offset:15 */    /* element_size: 1 */
52
+    mlx_uint32	len			:11;    /* bit_offset:16 */    /* element_size: 11 */
53
+    mlx_uint32	Type		:5;    /* bit_offset:27 */    /* element_size: 5 */
54
+    mlx_uint32	cls			:8;    /* bit_offset:32 */    /* element_size: 8 */
55
+    mlx_uint32	method		:7;    /* bit_offset:40 */    /* element_size: 7 */
56
+    mlx_uint32	r			:1;    /* bit_offset:47 */    /* element_size: 1 */
57
+    mlx_uint32	register_id	:16;    /* bit_offset:48 */    /* element_size: 16 */
58
+    mlx_uint64	tid			;    /* bit_offset:64 */    /* element_size: 64 */
59
+};
60
+
61
+struct reg_tlv {
62
+	mlx_uint32	reserved0	:16;    /* bit_offset:0 */    /* element_size: 16 */
63
+	mlx_uint32	len		:11;    /* bit_offset:16 */    /* element_size: 11 */
64
+	mlx_uint32	Type		:5;    /* bit_offset:27 */    /* element_size: 5 */
65
+	mlx_uint8	data[REG_ACCESS_MAX_REG_SIZE];
66
+};
67
+
68
+struct mail_box_tlv {
69
+	struct operation_tlv operation_tlv;
70
+	struct reg_tlv reg_tlv;
71
+};
72
+mlx_status
73
+mlx_reg_access(
74
+		IN mlx_utils *utils,
75
+		IN mlx_uint16  reg_id,
76
+		IN REG_ACCESS_OPT reg_opt,
77
+		IN OUT mlx_void	*reg_data,
78
+        IN mlx_size reg_size,
79
+        OUT mlx_uint32 *reg_status
80
+		);
81
+
82
+#endif /* MLX_REG_ACCESS_H_ */

+ 74
- 0
src/drivers/infiniband/mlx_utils/mlx_lib/mlx_vmac/mlx_vmac.c Visa fil

@@ -0,0 +1,74 @@
1
+/*
2
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
3
+ *
4
+ * This program is free software; you can redistribute it and/or
5
+ * modify it under the terms of the GNU General Public License as
6
+ * published by the Free Software Foundation; either version 2 of the
7
+ * License, or any later version.
8
+ *
9
+ * This program is distributed in the hope that it will be useful, but
10
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
11
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
12
+ * General Public License for more details.
13
+ *
14
+ * You should have received a copy of the GNU General Public License
15
+ * along with this program; if not, write to the Free Software
16
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17
+ * 02110-1301, USA.
18
+ */
19
+
20
+FILE_LICENCE ( GPL2_OR_LATER );
21
+
22
+#include "../../mlx_lib/mlx_vmac/mlx_vmac.h"
23
+#include "../../include/public/mlx_icmd.h"
24
+#include "../../include/public/mlx_bail.h"
25
+
26
+mlx_status
27
+mlx_vmac_query_virt_mac (
28
+	IN mlx_utils *utils,
29
+	OUT struct mlx_vmac_query_virt_mac *virt_mac
30
+	)
31
+{
32
+	mlx_status status = MLX_SUCCESS;
33
+	if (utils == NULL || virt_mac == NULL) {
34
+		status = MLX_INVALID_PARAMETER;
35
+		goto bad_param;
36
+	}
37
+
38
+	status = mlx_icmd_send_command(
39
+			utils,
40
+			QUERY_VIRTUAL_MAC,
41
+			virt_mac,
42
+			0,
43
+			sizeof(*virt_mac)
44
+			);
45
+	MLX_CHECK_STATUS(utils, status, icmd_err, "mlx_icmd_send_command failed");
46
+icmd_err:
47
+bad_param:
48
+	return status;
49
+}
50
+
51
+mlx_status
52
+mlx_vmac_set_virt_mac (
53
+	IN mlx_utils *utils,
54
+	OUT struct mlx_vmac_set_virt_mac *virt_mac
55
+	)
56
+{
57
+	mlx_status status = MLX_SUCCESS;
58
+	if (utils == NULL || virt_mac == NULL) {
59
+		status = MLX_INVALID_PARAMETER;
60
+		goto bad_param;
61
+	}
62
+
63
+	status = mlx_icmd_send_command(
64
+			utils,
65
+			SET_VIRTUAL_MAC,
66
+			virt_mac,
67
+			sizeof(*virt_mac),
68
+			0
69
+			);
70
+	MLX_CHECK_STATUS(utils, status, icmd_err, "mlx_icmd_send_command failed");
71
+icmd_err:
72
+bad_param:
73
+	return status;
74
+}

+ 60
- 0
src/drivers/infiniband/mlx_utils/mlx_lib/mlx_vmac/mlx_vmac.h Visa fil

@@ -0,0 +1,60 @@
1
+#ifndef MLX_VMAC_H_
2
+#define MLX_VMAC_H_
3
+
4
+/*
5
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20
+ * 02110-1301, USA.
21
+ */
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+
25
+#include "../../include/public/mlx_utils.h"
26
+
27
+struct mlx_vmac_query_virt_mac {
28
+	mlx_uint32 reserved0	:30;
29
+	mlx_uint32 mac_aux_v	:1;
30
+	mlx_uint32 virtual_mac_en	:1;
31
+	mlx_uint32 parmanent_mac_high	:16;
32
+	mlx_uint32 reserved1	:16;
33
+	mlx_uint32 parmanent_mac_low	:32;
34
+	mlx_uint32 virtual_mac_high	:16;
35
+	mlx_uint32 Reserved2	:16;
36
+	mlx_uint32 virtual_mac_low	:32;
37
+};
38
+
39
+struct mlx_vmac_set_virt_mac {
40
+	mlx_uint32 Reserved0	:30;
41
+	mlx_uint32 mac_aux_v	:1;
42
+	mlx_uint32 virtual_mac_en	:1;
43
+	mlx_uint32 reserved1	:32;
44
+	mlx_uint32 reserved2	:32;
45
+	mlx_uint32 virtual_mac_high;
46
+	mlx_uint32 virtual_mac_low;
47
+};
48
+
49
+mlx_status
50
+mlx_vmac_query_virt_mac (
51
+	IN mlx_utils *utils,
52
+	OUT struct mlx_vmac_query_virt_mac *virt_mac
53
+	);
54
+
55
+mlx_status
56
+mlx_vmac_set_virt_mac (
57
+	IN mlx_utils *utils,
58
+	OUT struct mlx_vmac_set_virt_mac *virt_mac
59
+	);
60
+#endif /* MLX_VMAC_H_ */

+ 84
- 0
src/drivers/infiniband/mlx_utils/mlx_lib/mlx_wol_rol/mlx_wol_rol.c Visa fil

@@ -0,0 +1,84 @@
1
+/*
2
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
3
+ *
4
+ * This program is free software; you can redistribute it and/or
5
+ * modify it under the terms of the GNU General Public License as
6
+ * published by the Free Software Foundation; either version 2 of the
7
+ * License, or any later version.
8
+ *
9
+ * This program is distributed in the hope that it will be useful, but
10
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
11
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
12
+ * General Public License for more details.
13
+ *
14
+ * You should have received a copy of the GNU General Public License
15
+ * along with this program; if not, write to the Free Software
16
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17
+ * 02110-1301, USA.
18
+ */
19
+
20
+FILE_LICENCE ( GPL2_OR_LATER );
21
+
22
+#include "mlx_wol_rol.h"
23
+#include "mlx_icmd.h"
24
+#include "mlx_memory.h"
25
+#include "mlx_bail.h"
26
+
27
+mlx_status
28
+mlx_set_wol (
29
+	IN mlx_utils *utils,
30
+	IN mlx_uint8 wol_mask
31
+	)
32
+{
33
+	mlx_status status = MLX_SUCCESS;
34
+	struct mlx_wol_rol wol_rol;
35
+
36
+	if (utils == NULL) {
37
+		status = MLX_INVALID_PARAMETER;
38
+		goto bad_param;
39
+	}
40
+
41
+	mlx_memory_set(utils, &wol_rol, 0, sizeof(wol_rol));
42
+	wol_rol.wol_mode_valid = TRUE;
43
+	wol_rol.wol_mode = wol_mask;
44
+	status = mlx_icmd_send_command(
45
+			utils,
46
+			SET_WOL_ROL,
47
+			&wol_rol,
48
+			sizeof(wol_rol),
49
+			0
50
+			);
51
+	MLX_CHECK_STATUS(utils, status, icmd_err, "mlx_icmd_send_command failed");
52
+icmd_err:
53
+bad_param:
54
+	return status;
55
+}
56
+
57
+mlx_status
58
+mlx_query_wol (
59
+	IN mlx_utils *utils,
60
+	OUT mlx_uint8 *wol_mask
61
+	)
62
+{
63
+	mlx_status status = MLX_SUCCESS;
64
+	struct mlx_wol_rol wol_rol;
65
+
66
+	if (utils == NULL || wol_mask == NULL) {
67
+		status = MLX_INVALID_PARAMETER;
68
+		goto bad_param;
69
+	}
70
+
71
+	mlx_memory_set(utils, &wol_rol, 0, sizeof(wol_rol));
72
+	status = mlx_icmd_send_command(
73
+			utils,
74
+			QUERY_WOL_ROL,
75
+			&wol_rol,
76
+			0,
77
+			sizeof(wol_rol)
78
+			);
79
+	MLX_CHECK_STATUS(utils, status, icmd_err, "mlx_icmd_send_command failed");
80
+	*wol_mask = wol_rol.wol_mode;
81
+icmd_err:
82
+bad_param:
83
+	return status;
84
+}

+ 61
- 0
src/drivers/infiniband/mlx_utils/mlx_lib/mlx_wol_rol/mlx_wol_rol.h Visa fil

@@ -0,0 +1,61 @@
1
+#ifndef MLX_WOL_ROL_H_
2
+#define MLX_WOL_ROL_H_
3
+
4
+/*
5
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
6
+ *
7
+ * This program is free software; you can redistribute it and/or
8
+ * modify it under the terms of the GNU General Public License as
9
+ * published by the Free Software Foundation; either version 2 of the
10
+ * License, or any later version.
11
+ *
12
+ * This program is distributed in the hope that it will be useful, but
13
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
14
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15
+ * General Public License for more details.
16
+ *
17
+ * You should have received a copy of the GNU General Public License
18
+ * along with this program; if not, write to the Free Software
19
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20
+ * 02110-1301, USA.
21
+ */
22
+
23
+FILE_LICENCE ( GPL2_OR_LATER );
24
+
25
+
26
+#include "mlx_utils.h"
27
+
28
+typedef enum {
29
+	WOL_MODE_DISABLE = 0x0,
30
+	WOL_MODE_SECURE = 0x2,
31
+	WOL_MODE_MAGIC = 0x4,
32
+	WOL_MODE_ARP = 0x8,
33
+	WOL_MODE_BC = 0x10,
34
+	WOL_MODE_MC = 0x20,
35
+	WOL_MODE_UC = 0x40,
36
+	WOL_MODE_PHY = 0x80,
37
+} WOL_MODE;
38
+
39
+struct mlx_wol_rol {
40
+	mlx_uint32 reserved0	:32;
41
+	mlx_uint32 reserved1	:32;
42
+	mlx_uint32 wol_mode		:8;
43
+	mlx_uint32 rol_mode		:8;
44
+	mlx_uint32 reserved3	:14;
45
+	mlx_uint32 wol_mode_valid	:1;
46
+	mlx_uint32 rol_mode_valid	:1;
47
+};
48
+
49
+mlx_status
50
+mlx_set_wol (
51
+	IN mlx_utils *utils,
52
+	IN mlx_uint8 wol_mask
53
+	);
54
+
55
+mlx_status
56
+mlx_query_wol (
57
+	IN mlx_utils *utils,
58
+	OUT mlx_uint8 *wol_mask
59
+	);
60
+
61
+#endif /* MLX_WOL_ROL_H_ */

+ 9
- 0
src/drivers/infiniband/mlx_utils/src/private/uefi/mlx_logging_impl.c Visa fil

@@ -0,0 +1,9 @@
1
+MlxDebugLogImpl()
2
+		{
3
+	DBGC((DEBUG),"");
4
+		}
5
+MlxInfoLogImpl()
6
+{
7
+	DBGC((INFO),"");
8
+			}
9
+}

+ 371
- 0
src/drivers/infiniband/mlx_utils/src/public/mlx_icmd.c Visa fil

@@ -0,0 +1,371 @@
1
+/*
2
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
3
+ *
4
+ * This program is free software; you can redistribute it and/or
5
+ * modify it under the terms of the GNU General Public License as
6
+ * published by the Free Software Foundation; either version 2 of the
7
+ * License, or any later version.
8
+ *
9
+ * This program is distributed in the hope that it will be useful, but
10
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
11
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
12
+ * General Public License for more details.
13
+ *
14
+ * You should have received a copy of the GNU General Public License
15
+ * along with this program; if not, write to the Free Software
16
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17
+ * 02110-1301, USA.
18
+ */
19
+
20
+
21
+FILE_LICENCE ( GPL2_OR_LATER );
22
+
23
+#include "../../include/public/mlx_bail.h"
24
+#include "../../include/public/mlx_icmd.h"
25
+#include "../../include/public/mlx_pci_gw.h"
26
+#include "../../include/public/mlx_utils.h"
27
+
28
+static
29
+mlx_status
30
+mlx_icmd_get_semaphore(
31
+				IN mlx_utils *utils
32
+				)
33
+{
34
+	mlx_status status = MLX_SUCCESS;
35
+	mlx_uint32 retries = 0;
36
+	mlx_uint32 semaphore_id;
37
+	mlx_uint32 buffer;
38
+	if (utils == NULL) {
39
+		status = MLX_INVALID_PARAMETER;
40
+		goto invalid_param;
41
+	}
42
+
43
+	status = mlx_utils_rand(utils, &semaphore_id);
44
+	MLX_CHECK_STATUS(utils, status, rand_err, "failed to get random number");
45
+#define ICMD_GET_SEMAPHORE_TRIES 2560
46
+	for (retries = 0 ; retries < ICMD_GET_SEMAPHORE_TRIES ; retries++) {
47
+		status = mlx_pci_gw_read( utils, PCI_GW_SPACE_SEMAPHORE,
48
+					MLX_ICMD_SEMAPHORE_ADDR, &buffer);
49
+		MLX_CHECK_STATUS(utils, status, read_err, "failed to read icmd semaphore");
50
+		if (buffer != 0) {
51
+			mlx_utils_delay_in_ms(10);
52
+			continue;
53
+		}
54
+		mlx_pci_gw_write( utils, PCI_GW_SPACE_SEMAPHORE,
55
+							MLX_ICMD_SEMAPHORE_ADDR, semaphore_id);
56
+		MLX_CHECK_STATUS(utils, status, set_err, "failed to set icmd semaphore");
57
+		status = mlx_pci_gw_read( utils, PCI_GW_SPACE_SEMAPHORE,
58
+							MLX_ICMD_SEMAPHORE_ADDR, &buffer);
59
+		MLX_CHECK_STATUS(utils, status, read_err, "failed to read icmd semaphore");
60
+		if (semaphore_id == buffer) {
61
+			status = MLX_SUCCESS;
62
+			utils->icmd.took_semaphore = TRUE;
63
+			break;
64
+		}
65
+		mlx_utils_delay_in_ms(10);
66
+	}
67
+	if (semaphore_id != buffer) {
68
+		status = MLX_FAILED;
69
+	}
70
+read_err:
71
+set_err:
72
+rand_err:
73
+invalid_param:
74
+	return status;
75
+}
76
+static
77
+mlx_status
78
+mlx_icmd_clear_semaphore(
79
+				IN mlx_utils *utils
80
+				)
81
+{
82
+	mlx_status status = MLX_SUCCESS;
83
+
84
+	if (utils == NULL) {
85
+		status = MLX_INVALID_PARAMETER;
86
+		goto invalid_param;
87
+	}
88
+
89
+	if (utils->icmd.took_semaphore == FALSE) {
90
+		goto semaphore_not_taken;
91
+	}
92
+	status = mlx_pci_gw_write( utils, PCI_GW_SPACE_SEMAPHORE,
93
+			MLX_ICMD_SEMAPHORE_ADDR, 0);
94
+	MLX_CHECK_STATUS(utils, status, read_err, "failed to clear icmd semaphore");
95
+
96
+	utils->icmd.took_semaphore = FALSE;
97
+read_err:
98
+semaphore_not_taken:
99
+invalid_param:
100
+	return status;
101
+}
102
+
103
+static
104
+mlx_status
105
+mlx_icmd_init(
106
+				IN mlx_utils *utils
107
+				)
108
+{
109
+	mlx_status status = MLX_SUCCESS;
110
+
111
+	if (utils == NULL) {
112
+		status = MLX_INVALID_PARAMETER;
113
+		goto invalid_param;
114
+	}
115
+	if (utils->icmd.icmd_opened == TRUE) {
116
+		goto already_opened;
117
+	}
118
+
119
+	utils->icmd.took_semaphore = FALSE;
120
+
121
+	status = mlx_pci_gw_read( utils, PCI_GW_SPACE_ALL_ICMD,
122
+			MLX_ICMD_MB_SIZE_ADDR, &utils->icmd.max_cmd_size);
123
+	MLX_CHECK_STATUS(utils, status, read_err, "failed to read icmd mail box size");
124
+
125
+	utils->icmd.icmd_opened = TRUE;
126
+read_err:
127
+already_opened:
128
+invalid_param:
129
+	return status;
130
+}
131
+
132
+static
133
+mlx_status
134
+mlx_icmd_set_opcode(
135
+				IN mlx_utils *utils,
136
+				IN mlx_uint16 opcode
137
+				)
138
+{
139
+	mlx_status status = MLX_SUCCESS;
140
+	mlx_uint32 buffer;
141
+
142
+	if (utils == NULL) {
143
+		status = MLX_INVALID_PARAMETER;
144
+		goto invalid_param;
145
+	}
146
+
147
+	status = mlx_pci_gw_read( utils, PCI_GW_SPACE_ALL_ICMD,
148
+				MLX_ICMD_CTRL_ADDR, &buffer);
149
+	MLX_CHECK_STATUS(utils, status, read_err, "failed to read icmd ctrl");
150
+
151
+#define MLX_ICMD_OPCODE_ALIGN 16
152
+#define MLX_ICMD_OPCODE_MASK 0xffff
153
+
154
+	buffer = buffer & ~(MLX_ICMD_OPCODE_MASK << MLX_ICMD_OPCODE_ALIGN);
155
+	buffer = buffer | (opcode << MLX_ICMD_OPCODE_ALIGN);
156
+
157
+	status = mlx_pci_gw_write( utils, PCI_GW_SPACE_ALL_ICMD,
158
+					MLX_ICMD_CTRL_ADDR, buffer);
159
+	MLX_CHECK_STATUS(utils, status, write_err, "failed to write icmd ctrl");
160
+write_err:
161
+read_err:
162
+invalid_param:
163
+	return status;
164
+}
165
+
166
+static
167
+mlx_status
168
+mlx_icmd_go(
169
+			IN mlx_utils *utils
170
+			)
171
+{
172
+	mlx_status status = MLX_SUCCESS;
173
+	mlx_uint32 buffer;
174
+	mlx_uint32 busy;
175
+	mlx_uint32 wait_iteration = 0;
176
+
177
+	if (utils == NULL) {
178
+		status = MLX_INVALID_PARAMETER;
179
+		goto invalid_param;
180
+	}
181
+
182
+	status = mlx_pci_gw_read( utils, PCI_GW_SPACE_ALL_ICMD,
183
+				MLX_ICMD_CTRL_ADDR, &buffer);
184
+	MLX_CHECK_STATUS(utils, status, read_err, "failed to read icmd ctrl");
185
+
186
+#define MLX_ICMD_BUSY_ALIGN 0
187
+#define MLX_ICMD_BUSY_MASK 0x1
188
+
189
+	busy = (buffer >> MLX_ICMD_BUSY_ALIGN) & MLX_ICMD_BUSY_MASK;
190
+	if (busy != 0) {
191
+		status = MLX_FAILED;
192
+		goto already_busy;
193
+	}
194
+
195
+	buffer = buffer | (1 << MLX_ICMD_BUSY_ALIGN);
196
+
197
+	status = mlx_pci_gw_write( utils, PCI_GW_SPACE_ALL_ICMD,
198
+					MLX_ICMD_CTRL_ADDR, buffer);
199
+	MLX_CHECK_STATUS(utils, status, write_err, "failed to write icmd ctrl");
200
+
201
+#define MLX_ICMD_BUSY_MAX_ITERATIONS 1024
202
+	do {
203
+		if (++wait_iteration > MLX_ICMD_BUSY_MAX_ITERATIONS) {
204
+			status = MLX_FAILED;
205
+			MLX_DEBUG_ERROR(utils, "ICMD time out");
206
+			goto busy_timeout;
207
+		}
208
+
209
+		mlx_utils_delay_in_ms(10);
210
+		status = mlx_pci_gw_read( utils, PCI_GW_SPACE_ALL_ICMD,
211
+					MLX_ICMD_CTRL_ADDR, &buffer);
212
+		MLX_CHECK_STATUS(utils, status, read_err, "failed to read icmd ctrl");
213
+		busy = (buffer >> MLX_ICMD_BUSY_ALIGN) & MLX_ICMD_BUSY_MASK;
214
+	} while (busy != 0);
215
+
216
+busy_timeout:
217
+write_err:
218
+already_busy:
219
+read_err:
220
+invalid_param:
221
+	return status;
222
+}
223
+
224
+static
225
+mlx_status
226
+mlx_icmd_get_status(
227
+			IN mlx_utils *utils,
228
+			OUT mlx_uint32 *out_status
229
+			)
230
+{
231
+	mlx_status status = MLX_SUCCESS;
232
+	mlx_uint32 buffer;
233
+
234
+	if (utils == NULL || out_status == NULL) {
235
+		status = MLX_INVALID_PARAMETER;
236
+		goto invalid_param;
237
+	}
238
+
239
+	status = mlx_pci_gw_read( utils, PCI_GW_SPACE_ALL_ICMD,
240
+				MLX_ICMD_CTRL_ADDR, &buffer);
241
+	MLX_CHECK_STATUS(utils, status, read_err, "failed to read icmd ctrl");
242
+
243
+#define MLX_ICMD_STATUS_ALIGN 8
244
+#define MLX_ICMD_STATUS_MASK 0xff
245
+
246
+	*out_status = (buffer >> MLX_ICMD_STATUS_ALIGN) & MLX_ICMD_STATUS_MASK;
247
+
248
+read_err:
249
+invalid_param:
250
+	return status;
251
+}
252
+
253
+static
254
+mlx_status
255
+mlx_icmd_write_buffer(
256
+		IN mlx_utils *utils,
257
+		IN mlx_void* data,
258
+		IN mlx_uint32 data_size
259
+		)
260
+{
261
+	mlx_status status = MLX_SUCCESS;
262
+	mlx_uint32 data_offset = 0;
263
+	mlx_size dword_size = sizeof(mlx_uint32);
264
+
265
+	if (utils == NULL || data == NULL) {
266
+		status = MLX_INVALID_PARAMETER;
267
+		goto invalid_param;
268
+	}
269
+
270
+	for (data_offset = 0 ; data_offset*dword_size < data_size ; data_offset++) {
271
+		status = mlx_pci_gw_write( utils, PCI_GW_SPACE_ALL_ICMD,
272
+							MLX_ICMD_MB_ADDR + data_offset*dword_size,
273
+							((mlx_uint32*)data)[data_offset]);
274
+		MLX_CHECK_STATUS(utils, status, write_err, "failed to write icmd MB");
275
+	}
276
+write_err:
277
+invalid_param:
278
+	return status;
279
+}
280
+
281
+
282
+static
283
+mlx_status
284
+mlx_icmd_read_buffer(
285
+		IN mlx_utils *utils,
286
+		OUT mlx_void* data,
287
+		IN mlx_uint32 data_size
288
+		)
289
+{
290
+	mlx_status status = MLX_SUCCESS;
291
+	mlx_uint32 data_offset = 0;
292
+	mlx_size dword_size = sizeof(mlx_uint32);
293
+
294
+	if (utils == NULL || data == NULL) {
295
+		status = MLX_INVALID_PARAMETER;
296
+		goto invalid_param;
297
+	}
298
+
299
+	for (data_offset = 0 ; data_offset*dword_size < data_size ; data_offset++) {
300
+		status = mlx_pci_gw_read( utils, PCI_GW_SPACE_ALL_ICMD,
301
+							MLX_ICMD_MB_ADDR + data_offset*dword_size,
302
+							(mlx_uint32*)data + data_offset);
303
+		MLX_CHECK_STATUS(utils, status, read_err, "failed to read icmd MB");
304
+	}
305
+read_err:
306
+invalid_param:
307
+	return status;
308
+}
309
+mlx_status
310
+mlx_icmd_send_command(
311
+				IN mlx_utils *utils,
312
+				IN  mlx_uint16 opcode,
313
+				IN OUT mlx_void* data,
314
+				IN mlx_uint32 write_data_size,
315
+				IN mlx_uint32 read_data_size
316
+				)
317
+{
318
+	mlx_status status = MLX_SUCCESS;
319
+	mlx_uint32 icmd_status;
320
+
321
+	if (utils == NULL || data == NULL) {
322
+		status = MLX_INVALID_PARAMETER;
323
+		goto invalid_param;
324
+	}
325
+	status = mlx_icmd_init(utils);
326
+	MLX_CHECK_STATUS(utils, status, open_err, "failed to open icmd");
327
+
328
+	if (write_data_size > utils->icmd.max_cmd_size ||
329
+			read_data_size > utils->icmd.max_cmd_size) {
330
+		status = MLX_INVALID_PARAMETER;
331
+		goto size_err;
332
+	}
333
+
334
+	status = mlx_icmd_get_semaphore(utils);
335
+	MLX_CHECK_STATUS(utils, status, semaphore_err, "failed to get icmd semaphore");
336
+
337
+	status = mlx_icmd_set_opcode(utils, opcode);
338
+	MLX_CHECK_STATUS(utils, status, opcode_err, "failed to set icmd opcode");
339
+
340
+	if (write_data_size != 0) {
341
+		status = mlx_icmd_write_buffer(utils, data, write_data_size);
342
+		MLX_CHECK_STATUS(utils, status, opcode_err, "failed to write icmd MB");
343
+	}
344
+
345
+	status = mlx_icmd_go(utils);
346
+	MLX_CHECK_STATUS(utils, status, go_err, "failed to activate icmd");
347
+
348
+	status = mlx_icmd_get_status(utils, &icmd_status);
349
+	MLX_CHECK_STATUS(utils, status, get_status_err, "failed to set icmd opcode");
350
+
351
+	if (icmd_status != 0) {
352
+		MLX_DEBUG_ERROR(utils, "icmd failed with status = %d\n", icmd_status);
353
+		status = MLX_FAILED;
354
+		goto icmd_failed;
355
+	}
356
+	if (read_data_size != 0) {
357
+		status = mlx_icmd_read_buffer(utils, data, read_data_size);
358
+		MLX_CHECK_STATUS(utils, status, read_err, "failed to read icmd MB");
359
+	}
360
+read_err:
361
+icmd_failed:
362
+get_status_err:
363
+go_err:
364
+opcode_err:
365
+	mlx_icmd_clear_semaphore(utils);
366
+semaphore_err:
367
+size_err:
368
+open_err:
369
+invalid_param:
370
+	return status;
371
+}

+ 238
- 0
src/drivers/infiniband/mlx_utils/src/public/mlx_memory.c Visa fil

@@ -0,0 +1,238 @@
1
+/*
2
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
3
+ *
4
+ * This program is free software; you can redistribute it and/or
5
+ * modify it under the terms of the GNU General Public License as
6
+ * published by the Free Software Foundation; either version 2 of the
7
+ * License, or any later version.
8
+ *
9
+ * This program is distributed in the hope that it will be useful, but
10
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
11
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
12
+ * General Public License for more details.
13
+ *
14
+ * You should have received a copy of the GNU General Public License
15
+ * along with this program; if not, write to the Free Software
16
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17
+ * 02110-1301, USA.
18
+ */
19
+
20
+FILE_LICENCE ( GPL2_OR_LATER );
21
+
22
+#include <stddef.h>
23
+#include "../../include/private/mlx_memory_priv.h"
24
+#include "../../include/public/mlx_memory.h"
25
+
26
+mlx_status
27
+mlx_memory_alloc(
28
+				IN mlx_utils *utils,
29
+				IN mlx_size size,
30
+				OUT mlx_void **ptr
31
+				)
32
+{
33
+	mlx_status status = MLX_SUCCESS;
34
+	*ptr = NULL;
35
+	if ( utils == NULL || size == 0 || *ptr != NULL ){
36
+		status = MLX_INVALID_PARAMETER;
37
+		goto bad_param;
38
+	}
39
+	status = mlx_memory_alloc_priv(utils, size, ptr);
40
+bad_param:
41
+	return status;
42
+}
43
+
44
+mlx_status
45
+mlx_memory_zalloc(
46
+				IN mlx_utils *utils,
47
+				IN mlx_size size,
48
+				OUT mlx_void **ptr
49
+				)
50
+{
51
+	mlx_status status = MLX_SUCCESS;
52
+	*ptr = NULL;
53
+	if ( utils == NULL || size == 0 || *ptr != NULL ){
54
+		status = MLX_INVALID_PARAMETER;
55
+		goto bad_param;
56
+	}
57
+	status = mlx_memory_zalloc_priv(utils, size, ptr);
58
+bad_param:
59
+	return status;
60
+}
61
+
62
+mlx_status
63
+mlx_memory_free(
64
+				IN mlx_utils *utils,
65
+				IN mlx_void **ptr
66
+				)
67
+{
68
+	mlx_status status = MLX_SUCCESS;
69
+	if ( utils == NULL ||  ptr == NULL || *ptr == NULL ){
70
+		status = MLX_INVALID_PARAMETER;
71
+		goto bad_param;
72
+	}
73
+	status = mlx_memory_free_priv(utils, *ptr);
74
+	*ptr = NULL;
75
+bad_param:
76
+	return status;
77
+}
78
+mlx_status
79
+mlx_memory_alloc_dma(
80
+					IN mlx_utils *utils,
81
+					IN mlx_size size ,
82
+					IN mlx_size align,
83
+					OUT mlx_void **ptr
84
+					)
85
+{
86
+	mlx_status status = MLX_SUCCESS;
87
+	*ptr = NULL;
88
+	if ( utils == NULL || size == 0 || *ptr != NULL ){
89
+		status = MLX_INVALID_PARAMETER;
90
+		goto bad_param;
91
+	}
92
+	status = mlx_memory_alloc_dma_priv(utils, size, align, ptr);
93
+bad_param:
94
+	return status;
95
+}
96
+
97
+mlx_status
98
+mlx_memory_free_dma(
99
+					IN mlx_utils *utils,
100
+					IN mlx_size size ,
101
+					IN mlx_void **ptr
102
+					)
103
+{
104
+	mlx_status status = MLX_SUCCESS;
105
+	if ( utils == NULL || size == 0 || ptr == NULL || *ptr == NULL ){
106
+		status = MLX_INVALID_PARAMETER;
107
+		goto bad_param;
108
+	}
109
+	status = mlx_memory_free_dma_priv(utils, size, *ptr);
110
+	*ptr = NULL;
111
+bad_param:
112
+	return status;
113
+}
114
+
115
+mlx_status
116
+mlx_memory_map_dma(
117
+					IN mlx_utils *utils,
118
+					IN mlx_void *addr ,
119
+					IN mlx_size number_of_bytes,
120
+					OUT mlx_physical_address *phys_addr,
121
+					OUT mlx_void **mapping
122
+					)
123
+{
124
+	mlx_status status = MLX_SUCCESS;
125
+	if ( utils == NULL || phys_addr == NULL ){
126
+		status = MLX_INVALID_PARAMETER;
127
+		goto bad_param;
128
+	}
129
+	status = mlx_memory_map_dma_priv(utils, addr, number_of_bytes, phys_addr, mapping);
130
+bad_param:
131
+	return status;
132
+}
133
+
134
+mlx_status
135
+mlx_memory_ummap_dma(
136
+					IN mlx_utils *utils,
137
+					IN mlx_void *mapping
138
+					)
139
+{
140
+	mlx_status status = MLX_SUCCESS;
141
+	if ( utils == NULL){
142
+		status = MLX_INVALID_PARAMETER;
143
+		goto bad_param;
144
+	}
145
+	status = mlx_memory_ummap_dma_priv(utils, mapping);
146
+bad_param:
147
+	return status;
148
+}
149
+
150
+mlx_status
151
+mlx_memory_cmp(
152
+			IN mlx_utils *utils,
153
+			IN mlx_void *first_block,
154
+			IN mlx_void *second_block,
155
+			IN mlx_size size,
156
+			OUT mlx_uint32 *out
157
+			)
158
+{
159
+	mlx_status status = MLX_SUCCESS;
160
+	if ( utils == NULL || first_block == NULL || second_block == NULL ||
161
+			out == NULL){
162
+		status = MLX_INVALID_PARAMETER;
163
+		goto bad_param;
164
+	}
165
+	status = mlx_memory_cmp_priv(utils, first_block, second_block, size, out);
166
+bad_param:
167
+	return status;
168
+}
169
+
170
+mlx_status
171
+mlx_memory_set(
172
+					IN mlx_utils *utils,
173
+					IN mlx_void *block,
174
+					IN mlx_int32 value,
175
+					IN mlx_size size
176
+					)
177
+{
178
+	mlx_status status = MLX_SUCCESS;
179
+	if ( utils == NULL || block == NULL){
180
+		status = MLX_INVALID_PARAMETER;
181
+		goto bad_param;
182
+	}
183
+	status = mlx_memory_set_priv(utils, block, value, size);
184
+bad_param:
185
+	return status;
186
+}
187
+
188
+mlx_status
189
+mlx_memory_cpy(
190
+			IN mlx_utils *utils,
191
+			OUT mlx_void *destination_buffer,
192
+			IN mlx_void *source_buffer,
193
+			IN mlx_size length
194
+			)
195
+{
196
+	mlx_status status = MLX_SUCCESS;
197
+	if ( utils == NULL || destination_buffer == NULL || source_buffer == NULL){
198
+		status = MLX_INVALID_PARAMETER;
199
+		goto bad_param;
200
+	}
201
+	status = mlx_memory_cpy_priv(utils, destination_buffer, source_buffer, length);
202
+bad_param:
203
+	return status;
204
+}
205
+
206
+mlx_status
207
+mlx_memory_cpu_to_be32(
208
+			IN mlx_utils *utils,
209
+			IN mlx_uint32 source,
210
+			IN mlx_uint32 *destination
211
+			)
212
+{
213
+	mlx_status status = MLX_SUCCESS;
214
+	if ( utils == NULL || destination == NULL ){
215
+		status = MLX_INVALID_PARAMETER;
216
+		goto bad_param;
217
+	}
218
+	status = mlx_memory_cpu_to_be32_priv(utils, source, destination);
219
+bad_param:
220
+	return status;
221
+}
222
+
223
+mlx_status
224
+mlx_memory_be32_to_cpu(
225
+			IN mlx_utils *utils,
226
+			IN mlx_uint32 source,
227
+			IN mlx_uint32 *destination
228
+			)
229
+{
230
+	mlx_status status = MLX_SUCCESS;
231
+	if ( utils == NULL || destination == NULL ){
232
+		status = MLX_INVALID_PARAMETER;
233
+		goto bad_param;
234
+	}
235
+	status = mlx_memory_be32_to_cpu_priv(utils, source, destination);
236
+bad_param:
237
+	return status;
238
+}

+ 117
- 0
src/drivers/infiniband/mlx_utils/src/public/mlx_pci.c Visa fil

@@ -0,0 +1,117 @@
1
+/*
2
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
3
+ *
4
+ * This program is free software; you can redistribute it and/or
5
+ * modify it under the terms of the GNU General Public License as
6
+ * published by the Free Software Foundation; either version 2 of the
7
+ * License, or any later version.
8
+ *
9
+ * This program is distributed in the hope that it will be useful, but
10
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
11
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
12
+ * General Public License for more details.
13
+ *
14
+ * You should have received a copy of the GNU General Public License
15
+ * along with this program; if not, write to the Free Software
16
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17
+ * 02110-1301, USA.
18
+ */
19
+
20
+FILE_LICENCE ( GPL2_OR_LATER );
21
+
22
+#include <stddef.h>
23
+#include "../../include/private/mlx_pci_priv.h"
24
+#include "../../include/public/mlx_pci.h"
25
+
26
+mlx_status
27
+mlx_pci_init(
28
+			IN mlx_utils *utils
29
+			)
30
+{
31
+	mlx_status status = MLX_SUCCESS;
32
+	if( utils == NULL){
33
+		status = MLX_INVALID_PARAMETER;
34
+		goto bail;
35
+	}
36
+	status = mlx_pci_init_priv(utils);
37
+bail:
38
+	return status;
39
+}
40
+
41
+mlx_status
42
+mlx_pci_read(
43
+			IN mlx_utils *utils,
44
+			IN mlx_pci_width width,
45
+			IN mlx_uint32 offset,
46
+			IN mlx_uintn count,
47
+			OUT mlx_void *buffer
48
+			)
49
+{
50
+	mlx_status status = MLX_SUCCESS;
51
+	if( utils == NULL || count == 0){
52
+		status = MLX_INVALID_PARAMETER;
53
+		goto bail;
54
+	}
55
+	status = mlx_pci_read_priv(utils, width, offset, count, buffer);
56
+bail:
57
+	return status;
58
+}
59
+
60
+mlx_status
61
+mlx_pci_write(
62
+			IN mlx_utils *utils,
63
+			IN mlx_pci_width width,
64
+			IN mlx_uint32 offset,
65
+			IN mlx_uintn count,
66
+			IN mlx_void *buffer
67
+			)
68
+{
69
+	mlx_status status = MLX_SUCCESS;
70
+	if( utils == NULL || count == 0){
71
+		status = MLX_INVALID_PARAMETER;
72
+		goto bail;
73
+	}
74
+	status = mlx_pci_write_priv(utils, width, offset, count, buffer);
75
+bail:
76
+	return status;
77
+}
78
+
79
+mlx_status
80
+mlx_pci_mem_read(
81
+				IN mlx_utils *utils,
82
+				IN mlx_pci_width width,
83
+				IN mlx_uint8 bar_index,
84
+				IN mlx_uint64 offset,
85
+				IN mlx_uintn count,
86
+				OUT mlx_void *buffer
87
+				)
88
+{
89
+	mlx_status status = MLX_SUCCESS;
90
+	if( utils == NULL || count == 0){
91
+		status = MLX_INVALID_PARAMETER;
92
+		goto bail;
93
+	}
94
+	status = mlx_pci_mem_read_priv(utils, bar_index, width, offset, count, buffer);
95
+bail:
96
+	return status;
97
+}
98
+
99
+mlx_status
100
+mlx_pci_mem_write(
101
+				IN mlx_utils *utils,
102
+				IN mlx_pci_width width,
103
+				IN mlx_uint8 bar_index,
104
+				IN mlx_uint64 offset,
105
+				IN mlx_uintn count,
106
+				IN mlx_void *buffer
107
+				)
108
+{
109
+	mlx_status status = MLX_SUCCESS;
110
+	if( utils == NULL || count == 0){
111
+		status = MLX_INVALID_PARAMETER;
112
+		goto bail;
113
+	}
114
+	status = mlx_pci_mem_write_priv(utils, width, bar_index, offset, count, buffer);
115
+bail:
116
+	return status;
117
+}

+ 392
- 0
src/drivers/infiniband/mlx_utils/src/public/mlx_pci_gw.c Visa fil

@@ -0,0 +1,392 @@
1
+/*
2
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
3
+ *
4
+ * This program is free software; you can redistribute it and/or
5
+ * modify it under the terms of the GNU General Public License as
6
+ * published by the Free Software Foundation; either version 2 of the
7
+ * License, or any later version.
8
+ *
9
+ * This program is distributed in the hope that it will be useful, but
10
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
11
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
12
+ * General Public License for more details.
13
+ *
14
+ * You should have received a copy of the GNU General Public License
15
+ * along with this program; if not, write to the Free Software
16
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17
+ * 02110-1301, USA.
18
+ */
19
+
20
+FILE_LICENCE ( GPL2_OR_LATER );
21
+
22
+#include "../../include/public/mlx_pci_gw.h"
23
+#include "../../include/public/mlx_bail.h"
24
+#include "../../include/public/mlx_pci.h"
25
+#include "../../include/public/mlx_logging.h"
26
+
27
+/* Lock/unlock GW on each VSEC access */
28
+#undef VSEC_DEBUG
29
+
30
+static
31
+mlx_status
32
+mlx_pci_gw_check_capability_id(
33
+							IN mlx_utils *utils,
34
+							IN mlx_uint8 cap_pointer,
35
+							OUT mlx_boolean *bool
36
+							)
37
+{
38
+	mlx_status 		status = MLX_SUCCESS;
39
+	mlx_uint8 		offset = cap_pointer + PCI_GW_CAPABILITY_ID_OFFSET;
40
+	mlx_uint8 		id = 0;
41
+	status = mlx_pci_read(utils, MlxPciWidthUint8, offset,
42
+				1, &id);
43
+	MLX_CHECK_STATUS(utils, status, read_err,"failed to read capability id");
44
+	*bool = ( id == PCI_GW_CAPABILITY_ID );
45
+read_err:
46
+	return status;
47
+}
48
+
49
+static
50
+mlx_status
51
+mlx_pci_gw_get_ownership(
52
+						IN mlx_utils *utils
53
+						)
54
+{
55
+	mlx_status 			status = MLX_SUCCESS;
56
+	mlx_uint32			cap_offset = utils->pci_gw.pci_cmd_offset;
57
+	mlx_uint32 			semaphore = 0;
58
+	mlx_uint32		 	counter = 0;
59
+	mlx_uint32 			get_semaphore_try = 0;
60
+	mlx_uint32 			get_ownership_try = 0;
61
+
62
+	for( ; get_ownership_try < PCI_GW_GET_OWNERSHIP_TRIES; get_ownership_try ++){
63
+		for( ; get_semaphore_try <= PCI_GW_SEMPHORE_TRIES ; get_semaphore_try++){
64
+			status = mlx_pci_read(utils, MlxPciWidthUint32, cap_offset + PCI_GW_CAPABILITY_SEMAPHORE_OFFSET,
65
+					1, &semaphore);
66
+			MLX_CHECK_STATUS(utils, status, read_err,"failed to read semaphore");
67
+			if( semaphore == 0 ){
68
+				break;
69
+			}
70
+			mlx_utils_delay_in_us(10);
71
+		}
72
+		if( semaphore != 0 ){
73
+			status = MLX_FAILED;
74
+			goto semaphore_err;
75
+		}
76
+
77
+		status = mlx_pci_read(utils, MlxPciWidthUint32, cap_offset + PCI_GW_CAPABILITY_COUNTER_OFFSET,
78
+						1, &counter);
79
+		MLX_CHECK_STATUS(utils, status, read_err, "failed to read counter");
80
+
81
+		status = mlx_pci_write(utils, MlxPciWidthUint32, cap_offset + PCI_GW_CAPABILITY_SEMAPHORE_OFFSET,
82
+						1, &counter);
83
+		MLX_CHECK_STATUS(utils, status, write_err,"failed to write semaphore");
84
+
85
+		status = mlx_pci_read(utils, MlxPciWidthUint32, cap_offset + PCI_GW_CAPABILITY_SEMAPHORE_OFFSET,
86
+						1, &semaphore);
87
+		MLX_CHECK_STATUS(utils, status, read_err,"failed to read semaphore");
88
+		if( counter == semaphore ){
89
+			break;
90
+		}
91
+	}
92
+	if( counter != semaphore ){
93
+		status = MLX_FAILED;
94
+	}
95
+write_err:
96
+read_err:
97
+semaphore_err:
98
+	return status;
99
+}
100
+
101
+static
102
+mlx_status
103
+mlx_pci_gw_free_ownership(
104
+						IN mlx_utils *utils
105
+						)
106
+{
107
+	mlx_status 		status = MLX_SUCCESS;
108
+	mlx_uint32		cap_offset = utils->pci_gw.pci_cmd_offset;
109
+	mlx_uint32 		value = 0;
110
+
111
+	status = mlx_pci_write(utils, MlxPciWidthUint32, cap_offset + PCI_GW_CAPABILITY_SEMAPHORE_OFFSET,
112
+					1, &value);
113
+	MLX_CHECK_STATUS(utils, status, write_err,"failed to write semaphore");
114
+write_err:
115
+	return status;
116
+}
117
+
118
+static
119
+mlx_status
120
+mlx_pci_gw_set_space(
121
+					IN mlx_utils *utils,
122
+					IN mlx_pci_gw_space space
123
+					)
124
+{
125
+	mlx_status 		status = MLX_SUCCESS;
126
+	mlx_uint32		cap_offset = utils->pci_gw.pci_cmd_offset;;
127
+	mlx_uint8		space_status = 0;
128
+
129
+	/* set nodnic*/
130
+	status = mlx_pci_write(utils, MlxPciWidthUint16, cap_offset + PCI_GW_CAPABILITY_SPACE_OFFSET, 1, &space);
131
+	MLX_CHECK_STATUS(utils, status, read_error,"failed to write capability space");
132
+
133
+	status = mlx_pci_read(utils, MlxPciWidthUint8, cap_offset + PCI_GW_CAPABILITY_STATUS_OFFSET, 1, &space_status);
134
+	MLX_CHECK_STATUS(utils, status, read_error,"failed to read capability status");
135
+	if( (space_status & 0x20) == 0){
136
+		status = MLX_FAILED;
137
+		goto space_unsupported;
138
+	}
139
+read_error:
140
+space_unsupported:
141
+	return status;
142
+}
143
+
144
+static
145
+mlx_status
146
+mlx_pci_gw_wait_for_flag_value(
147
+							IN mlx_utils *utils,
148
+							IN mlx_boolean value
149
+							)
150
+{
151
+	mlx_status 		status = MLX_SUCCESS;
152
+	mlx_uint32 		try = 0;
153
+	mlx_uint32		cap_offset = utils->pci_gw.pci_cmd_offset;
154
+	mlx_uint32		flag = 0;
155
+
156
+	for(; try < PCI_GW_READ_FLAG_TRIES ; try ++ ) {
157
+		status = mlx_pci_read(utils, MlxPciWidthUint32, cap_offset + PCI_GW_CAPABILITY_FLAG_OFFSET, 1, &flag);
158
+		MLX_CHECK_STATUS(utils, status, read_error, "failed to read capability flag");
159
+		if( ((flag & 0x80000000) != 0) == value ){
160
+			goto flag_valid;
161
+		}
162
+		mlx_utils_delay_in_us(10);
163
+	}
164
+	status = MLX_FAILED;
165
+flag_valid:
166
+read_error:
167
+	return status;
168
+}
169
+static
170
+mlx_status
171
+mlx_pci_gw_search_capability(
172
+				IN mlx_utils *utils,
173
+				OUT mlx_uint32	*cap_offset
174
+				)
175
+{
176
+	mlx_status 		status = MLX_SUCCESS;
177
+	mlx_uint8 		cap_pointer = 0;
178
+	mlx_boolean		is_capability = FALSE;
179
+
180
+	if( cap_offset == NULL || utils == NULL){
181
+		status = MLX_INVALID_PARAMETER;
182
+		goto bad_param;
183
+	}
184
+
185
+	//get first capability pointer
186
+	status = mlx_pci_read(utils, MlxPciWidthUint8, PCI_GW_FIRST_CAPABILITY_POINTER_OFFSET,
187
+			1, &cap_pointer);
188
+	MLX_CHECK_STATUS(utils, status, read_err,
189
+			"failed to read capability pointer");
190
+
191
+	//search the right capability
192
+	while( cap_pointer != 0 ){
193
+		status = mlx_pci_gw_check_capability_id(utils, cap_pointer, &is_capability);
194
+		MLX_CHECK_STATUS(utils, status, check_err
195
+				,"failed to check capability id");
196
+
197
+		if( is_capability == TRUE ){
198
+			*cap_offset = cap_pointer;
199
+			break;
200
+		}
201
+
202
+		status = mlx_pci_read(utils, MlxPciWidthUint8, cap_pointer +
203
+				PCI_GW_CAPABILITY_NEXT_POINTER_OFFSET ,
204
+				1, &cap_pointer);
205
+		MLX_CHECK_STATUS(utils, status, read_err,
206
+				"failed to read capability pointer");
207
+	}
208
+	if( is_capability != TRUE ){
209
+		status = MLX_NOT_FOUND;
210
+	}
211
+check_err:
212
+read_err:
213
+bad_param:
214
+	return status;
215
+}
216
+
217
+mlx_status
218
+mlx_pci_gw_init(
219
+			IN mlx_utils *utils
220
+			)
221
+{
222
+	mlx_status 		status = MLX_SUCCESS;
223
+	mlx_pci_gw *pci_gw = NULL;
224
+
225
+	if( utils == NULL){
226
+		status = MLX_INVALID_PARAMETER;
227
+		goto bad_param;
228
+	}
229
+
230
+	pci_gw = &utils->pci_gw;
231
+
232
+	status = mlx_pci_gw_search_capability(utils, &pci_gw->pci_cmd_offset);
233
+	MLX_CHECK_STATUS(utils, status, cap_err,
234
+					"mlx_pci_gw_search_capability failed");
235
+
236
+#if ! defined ( VSEC_DEBUG )
237
+	status = mlx_pci_gw_get_ownership(utils);
238
+	MLX_CHECK_STATUS(utils, status, ownership_err,"failed to get ownership");
239
+ownership_err:
240
+#endif
241
+cap_err:
242
+bad_param:
243
+	return status;
244
+}
245
+
246
+mlx_status
247
+mlx_pci_gw_teardown(
248
+		IN mlx_utils *utils __attribute__ ((unused))
249
+		)
250
+{
251
+#if ! defined ( VSEC_DEBUG )
252
+	mlx_pci_gw_free_ownership(utils);
253
+#endif
254
+	return MLX_SUCCESS;
255
+}
256
+
257
+mlx_status
258
+mlx_pci_gw_read(
259
+		IN mlx_utils *utils,
260
+		IN mlx_pci_gw_space space,
261
+		IN mlx_uint32 address,
262
+		OUT mlx_pci_gw_buffer *buffer
263
+		)
264
+{
265
+	mlx_status 		status = MLX_SUCCESS;
266
+	mlx_pci_gw 		*pci_gw = NULL;
267
+	mlx_uint32		cap_offset = 0;
268
+
269
+	if (utils == NULL || buffer == NULL || utils->pci_gw.pci_cmd_offset == 0) {
270
+		status = MLX_INVALID_PARAMETER;
271
+		goto bad_param;
272
+	}
273
+
274
+	mlx_utils_acquire_lock(utils);
275
+
276
+	pci_gw = &utils->pci_gw;
277
+	cap_offset = pci_gw->pci_cmd_offset;
278
+
279
+#if ! defined ( VSEC_DEBUG )
280
+	if (pci_gw->space != space) {
281
+		   status = mlx_pci_gw_set_space(utils, space);
282
+		   MLX_CHECK_STATUS(utils, status, space_error,"failed to set space");
283
+		   pci_gw->space = space;
284
+	}
285
+#else
286
+	status = mlx_pci_gw_get_ownership(utils);
287
+	MLX_CHECK_STATUS(utils, status, ownership_err,"failed to get ownership");
288
+
289
+	status = mlx_pci_gw_set_space(utils, space);
290
+	MLX_CHECK_STATUS(utils, status, space_error,"failed to set space");
291
+	pci_gw->space = space;
292
+#endif
293
+
294
+	status = mlx_pci_write(utils, MlxPciWidthUint32, cap_offset + PCI_GW_CAPABILITY_ADDRESS_OFFSET, 1, &address);
295
+	MLX_CHECK_STATUS(utils, status, read_error,"failed to write capability address");
296
+
297
+#if defined ( DEVICE_CX3 )
298
+	/* WA for PCI issue (race) */
299
+	mlx_utils_delay_in_us ( 10 );
300
+#endif
301
+
302
+	status = mlx_pci_gw_wait_for_flag_value(utils, TRUE);
303
+	MLX_CHECK_STATUS(utils, status, read_error, "flag failed to change");
304
+
305
+	status = mlx_pci_read(utils, MlxPciWidthUint32, cap_offset + PCI_GW_CAPABILITY_DATA_OFFSET, 1, buffer);
306
+	MLX_CHECK_STATUS(utils, status, read_error,"failed to read capability data");
307
+
308
+#if defined ( VSEC_DEBUG )
309
+	status = mlx_pci_gw_free_ownership(utils);
310
+	MLX_CHECK_STATUS(utils, status, free_err,
311
+						"mlx_pci_gw_free_ownership failed");
312
+free_err:
313
+	mlx_utils_release_lock(utils);
314
+	return status;
315
+#endif
316
+read_error:
317
+space_error:
318
+#if defined ( VSEC_DEBUG )
319
+	mlx_pci_gw_free_ownership(utils);
320
+ownership_err:
321
+#endif
322
+mlx_utils_release_lock(utils);
323
+bad_param:
324
+	return status;
325
+}
326
+
327
+mlx_status
328
+mlx_pci_gw_write(
329
+				IN mlx_utils *utils,
330
+				IN mlx_pci_gw_space space,
331
+				IN mlx_uint32 address,
332
+				IN mlx_pci_gw_buffer buffer
333
+				)
334
+{
335
+	mlx_status 		status = MLX_SUCCESS;
336
+	mlx_pci_gw 		*pci_gw = NULL;
337
+	mlx_uint32		cap_offset = 0;
338
+	mlx_uint32		fixed_address = address | PCI_GW_WRITE_FLAG;
339
+
340
+	if (utils == NULL || utils->pci_gw.pci_cmd_offset == 0) {
341
+		status = MLX_INVALID_PARAMETER;
342
+		goto bad_param;
343
+	}
344
+
345
+	mlx_utils_acquire_lock(utils);
346
+
347
+	pci_gw = &utils->pci_gw;
348
+	cap_offset = pci_gw->pci_cmd_offset;
349
+
350
+#if ! defined ( VSEC_DEBUG )
351
+	if (pci_gw->space != space) {
352
+		   status = mlx_pci_gw_set_space(utils, space);
353
+		   MLX_CHECK_STATUS(utils, status, space_error,"failed to set space");
354
+		   pci_gw->space = space;
355
+	}
356
+#else
357
+	status = mlx_pci_gw_get_ownership(utils);
358
+	MLX_CHECK_STATUS(utils, status, ownership_err,"failed to get ownership");
359
+
360
+	status = mlx_pci_gw_set_space(utils, space);
361
+	MLX_CHECK_STATUS(utils, status, space_error,"failed to set space");
362
+	pci_gw->space = space;
363
+#endif
364
+	status = mlx_pci_write(utils, MlxPciWidthUint32, cap_offset + PCI_GW_CAPABILITY_DATA_OFFSET, 1, &buffer);
365
+	MLX_CHECK_STATUS(utils, status, read_error,"failed to write capability data");
366
+
367
+	status = mlx_pci_write(utils, MlxPciWidthUint32, cap_offset + PCI_GW_CAPABILITY_ADDRESS_OFFSET, 1, &fixed_address);
368
+	MLX_CHECK_STATUS(utils, status, read_error,"failed to write capability address");
369
+
370
+	status = mlx_pci_gw_wait_for_flag_value(utils, FALSE);
371
+	MLX_CHECK_STATUS(utils, status, read_error, "flag failed to change");
372
+#if defined ( VSEC_DEBUG )
373
+	status = mlx_pci_gw_free_ownership(utils);
374
+	MLX_CHECK_STATUS(utils, status, free_err,
375
+						"mlx_pci_gw_free_ownership failed");
376
+free_err:
377
+mlx_utils_release_lock(utils);
378
+	return status;
379
+#endif
380
+read_error:
381
+space_error:
382
+#if defined ( VSEC_DEBUG )
383
+	mlx_pci_gw_free_ownership(utils);
384
+ownership_err:
385
+#endif
386
+mlx_utils_release_lock(utils);
387
+bad_param:
388
+	return status;
389
+}
390
+
391
+
392
+

+ 121
- 0
src/drivers/infiniband/mlx_utils/src/public/mlx_utils.c Visa fil

@@ -0,0 +1,121 @@
1
+/*
2
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
3
+ *
4
+ * This program is free software; you can redistribute it and/or
5
+ * modify it under the terms of the GNU General Public License as
6
+ * published by the Free Software Foundation; either version 2 of the
7
+ * License, or any later version.
8
+ *
9
+ * This program is distributed in the hope that it will be useful, but
10
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
11
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
12
+ * General Public License for more details.
13
+ *
14
+ * You should have received a copy of the GNU General Public License
15
+ * along with this program; if not, write to the Free Software
16
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17
+ * 02110-1301, USA.
18
+ */
19
+
20
+FILE_LICENCE ( GPL2_OR_LATER );
21
+
22
+#include <stddef.h>
23
+#include "../../include/private/mlx_utils_priv.h"
24
+#include "../../include/public/mlx_pci.h"
25
+#include "../../include/public/mlx_utils.h"
26
+
27
+mlx_status
28
+mlx_utils_init(
29
+				IN mlx_utils *utils,
30
+				IN mlx_pci *pci
31
+				)
32
+{
33
+	mlx_status status = MLX_SUCCESS;
34
+	if( pci == NULL || utils == NULL ){
35
+		status = MLX_INVALID_PARAMETER;
36
+		goto bail;
37
+	}
38
+	utils->pci = pci;
39
+	status = mlx_pci_init(utils);
40
+	status = mlx_utils_init_lock(utils);
41
+bail:
42
+	return status;
43
+}
44
+
45
+mlx_status
46
+mlx_utils_teardown(
47
+				IN mlx_utils *utils __attribute__ ((unused))
48
+				)
49
+{
50
+	mlx_status status = MLX_SUCCESS;
51
+	mlx_utils_free_lock(utils);
52
+	return status;
53
+}
54
+
55
+mlx_status
56
+mlx_utils_delay_in_ms(
57
+			IN mlx_uint32 msecs
58
+		)
59
+{
60
+	mlx_utils_delay_in_ms_priv(msecs);
61
+	return MLX_SUCCESS;
62
+}
63
+mlx_status
64
+mlx_utils_delay_in_us(
65
+			IN mlx_uint32 usecs
66
+		)
67
+{
68
+	mlx_utils_delay_in_us_priv(usecs);
69
+	return MLX_SUCCESS;
70
+}
71
+mlx_status
72
+mlx_utils_ilog2(
73
+			IN mlx_uint32 i,
74
+			OUT mlx_uint32 *log
75
+		)
76
+{
77
+	mlx_utils_ilog2_priv(i, log);
78
+	return MLX_SUCCESS;
79
+}
80
+
81
+mlx_status
82
+mlx_utils_init_lock(
83
+			IN OUT mlx_utils *utils
84
+		)
85
+{
86
+	return mlx_utils_init_lock_priv(&(utils->lock));
87
+
88
+}
89
+
90
+mlx_status
91
+mlx_utils_free_lock(
92
+			IN OUT mlx_utils *utils
93
+		)
94
+{
95
+	return mlx_utils_free_lock_priv(utils->lock);
96
+}
97
+
98
+mlx_status
99
+mlx_utils_acquire_lock (
100
+			IN OUT mlx_utils *utils
101
+		)
102
+{
103
+	return mlx_utils_acquire_lock_priv(utils->lock);
104
+}
105
+
106
+mlx_status
107
+mlx_utils_release_lock (
108
+		IN OUT mlx_utils *utils
109
+		)
110
+{
111
+	return mlx_utils_release_lock_priv(utils->lock);
112
+}
113
+
114
+mlx_status
115
+mlx_utils_rand (
116
+		IN mlx_utils *utils,
117
+		OUT mlx_uint32 *rand_num
118
+		)
119
+{
120
+	return mlx_utils_rand_priv(utils, rand_num);
121
+}

+ 61
- 0
src/drivers/infiniband/mlx_utils_flexboot/include/mlx_logging_priv.h Visa fil

@@ -0,0 +1,61 @@
1
+/*
2
+ * DebugPriv.h
3
+ *
4
+ *  Created on: Jan 19, 2015
5
+ *      Author: maord
6
+ */
7
+
8
+#ifndef STUB_MLXUTILS_INCLUDE_PRIVATE_FLEXBOOT_DEBUG_H_
9
+#define STUB_MLXUTILS_INCLUDE_PRIVATE_FLEXBOOT_DEBUG_H_
10
+
11
+#include <stdio.h>
12
+#include <compiler.h>
13
+
14
+#define MLX_DEBUG_FATAL_ERROR_PRIVATE(...)		do {				\
15
+		DBG("%s: ",__func__);						\
16
+		DBG(__VA_ARGS__);			\
17
+	} while ( 0 )
18
+
19
+#define MLX_DEBUG_ERROR_PRIVATE(id, ...)		do {				\
20
+		DBGC(id, "%s: ",__func__);			\
21
+		DBGC(id, __VA_ARGS__);			\
22
+	} while ( 0 )
23
+
24
+#define MLX_DEBUG_WARN_PRIVATE(id, ...)		do {				\
25
+		DBGC(id, "%s: ",__func__);			\
26
+		DBGC(id, __VA_ARGS__);			\
27
+	} while ( 0 )
28
+
29
+#define MLX_DEBUG_INFO1_PRIVATE(id, ...)		do {				\
30
+		DBGC(id, "%s: ",__func__);			\
31
+		DBGC(id, __VA_ARGS__);			\
32
+	} while ( 0 )
33
+
34
+#define MLX_DEBUG_INFO2_PRIVATE(id, ...)		do {				\
35
+		DBGC2(id, "%s: ",__func__);			\
36
+		DBGC2(id, __VA_ARGS__);			\
37
+	} while ( 0 )
38
+
39
+#define MLX_DBG_ERROR_PRIVATE(...)		do {				\
40
+		DBG("%s: ",__func__);			\
41
+		DBG(__VA_ARGS__);			\
42
+	} while ( 0 )
43
+
44
+#define MLX_DBG_WARN_PRIVATE(...)		do {				\
45
+		DBG("%s: ",__func__);			\
46
+		DBG(__VA_ARGS__);			\
47
+	} while ( 0 )
48
+
49
+#define MLX_DBG_INFO1_PRIVATE(...)		do {				\
50
+		DBG("%s: ",__func__);			\
51
+		DBG(__VA_ARGS__);			\
52
+	} while ( 0 )
53
+
54
+#define MLX_DBG_INFO2_PRIVATE(...)		do {				\
55
+		DBG2("%s: ",__func__);			\
56
+		DBG2(__VA_ARGS__);			\
57
+	} while ( 0 )
58
+
59
+
60
+
61
+#endif /* STUB_MLXUTILS_INCLUDE_PRIVATE_FLEXBOOT_DEBUG_H_ */

+ 60
- 0
src/drivers/infiniband/mlx_utils_flexboot/include/mlx_types_priv.h Visa fil

@@ -0,0 +1,60 @@
1
+/*
2
+ * types.h
3
+ *
4
+ *  Created on: Jan 18, 2015
5
+ *      Author: maord
6
+ */
7
+
8
+#ifndef A_MLXUTILS_INCLUDE_PUBLIC_TYPES_H_
9
+#define A_MLXUTILS_INCLUDE_PUBLIC_TYPES_H_
10
+#include <stdint.h>
11
+//#include <errno.h>
12
+#include <ipxe/pci.h>
13
+
14
+#define MLX_SUCCESS 0
15
+#define MLX_OUT_OF_RESOURCES (-1)
16
+//(-ENOMEM)
17
+#define MLX_INVALID_PARAMETER (-2)
18
+//(-EINVAL)
19
+#define MLX_UNSUPPORTED (-3)
20
+//(-ENOSYS)
21
+#define MLX_NOT_FOUND (-4)
22
+
23
+#define MLX_FAILED (-5)
24
+
25
+#undef TRUE
26
+#define TRUE	1
27
+#undef FALSE
28
+#define FALSE	!TRUE
29
+
30
+typedef int mlx_status;
31
+
32
+typedef uint8_t		mlx_uint8;
33
+typedef uint16_t	mlx_uint16;
34
+typedef uint32_t	mlx_uint32;
35
+typedef uint64_t	mlx_uint64;
36
+typedef uint32_t 	mlx_uintn;
37
+
38
+typedef int8_t		mlx_int8;
39
+typedef int16_t		mlx_int16;;
40
+typedef int32_t		mlx_int32;
41
+typedef int64_t		mlx_int64;
42
+typedef uint8_t		mlx_boolean;
43
+
44
+typedef struct pci_device	mlx_pci;
45
+
46
+typedef size_t		mlx_size;
47
+
48
+typedef void		mlx_void;
49
+
50
+#define MAC_ADDR_LEN 6
51
+typedef unsigned long	mlx_physical_address;
52
+typedef union {
53
+	struct {
54
+		uint32_t low;
55
+		uint32_t high;
56
+	} __attribute__ (( packed ));
57
+	uint8_t addr[MAC_ADDR_LEN];
58
+} mlx_mac_address;
59
+
60
+#endif /* A_MLXUTILS_INCLUDE_PUBLIC_TYPES_H_ */

+ 172
- 0
src/drivers/infiniband/mlx_utils_flexboot/src/mlx_memory_priv.c Visa fil

@@ -0,0 +1,172 @@
1
+/*
2
+ * MemoryPriv.c
3
+ *
4
+ *  Created on: Jan 21, 2015
5
+ *      Author: maord
6
+ */
7
+
8
+#include <ipxe/malloc.h>
9
+#include <stddef.h>
10
+#include <byteswap.h>
11
+#include <ipxe/io.h>
12
+#include "../../mlx_utils/include/private/mlx_memory_priv.h"
13
+
14
+
15
+mlx_status
16
+mlx_memory_alloc_priv(
17
+				IN mlx_utils *utils __attribute__ ((unused)),
18
+				IN mlx_size size,
19
+				OUT mlx_void **ptr
20
+				)
21
+{
22
+	mlx_status status = MLX_SUCCESS;
23
+	*ptr = malloc(size);
24
+	if(*ptr == NULL){
25
+		status = MLX_OUT_OF_RESOURCES;
26
+	}
27
+	return status;
28
+}
29
+
30
+mlx_status
31
+mlx_memory_zalloc_priv(
32
+				IN mlx_utils *utils __attribute__ ((unused)),
33
+				IN mlx_size size,
34
+				OUT mlx_void **ptr
35
+				)
36
+{
37
+	mlx_status status = MLX_SUCCESS;
38
+	*ptr = zalloc(size);
39
+	if(*ptr == NULL){
40
+		status = MLX_OUT_OF_RESOURCES;
41
+	}
42
+	return status;
43
+}
44
+
45
+mlx_status
46
+mlx_memory_free_priv(
47
+				IN mlx_utils *utils __attribute__ ((unused)),
48
+				IN mlx_void *ptr
49
+				)
50
+{
51
+	mlx_status status = MLX_SUCCESS;
52
+	free(ptr);
53
+	return status;
54
+}
55
+mlx_status
56
+mlx_memory_alloc_dma_priv(
57
+					IN mlx_utils *utils __attribute__ ((unused)),
58
+					IN mlx_size size ,
59
+					IN mlx_size align,
60
+					OUT mlx_void **ptr
61
+					)
62
+{
63
+	mlx_status status = MLX_SUCCESS;
64
+	*ptr = malloc_dma(size, align);
65
+	if (*ptr == NULL) {
66
+		status = MLX_OUT_OF_RESOURCES;
67
+	} else {
68
+		memset(*ptr, 0, size);
69
+	}
70
+	return status;
71
+}
72
+
73
+mlx_status
74
+mlx_memory_free_dma_priv(
75
+					IN mlx_utils *utils __attribute__ ((unused)),
76
+					IN mlx_size size ,
77
+					IN mlx_void *ptr
78
+					)
79
+{
80
+	mlx_status status = MLX_SUCCESS;
81
+	free_dma(ptr, size);
82
+	return status;
83
+}
84
+mlx_status
85
+mlx_memory_map_dma_priv(
86
+					IN mlx_utils *utils __attribute__ ((unused)),
87
+					IN mlx_void *addr ,
88
+					IN mlx_size number_of_bytes __attribute__ ((unused)),
89
+					OUT mlx_physical_address *phys_addr,
90
+					OUT mlx_void **mapping __attribute__ ((unused))
91
+					)
92
+{
93
+	mlx_status status = MLX_SUCCESS;
94
+	*phys_addr = virt_to_bus(addr);
95
+	return status;
96
+}
97
+
98
+mlx_status
99
+mlx_memory_ummap_dma_priv(
100
+					IN mlx_utils *utils __attribute__ ((unused)),
101
+					IN mlx_void *mapping __attribute__ ((unused))
102
+					)
103
+{
104
+	mlx_status status = MLX_SUCCESS;
105
+	return status;
106
+}
107
+
108
+mlx_status
109
+mlx_memory_cmp_priv(
110
+					IN mlx_utils *utils __unused,
111
+					IN mlx_void *first_block,
112
+					IN mlx_void *second_block,
113
+					IN mlx_size size,
114
+					OUT mlx_uint32 *out
115
+					)
116
+{
117
+	mlx_status status = MLX_SUCCESS;
118
+	*out = memcmp(first_block, second_block, size);
119
+	return status;
120
+}
121
+
122
+mlx_status
123
+mlx_memory_set_priv(
124
+					IN mlx_utils *utils __unused,
125
+					IN mlx_void *block,
126
+					IN mlx_int32 value,
127
+					IN mlx_size size
128
+					)
129
+{
130
+	mlx_status status = MLX_SUCCESS;
131
+	memset(block, value, size);
132
+	return status;
133
+}
134
+
135
+mlx_status
136
+mlx_memory_cpy_priv(
137
+					IN mlx_utils *utils __unused,
138
+					OUT mlx_void *destination_buffer,
139
+					IN mlx_void *source_buffer,
140
+					IN mlx_size length
141
+					)
142
+{
143
+	mlx_status status = MLX_SUCCESS;
144
+	memcpy(destination_buffer, source_buffer, length);
145
+	return status;
146
+}
147
+
148
+mlx_status
149
+mlx_memory_cpu_to_be32_priv(
150
+			IN mlx_utils *utils __unused,
151
+			IN mlx_uint32 source,
152
+			IN mlx_uint32 *destination
153
+			)
154
+{
155
+	mlx_status status = MLX_SUCCESS;
156
+	*destination = cpu_to_be32(source);
157
+	return status;
158
+}
159
+
160
+
161
+mlx_status
162
+mlx_memory_be32_to_cpu_priv(
163
+			IN mlx_utils *utils __unused,
164
+			IN mlx_uint32 source,
165
+			IN mlx_uint32 *destination
166
+			)
167
+{
168
+	mlx_status status = MLX_SUCCESS;
169
+	*destination = be32_to_cpu(source);
170
+	return status;
171
+}
172
+

+ 182
- 0
src/drivers/infiniband/mlx_utils_flexboot/src/mlx_pci_priv.c Visa fil

@@ -0,0 +1,182 @@
1
+/*
2
+ * MlxPciPriv.c
3
+ *
4
+ *  Created on: Jan 21, 2015
5
+ *      Author: maord
6
+ */
7
+
8
+#include <ipxe/pci.h>
9
+#include "../../mlx_utils/include/private/mlx_pci_priv.h"
10
+
11
+
12
+static
13
+mlx_status
14
+mlx_pci_config_byte(
15
+		IN mlx_utils *utils,
16
+		IN mlx_boolean read,
17
+		IN mlx_uint32 offset,
18
+		IN OUT mlx_uint8 *buffer
19
+		)
20
+{
21
+	mlx_status status = MLX_SUCCESS;
22
+	if (read) {
23
+		status = pci_read_config_byte(utils->pci, offset, buffer);
24
+	}else {
25
+		status = pci_write_config_byte(utils->pci, offset, *buffer);
26
+	}
27
+	return status;
28
+}
29
+
30
+static
31
+mlx_status
32
+mlx_pci_config_word(
33
+		IN mlx_utils *utils,
34
+		IN mlx_boolean read,
35
+		IN mlx_uint32 offset,
36
+		IN OUT mlx_uint16 *buffer
37
+		)
38
+{
39
+	mlx_status status = MLX_SUCCESS;
40
+	if (read) {
41
+		status = pci_read_config_word(utils->pci, offset, buffer);
42
+	}else {
43
+		status = pci_write_config_word(utils->pci, offset, *buffer);
44
+	}
45
+	return status;
46
+}
47
+
48
+static
49
+mlx_status
50
+mlx_pci_config_dword(
51
+		IN mlx_utils *utils,
52
+		IN mlx_boolean read,
53
+		IN mlx_uint32 offset,
54
+		IN OUT mlx_uint32 *buffer
55
+		)
56
+{
57
+	mlx_status status = MLX_SUCCESS;
58
+	if (read) {
59
+		status = pci_read_config_dword(utils->pci, offset, buffer);
60
+	}else {
61
+		status = pci_write_config_dword(utils->pci, offset, *buffer);
62
+	}
63
+	return status;
64
+}
65
+static
66
+mlx_status
67
+mlx_pci_config(
68
+		IN mlx_utils *utils,
69
+		IN mlx_boolean read,
70
+		IN mlx_pci_width width,
71
+		IN mlx_uint32 offset,
72
+		IN mlx_uintn count,
73
+		IN OUT mlx_void *buffer
74
+		)
75
+{
76
+	mlx_status status = MLX_SUCCESS;
77
+	mlx_uint8 *tmp =  (mlx_uint8*)buffer;
78
+	mlx_uintn iteration = 0;
79
+	if( width == MlxPciWidthUint64) {
80
+		width = MlxPciWidthUint32;
81
+		count = count * 2;
82
+	}
83
+
84
+	for(;iteration < count ; iteration++) {
85
+		switch (width){
86
+		case MlxPciWidthUint8:
87
+			status = mlx_pci_config_byte(utils, read , offset++, tmp++);
88
+			break;
89
+		case MlxPciWidthUint16:
90
+			status = mlx_pci_config_word(utils, read , offset, (mlx_uint16*)tmp);
91
+			tmp += 2;
92
+			offset += 2;
93
+			break;
94
+		case MlxPciWidthUint32:
95
+			status = mlx_pci_config_dword(utils, read , offset, (mlx_uint32*)tmp);
96
+			tmp += 4;
97
+			offset += 4;
98
+			break;
99
+		default:
100
+			status = MLX_INVALID_PARAMETER;
101
+		}
102
+		if(status != MLX_SUCCESS) {
103
+			goto config_error;
104
+		}
105
+	}
106
+config_error:
107
+	return status;
108
+}
109
+mlx_status
110
+mlx_pci_init_priv(
111
+			IN mlx_utils *utils
112
+			)
113
+{
114
+	mlx_status status = MLX_SUCCESS;
115
+	adjust_pci_device ( utils->pci );
116
+#ifdef DEVICE_CX3
117
+	utils->config = ioremap ( pci_bar_start ( utils->pci, PCI_BASE_ADDRESS_0),
118
+			0x100000 );
119
+#endif
120
+	return status;
121
+}
122
+
123
+mlx_status
124
+mlx_pci_read_priv(
125
+			IN mlx_utils *utils,
126
+			IN mlx_pci_width width,
127
+			IN mlx_uint32 offset,
128
+			IN mlx_uintn count,
129
+			OUT mlx_void *buffer
130
+			)
131
+{
132
+	mlx_status status = MLX_SUCCESS;
133
+	status = mlx_pci_config(utils, TRUE, width, offset, count, buffer);
134
+	return status;
135
+}
136
+
137
+mlx_status
138
+mlx_pci_write_priv(
139
+			IN mlx_utils *utils,
140
+			IN mlx_pci_width width,
141
+			IN mlx_uint32 offset,
142
+			IN mlx_uintn count,
143
+			IN mlx_void *buffer
144
+			)
145
+{
146
+	mlx_status status = MLX_SUCCESS;
147
+	status = mlx_pci_config(utils, FALSE, width, offset, count, buffer);
148
+	return status;
149
+}
150
+
151
+mlx_status
152
+mlx_pci_mem_read_priv(
153
+				IN mlx_utils *utils  __attribute__ ((unused)),
154
+				IN mlx_pci_width width  __attribute__ ((unused)),
155
+				IN mlx_uint8 bar_index  __attribute__ ((unused)),
156
+				IN mlx_uint64 offset,
157
+				IN mlx_uintn count  __attribute__ ((unused)),
158
+				OUT mlx_void *buffer
159
+				)
160
+{
161
+	if (buffer == NULL || width != MlxPciWidthUint32)
162
+		return MLX_INVALID_PARAMETER;
163
+	*((mlx_uint32 *)buffer) = readl(offset);
164
+	return MLX_SUCCESS;
165
+}
166
+
167
+mlx_status
168
+mlx_pci_mem_write_priv(
169
+				IN mlx_utils *utils  __attribute__ ((unused)),
170
+				IN mlx_pci_width width  __attribute__ ((unused)),
171
+				IN mlx_uint8 bar_index  __attribute__ ((unused)),
172
+				IN mlx_uint64 offset,
173
+				IN mlx_uintn count  __attribute__ ((unused)),
174
+				IN mlx_void *buffer
175
+				)
176
+{
177
+	if (buffer == NULL || width != MlxPciWidthUint32)
178
+		return MLX_INVALID_PARAMETER;
179
+	barrier();
180
+	writel(*((mlx_uint32 *)buffer), offset);
181
+	return MLX_SUCCESS;
182
+}

+ 83
- 0
src/drivers/infiniband/mlx_utils_flexboot/src/mlx_utils_priv.c Visa fil

@@ -0,0 +1,83 @@
1
+/*
2
+ * MlxUtilsPriv.c
3
+ *
4
+ *  Created on: Jan 25, 2015
5
+ *      Author: maord
6
+ */
7
+
8
+#include <unistd.h>
9
+#include <stdlib.h>
10
+#include <strings.h>
11
+#include "../../mlx_utils/include/private/mlx_utils_priv.h"
12
+
13
+mlx_status
14
+mlx_utils_delay_in_ms_priv(
15
+			IN mlx_uint32 msecs
16
+		)
17
+{
18
+	mdelay(msecs);
19
+	return MLX_SUCCESS;
20
+}
21
+
22
+mlx_status
23
+mlx_utils_delay_in_us_priv(
24
+			IN mlx_uint32 usecs
25
+		)
26
+{
27
+	udelay(usecs);
28
+	return MLX_SUCCESS;
29
+}
30
+
31
+mlx_status
32
+mlx_utils_ilog2_priv(
33
+			IN mlx_uint32 i,
34
+			OUT mlx_uint32 *log
35
+		)
36
+{
37
+	*log = ( fls ( i ) - 1 );
38
+	return MLX_SUCCESS;
39
+}
40
+
41
+mlx_status
42
+mlx_utils_init_lock_priv(
43
+			OUT void **lock __unused
44
+		)
45
+{
46
+	return MLX_SUCCESS;
47
+}
48
+
49
+mlx_status
50
+mlx_utils_free_lock_priv(
51
+			IN void *lock __unused
52
+		)
53
+{
54
+	return MLX_SUCCESS;
55
+}
56
+
57
+mlx_status
58
+mlx_utils_acquire_lock_priv (
59
+			IN void *lock __unused
60
+		)
61
+{
62
+	return MLX_SUCCESS;
63
+}
64
+
65
+mlx_status
66
+mlx_utils_release_lock_priv (
67
+			IN void *lock __unused
68
+		)
69
+{
70
+	return MLX_SUCCESS;
71
+}
72
+
73
+mlx_status
74
+mlx_utils_rand_priv (
75
+			IN  mlx_utils *utils __unused,
76
+			OUT mlx_uint32 *rand_num
77
+		)
78
+{
79
+	do {
80
+		*rand_num = rand();
81
+	} while ( *rand_num == 0 );
82
+	return MLX_SUCCESS;
83
+}

+ 47
- 0
src/drivers/infiniband/nodnic_prm.h Visa fil

@@ -0,0 +1,47 @@
1
+/*
2
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
3
+ *
4
+ * This program is free software; you can redistribute it and/or
5
+ * modify it under the terms of the GNU General Public License as
6
+ * published by the Free Software Foundation; either version 2 of the
7
+ * License, or any later version.
8
+ *
9
+ * This program is distributed in the hope that it will be useful, but
10
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
11
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
12
+ * General Public License for more details.
13
+ *
14
+ * You should have received a copy of the GNU General Public License
15
+ * along with this program; if not, write to the Free Software
16
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17
+ * 02110-1301, USA.
18
+ */
19
+
20
+FILE_LICENCE ( GPL2_OR_LATER );
21
+
22
+#ifndef SRC_DRIVERS_INFINIBAND_MLX_NODNIC_INCLUDE_PRM_NODNIC_PRM_H_
23
+#define SRC_DRIVERS_INFINIBAND_MLX_NODNIC_INCLUDE_PRM_NODNIC_PRM_H_
24
+
25
+#include "mlx_bitops.h"
26
+
27
+struct nodnic_wqe_segment_data_ptr_st {	/* Little Endian */
28
+    pseudo_bit_t	byte_count[0x0001f];
29
+    pseudo_bit_t	always0[0x00001];
30
+/* -------------- */
31
+    pseudo_bit_t	l_key[0x00020];
32
+/* -------------- */
33
+    pseudo_bit_t	local_address_h[0x00020];
34
+/* -------------- */
35
+    pseudo_bit_t	local_address_l[0x00020];
36
+/* -------------- */
37
+};
38
+
39
+struct MLX_DECLARE_STRUCT ( nodnic_wqe_segment_data_ptr );
40
+
41
+#define HERMON_MAX_SCATTER 1
42
+
43
+struct nodnic_recv_wqe {
44
+	struct nodnic_wqe_segment_data_ptr data[HERMON_MAX_SCATTER];
45
+} __attribute__ (( packed ));
46
+
47
+#endif /* SRC_DRIVERS_INFINIBAND_MLX_NODNIC_INCLUDE_PRM_NODNIC_PRM_H_ */

+ 143
- 0
src/drivers/infiniband/nodnic_shomron_prm.h Visa fil

@@ -0,0 +1,143 @@
1
+/*
2
+ * Copyright (C) 2015 Mellanox Technologies Ltd.
3
+ *
4
+ * This program is free software; you can redistribute it and/or
5
+ * modify it under the terms of the GNU General Public License as
6
+ * published by the Free Software Foundation; either version 2 of the
7
+ * License, or any later version.
8
+ *
9
+ * This program is distributed in the hope that it will be useful, but
10
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
11
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
12
+ * General Public License for more details.
13
+ *
14
+ * You should have received a copy of the GNU General Public License
15
+ * along with this program; if not, write to the Free Software
16
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
17
+ * 02110-1301, USA.
18
+ */
19
+
20
+FILE_LICENCE ( GPL2_OR_LATER );
21
+
22
+#ifndef SRC_DRIVERS_INFINIBAND_MLX_NODNIC_INCLUDE_PRM_NODNIC_SHOMRON_PRM_H_
23
+#define SRC_DRIVERS_INFINIBAND_MLX_NODNIC_INCLUDE_PRM_NODNIC_SHOMRON_PRM_H_
24
+
25
+
26
+
27
+#include "nodnic_prm.h"
28
+
29
+
30
+#define SHOMRON_MAX_GATHER 1
31
+
32
+/* Send wqe segment ctrl */
33
+
34
+struct shomronprm_wqe_segment_ctrl_send_st {	/* Little Endian */
35
+    pseudo_bit_t	opcode[0x00008];
36
+    pseudo_bit_t	wqe_index[0x00010];
37
+    pseudo_bit_t	reserved1[0x00008];
38
+/* -------------- */
39
+    pseudo_bit_t	ds[0x00006];           /* descriptor (wqe) size in 16bytes chunk */
40
+    pseudo_bit_t	reserved2[0x00002];
41
+    pseudo_bit_t	qpn[0x00018];
42
+/* -------------- */
43
+	pseudo_bit_t	reserved3[0x00002];
44
+	pseudo_bit_t	ce[0x00002];
45
+	pseudo_bit_t	reserved4[0x0001c];
46
+/* -------------- */
47
+	pseudo_bit_t	reserved5[0x00040];
48
+/* -------------- */
49
+	pseudo_bit_t	mss[0x0000e];
50
+	pseudo_bit_t	reserved6[0x0000e];
51
+	pseudo_bit_t	cs13_inner[0x00001];
52
+	pseudo_bit_t	cs14_inner[0x00001];
53
+	pseudo_bit_t	cs13[0x00001];
54
+	pseudo_bit_t	cs14[0x00001];
55
+/* -------------- */
56
+	pseudo_bit_t	reserved7[0x00020];
57
+/* -------------- */
58
+	pseudo_bit_t	inline_headers1[0x00010];
59
+	pseudo_bit_t	inline_headers_size[0x0000a]; //sum size of inline_hdr1+inline_hdrs (0x10)
60
+	pseudo_bit_t	reserved8[0x00006];
61
+/* -------------- */
62
+	pseudo_bit_t	inline_headers2[0x00020];
63
+/* -------------- */
64
+	pseudo_bit_t	inline_headers3[0x00020];
65
+/* -------------- */
66
+	pseudo_bit_t	inline_headers4[0x00020];
67
+/* -------------- */
68
+	pseudo_bit_t	inline_headers5[0x00020];
69
+};
70
+
71
+
72
+
73
+/* Completion Queue Entry Format        #### michal - fixed by gdror */
74
+
75
+struct shomronprm_completion_queue_entry_st {	/* Little Endian */
76
+
77
+	pseudo_bit_t	reserved1[0x00080];
78
+/* -------------- */
79
+	pseudo_bit_t	reserved2[0x00010];
80
+	pseudo_bit_t	ml_path[0x00007];
81
+	pseudo_bit_t	reserved3[0x00009];
82
+/* -------------- */
83
+	pseudo_bit_t	slid[0x00010];
84
+	pseudo_bit_t	reserved4[0x00010];
85
+/* -------------- */
86
+	pseudo_bit_t	rqpn[0x00018];
87
+	pseudo_bit_t	sl[0x00004];
88
+	pseudo_bit_t	l3_hdr[0x00002];
89
+	pseudo_bit_t	reserved5[0x00002];
90
+/* -------------- */
91
+	pseudo_bit_t	reserved10[0x00020];
92
+/* -------------- */
93
+	pseudo_bit_t	srqn[0x00018];
94
+	pseudo_bit_t	reserved11[0x0008];
95
+/* -------------- */
96
+	pseudo_bit_t	pkey_index[0x00020];
97
+/* -------------- */
98
+	pseudo_bit_t	reserved6[0x00020];
99
+/* -------------- */
100
+	pseudo_bit_t	byte_cnt[0x00020];
101
+/* -------------- */
102
+	pseudo_bit_t	reserved7[0x00040];
103
+/* -------------- */
104
+	pseudo_bit_t	qpn[0x00018];
105
+	pseudo_bit_t	rx_drop_counter[0x00008];
106
+/* -------------- */
107
+	pseudo_bit_t	owner[0x00001];
108
+	pseudo_bit_t	reserved8[0x00003];
109
+	pseudo_bit_t	opcode[0x00004];
110
+	pseudo_bit_t	reserved9[0x00008];
111
+	pseudo_bit_t	wqe_counter[0x00010];
112
+};
113
+
114
+
115
+/* Completion with Error CQE             #### michal - gdror fixed */
116
+
117
+struct shomronprm_completion_with_error_st {	/* Little Endian */
118
+	pseudo_bit_t	reserved1[0x001a0];
119
+	/* -------------- */
120
+	pseudo_bit_t	syndrome[0x00008];
121
+	pseudo_bit_t	vendor_error_syndrome[0x00008];
122
+	pseudo_bit_t	reserved2[0x00010];
123
+	/* -------------- */
124
+	pseudo_bit_t	reserved3[0x00040];
125
+};
126
+
127
+
128
+struct MLX_DECLARE_STRUCT ( shomronprm_wqe_segment_ctrl_send );
129
+struct MLX_DECLARE_STRUCT ( shomronprm_completion_queue_entry );
130
+struct MLX_DECLARE_STRUCT ( shomronprm_completion_with_error );
131
+
132
+struct shomron_nodnic_eth_send_wqe {
133
+	struct shomronprm_wqe_segment_ctrl_send ctrl;
134
+	struct nodnic_wqe_segment_data_ptr data[SHOMRON_MAX_GATHER];
135
+} __attribute__ (( packed ));
136
+
137
+union shomronprm_completion_entry {
138
+	struct shomronprm_completion_queue_entry normal;
139
+	struct shomronprm_completion_with_error error;
140
+} __attribute__ (( packed ));
141
+
142
+
143
+#endif /* SRC_DRIVERS_INFINIBAND_MLX_NODNIC_INCLUDE_PRM_NODNIC_SHOMRON_PRM_H_ */

+ 2
- 0
src/include/ipxe/errfile.h Visa fil

@@ -186,6 +186,8 @@ FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
186 186
 #define ERRFILE_smsc95xx	     ( ERRFILE_DRIVER | 0x007a0000 )
187 187
 #define ERRFILE_acm		     ( ERRFILE_DRIVER | 0x007b0000 )
188 188
 #define ERRFILE_eoib		     ( ERRFILE_DRIVER | 0x007c0000 )
189
+#define ERRFILE_golan		     ( ERRFILE_DRIVER | 0x007d0000 )
190
+#define ERRFILE_flexboot_nodnic	     ( ERRFILE_DRIVER | 0x007e0000 )
189 191
 
190 192
 #define ERRFILE_aoe			( ERRFILE_NET | 0x00000000 )
191 193
 #define ERRFILE_arp			( ERRFILE_NET | 0x00010000 )

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