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usbdrvasm20.inc 15KB

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  1. /* Name: usbdrvasm20.inc
  2. * Project: V-USB, virtual USB port for Atmel's(r) AVR(r) microcontrollers
  3. * Author: Jeroen Benschop
  4. * Based on usbdrvasm16.inc from Christian Starkjohann
  5. * Creation Date: 2008-03-05
  6. * Tabsize: 4
  7. * Copyright: (c) 2008 by Jeroen Benschop and OBJECTIVE DEVELOPMENT Software GmbH
  8. * License: GNU GPL v2 (see License.txt), GNU GPL v3 or proprietary (CommercialLicense.txt)
  9. * Revision: $Id: usbdrvasm20.inc 740 2009-04-13 18:23:31Z cs $
  10. */
  11. /* Do not link this file! Link usbdrvasm.S instead, which includes the
  12. * appropriate implementation!
  13. */
  14. /*
  15. General Description:
  16. This file is the 20 MHz version of the asssembler part of the USB driver. It
  17. requires a 20 MHz crystal (not a ceramic resonator and not a calibrated RC
  18. oscillator).
  19. See usbdrv.h for a description of the entire driver.
  20. Since almost all of this code is timing critical, don't change unless you
  21. really know what you are doing! Many parts require not only a maximum number
  22. of CPU cycles, but even an exact number of cycles!
  23. */
  24. #define leap2 x3
  25. #ifdef __IAR_SYSTEMS_ASM__
  26. #define nextInst $+2
  27. #else
  28. #define nextInst .+0
  29. #endif
  30. ;max stack usage: [ret(2), YL, SREG, YH, bitcnt, shift, x1, x2, x3, x4, cnt] = 12 bytes
  31. ;nominal frequency: 20 MHz -> 13.333333 cycles per bit, 106.666667 cycles per byte
  32. ; Numbers in brackets are clocks counted from center of last sync bit
  33. ; when instruction starts
  34. ;register use in receive loop:
  35. ; shift assembles the byte currently being received
  36. ; x1 holds the D+ and D- line state
  37. ; x2 holds the previous line state
  38. ; x4 (leap) is used to add a leap cycle once every three bytes received
  39. ; X3 (leap2) is used to add a leap cycle once every three stuff bits received
  40. ; bitcnt is used to determine when a stuff bit is due
  41. ; cnt holds the number of bytes left in the receive buffer
  42. USB_INTR_VECTOR:
  43. ;order of registers pushed: YL, SREG YH, [sofError], bitcnt, shift, x1, x2, x3, x4, cnt
  44. push YL ;[-28] push only what is necessary to sync with edge ASAP
  45. in YL, SREG ;[-26]
  46. push YL ;[-25]
  47. push YH ;[-23]
  48. ;----------------------------------------------------------------------------
  49. ; Synchronize with sync pattern:
  50. ;----------------------------------------------------------------------------
  51. ;sync byte (D-) pattern LSb to MSb: 01010100 [1 = idle = J, 0 = K]
  52. ;sync up with J to K edge during sync pattern -- use fastest possible loops
  53. ;The first part waits at most 1 bit long since we must be in sync pattern.
  54. ;YL is guarenteed to be < 0x80 because I flag is clear. When we jump to
  55. ;waitForJ, ensure that this prerequisite is met.
  56. waitForJ:
  57. inc YL
  58. sbis USBIN, USBMINUS
  59. brne waitForJ ; just make sure we have ANY timeout
  60. waitForK:
  61. ;The following code results in a sampling window of < 1/4 bit which meets the spec.
  62. sbis USBIN, USBMINUS ;[-19]
  63. rjmp foundK ;[-18]
  64. sbis USBIN, USBMINUS
  65. rjmp foundK
  66. sbis USBIN, USBMINUS
  67. rjmp foundK
  68. sbis USBIN, USBMINUS
  69. rjmp foundK
  70. sbis USBIN, USBMINUS
  71. rjmp foundK
  72. sbis USBIN, USBMINUS
  73. rjmp foundK
  74. sbis USBIN, USBMINUS
  75. rjmp foundK
  76. sbis USBIN, USBMINUS
  77. rjmp foundK
  78. sbis USBIN, USBMINUS
  79. rjmp foundK
  80. #if USB_COUNT_SOF
  81. lds YL, usbSofCount
  82. inc YL
  83. sts usbSofCount, YL
  84. #endif /* USB_COUNT_SOF */
  85. #ifdef USB_SOF_HOOK
  86. USB_SOF_HOOK
  87. #endif
  88. rjmp sofError
  89. foundK: ;[-16]
  90. ;{3, 5} after falling D- edge, average delay: 4 cycles
  91. ;bit0 should be at 34 for center sampling. Currently at 4 so 30 cylces till bit 0 sample
  92. ;use 1 bit time for setup purposes, then sample again. Numbers in brackets
  93. ;are cycles from center of first sync (double K) bit after the instruction
  94. push bitcnt ;[-16]
  95. ; [---] ;[-15]
  96. lds YL, usbInputBufOffset;[-14]
  97. ; [---] ;[-13]
  98. clr YH ;[-12]
  99. subi YL, lo8(-(usbRxBuf));[-11] [rx loop init]
  100. sbci YH, hi8(-(usbRxBuf));[-10] [rx loop init]
  101. push shift ;[-9]
  102. ; [---] ;[-8]
  103. ldi shift,0x40 ;[-7] set msb to "1" so processing bit7 can be detected
  104. nop2 ;[-6]
  105. ; [---] ;[-5]
  106. ldi bitcnt, 5 ;[-4] [rx loop init]
  107. sbis USBIN, USBMINUS ;[-3] we want two bits K (sample 3 cycles too early)
  108. rjmp haveTwoBitsK ;[-2]
  109. pop shift ;[-1] undo the push from before
  110. pop bitcnt ;[1]
  111. rjmp waitForK ;[3] this was not the end of sync, retry
  112. ; The entire loop from waitForK until rjmp waitForK above must not exceed two
  113. ; bit times (= 27 cycles).
  114. ;----------------------------------------------------------------------------
  115. ; push more registers and initialize values while we sample the first bits:
  116. ;----------------------------------------------------------------------------
  117. haveTwoBitsK:
  118. push x1 ;[0]
  119. push x2 ;[2]
  120. push x3 ;[4] (leap2)
  121. ldi leap2, 0x55 ;[6] add leap cycle on 2nd,5th,8th,... stuff bit
  122. push x4 ;[7] == leap
  123. ldi leap, 0x55 ;[9] skip leap cycle on 2nd,5th,8th,... byte received
  124. push cnt ;[10]
  125. ldi cnt, USB_BUFSIZE ;[12] [rx loop init]
  126. ldi x2, 1<<USBPLUS ;[13] current line state is K state. D+=="1", D-=="0"
  127. bit0:
  128. in x1, USBIN ;[0] sample line state
  129. andi x1, USBMASK ;[1] filter only D+ and D- bits
  130. rjmp handleBit ;[2] make bit0 14 cycles long
  131. ;----------------------------------------------------------------------------
  132. ; Process bit7. However, bit 6 still may need unstuffing.
  133. ;----------------------------------------------------------------------------
  134. b6checkUnstuff:
  135. dec bitcnt ;[9]
  136. breq unstuff6 ;[10]
  137. bit7:
  138. subi cnt, 1 ;[11] cannot use dec becaus it does not affect the carry flag
  139. brcs overflow ;[12] Too many bytes received. Ignore packet
  140. in x1, USBIN ;[0] sample line state
  141. andi x1, USBMASK ;[1] filter only D+ and D- bits
  142. cpse x1, x2 ;[2] when previous line state equals current line state, handle "1"
  143. rjmp b7handle0 ;[3] when line state differs, handle "0"
  144. sec ;[4]
  145. ror shift ;[5] shift "1" into the data
  146. st y+, shift ;[6] store the data into the buffer
  147. ldi shift, 0x40 ;[7] reset data for receiving the next byte
  148. subi leap, 0x55 ;[9] trick to introduce a leap cycle every 3 bytes
  149. brcc nextInst ;[10 or 11] it will fail after 85 bytes. However low speed can only receive 11
  150. dec bitcnt ;[11 or 12]
  151. brne bit0 ;[12 or 13]
  152. ldi x1, 1 ;[13 or 14] unstuffing bit 7
  153. in bitcnt, USBIN ;[0] sample stuff bit
  154. rjmp unstuff ;[1]
  155. b7handle0:
  156. mov x2,x1 ;[5] Set x2 to current line state
  157. ldi bitcnt, 6 ;[6]
  158. lsr shift ;[7] shift "0" into the data
  159. st y+, shift ;[8] store data into the buffer
  160. ldi shift, 0x40 ;[10] reset data for receiving the next byte
  161. subi leap, 0x55 ;[11] trick to introduce a leap cycle every 3 bytes
  162. brcs bit0 ;[12] it will fail after 85 bytes. However low speed can only receive 11
  163. rjmp bit0 ;[13]
  164. ;----------------------------------------------------------------------------
  165. ; Handle unstuff
  166. ; x1==0xFF indicate unstuffing bit6
  167. ;----------------------------------------------------------------------------
  168. unstuff6:
  169. ldi x1,0xFF ;[12] indicate unstuffing bit 6
  170. in bitcnt, USBIN ;[0] sample stuff bit
  171. nop ;[1] fix timing
  172. unstuff: ;b0-5 b6 b7
  173. mov x2,bitcnt ;[3] [2] [3] Set x2 to match line state
  174. subi leap2, 0x55 ;[4] [3] [4] delay loop
  175. brcs nextInst ;[5] [4] [5] add one cycle every three stuff bits
  176. sbci leap2,0 ;[6] [5] [6]
  177. ldi bitcnt,6 ;[7] [6] [7] reset bit stuff counter
  178. andi x2, USBMASK ;[8] [7] [8] only keep D+ and D-
  179. cpi x1,0 ;[9] [8] [9]
  180. brmi bit7 ;[10] [9] [10] finished unstuffing bit6 When x1<0
  181. breq bitloop ;[11] --- [11] finished unstuffing bit0-5 when x1=0
  182. nop ;--- --- [12]
  183. in x1, USBIN ;--- --- [0] sample line state for bit0
  184. andi x1, USBMASK ;--- --- [1] filter only D+ and D- bits
  185. rjmp handleBit ;--- --- [2] make bit0 14 cycles long
  186. ;----------------------------------------------------------------------------
  187. ; Receiver loop (numbers in brackets are cycles within byte after instr)
  188. ;----------------------------------------------------------------------------
  189. bitloop:
  190. in x1, USBIN ;[0] sample line state
  191. andi x1, USBMASK ;[1] filter only D+ and D- bits
  192. breq se0 ;[2] both lines are low so handle se0
  193. handleBit:
  194. cpse x1, x2 ;[3] when previous line state equals current line state, handle "1"
  195. rjmp handle0 ;[4] when line state differs, handle "0"
  196. sec ;[5]
  197. ror shift ;[6] shift "1" into the data
  198. brcs b6checkUnstuff ;[7] When after shift C is set, next bit is bit7
  199. nop2 ;[8]
  200. dec bitcnt ;[10]
  201. brne bitloop ;[11]
  202. ldi x1,0 ;[12] indicate unstuff for bit other than bit6 or bit7
  203. in bitcnt, USBIN ;[0] sample stuff bit
  204. rjmp unstuff ;[1]
  205. handle0:
  206. mov x2, x1 ;[6] Set x2 to current line state
  207. ldi bitcnt, 6 ;[7] reset unstuff counter.
  208. lsr shift ;[8] shift "0" into the data
  209. brcs bit7 ;[9] When after shift C is set, next bit is bit7
  210. nop ;[10]
  211. rjmp bitloop ;[11]
  212. ;----------------------------------------------------------------------------
  213. ; End of receive loop. Now start handling EOP
  214. ;----------------------------------------------------------------------------
  215. macro POP_STANDARD ; 14 cycles
  216. pop cnt
  217. pop x4
  218. pop x3
  219. pop x2
  220. pop x1
  221. pop shift
  222. pop bitcnt
  223. endm
  224. macro POP_RETI ; 7 cycles
  225. pop YH
  226. pop YL
  227. out SREG, YL
  228. pop YL
  229. endm
  230. #include "asmcommon.inc"
  231. ; USB spec says:
  232. ; idle = J
  233. ; J = (D+ = 0), (D- = 1)
  234. ; K = (D+ = 1), (D- = 0)
  235. ; Spec allows 7.5 bit times from EOP to SOP for replies
  236. ; 7.5 bit times is 100 cycles. This implementation arrives a bit later at se0
  237. ; then specified in the include file but there is plenty of time
  238. bitstuffN:
  239. eor x1, x4 ;[8]
  240. ldi x2, 0 ;[9]
  241. nop2 ;[10]
  242. out USBOUT, x1 ;[12] <-- out
  243. rjmp didStuffN ;[0]
  244. bitstuff7:
  245. eor x1, x4 ;[6]
  246. ldi x2, 0 ;[7] Carry is zero due to brcc
  247. rol shift ;[8] compensate for ror shift at branch destination
  248. nop2 ;[9]
  249. rjmp didStuff7 ;[11]
  250. sendNakAndReti:
  251. ldi x3, USBPID_NAK ;[-18]
  252. rjmp sendX3AndReti ;[-17]
  253. sendAckAndReti:
  254. ldi cnt, USBPID_ACK ;[-17]
  255. sendCntAndReti:
  256. mov x3, cnt ;[-16]
  257. sendX3AndReti:
  258. ldi YL, 20 ;[-15] x3==r20 address is 20
  259. ldi YH, 0 ;[-14]
  260. ldi cnt, 2 ;[-13]
  261. ; rjmp usbSendAndReti fallthrough
  262. ;usbSend:
  263. ;pointer to data in 'Y'
  264. ;number of bytes in 'cnt' -- including sync byte [range 2 ... 12]
  265. ;uses: x1...x4, btcnt, shift, cnt, Y
  266. ;Numbers in brackets are time since first bit of sync pattern is sent
  267. ;We don't match the transfer rate exactly (don't insert leap cycles every third
  268. ;byte) because the spec demands only 1.5% precision anyway.
  269. usbSendAndReti: ; 12 cycles until SOP
  270. in x2, USBDDR ;[-12]
  271. ori x2, USBMASK ;[-11]
  272. sbi USBOUT, USBMINUS;[-10] prepare idle state; D+ and D- must have been 0 (no pullups)
  273. in x1, USBOUT ;[-8] port mirror for tx loop
  274. out USBDDR, x2 ;[-7] <- acquire bus
  275. ; need not init x2 (bitstuff history) because sync starts with 0
  276. ldi x4, USBMASK ;[-6] exor mask
  277. ldi shift, 0x80 ;[-5] sync byte is first byte sent
  278. txByteLoop:
  279. ldi bitcnt, 0x49 ;[-4] [10] binary 01001001
  280. txBitLoop:
  281. sbrs shift, 0 ;[-3] [10] [11]
  282. eor x1, x4 ;[-2] [11] [12]
  283. out USBOUT, x1 ;[-1] [12] [13] <-- out N
  284. ror shift ;[0] [13] [14]
  285. ror x2 ;[1]
  286. didStuffN:
  287. nop2 ;[2]
  288. nop ;[4]
  289. cpi x2, 0xfc ;[5]
  290. brcc bitstuffN ;[6]
  291. lsr bitcnt ;[7]
  292. brcc txBitLoop ;[8]
  293. brne txBitLoop ;[9]
  294. sbrs shift, 0 ;[10]
  295. eor x1, x4 ;[11]
  296. didStuff7:
  297. out USBOUT, x1 ;[-1] [13] <-- out 7
  298. ror shift ;[0] [14]
  299. ror x2 ;[1]
  300. nop ;[2]
  301. cpi x2, 0xfc ;[3]
  302. brcc bitstuff7 ;[4]
  303. ld shift, y+ ;[5]
  304. dec cnt ;[7]
  305. brne txByteLoop ;[8]
  306. ;make SE0:
  307. cbr x1, USBMASK ;[9] prepare SE0 [spec says EOP may be 25 to 30 cycles]
  308. lds x2, usbNewDeviceAddr;[10]
  309. lsl x2 ;[12] we compare with left shifted address
  310. out USBOUT, x1 ;[13] <-- out SE0 -- from now 2 bits = 22 cycles until bus idle
  311. subi YL, 20 + 2 ;[0] Only assign address on data packets, not ACK/NAK in x3
  312. sbci YH, 0 ;[1]
  313. ;2006-03-06: moved transfer of new address to usbDeviceAddr from C-Code to asm:
  314. ;set address only after data packet was sent, not after handshake
  315. breq skipAddrAssign ;[2]
  316. sts usbDeviceAddr, x2; if not skipped: SE0 is one cycle longer
  317. skipAddrAssign:
  318. ;end of usbDeviceAddress transfer
  319. ldi x2, 1<<USB_INTR_PENDING_BIT;[4] int0 occurred during TX -- clear pending flag
  320. USB_STORE_PENDING(x2) ;[5]
  321. ori x1, USBIDLE ;[6]
  322. in x2, USBDDR ;[7]
  323. cbr x2, USBMASK ;[8] set both pins to input
  324. mov x3, x1 ;[9]
  325. cbr x3, USBMASK ;[10] configure no pullup on both pins
  326. ldi x4, 5 ;[11]
  327. se0Delay:
  328. dec x4 ;[12] [15] [18] [21] [24]
  329. brne se0Delay ;[13] [16] [19] [22] [25]
  330. out USBOUT, x1 ;[26] <-- out J (idle) -- end of SE0 (EOP signal)
  331. out USBDDR, x2 ;[27] <-- release bus now
  332. out USBOUT, x3 ;[28] <-- ensure no pull-up resistors are active
  333. rjmp doReturn